Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 | Date : Sat Mar 13 12:29:52 2021 | Host : baby running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -file ngFEC_top_timing_summary_routed.rpt -pb ngFEC_top_timing_summary_routed.pb -rpx ngFEC_top_timing_summary_routed.rpx -warn_on_violation | Design : ngFEC_top | Device : xcku115-flva2104 | Speed File : -1 PRODUCTION 1.26 12-04-2018 | Temperature Grade : C ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (34) 6. checking no_output_delay (28) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (34) ------------------------------- There are 34 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (28) -------------------------------- There are 28 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.154 0.000 0 876399 0.029 0.000 0 876399 0.282 0.000 0 393451 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- DRPclk {0.000 10.000} 20.000 50.000 GBT_refclk0 {0.000 1.559} 3.119 320.616 gtwiz_userclk_rx_srcclk_out[0] {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_1 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_10 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_11 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_2 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_3 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_4 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_5 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_6 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_7 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_8 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_9 {0.000 4.159} 8.317 120.231 qpll0outclk_out[0] {0.000 0.097} 0.195 5129.849 qpll0outrefclk_out[0] {0.000 1.559} 3.119 320.616 txoutclk_out[0]_49 {0.000 1.559} 3.119 320.616 GBT_refclk1 {0.000 1.559} 3.119 320.616 gtwiz_userclk_rx_srcclk_out[0]_12 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_13 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_14 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_15 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_16 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_17 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_18 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_19 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_20 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_21 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_22 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_23 {0.000 4.159} 8.317 120.231 GBT_refclk2 {0.000 1.559} 3.119 320.616 gtwiz_userclk_rx_srcclk_out[0]_24 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_25 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_26 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_27 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_28 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_29 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_30 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_31 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_32 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_33 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_34 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_35 {0.000 4.159} 8.317 120.231 GBT_refclk3 {0.000 1.559} 3.119 320.616 gtwiz_userclk_rx_srcclk_out[0]_36 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_37 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_38 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_39 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_40 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_41 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_42 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_43 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_44 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_45 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_46 {0.000 4.159} 8.317 120.231 gtwiz_userclk_rx_srcclk_out[0]_47 {0.000 4.159} 8.317 120.231 TTC_rx_refclk {0.000 1.559} 3.119 320.616 qpll1outclk_out[0] {0.000 0.097} 0.195 5129.849 rxoutclk_out[0]_1 {0.000 1.559} 3.119 320.616 qpll1outrefclk_out[0] {0.000 1.559} 3.119 320.616 TTC_rxusrclk {0.000 1.559} 3.119 320.616 fabric_clk_in {0.000 12.476} 24.952 40.077 CLKFBOUT {6.238 18.714} 24.952 40.077 fabric_clk_dcm {0.000 12.476} 24.952 40.077 tx_wordclk_dcm {0.000 4.159} 8.317 120.231 clk125 {0.000 4.000} 8.000 125.000 clk250 {0.000 2.000} 4.000 250.000 fabric_clk {0.000 12.476} 24.952 40.077 ipb_clk {0.000 16.000} 32.000 31.250 refclk125 {0.000 4.000} 8.000 125.000 DRPclk_dcm {0.000 10.000} 20.000 50.000 clk125_dcm {0.000 4.000} 8.000 125.000 clk250_dcm {0.000 2.000} 4.000 250.000 ipb_clk_dcm {0.000 16.000} 32.000 31.250 rxoutclk_out[0] {0.000 3.200} 6.400 156.250 txoutclk_out[0]_48 {0.000 3.200} 6.400 156.250 axi_c2c_phy_clk {0.000 6.400} 12.800 78.125 rx_rcvclk {0.000 1.559} 3.119 320.616 tx_wordclk {0.000 4.159} 8.317 120.236 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- DRPclk 16.129 0.000 0 8305 0.037 0.000 0 8305 8.200 0.000 0 4215 gtwiz_userclk_rx_srcclk_out[0] 2.486 0.000 0 1308 0.037 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_1 3.498 0.000 0 1308 0.041 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_10 3.272 0.000 0 1308 0.034 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_11 3.153 0.000 0 1308 0.035 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_2 4.186 0.000 0 1308 0.036 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_3 2.349 0.000 0 1308 0.038 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_4 2.428 0.000 0 1308 0.040 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_5 2.044 0.000 0 1308 0.036 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_6 2.853 0.000 0 1308 0.044 0.000 0 1308 0.485 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_7 2.692 0.000 0 1308 0.036 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_8 2.280 0.000 0 1308 0.040 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_9 3.532 0.000 0 1308 0.038 0.000 0 1308 0.493 0.000 0 675 txoutclk_out[0]_49 0.477 0.000 0 1587 0.032 0.000 0 1587 0.407 0.000 0 540 gtwiz_userclk_rx_srcclk_out[0]_12 2.497 0.000 0 1308 0.035 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_13 3.408 0.000 0 1308 0.040 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_14 3.158 0.000 0 1308 0.039 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_15 3.354 0.000 0 1308 0.035 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_16 1.858 0.000 0 1308 0.033 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_17 3.270 0.000 0 1308 0.035 0.000 0 1308 0.485 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_18 2.699 0.000 0 1308 0.033 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_19 2.878 0.000 0 1308 0.042 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_20 1.922 0.000 0 1308 0.039 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_21 3.165 0.000 0 1308 0.037 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_22 3.569 0.000 0 1308 0.040 0.000 0 1308 0.493 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_23 3.766 0.000 0 1308 0.039 0.000 0 1308 0.494 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_24 2.638 0.000 0 1308 0.032 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_25 3.291 0.000 0 1308 0.034 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_26 3.693 0.000 0 1308 0.036 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_27 3.441 0.000 0 1308 0.036 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_28 3.366 0.000 0 1308 0.030 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_29 3.092 0.000 0 1308 0.039 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_30 3.447 0.000 0 1308 0.030 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_31 3.016 0.000 0 1308 0.034 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_32 3.761 0.000 0 1308 0.048 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_33 3.506 0.000 0 1308 0.030 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_34 3.279 0.000 0 1308 0.033 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_35 4.492 0.000 0 1308 0.031 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_36 4.051 0.000 0 1308 0.032 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_37 2.458 0.000 0 1308 0.031 0.000 0 1308 0.504 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_38 3.225 0.000 0 1308 0.032 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_39 4.185 0.000 0 1308 0.037 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_40 3.870 0.000 0 1308 0.035 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_41 3.171 0.000 0 1308 0.034 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_42 3.630 0.000 0 1308 0.038 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_43 2.559 0.000 0 1308 0.031 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_44 2.735 0.000 0 1308 0.036 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_45 3.659 0.000 0 1308 0.031 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_46 3.118 0.000 0 1308 0.030 0.000 0 1308 0.510 0.000 0 675 gtwiz_userclk_rx_srcclk_out[0]_47 3.239 0.000 0 1308 0.035 0.000 0 1308 0.510 0.000 0 675 rxoutclk_out[0]_1 1.532 0.000 0 1 TTC_rxusrclk 0.154 0.000 0 3842 0.031 0.000 0 3842 0.407 0.000 0 1861 fabric_clk_in 20.969 0.000 0 862 0.046 0.000 0 862 6.238 0.000 0 792 CLKFBOUT 23.365 0.000 0 3 fabric_clk_dcm 23.365 0.000 0 2 tx_wordclk_dcm 6.730 0.000 0 2 clk125 2.365 0.000 0 1903 0.036 0.000 0 1903 3.048 0.000 0 930 clk250 0.163 0.000 0 55692 0.036 0.000 0 55692 1.048 0.000 0 14374 fabric_clk 7.164 0.000 0 163569 0.030 0.000 0 163569 11.390 0.000 0 103803 ipb_clk 2.507 0.000 0 469628 0.030 0.000 0 469628 15.048 0.000 0 204768 refclk125 1.600 0.000 0 2 DRPclk_dcm 18.413 0.000 0 2 clk125_dcm 6.413 0.000 0 2 clk250_dcm 2.413 0.000 0 2 ipb_clk_dcm 30.413 0.000 0 2 rxoutclk_out[0] 3.825 0.000 0 1190 0.030 0.000 0 1190 0.495 0.000 0 618 txoutclk_out[0]_48 0.282 0.000 0 3 axi_c2c_phy_clk 7.984 0.000 0 3392 0.030 0.000 0 3392 0.583 0.000 0 1684 tx_wordclk 0.167 0.000 0 54028 0.030 0.000 0 54028 0.495 0.000 0 27445 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ipb_clk clk250 1.298 0.000 0 34 0.036 0.000 0 34 clk250 ipb_clk 0.625 0.000 0 6912 0.030 0.000 0 6912 fabric_clk tx_wordclk 4.096 0.000 0 3937 0.029 0.000 0 3937 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** DRPclk DRPclk 15.411 0.000 0 240 0.250 0.000 0 240 **async_default** TTC_rxusrclk TTC_rxusrclk 0.154 0.000 0 1096 0.107 0.000 0 1096 **async_default** axi_c2c_phy_clk axi_c2c_phy_clk 10.643 0.000 0 23 0.264 0.000 0 23 **async_default** clk125 clk125 2.056 0.000 0 41 0.230 0.000 0 41 **async_default** fabric_clk fabric_clk 8.583 0.000 0 11472 0.081 0.000 0 11472 **async_default** gtwiz_userclk_rx_srcclk_out[0] gtwiz_userclk_rx_srcclk_out[0] 5.734 0.000 0 391 0.170 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 5.232 0.000 0 391 0.188 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_10 gtwiz_userclk_rx_srcclk_out[0]_10 5.023 0.000 0 391 0.146 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_11 gtwiz_userclk_rx_srcclk_out[0]_11 4.913 0.000 0 391 0.154 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_12 gtwiz_userclk_rx_srcclk_out[0]_12 4.286 0.000 0 391 0.138 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_13 gtwiz_userclk_rx_srcclk_out[0]_13 3.923 0.000 0 391 0.142 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_14 gtwiz_userclk_rx_srcclk_out[0]_14 2.177 0.000 0 391 0.176 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_15 gtwiz_userclk_rx_srcclk_out[0]_15 5.622 0.000 0 391 0.154 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_16 gtwiz_userclk_rx_srcclk_out[0]_16 4.574 0.000 0 391 0.151 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_17 gtwiz_userclk_rx_srcclk_out[0]_17 4.263 0.000 0 391 0.171 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_18 gtwiz_userclk_rx_srcclk_out[0]_18 4.177 0.000 0 391 0.144 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_19 gtwiz_userclk_rx_srcclk_out[0]_19 4.404 0.000 0 391 0.162 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 4.963 0.000 0 391 0.161 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_20 gtwiz_userclk_rx_srcclk_out[0]_20 5.139 0.000 0 391 0.143 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_21 gtwiz_userclk_rx_srcclk_out[0]_21 5.343 0.000 0 391 0.186 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_22 gtwiz_userclk_rx_srcclk_out[0]_22 5.109 0.000 0 391 0.209 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_23 gtwiz_userclk_rx_srcclk_out[0]_23 6.165 0.000 0 391 0.138 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_24 gtwiz_userclk_rx_srcclk_out[0]_24 4.096 0.000 0 391 0.134 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_25 gtwiz_userclk_rx_srcclk_out[0]_25 4.220 0.000 0 391 0.138 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_26 gtwiz_userclk_rx_srcclk_out[0]_26 5.217 0.000 0 391 0.148 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_27 gtwiz_userclk_rx_srcclk_out[0]_27 4.443 0.000 0 391 0.133 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_28 gtwiz_userclk_rx_srcclk_out[0]_28 5.210 0.000 0 391 0.201 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_29 gtwiz_userclk_rx_srcclk_out[0]_29 5.335 0.000 0 391 0.102 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 4.028 0.000 0 391 0.102 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_30 gtwiz_userclk_rx_srcclk_out[0]_30 4.894 0.000 0 391 0.174 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_31 gtwiz_userclk_rx_srcclk_out[0]_31 4.963 0.000 0 391 0.130 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_32 gtwiz_userclk_rx_srcclk_out[0]_32 5.263 0.000 0 391 0.131 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_33 gtwiz_userclk_rx_srcclk_out[0]_33 4.837 0.000 0 391 0.176 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_34 gtwiz_userclk_rx_srcclk_out[0]_34 4.041 0.000 0 391 0.144 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_35 gtwiz_userclk_rx_srcclk_out[0]_35 5.239 0.000 0 391 0.146 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_36 gtwiz_userclk_rx_srcclk_out[0]_36 4.943 0.000 0 391 0.112 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_37 gtwiz_userclk_rx_srcclk_out[0]_37 3.774 0.000 0 391 0.210 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_38 gtwiz_userclk_rx_srcclk_out[0]_38 3.630 0.000 0 391 0.175 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_39 gtwiz_userclk_rx_srcclk_out[0]_39 4.460 0.000 0 391 0.215 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 3.966 0.000 0 391 0.112 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_40 gtwiz_userclk_rx_srcclk_out[0]_40 4.733 0.000 0 391 0.201 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_41 gtwiz_userclk_rx_srcclk_out[0]_41 3.911 0.000 0 391 0.158 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_42 gtwiz_userclk_rx_srcclk_out[0]_42 4.537 0.000 0 391 0.146 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_43 gtwiz_userclk_rx_srcclk_out[0]_43 4.180 0.000 0 391 0.128 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_44 gtwiz_userclk_rx_srcclk_out[0]_44 5.652 0.000 0 391 0.146 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_45 gtwiz_userclk_rx_srcclk_out[0]_45 4.530 0.000 0 391 0.173 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_46 gtwiz_userclk_rx_srcclk_out[0]_46 3.590 0.000 0 391 0.135 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_47 gtwiz_userclk_rx_srcclk_out[0]_47 5.865 0.000 0 391 0.195 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 3.482 0.000 0 391 0.187 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 4.129 0.000 0 391 0.128 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 4.748 0.000 0 391 0.175 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 4.806 0.000 0 391 0.170 0.000 0 391 **async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 4.803 0.000 0 391 0.140 0.000 0 391 **async_default** rxoutclk_out[0] rxoutclk_out[0] 5.586 0.000 0 8 0.142 0.000 0 8 **async_default** tx_wordclk tx_wordclk 0.414 0.000 0 11044 0.112 0.000 0 11044 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: DRPclk To Clock: DRPclk Setup : 0 Failing Endpoints, Worst Slack 16.129ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.037ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 8.200ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 16.129ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/rx_timer_sat_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_reg/D (rising edge-triggered cell FDSE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.005ns (logic 0.449ns (11.211%) route 3.556ns (88.789%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: 0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.160ns = ( 23.160 - 20.000 ) Source Clock Delay (SCD): 3.249ns Clock Pessimism Removal (CPR): 0.238ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.249ns (routing 0.701ns, distribution 2.548ns) Clock Net Delay (Destination): 3.160ns (routing 0.646ns, distribution 2.514ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.249 3.249 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X93Y480 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/rx_timer_sat_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y480 FDRE (Prop_HFF2_SLICEL_C_Q) 0.137 3.386 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/rx_timer_sat_reg/Q net (fo=4, routed) 1.160 4.546 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/rx_timer_sat_reg_n_0 SLICE_X98Y487 LUT6 (Prop_G6LUT_SLICEL_I1_O) 0.051 4.597 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_i_2__16/O net (fo=1, routed) 2.350 6.947 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr SLICE_X98Y486 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.261 7.208 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_i_1__16/O net (fo=1, routed) 0.046 7.254 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_i_1__16_n_0 SLICE_X98Y486 FDSE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_reg/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.160 23.160 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X98Y486 FDSE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_reg/C clock pessimism 0.238 23.398 clock uncertainty -0.079 23.319 SLICE_X98Y486 FDSE (Setup_HFF2_SLICEL_C_D) 0.064 23.383 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/timer_clr_reg ------------------------------------------------------------------- required time 23.383 arrival time -7.254 ------------------------------------------------------------------- slack 16.129 Slack (MET) : 16.478ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.227ns (logic 0.594ns (18.407%) route 2.633ns (81.593%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.156ns = ( 23.156 - 20.000 ) Source Clock Delay (SCD): 3.575ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.575ns (routing 0.701ns, distribution 2.874ns) Clock Net Delay (Destination): 3.156ns (routing 0.646ns, distribution 2.510ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.575 3.575 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X97Y508 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y508 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.714 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/Q net (fo=2, routed) 1.375 5.089 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] SLICE_X96Y508 LUT4 (Prop_A6LUT_SLICEL_I2_O) 0.146 5.235 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/O net (fo=1, routed) 0.071 5.306 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15_n_0 SLICE_X96Y508 LUT6 (Prop_C6LUT_SLICEL_I2_O) 0.088 5.394 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/O net (fo=2, routed) 0.308 5.702 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13_n_0 SLICE_X98Y508 LUT5 (Prop_F6LUT_SLICEL_I1_O) 0.221 5.923 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/O net (fo=26, routed) 0.879 6.802 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15_n_0 SLICE_X97Y510 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.156 23.156 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X97Y510 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C clock pessimism 0.257 23.413 clock uncertainty -0.079 23.334 SLICE_X97Y510 FDCE (Setup_AFF_SLICEM_C_CE) -0.054 23.280 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24] ------------------------------------------------------------------- required time 23.280 arrival time -6.802 ------------------------------------------------------------------- slack 16.478 Slack (MET) : 16.478ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.227ns (logic 0.594ns (18.407%) route 2.633ns (81.593%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.156ns = ( 23.156 - 20.000 ) Source Clock Delay (SCD): 3.575ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.575ns (routing 0.701ns, distribution 2.874ns) Clock Net Delay (Destination): 3.156ns (routing 0.646ns, distribution 2.510ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.575 3.575 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X97Y508 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y508 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.714 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/Q net (fo=2, routed) 1.375 5.089 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] SLICE_X96Y508 LUT4 (Prop_A6LUT_SLICEL_I2_O) 0.146 5.235 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/O net (fo=1, routed) 0.071 5.306 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15_n_0 SLICE_X96Y508 LUT6 (Prop_C6LUT_SLICEL_I2_O) 0.088 5.394 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/O net (fo=2, routed) 0.308 5.702 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13_n_0 SLICE_X98Y508 LUT5 (Prop_F6LUT_SLICEL_I1_O) 0.221 5.923 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/O net (fo=26, routed) 0.879 6.802 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15_n_0 SLICE_X97Y510 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.156 23.156 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X97Y510 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/C clock pessimism 0.257 23.413 clock uncertainty -0.079 23.334 SLICE_X97Y510 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 23.280 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25] ------------------------------------------------------------------- required time 23.280 arrival time -6.802 ------------------------------------------------------------------- slack 16.478 Slack (MET) : 16.578ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.198ns (logic 0.594ns (18.574%) route 2.604ns (81.426%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.147ns = ( 23.147 - 20.000 ) Source Clock Delay (SCD): 3.575ns Clock Pessimism Removal (CPR): 0.338ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.575ns (routing 0.701ns, distribution 2.874ns) Clock Net Delay (Destination): 3.147ns (routing 0.646ns, distribution 2.501ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.575 3.575 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X97Y508 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y508 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.714 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/Q net (fo=2, routed) 1.375 5.089 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] SLICE_X96Y508 LUT4 (Prop_A6LUT_SLICEL_I2_O) 0.146 5.235 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/O net (fo=1, routed) 0.071 5.306 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15_n_0 SLICE_X96Y508 LUT6 (Prop_C6LUT_SLICEL_I2_O) 0.088 5.394 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/O net (fo=2, routed) 0.308 5.702 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13_n_0 SLICE_X98Y508 LUT5 (Prop_F6LUT_SLICEL_I1_O) 0.221 5.923 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/O net (fo=26, routed) 0.850 6.773 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15_n_0 SLICE_X97Y509 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.147 23.147 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X97Y509 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/C clock pessimism 0.338 23.485 clock uncertainty -0.079 23.406 SLICE_X97Y509 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 23.351 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20] ------------------------------------------------------------------- required time 23.351 arrival time -6.773 ------------------------------------------------------------------- slack 16.578 Slack (MET) : 16.578ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.198ns (logic 0.594ns (18.574%) route 2.604ns (81.426%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.147ns = ( 23.147 - 20.000 ) Source Clock Delay (SCD): 3.575ns Clock Pessimism Removal (CPR): 0.338ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.575ns (routing 0.701ns, distribution 2.874ns) Clock Net Delay (Destination): 3.147ns (routing 0.646ns, distribution 2.501ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.575 3.575 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X97Y508 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y508 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.714 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/Q net (fo=2, routed) 1.375 5.089 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] SLICE_X96Y508 LUT4 (Prop_A6LUT_SLICEL_I2_O) 0.146 5.235 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/O net (fo=1, routed) 0.071 5.306 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15_n_0 SLICE_X96Y508 LUT6 (Prop_C6LUT_SLICEL_I2_O) 0.088 5.394 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/O net (fo=2, routed) 0.308 5.702 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13_n_0 SLICE_X98Y508 LUT5 (Prop_F6LUT_SLICEL_I1_O) 0.221 5.923 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/O net (fo=26, routed) 0.850 6.773 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15_n_0 SLICE_X97Y509 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.147 23.147 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X97Y509 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/C clock pessimism 0.338 23.485 clock uncertainty -0.079 23.406 SLICE_X97Y509 FDCE (Setup_FFF_SLICEM_C_CE) -0.055 23.351 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21] ------------------------------------------------------------------- required time 23.351 arrival time -6.773 ------------------------------------------------------------------- slack 16.578 Slack (MET) : 16.578ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.198ns (logic 0.594ns (18.574%) route 2.604ns (81.426%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.147ns = ( 23.147 - 20.000 ) Source Clock Delay (SCD): 3.575ns Clock Pessimism Removal (CPR): 0.338ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.575ns (routing 0.701ns, distribution 2.874ns) Clock Net Delay (Destination): 3.147ns (routing 0.646ns, distribution 2.501ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.575 3.575 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X97Y508 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y508 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.714 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/Q net (fo=2, routed) 1.375 5.089 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] SLICE_X96Y508 LUT4 (Prop_A6LUT_SLICEL_I2_O) 0.146 5.235 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/O net (fo=1, routed) 0.071 5.306 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15_n_0 SLICE_X96Y508 LUT6 (Prop_C6LUT_SLICEL_I2_O) 0.088 5.394 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/O net (fo=2, routed) 0.308 5.702 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13_n_0 SLICE_X98Y508 LUT5 (Prop_F6LUT_SLICEL_I1_O) 0.221 5.923 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/O net (fo=26, routed) 0.850 6.773 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15_n_0 SLICE_X97Y509 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.147 23.147 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X97Y509 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/C clock pessimism 0.338 23.485 clock uncertainty -0.079 23.406 SLICE_X97Y509 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 23.351 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22] ------------------------------------------------------------------- required time 23.351 arrival time -6.773 ------------------------------------------------------------------- slack 16.578 Slack (MET) : 16.578ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[23]/CE (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.198ns (logic 0.594ns (18.574%) route 2.604ns (81.426%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.147ns = ( 23.147 - 20.000 ) Source Clock Delay (SCD): 3.575ns Clock Pessimism Removal (CPR): 0.338ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.575ns (routing 0.701ns, distribution 2.874ns) Clock Net Delay (Destination): 3.147ns (routing 0.646ns, distribution 2.501ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.575 3.575 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X97Y508 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y508 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.714 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/Q net (fo=2, routed) 1.375 5.089 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12] SLICE_X96Y508 LUT4 (Prop_A6LUT_SLICEL_I2_O) 0.146 5.235 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15/O net (fo=1, routed) 0.071 5.306 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_6__15_n_0 SLICE_X96Y508 LUT6 (Prop_C6LUT_SLICEL_I2_O) 0.088 5.394 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13/O net (fo=2, routed) 0.308 5.702 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__13_n_0 SLICE_X98Y508 LUT5 (Prop_F6LUT_SLICEL_I1_O) 0.221 5.923 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15/O net (fo=26, routed) 0.850 6.773 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__15_n_0 SLICE_X97Y509 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[23]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.147 23.147 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X97Y509 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[23]/C clock pessimism 0.338 23.485 clock uncertainty -0.079 23.406 SLICE_X97Y509 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 23.351 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[23] ------------------------------------------------------------------- required time 23.351 arrival time -6.773 ------------------------------------------------------------------- slack 16.578 Slack (MET) : 16.662ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[4]/CE (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.133ns (logic 0.445ns (14.204%) route 2.688ns (85.796%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: -0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.809ns = ( 22.809 - 20.000 ) Source Clock Delay (SCD): 3.188ns Clock Pessimism Removal (CPR): 0.308ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.188ns (routing 0.701ns, distribution 2.487ns) Clock Net Delay (Destination): 2.809ns (routing 0.646ns, distribution 2.163ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.188 3.188 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/aurora_init_clk SLICE_X95Y87 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y87 FDRE (Prop_AFF_SLICEM_C_Q) 0.140 3.328 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/Q net (fo=4, routed) 0.918 4.246 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16] SLICE_X96Y87 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.218 4.464 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1/O net (fo=1, routed) 0.840 5.304 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1_n_0 SLICE_X94Y86 LUT3 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.391 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_1__1/O net (fo=25, routed) 0.930 6.321 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr SLICE_X95Y85 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.809 22.809 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/aurora_init_clk SLICE_X95Y85 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[4]/C clock pessimism 0.308 23.117 clock uncertainty -0.079 23.038 SLICE_X95Y85 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 22.983 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[4] ------------------------------------------------------------------- required time 22.983 arrival time -6.321 ------------------------------------------------------------------- slack 16.662 Slack (MET) : 16.662ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[5]/CE (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.133ns (logic 0.445ns (14.204%) route 2.688ns (85.796%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: -0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.809ns = ( 22.809 - 20.000 ) Source Clock Delay (SCD): 3.188ns Clock Pessimism Removal (CPR): 0.308ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.188ns (routing 0.701ns, distribution 2.487ns) Clock Net Delay (Destination): 2.809ns (routing 0.646ns, distribution 2.163ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.188 3.188 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/aurora_init_clk SLICE_X95Y87 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y87 FDRE (Prop_AFF_SLICEM_C_Q) 0.140 3.328 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/Q net (fo=4, routed) 0.918 4.246 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16] SLICE_X96Y87 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.218 4.464 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1/O net (fo=1, routed) 0.840 5.304 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1_n_0 SLICE_X94Y86 LUT3 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.391 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_1__1/O net (fo=25, routed) 0.930 6.321 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr SLICE_X95Y85 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.809 22.809 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/aurora_init_clk SLICE_X95Y85 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[5]/C clock pessimism 0.308 23.117 clock uncertainty -0.079 23.038 SLICE_X95Y85 FDRE (Setup_FFF_SLICEM_C_CE) -0.055 22.983 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[5] ------------------------------------------------------------------- required time 22.983 arrival time -6.321 ------------------------------------------------------------------- slack 16.662 Slack (MET) : 16.662ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[6]/CE (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 3.133ns (logic 0.445ns (14.204%) route 2.688ns (85.796%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: -0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.809ns = ( 22.809 - 20.000 ) Source Clock Delay (SCD): 3.188ns Clock Pessimism Removal (CPR): 0.308ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.188ns (routing 0.701ns, distribution 2.487ns) Clock Net Delay (Destination): 2.809ns (routing 0.646ns, distribution 2.163ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.188 3.188 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/aurora_init_clk SLICE_X95Y87 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y87 FDRE (Prop_AFF_SLICEM_C_Q) 0.140 3.328 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16]/Q net (fo=4, routed) 0.918 4.246 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[16] SLICE_X96Y87 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.218 4.464 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1/O net (fo=1, routed) 0.840 5.304 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_3__1_n_0 SLICE_X94Y86 LUT3 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.391 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr[0]_i_1__1/O net (fo=25, routed) 0.930 6.321 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr SLICE_X95Y85 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.809 22.809 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/aurora_init_clk SLICE_X95Y85 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[6]/C clock pessimism 0.308 23.117 clock uncertainty -0.079 23.038 SLICE_X95Y85 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 22.983 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/timer_ctr_reg[6] ------------------------------------------------------------------- required time 22.983 arrival time -6.321 ------------------------------------------------------------------- slack 16.662 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.269ns (logic 0.209ns (77.695%) route 0.060ns (22.305%)) Logic Levels: 4 (CARRY8=4) Clock Path Skew: 0.176ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.411ns Source Clock Delay (SCD): 1.209ns Clock Pessimism Removal (CPR): 0.026ns Clock Net Delay (Source): 1.209ns (routing 0.240ns, distribution 0.969ns) Clock Net Delay (Destination): 1.411ns (routing 0.266ns, distribution 1.145ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.209 1.209 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/aurora_init_clk SLICE_X32Y237 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y237 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.258 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/Q net (fo=2, routed) 0.050 1.308 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1] SLICE_X32Y237 CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7]) 0.094 1.402 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__30/CO[7] net (fo=1, routed) 0.000 1.402 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__30_n_0 SLICE_X32Y238 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.016 1.418 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__30/CO[7] net (fo=1, routed) 0.000 1.418 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__30_n_0 SLICE_X32Y239 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.016 1.434 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__30/CO[7] net (fo=1, routed) 0.000 1.434 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__30_n_0 SLICE_X32Y240 CARRY8 (Prop_CARRY8_SLICEL_CI_O[0]) 0.034 1.468 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__30/O[0] net (fo=1, routed) 0.010 1.478 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__30_n_15 SLICE_X32Y240 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.411 1.411 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/aurora_init_clk SLICE_X32Y240 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C clock pessimism -0.026 1.385 SLICE_X32Y240 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.441 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24] ------------------------------------------------------------------- required time -1.441 arrival time 1.478 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.038ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[0]/D (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.187ns (logic 0.094ns (50.267%) route 0.093ns (49.733%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.601ns Source Clock Delay (SCD): 1.365ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 1.365ns (routing 0.240ns, distribution 1.125ns) Clock Net Delay (Destination): 1.601ns (routing 0.266ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.365 1.365 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/drpclk_in[0] SLICE_X137Y2 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y2 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 1.414 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/Q net (fo=3, routed) 0.077 1.491 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/gtwiz_reset_tx_pll_and_datapath_dly SLICE_X139Y2 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.045 1.536 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/FSM_sequential_sm_reset_tx[0]_i_1/O net (fo=1, routed) 0.016 1.552 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_tx__0[0] SLICE_X139Y2 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[0]/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.601 1.601 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/drpclk_in[0] SLICE_X139Y2 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[0]/C clock pessimism -0.143 1.458 SLICE_X139Y2 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.514 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[0] ------------------------------------------------------------------- required time -1.514 arrival time 1.552 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.247ns (logic 0.188ns (76.113%) route 0.059ns (23.887%)) Logic Levels: 3 (CARRY8=3) Clock Path Skew: 0.151ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.184ns Clock Pessimism Removal (CPR): 0.046ns Clock Net Delay (Source): 1.184ns (routing 0.240ns, distribution 0.944ns) Clock Net Delay (Destination): 1.381ns (routing 0.266ns, distribution 1.115ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.184 1.184 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X90Y478 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X90Y478 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.233 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/Q net (fo=2, routed) 0.049 1.282 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8] SLICE_X90Y478 CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7]) 0.089 1.371 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__17/CO[7] net (fo=1, routed) 0.000 1.371 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__17_n_0 SLICE_X90Y479 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.016 1.387 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__17/CO[7] net (fo=1, routed) 0.000 1.387 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__17_n_0 SLICE_X90Y480 CARRY8 (Prop_CARRY8_SLICEM_CI_O[0]) 0.034 1.421 r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__17/O[0] net (fo=1, routed) 0.010 1.431 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__17_n_15 SLICE_X90Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.381 1.381 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/aurora_init_clk SLR Crossing[0->1] SLICE_X90Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C clock pessimism -0.046 1.335 SLICE_X90Y480 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.391 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24] ------------------------------------------------------------------- required time -1.391 arrival time 1.431 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/FSM_sequential_sm_init_reg[0]/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/D (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.176ns (logic 0.080ns (45.455%) route 0.096ns (54.545%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.394ns Source Clock Delay (SCD): 1.179ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.179ns (routing 0.240ns, distribution 0.939ns) Clock Net Delay (Destination): 1.394ns (routing 0.266ns, distribution 1.128ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.179 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk SLICE_X39Y274 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/FSM_sequential_sm_init_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y274 FDRE (Prop_HFF2_SLICEM_C_Q) 0.048 1.227 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/FSM_sequential_sm_init_reg[0]/Q net (fo=7, routed) 0.080 1.307 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/sm_init[0] SLICE_X37Y274 LUT6 (Prop_H6LUT_SLICEM_I1_O) 0.032 1.339 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_i_1__34/O net (fo=1, routed) 0.016 1.355 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_i_1__34_n_0 SLICE_X37Y274 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.394 1.394 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk SLICE_X37Y274 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C clock pessimism -0.136 1.258 SLICE_X37Y274 FDRE (Hold_HFF_SLICEM_C_D) 0.056 1.314 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg ------------------------------------------------------------------- required time -1.314 arrival time 1.355 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/rx_timer_sat_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_reg/D (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.152ns (logic 0.063ns (41.447%) route 0.089ns (58.553%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.460ns Source Clock Delay (SCD): 1.236ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 1.236ns (routing 0.240ns, distribution 0.996ns) Clock Net Delay (Destination): 1.460ns (routing 0.266ns, distribution 1.194ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.236 1.236 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk SLICE_X113Y212 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/rx_timer_sat_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y212 FDRE (Prop_CFF2_SLICEM_C_Q) 0.048 1.284 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/rx_timer_sat_reg/Q net (fo=4, routed) 0.077 1.361 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/rx_timer_sat_reg_n_0 SLICE_X113Y213 LUT6 (Prop_A6LUT_SLICEM_I1_O) 0.015 1.376 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_i_1__10/O net (fo=1, routed) 0.012 1.388 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_i_1__10_n_0 SLICE_X113Y213 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_reg/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.460 1.460 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk SLICE_X113Y213 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_reg/C clock pessimism -0.170 1.290 SLICE_X113Y213 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.346 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_rx_out_reg ------------------------------------------------------------------- required time -1.346 arrival time 1.388 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[1]/D (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.192ns (logic 0.104ns (54.167%) route 0.088ns (45.833%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.601ns Source Clock Delay (SCD): 1.365ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 1.365ns (routing 0.240ns, distribution 1.125ns) Clock Net Delay (Destination): 1.601ns (routing 0.266ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.365 1.365 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/drpclk_in[0] SLICE_X137Y2 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y2 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 1.414 f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/Q net (fo=3, routed) 0.077 1.491 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/gtwiz_reset_tx_pll_and_datapath_dly SLICE_X139Y2 LUT4 (Prop_D5LUT_SLICEL_I1_O) 0.055 1.546 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/FSM_sequential_sm_reset_tx[1]_i_1/O net (fo=1, routed) 0.011 1.557 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/sm_reset_tx__0[1] SLICE_X139Y2 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[1]/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.601 1.601 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/drpclk_in[0] SLICE_X139Y2 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[1]/C clock pessimism -0.143 1.458 SLICE_X139Y2 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.514 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_tx_reg[1] ------------------------------------------------------------------- required time -1.514 arrival time 1.557 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/rx_timer_sat_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_reg/D (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.157ns (logic 0.064ns (40.764%) route 0.093ns (59.236%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.523ns Source Clock Delay (SCD): 1.299ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.299ns (routing 0.240ns, distribution 1.059ns) Clock Net Delay (Destination): 1.523ns (routing 0.266ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.299 1.299 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X107Y526 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/rx_timer_sat_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y526 FDRE (Prop_CFF2_SLICEM_C_Q) 0.048 1.347 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/rx_timer_sat_reg/Q net (fo=4, routed) 0.078 1.425 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/rx_timer_sat_reg_n_0 SLICE_X107Y527 LUT6 (Prop_B6LUT_SLICEM_I1_O) 0.016 1.441 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_i_1__19/O net (fo=1, routed) 0.015 1.456 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_i_1__19_n_0 SLICE_X107Y527 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_reg/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.523 1.523 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X107Y527 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_reg/C clock pessimism -0.168 1.355 SLICE_X107Y527 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.411 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_rx_out_reg ------------------------------------------------------------------- required time -1.411 arrival time 1.456 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/C (rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_reg/D (rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.171ns (logic 0.078ns (45.614%) route 0.093ns (54.386%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.411ns Source Clock Delay (SCD): 1.209ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 1.209ns (routing 0.240ns, distribution 0.969ns) Clock Net Delay (Destination): 1.411ns (routing 0.266ns, distribution 1.145ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.209 1.209 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/aurora_init_clk SLICE_X31Y154 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y154 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.257 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/Q net (fo=3, routed) 0.077 1.334 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18] SLICE_X30Y154 LUT6 (Prop_D6LUT_SLICEL_I1_O) 0.030 1.364 r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_i_1__24/O net (fo=1, routed) 0.016 1.380 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_i_1__24_n_0 SLICE_X30Y154 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_reg/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.411 1.411 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/aurora_init_clk SLICE_X30Y154 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_reg/C clock pessimism -0.132 1.279 SLICE_X30Y154 FDPE (Hold_DFF_SLICEL_C_D) 0.056 1.335 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genReset_s_reg ------------------------------------------------------------------- required time -1.335 arrival time 1.380 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C (rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/D (rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.171ns (logic 0.048ns (28.070%) route 0.123ns (71.930%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.477ns Source Clock Delay (SCD): 1.267ns Clock Pessimism Removal (CPR): 0.140ns Clock Net Delay (Source): 1.267ns (routing 0.240ns, distribution 1.027ns) Clock Net Delay (Destination): 1.477ns (routing 0.266ns, distribution 1.211ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.267 1.267 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X103Y442 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C ------------------------------------------------------------------- ------------------- SLICE_X103Y442 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.315 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/Q net (fo=1, routed) 0.123 1.438 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3 SLICE_X101Y442 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.477 1.477 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X101Y442 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C clock pessimism -0.140 1.337 SLICE_X101Y442 FDPE (Hold_AFF_SLICEM_C_D) 0.056 1.393 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time -1.393 arrival time 1.438 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/tx_timer_sat_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/D (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: DRPclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.174ns (logic 0.078ns (44.828%) route 0.096ns (55.172%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.146ns Clock Pessimism Removal (CPR): 0.118ns Clock Net Delay (Source): 1.146ns (routing 0.240ns, distribution 0.906ns) Clock Net Delay (Destination): 1.336ns (routing 0.266ns, distribution 1.070ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.146 1.146 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/aurora_init_clk SLICE_X84Y66 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/tx_timer_sat_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y66 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.194 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/tx_timer_sat_reg/Q net (fo=3, routed) 0.081 1.275 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/tx_timer_sat_reg_n_0 SLICE_X86Y66 LUT6 (Prop_B6LUT_SLICEL_I3_O) 0.030 1.305 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_i_1__0/O net (fo=1, routed) 0.015 1.320 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_i_1__0_n_0 SLICE_X86Y66 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/D ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.336 1.336 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/aurora_init_clk SLICE_X86Y66 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C clock pessimism -0.118 1.218 SLICE_X86Y66 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.274 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg ------------------------------------------------------------------- required time -1.274 arrival time 1.320 ------------------------------------------------------------------- slack 0.046 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: DRPclk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { i_DRPclk_bufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 20.000 16.000 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a SRL16E/CLK n/a 1.356 20.000 18.644 SLICE_X142Y26 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/u_rst_sync_btf_sync/stg5_reg_srl2/CLK Min Period n/a SRLC32E/CLK n/a 1.356 20.000 18.644 SLICE_X142Y21 i_axi_slave/i_aurora/inst/support_reset_logic_i/dly_gt_rst_r_reg[17]_srl18/CLK Min Period n/a SRLC32E/CLK n/a 1.356 20.000 18.644 SLICE_X119Y23 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[126]_srl28/CLK Min Period n/a SRLC32E/CLK n/a 1.356 20.000 18.644 SLICE_X119Y23 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[34]_srl32/CLK Min Period n/a SRLC32E/CLK n/a 1.356 20.000 18.644 SLICE_X119Y23 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[66]_srl32/CLK Min Period n/a SRLC32E/CLK n/a 1.356 20.000 18.644 SLICE_X119Y23 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[98]_srl32/CLK Min Period n/a FDPE/C n/a 0.550 20.000 19.450 SLICE_X82Y67 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genReset_s_reg/C Min Period n/a FDCE/C n/a 0.550 20.000 19.450 SLICE_X81Y66 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C Min Period n/a FDCE/C n/a 0.550 20.000 19.450 SLICE_X81Y67 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/C Low Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 10.000 8.200 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 10.000 8.200 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow SRL16E/CLK n/a 0.678 10.000 9.322 SLICE_X142Y26 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/u_rst_sync_btf_sync/stg5_reg_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.678 10.000 9.322 SLICE_X142Y26 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/u_rst_sync_btf_sync/stg5_reg_srl2/CLK Low Pulse Width Slow SRLC32E/CLK n/a 0.678 10.000 9.322 SLICE_X142Y21 i_axi_slave/i_aurora/inst/support_reset_logic_i/dly_gt_rst_r_reg[17]_srl18/CLK Low Pulse Width Slow SRLC32E/CLK n/a 0.678 10.000 9.322 SLICE_X119Y23 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[126]_srl28/CLK Low Pulse Width Slow SRLC32E/CLK n/a 0.678 10.000 9.322 SLICE_X119Y23 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[34]_srl32/CLK Low Pulse Width Slow SRLC32E/CLK n/a 0.678 10.000 9.322 SLICE_X119Y23 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[66]_srl32/CLK Low Pulse Width Slow SRLC32E/CLK n/a 0.678 10.000 9.322 SLICE_X119Y23 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[98]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.678 10.000 9.322 SLICE_X142Y21 i_axi_slave/i_aurora/inst/support_reset_logic_i/dly_gt_rst_r_reg[17]_srl18/CLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 10.000 8.200 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 10.000 8.200 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow SRL16E/CLK n/a 0.678 10.000 9.322 SLICE_X142Y26 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/u_rst_sync_btf_sync/stg5_reg_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.678 10.000 9.322 SLICE_X142Y26 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/u_rst_sync_btf_sync/stg5_reg_srl2/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.678 10.000 9.322 SLICE_X142Y21 i_axi_slave/i_aurora/inst/support_reset_logic_i/dly_gt_rst_r_reg[17]_srl18/CLK High Pulse Width Fast SRLC32E/CLK n/a 0.678 10.000 9.322 SLICE_X142Y21 i_axi_slave/i_aurora/inst/support_reset_logic_i/dly_gt_rst_r_reg[17]_srl18/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.678 10.000 9.322 SLICE_X119Y23 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[126]_srl28/CLK High Pulse Width Fast SRLC32E/CLK n/a 0.678 10.000 9.322 SLICE_X119Y23 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[126]_srl28/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.678 10.000 9.322 SLICE_X119Y23 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[34]_srl32/CLK High Pulse Width Fast SRLC32E/CLK n/a 0.678 10.000 9.322 SLICE_X119Y23 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.standard_cc_module_inst/pma_init_stage_reg[34]_srl32/CLK --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0] To Clock: gtwiz_userclk_rx_srcclk_out[0] Setup : 0 Failing Endpoints, Worst Slack 2.486ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.037ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.486ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 5.134ns (logic 1.548ns (30.152%) route 3.586ns (69.848%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.607ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.170ns = ( 11.487 - 8.317 ) Source Clock Delay (SCD): 4.079ns Clock Pessimism Removal (CPR): 0.302ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.604ns (routing 1.577ns, distribution 2.027ns) Clock Net Delay (Destination): 2.772ns (routing 1.441ns, distribution 1.331ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.604 4.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 5.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.797 8.037 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] SLICE_X86Y65 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.219 8.256 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.188 8.444 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y65 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.168 8.612 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/O net (fo=7, routed) 0.601 9.213 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X86Y65 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.772 11.487 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y65 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.302 11.789 clock uncertainty -0.035 11.754 SLICE_X86Y65 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.699 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.699 arrival time -9.213 ------------------------------------------------------------------- slack 2.486 Slack (MET) : 2.491ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 5.130ns (logic 1.548ns (30.175%) route 3.582ns (69.825%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.607ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.170ns = ( 11.487 - 8.317 ) Source Clock Delay (SCD): 4.079ns Clock Pessimism Removal (CPR): 0.302ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.604ns (routing 1.577ns, distribution 2.027ns) Clock Net Delay (Destination): 2.772ns (routing 1.441ns, distribution 1.331ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.604 4.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 5.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.797 8.037 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] SLICE_X86Y65 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.219 8.256 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.188 8.444 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y65 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.168 8.612 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/O net (fo=7, routed) 0.597 9.209 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X86Y65 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.772 11.487 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y65 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.302 11.789 clock uncertainty -0.035 11.754 SLICE_X86Y65 FDRE (Setup_AFF_SLICEL_C_CE) -0.054 11.700 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.700 arrival time -9.209 ------------------------------------------------------------------- slack 2.491 Slack (MET) : 2.574ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 5.059ns (logic 1.643ns (32.477%) route 3.416ns (67.523%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.594ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.184ns = ( 11.501 - 8.317 ) Source Clock Delay (SCD): 4.079ns Clock Pessimism Removal (CPR): 0.301ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.604ns (routing 1.577ns, distribution 2.027ns) Clock Net Delay (Destination): 2.786ns (routing 1.441ns, distribution 1.345ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.604 4.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 5.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.797 8.037 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] SLICE_X86Y65 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.219 8.256 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.182 8.438 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y65 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 8.528 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7/O net (fo=1, routed) 0.084 8.612 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7_n_0 SLICE_X85Y65 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 8.785 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1/O net (fo=2, routed) 0.353 9.138 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1_n_0 SLICE_X84Y65 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.786 11.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y65 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.301 11.803 clock uncertainty -0.035 11.767 SLICE_X84Y65 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.712 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.712 arrival time -9.138 ------------------------------------------------------------------- slack 2.574 Slack (MET) : 2.574ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 5.059ns (logic 1.643ns (32.477%) route 3.416ns (67.523%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.594ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.184ns = ( 11.501 - 8.317 ) Source Clock Delay (SCD): 4.079ns Clock Pessimism Removal (CPR): 0.301ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.604ns (routing 1.577ns, distribution 2.027ns) Clock Net Delay (Destination): 2.786ns (routing 1.441ns, distribution 1.345ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.604 4.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 5.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.797 8.037 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] SLICE_X86Y65 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.219 8.256 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.182 8.438 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y65 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 8.528 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7/O net (fo=1, routed) 0.084 8.612 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7_n_0 SLICE_X85Y65 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 8.785 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1/O net (fo=2, routed) 0.353 9.138 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1_n_0 SLICE_X84Y65 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.786 11.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y65 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.301 11.803 clock uncertainty -0.035 11.767 SLICE_X84Y65 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.712 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.712 arrival time -9.138 ------------------------------------------------------------------- slack 2.574 Slack (MET) : 2.647ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 4.957ns (logic 1.548ns (31.229%) route 3.409ns (68.771%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.623ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.154ns = ( 11.471 - 8.317 ) Source Clock Delay (SCD): 4.079ns Clock Pessimism Removal (CPR): 0.302ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.604ns (routing 1.577ns, distribution 2.027ns) Clock Net Delay (Destination): 2.756ns (routing 1.441ns, distribution 1.315ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.604 4.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 5.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.797 8.037 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] SLICE_X86Y65 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.219 8.256 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.188 8.444 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y65 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.168 8.612 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/O net (fo=7, routed) 0.424 9.036 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X86Y64 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.756 11.471 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y64 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.302 11.773 clock uncertainty -0.035 11.738 SLICE_X86Y64 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.683 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.683 arrival time -9.036 ------------------------------------------------------------------- slack 2.647 Slack (MET) : 2.652ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 4.953ns (logic 1.548ns (31.254%) route 3.405ns (68.746%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.623ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.154ns = ( 11.471 - 8.317 ) Source Clock Delay (SCD): 4.079ns Clock Pessimism Removal (CPR): 0.302ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.604ns (routing 1.577ns, distribution 2.027ns) Clock Net Delay (Destination): 2.756ns (routing 1.441ns, distribution 1.315ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.604 4.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 5.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.797 8.037 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] SLICE_X86Y65 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.219 8.256 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.188 8.444 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y65 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.168 8.612 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/O net (fo=7, routed) 0.420 9.032 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X86Y64 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.756 11.471 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y64 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.302 11.773 clock uncertainty -0.035 11.738 SLICE_X86Y64 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 11.684 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.684 arrival time -9.032 ------------------------------------------------------------------- slack 2.652 Slack (MET) : 2.652ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 4.953ns (logic 1.548ns (31.254%) route 3.405ns (68.746%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.623ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.154ns = ( 11.471 - 8.317 ) Source Clock Delay (SCD): 4.079ns Clock Pessimism Removal (CPR): 0.302ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.604ns (routing 1.577ns, distribution 2.027ns) Clock Net Delay (Destination): 2.756ns (routing 1.441ns, distribution 1.315ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.604 4.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 5.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.797 8.037 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] SLICE_X86Y65 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.219 8.256 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.188 8.444 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y65 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.168 8.612 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__0/O net (fo=7, routed) 0.420 9.032 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X86Y64 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.756 11.471 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y64 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.302 11.773 clock uncertainty -0.035 11.738 SLICE_X86Y64 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.684 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.684 arrival time -9.032 ------------------------------------------------------------------- slack 2.652 Slack (MET) : 2.688ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 4.935ns (logic 1.530ns (31.003%) route 3.405ns (68.997%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.604ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.173ns = ( 11.490 - 8.317 ) Source Clock Delay (SCD): 4.079ns Clock Pessimism Removal (CPR): 0.302ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.604ns (routing 1.577ns, distribution 2.027ns) Clock Net Delay (Destination): 2.775ns (routing 1.441ns, distribution 1.334ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.604 4.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 5.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.797 8.037 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] SLICE_X86Y65 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.219 8.256 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.261 8.517 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y66 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.150 8.667 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/O net (fo=5, routed) 0.347 9.014 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X85Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.775 11.490 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.302 11.792 clock uncertainty -0.035 11.757 SLICE_X85Y67 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.702 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.702 arrival time -9.014 ------------------------------------------------------------------- slack 2.688 Slack (MET) : 2.688ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 4.935ns (logic 1.530ns (31.003%) route 3.405ns (68.997%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.604ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.173ns = ( 11.490 - 8.317 ) Source Clock Delay (SCD): 4.079ns Clock Pessimism Removal (CPR): 0.302ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.604ns (routing 1.577ns, distribution 2.027ns) Clock Net Delay (Destination): 2.775ns (routing 1.441ns, distribution 1.334ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.604 4.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 5.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.797 8.037 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] SLICE_X86Y65 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.219 8.256 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.261 8.517 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y66 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.150 8.667 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/O net (fo=5, routed) 0.347 9.014 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X85Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.775 11.490 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.302 11.792 clock uncertainty -0.035 11.757 SLICE_X85Y67 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.702 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.702 arrival time -9.014 ------------------------------------------------------------------- slack 2.688 Slack (MET) : 2.692ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 4.932ns (logic 1.530ns (31.022%) route 3.402ns (68.978%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.604ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.173ns = ( 11.490 - 8.317 ) Source Clock Delay (SCD): 4.079ns Clock Pessimism Removal (CPR): 0.302ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.604ns (routing 1.577ns, distribution 2.027ns) Clock Net Delay (Destination): 2.775ns (routing 1.441ns, distribution 1.334ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.604 4.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 5.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.797 8.037 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[3] SLICE_X86Y65 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.219 8.256 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/O net (fo=5, routed) 0.261 8.517 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y66 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.150 8.667 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/O net (fo=5, routed) 0.344 9.011 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X85Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.775 11.490 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y67 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.302 11.792 clock uncertainty -0.035 11.757 SLICE_X85Y67 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.703 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.703 arrival time -9.011 ------------------------------------------------------------------- slack 2.692 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].rx_data_ngccm_reg[0][79]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.192ns (logic 0.049ns (25.521%) route 0.143ns (74.479%)) Logic Levels: 0 Clock Path Skew: 0.099ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.542ns Source Clock Delay (SCD): 1.315ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 1.197ns (routing 0.667ns, distribution 0.530ns) Clock Net Delay (Destination): 1.377ns (routing 0.748ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.197 1.315 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X78Y60 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y60 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.364 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/Q net (fo=1, routed) 0.143 1.507 rx_data[0][79] SLICE_X77Y59 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][79]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.377 1.542 RX_WORDCLK_O[0] SLICE_X77Y59 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][79]/C clock pessimism -0.128 1.414 SLICE_X77Y59 FDCE (Hold_HFF2_SLICEM_C_D) 0.056 1.470 SFP_GEN[0].rx_data_ngccm_reg[0][79] ------------------------------------------------------------------- required time -1.470 arrival time 1.507 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.183ns (logic 0.094ns (51.366%) route 0.089ns (48.634%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.573ns Source Clock Delay (SCD): 1.313ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 1.195ns (routing 0.667ns, distribution 0.528ns) Clock Net Delay (Destination): 1.408ns (routing 0.748ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.195 1.313 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X78Y60 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y60 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.362 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Q net (fo=2, routed) 0.073 1.435 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_9_in SLICE_X79Y60 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.480 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1/O net (fo=1, routed) 0.016 1.496 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] SLICE_X79Y60 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.408 1.573 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X79Y60 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.175 1.398 SLICE_X79Y60 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.454 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.454 arrival time 1.496 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].rx_data_ngccm_reg[0][45]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.180ns (logic 0.049ns (27.222%) route 0.131ns (72.778%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.571ns Source Clock Delay (SCD): 1.314ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 1.196ns (routing 0.667ns, distribution 0.529ns) Clock Net Delay (Destination): 1.406ns (routing 0.748ns, distribution 0.658ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.196 1.314 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X78Y62 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y62 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.363 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.131 1.494 rx_data[0][45] SLICE_X80Y62 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][45]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.406 1.571 RX_WORDCLK_O[0] SLICE_X80Y62 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][45]/C clock pessimism -0.175 1.396 SLICE_X80Y62 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.451 SFP_GEN[0].rx_data_ngccm_reg[0][45] ------------------------------------------------------------------- required time -1.451 arrival time 1.494 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].rx_data_ngccm_reg[0][5]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.584ns Source Clock Delay (SCD): 1.336ns Clock Pessimism Removal (CPR): 0.207ns Clock Net Delay (Source): 1.218ns (routing 0.667ns, distribution 0.551ns) Clock Net Delay (Destination): 1.419ns (routing 0.748ns, distribution 0.671ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.336 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X81Y63 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y63 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.384 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.093 1.477 rx_data[0][5] SLICE_X81Y64 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.419 1.584 RX_WORDCLK_O[0] SLICE_X81Y64 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][5]/C clock pessimism -0.207 1.377 SLICE_X81Y64 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.433 SFP_GEN[0].rx_data_ngccm_reg[0][5] ------------------------------------------------------------------- required time -1.433 arrival time 1.477 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].rx_data_ngccm_reg[0][71]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.192ns (logic 0.048ns (25.000%) route 0.144ns (75.000%)) Logic Levels: 0 Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.560ns Source Clock Delay (SCD): 1.297ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 1.179ns (routing 0.667ns, distribution 0.512ns) Clock Net Delay (Destination): 1.395ns (routing 0.748ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.179 1.297 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X80Y57 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y57 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.345 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/Q net (fo=1, routed) 0.144 1.489 rx_data[0][71] SLICE_X77Y57 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][71]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.395 1.560 RX_WORDCLK_O[0] SLICE_X77Y57 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][71]/C clock pessimism -0.172 1.388 SLICE_X77Y57 FDCE (Hold_CFF2_SLICEM_C_D) 0.056 1.444 SFP_GEN[0].rx_data_ngccm_reg[0][71] ------------------------------------------------------------------- required time -1.444 arrival time 1.489 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].rx_data_ngccm_reg[0][33]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.150ns (logic 0.049ns (32.667%) route 0.101ns (67.333%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.349ns Clock Pessimism Removal (CPR): 0.207ns Clock Net Delay (Source): 1.231ns (routing 0.667ns, distribution 0.564ns) Clock Net Delay (Destination): 1.441ns (routing 0.748ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.231 1.349 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X83Y64 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X83Y64 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.398 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/Q net (fo=1, routed) 0.101 1.499 rx_data[0][33] SLICE_X83Y65 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][33]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.441 1.606 RX_WORDCLK_O[0] SLICE_X83Y65 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][33]/C clock pessimism -0.207 1.399 SLICE_X83Y65 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.454 SFP_GEN[0].rx_data_ngccm_reg[0][33] ------------------------------------------------------------------- required time -1.454 arrival time 1.499 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.249ns (logic 0.079ns (31.727%) route 0.170ns (68.273%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.147ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.573ns Source Clock Delay (SCD): 1.298ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 1.180ns (routing 0.667ns, distribution 0.513ns) Clock Net Delay (Destination): 1.408ns (routing 0.748ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.180 1.298 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X80Y58 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y58 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.346 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.155 1.501 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[0] SLICE_X79Y60 LUT3 (Prop_B6LUT_SLICEM_I2_O) 0.031 1.532 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1/O net (fo=1, routed) 0.015 1.547 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] SLICE_X79Y60 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.408 1.573 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y60 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.128 1.445 SLICE_X79Y60 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.501 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.501 arrival time 1.547 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[20]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.148ns (logic 0.094ns (63.513%) route 0.054ns (36.486%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.609ns Source Clock Delay (SCD): 1.347ns Clock Pessimism Removal (CPR): 0.218ns Clock Net Delay (Source): 1.229ns (routing 0.667ns, distribution 0.562ns) Clock Net Delay (Destination): 1.444ns (routing 0.748ns, distribution 0.696ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.347 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y62 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.396 f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.038 1.434 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X84Y62 LUT5 (Prop_C6LUT_SLICEL_I1_O) 0.045 1.479 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0[20]_i_1__1/O net (fo=1, routed) 0.016 1.495 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg00[20] SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.444 1.609 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[20]/C clock pessimism -0.218 1.391 SLICE_X84Y62 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.447 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[20] ------------------------------------------------------------------- required time -1.447 arrival time 1.495 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[0].rx_data_ngccm_reg[0][44]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[44]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.574ns Source Clock Delay (SCD): 1.319ns Clock Pessimism Removal (CPR): 0.215ns Clock Net Delay (Source): 1.201ns (routing 0.667ns, distribution 0.534ns) Clock Net Delay (Destination): 1.409ns (routing 0.748ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.201 1.319 RX_WORDCLK_O[0] SLICE_X80Y62 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][44]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y62 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.368 r SFP_GEN[0].rx_data_ngccm_reg[0][44]/Q net (fo=1, routed) 0.034 1.402 g_gbt_bank[0].gbtbank/RX_Word_rx40_reg[78][20] SLICE_X80Y62 LUT3 (Prop_C6LUT_SLICEL_I1_O) 0.045 1.447 r g_gbt_bank[0].gbtbank/RX_Word_rx40[44]_i_1/O net (fo=1, routed) 0.016 1.463 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[83]_0[26] SLICE_X80Y62 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[44]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.409 1.574 SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y62 FDCE r SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[44]/C clock pessimism -0.215 1.359 SLICE_X80Y62 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.415 SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[44] ------------------------------------------------------------------- required time -1.415 arrival time 1.463 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[0].rx_data_ngccm_reg[0][6]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.158ns (logic 0.048ns (30.380%) route 0.110ns (69.620%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.346ns Clock Pessimism Removal (CPR): 0.208ns Clock Net Delay (Source): 1.228ns (routing 0.667ns, distribution 0.561ns) Clock Net Delay (Destination): 1.441ns (routing 0.748ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.346 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X83Y63 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X83Y63 FDRE (Prop_CFF2_SLICEM_C_Q) 0.048 1.394 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.110 1.504 rx_data[0][6] SLICE_X83Y65 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.441 1.606 RX_WORDCLK_O[0] SLICE_X83Y65 FDCE r SFP_GEN[0].rx_data_ngccm_reg[0][6]/C clock pessimism -0.208 1.398 SLICE_X83Y65 FDCE (Hold_GFF2_SLICEM_C_D) 0.056 1.454 SFP_GEN[0].rx_data_ngccm_reg[0][6] ------------------------------------------------------------------- required time -1.454 arrival time 1.504 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0] Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y29 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y50 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X52Y51 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y66 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y66 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y66 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y64 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y61 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y59 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[42]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y59 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[56]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y59 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[58]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y59 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[42]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y59 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[56]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y59 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[58]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y66 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y66 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y66 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y64 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y61 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y61 SFP_GEN[0].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_1 To Clock: gtwiz_userclk_rx_srcclk_out[0]_1 Setup : 0 Failing Endpoints, Worst Slack 3.498ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.041ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.498ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.511ns (logic 1.704ns (37.774%) route 2.807ns (62.226%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.746ns = ( 11.063 - 8.317 ) Source Clock Delay (SCD): 3.220ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.745ns (routing 1.142ns, distribution 1.603ns) Clock Net Delay (Destination): 2.348ns (routing 1.042ns, distribution 1.306ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.745 3.220 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.381 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.023 6.404 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X109Y221 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.648 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.208 6.856 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y223 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 7.100 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9/O net (fo=1, routed) 0.158 7.258 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9_n_0 SLICE_X109Y222 LUT6 (Prop_D6LUT_SLICEM_I5_O) 0.055 7.313 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9/O net (fo=2, routed) 0.418 7.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9_n_0 SLICE_X109Y221 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.348 11.063 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y221 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.256 11.319 clock uncertainty -0.035 11.284 SLICE_X109Y221 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.229 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.229 arrival time -7.731 ------------------------------------------------------------------- slack 3.498 Slack (MET) : 3.581ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.430ns (logic 1.704ns (38.465%) route 2.726ns (61.535%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.747ns = ( 11.064 - 8.317 ) Source Clock Delay (SCD): 3.220ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.745ns (routing 1.142ns, distribution 1.603ns) Clock Net Delay (Destination): 2.349ns (routing 1.042ns, distribution 1.307ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.745 3.220 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.381 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.023 6.404 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X109Y221 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.648 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.208 6.856 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y223 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 7.100 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9/O net (fo=1, routed) 0.158 7.258 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9_n_0 SLICE_X109Y222 LUT6 (Prop_D6LUT_SLICEM_I5_O) 0.055 7.313 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9/O net (fo=2, routed) 0.337 7.650 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9_n_0 SLICE_X109Y221 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.349 11.064 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y221 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.256 11.320 clock uncertainty -0.035 11.285 SLICE_X109Y221 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 11.231 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.231 arrival time -7.650 ------------------------------------------------------------------- slack 3.581 Slack (MET) : 3.723ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.289ns (logic 1.551ns (36.162%) route 2.738ns (63.838%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.749ns = ( 11.066 - 8.317 ) Source Clock Delay (SCD): 3.220ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.745ns (routing 1.142ns, distribution 1.603ns) Clock Net Delay (Destination): 2.351ns (routing 1.042ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.745 3.220 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.381 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.023 6.404 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X109Y221 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.648 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.196 6.844 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y223 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 6.990 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/O net (fo=3, routed) 0.519 7.509 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 SLICE_X109Y223 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.351 11.066 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y223 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.256 11.322 clock uncertainty -0.035 11.287 SLICE_X109Y223 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.232 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.232 arrival time -7.509 ------------------------------------------------------------------- slack 3.723 Slack (MET) : 3.723ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.289ns (logic 1.551ns (36.162%) route 2.738ns (63.838%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.749ns = ( 11.066 - 8.317 ) Source Clock Delay (SCD): 3.220ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.745ns (routing 1.142ns, distribution 1.603ns) Clock Net Delay (Destination): 2.351ns (routing 1.042ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.745 3.220 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.381 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.023 6.404 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X109Y221 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.648 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.196 6.844 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y223 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 6.990 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/O net (fo=3, routed) 0.519 7.509 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 SLICE_X109Y223 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.351 11.066 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y223 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.256 11.322 clock uncertainty -0.035 11.287 SLICE_X109Y223 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.232 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.232 arrival time -7.509 ------------------------------------------------------------------- slack 3.723 Slack (MET) : 3.727ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.286ns (logic 1.551ns (36.188%) route 2.735ns (63.812%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.749ns = ( 11.066 - 8.317 ) Source Clock Delay (SCD): 3.220ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.745ns (routing 1.142ns, distribution 1.603ns) Clock Net Delay (Destination): 2.351ns (routing 1.042ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.745 3.220 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.381 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.023 6.404 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X109Y221 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.648 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.196 6.844 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y223 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 6.990 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/O net (fo=3, routed) 0.516 7.506 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 SLICE_X109Y223 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.351 11.066 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y223 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.256 11.322 clock uncertainty -0.035 11.287 SLICE_X109Y223 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.233 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.233 arrival time -7.506 ------------------------------------------------------------------- slack 3.727 Slack (MET) : 3.737ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.271ns (logic 1.495ns (35.004%) route 2.776ns (64.996%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.748ns = ( 11.065 - 8.317 ) Source Clock Delay (SCD): 3.220ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.745ns (routing 1.142ns, distribution 1.603ns) Clock Net Delay (Destination): 2.350ns (routing 1.042ns, distribution 1.308ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.745 3.220 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.381 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.023 6.404 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X109Y221 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.648 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.178 6.826 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y222 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.090 6.916 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__10/O net (fo=7, routed) 0.575 7.491 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X109Y223 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.350 11.065 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y223 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.256 11.321 clock uncertainty -0.035 11.286 SLICE_X109Y223 FDRE (Setup_EFF2_SLICEM_C_CE) -0.058 11.228 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.228 arrival time -7.491 ------------------------------------------------------------------- slack 3.737 Slack (MET) : 3.743ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.268ns (logic 1.495ns (35.028%) route 2.773ns (64.972%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.748ns = ( 11.065 - 8.317 ) Source Clock Delay (SCD): 3.220ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.745ns (routing 1.142ns, distribution 1.603ns) Clock Net Delay (Destination): 2.350ns (routing 1.042ns, distribution 1.308ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.745 3.220 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.381 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.023 6.404 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X109Y221 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.648 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.178 6.826 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y222 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.090 6.916 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__10/O net (fo=7, routed) 0.572 7.488 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X109Y223 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.350 11.065 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y223 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.256 11.321 clock uncertainty -0.035 11.286 SLICE_X109Y223 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.231 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.231 arrival time -7.488 ------------------------------------------------------------------- slack 3.743 Slack (MET) : 3.797ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.208ns (logic 1.557ns (37.001%) route 2.651ns (62.999%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.742ns = ( 11.059 - 8.317 ) Source Clock Delay (SCD): 3.220ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.745ns (routing 1.142ns, distribution 1.603ns) Clock Net Delay (Destination): 2.344ns (routing 1.042ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.745 3.220 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.381 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.023 6.404 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X109Y221 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.648 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.203 6.851 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y223 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 7.003 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__10/O net (fo=5, routed) 0.425 7.428 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X109Y224 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.344 11.059 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y224 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.256 11.315 clock uncertainty -0.035 11.280 SLICE_X109Y224 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.225 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.225 arrival time -7.428 ------------------------------------------------------------------- slack 3.797 Slack (MET) : 3.797ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.208ns (logic 1.557ns (37.001%) route 2.651ns (62.999%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.742ns = ( 11.059 - 8.317 ) Source Clock Delay (SCD): 3.220ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.745ns (routing 1.142ns, distribution 1.603ns) Clock Net Delay (Destination): 2.344ns (routing 1.042ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.745 3.220 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.381 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.023 6.404 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X109Y221 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.648 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.203 6.851 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y223 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 7.003 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__10/O net (fo=5, routed) 0.425 7.428 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X109Y224 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.344 11.059 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y224 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.256 11.315 clock uncertainty -0.035 11.280 SLICE_X109Y224 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.225 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.225 arrival time -7.428 ------------------------------------------------------------------- slack 3.797 Slack (MET) : 3.801ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 4.205ns (logic 1.557ns (37.027%) route 2.648ns (62.973%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.742ns = ( 11.059 - 8.317 ) Source Clock Delay (SCD): 3.220ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.745ns (routing 1.142ns, distribution 1.603ns) Clock Net Delay (Destination): 2.344ns (routing 1.042ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.745 3.220 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.381 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.023 6.404 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X109Y221 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.648 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/O net (fo=5, routed) 0.203 6.851 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y223 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 7.003 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__10/O net (fo=5, routed) 0.422 7.425 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X109Y224 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.344 11.059 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y224 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.256 11.315 clock uncertainty -0.035 11.280 SLICE_X109Y224 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.226 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.226 arrival time -7.425 ------------------------------------------------------------------- slack 3.801 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].rx_data_ngccm_reg[10][0]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.168ns (logic 0.048ns (28.571%) route 0.120ns (71.429%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.111ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.993ns (routing 0.477ns, distribution 0.516ns) Clock Net Delay (Destination): 1.172ns (routing 0.537ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.111 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X105Y211 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y211 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/Q net (fo=1, routed) 0.120 1.279 rx_data[10][0] SLICE_X106Y211 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.337 RX_WORDCLK_O[10] SLICE_X106Y211 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][0]/C clock pessimism -0.155 1.182 SLICE_X106Y211 FDCE (Hold_EFF_SLICEM_C_D) 0.056 1.238 SFP_GEN[10].rx_data_ngccm_reg[10][0] ------------------------------------------------------------------- required time -1.238 arrival time 1.279 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.361ns Source Clock Delay (SCD): 1.124ns Clock Pessimism Removal (CPR): 0.193ns Clock Net Delay (Source): 1.006ns (routing 0.477ns, distribution 0.529ns) Clock Net Delay (Destination): 1.196ns (routing 0.537ns, distribution 0.659ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.006 1.124 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X104Y216 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X104Y216 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.173 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.034 1.207 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X104Y216 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.252 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__9/O net (fo=1, routed) 0.016 1.268 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] SLICE_X104Y216 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.196 1.361 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X104Y216 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.193 1.168 SLICE_X104Y216 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.224 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.224 arrival time 1.268 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[34]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.049ns (25.926%) route 0.140ns (74.074%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.998ns (routing 0.477ns, distribution 0.521ns) Clock Net Delay (Destination): 1.192ns (routing 0.537ns, distribution 0.655ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X103Y217 FDCE r SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[34]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y217 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.165 r SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[34]/Q net (fo=1, routed) 0.140 1.305 SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[5] SLICE_X102Y217 FDRE r SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.357 SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y217 FDRE r SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C clock pessimism -0.154 1.203 SLICE_X102Y217 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.259 SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34] ------------------------------------------------------------------- required time -1.259 arrival time 1.305 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_rx_rs_err[10].rx_rs_err_cnt_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.065ns (41.667%) route 0.091ns (58.333%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.360ns Source Clock Delay (SCD): 1.122ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 1.004ns (routing 0.477ns, distribution 0.527ns) Clock Net Delay (Destination): 1.195ns (routing 0.537ns, distribution 0.658ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.122 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/CLK SLICE_X110Y218 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X110Y218 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.171 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/Q net (fo=4, routed) 0.075 1.246 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg_0 SLICE_X110Y217 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.016 1.262 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/g_rx_rs_err[10].rx_rs_err_cnt[10]_i_1/O net (fo=1, routed) 0.016 1.278 g_gbt_bank[0].gbtbank_n_153 SLICE_X110Y217 FDRE r g_rx_rs_err[10].rx_rs_err_cnt_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.195 1.360 RX_WORDCLK_O[10] SLICE_X110Y217 FDRE r g_rx_rs_err[10].rx_rs_err_cnt_reg[10]/C clock pessimism -0.186 1.174 SLICE_X110Y217 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.230 g_rx_rs_err[10].rx_rs_err_cnt_reg[10] ------------------------------------------------------------------- required time -1.230 arrival time 1.278 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.193ns Clock Net Delay (Source): 1.005ns (routing 0.477ns, distribution 0.528ns) Clock Net Delay (Destination): 1.192ns (routing 0.537ns, distribution 0.655ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.123 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X103Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y214 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.172 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.035 1.207 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_29_in SLICE_X103Y214 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.045 1.252 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__9/O net (fo=1, routed) 0.016 1.268 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] SLICE_X103Y214 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.357 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X103Y214 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.193 1.164 SLICE_X103Y214 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.220 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.220 arrival time 1.268 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.363ns Source Clock Delay (SCD): 1.132ns Clock Pessimism Removal (CPR): 0.226ns Clock Net Delay (Source): 1.014ns (routing 0.477ns, distribution 0.537ns) Clock Net Delay (Destination): 1.198ns (routing 0.537ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.132 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X107Y221 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y221 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.181 r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/Q net (fo=9, routed) 0.033 1.214 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt_reg[10][7]_0[3] SLICE_X107Y221 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.229 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt[10][3]_i_1/O net (fo=1, routed) 0.012 1.241 g_gbt_bank[0].gbtbank/i_gbt_bank_n_358 SLICE_X107Y221 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.198 1.363 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X107Y221 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C clock pessimism -0.226 1.137 SLICE_X107Y221 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.193 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3] ------------------------------------------------------------------- required time -1.193 arrival time 1.241 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.049ns (30.625%) route 0.111ns (69.375%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.112ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.994ns (routing 0.477ns, distribution 0.517ns) Clock Net Delay (Destination): 1.188ns (routing 0.537ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.112 SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y215 FDCE r SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y215 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.161 r SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[17]/Q net (fo=5, routed) 0.111 1.272 SFP_GEN[10].ngCCM_gbt/gbt_rx_checker/Q[1] SLICE_X102Y214 FDRE r SFP_GEN[10].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 SFP_GEN[10].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y214 FDRE r SFP_GEN[10].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[1]/C clock pessimism -0.186 1.167 SLICE_X102Y214 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.223 SFP_GEN[10].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[1] ------------------------------------------------------------------- required time -1.223 arrival time 1.272 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.094ns (63.946%) route 0.053ns (36.054%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.196ns Clock Net Delay (Source): 1.003ns (routing 0.477ns, distribution 0.526ns) Clock Net Delay (Destination): 1.194ns (routing 0.537ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.121 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X108Y208 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y208 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.170 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Q net (fo=2, routed) 0.037 1.207 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_9_in SLICE_X108Y208 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.252 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__9/O net (fo=1, routed) 0.016 1.268 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] SLICE_X108Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X108Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.196 1.163 SLICE_X108Y208 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.219 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.219 arrival time 1.268 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].rx_data_ngccm_reg[10][68]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.162ns (logic 0.049ns (30.247%) route 0.113ns (69.753%)) Logic Levels: 0 Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.370ns Source Clock Delay (SCD): 1.128ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.010ns (routing 0.477ns, distribution 0.533ns) Clock Net Delay (Destination): 1.205ns (routing 0.537ns, distribution 0.668ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.128 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X110Y200 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y200 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.177 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.113 1.290 rx_data[10][68] SLICE_X110Y201 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][68]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.205 1.370 RX_WORDCLK_O[10] SLICE_X110Y201 FDCE r SFP_GEN[10].rx_data_ngccm_reg[10][68]/C clock pessimism -0.185 1.185 SLICE_X110Y201 FDCE (Hold_HFF_SLICEM_C_D) 0.056 1.241 SFP_GEN[10].rx_data_ngccm_reg[10][68] ------------------------------------------------------------------- required time -1.241 arrival time 1.290 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.095ns (64.626%) route 0.052ns (35.374%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.124ns Clock Pessimism Removal (CPR): 0.193ns Clock Net Delay (Source): 1.006ns (routing 0.477ns, distribution 0.529ns) Clock Net Delay (Destination): 1.193ns (routing 0.537ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.006 1.124 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X103Y215 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y215 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.173 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.036 1.209 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in SLICE_X103Y215 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.046 1.255 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__9/O net (fo=1, routed) 0.016 1.271 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[16] SLICE_X103Y215 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.193 1.358 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X103Y215 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.193 1.165 SLICE_X103Y215 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.221 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.221 arrival time 1.271 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_1 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y78 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X108Y223 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X107Y221 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X107Y221 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X107Y221 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X107Y221 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X107Y223 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X107Y223 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y223 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y223 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y223 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y220 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y220 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y220 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y223 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C High Pulse Width Slow FDPE/C n/a 0.275 4.159 3.884 SLICE_X111Y220 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y234 g_clock_rate_din[10].ngccm_status_cnt_reg[10][5]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y234 g_clock_rate_din[10].ngccm_status_cnt_reg[10][6]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y234 g_clock_rate_din[10].ngccm_status_cnt_reg[10][7]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y234 g_clock_rate_din[10].rx_test_comm_cnt_reg[10]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_10 To Clock: gtwiz_userclk_rx_srcclk_out[0]_10 Setup : 0 Failing Endpoints, Worst Slack 3.272ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.272ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.714ns (logic 1.628ns (34.535%) route 3.086ns (65.465%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.242ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.352ns = ( 10.669 - 8.317 ) Source Clock Delay (SCD): 2.814ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.339ns (routing 0.723ns, distribution 1.616ns) Clock Net Delay (Destination): 1.954ns (routing 0.655ns, distribution 1.299ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.339 2.814 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.900 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.409 6.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X118Y194 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 6.532 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.187 6.719 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X118Y195 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.146 6.865 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7/O net (fo=1, routed) 0.084 6.949 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7_n_0 SLICE_X118Y195 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 7.122 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7/O net (fo=2, routed) 0.406 7.528 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7_n_0 SLICE_X118Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.669 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X118Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.220 10.890 clock uncertainty -0.035 10.854 SLICE_X118Y194 FDCE (Setup_AFF_SLICEM_C_CE) -0.054 10.800 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.800 arrival time -7.528 ------------------------------------------------------------------- slack 3.272 Slack (MET) : 3.272ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.714ns (logic 1.628ns (34.535%) route 3.086ns (65.465%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.242ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.352ns = ( 10.669 - 8.317 ) Source Clock Delay (SCD): 2.814ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.339ns (routing 0.723ns, distribution 1.616ns) Clock Net Delay (Destination): 1.954ns (routing 0.655ns, distribution 1.299ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.339 2.814 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.900 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.409 6.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X118Y194 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 6.532 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.187 6.719 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X118Y195 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.146 6.865 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7/O net (fo=1, routed) 0.084 6.949 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7_n_0 SLICE_X118Y195 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 7.122 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7/O net (fo=2, routed) 0.406 7.528 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7_n_0 SLICE_X118Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.954 10.669 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X118Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.220 10.890 clock uncertainty -0.035 10.854 SLICE_X118Y194 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 10.800 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.800 arrival time -7.528 ------------------------------------------------------------------- slack 3.272 Slack (MET) : 3.490ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.510ns (logic 1.398ns (30.998%) route 3.112ns (69.002%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.370ns = ( 10.687 - 8.317 ) Source Clock Delay (SCD): 2.814ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.339ns (routing 0.723ns, distribution 1.616ns) Clock Net Delay (Destination): 1.972ns (routing 0.655ns, distribution 1.317ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.339 2.814 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.900 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.409 6.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X118Y194 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 6.532 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.185 6.717 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X118Y195 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.089 6.806 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/O net (fo=7, routed) 0.518 7.324 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X116Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.972 10.687 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.220 10.907 clock uncertainty -0.035 10.872 SLICE_X116Y195 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.814 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.814 arrival time -7.324 ------------------------------------------------------------------- slack 3.490 Slack (MET) : 3.497ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.506ns (logic 1.398ns (31.025%) route 3.108ns (68.975%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.370ns = ( 10.687 - 8.317 ) Source Clock Delay (SCD): 2.814ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.339ns (routing 0.723ns, distribution 1.616ns) Clock Net Delay (Destination): 1.972ns (routing 0.655ns, distribution 1.317ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.339 2.814 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.900 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.409 6.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X118Y194 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 6.532 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.185 6.717 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X118Y195 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.089 6.806 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/O net (fo=7, routed) 0.514 7.320 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X116Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.972 10.687 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.220 10.907 clock uncertainty -0.035 10.872 SLICE_X116Y195 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.817 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.817 arrival time -7.320 ------------------------------------------------------------------- slack 3.497 Slack (MET) : 3.614ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.374ns (logic 1.398ns (31.962%) route 2.976ns (68.038%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.358ns = ( 10.675 - 8.317 ) Source Clock Delay (SCD): 2.814ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.339ns (routing 0.723ns, distribution 1.616ns) Clock Net Delay (Destination): 1.960ns (routing 0.655ns, distribution 1.305ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.339 2.814 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.900 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.409 6.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X118Y194 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 6.532 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.185 6.717 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X118Y195 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.089 6.806 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/O net (fo=7, routed) 0.382 7.188 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X117Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.960 10.675 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.220 10.895 clock uncertainty -0.035 10.860 SLICE_X117Y195 FDRE (Setup_EFF2_SLICEL_C_CE) -0.058 10.802 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.802 arrival time -7.188 ------------------------------------------------------------------- slack 3.614 Slack (MET) : 3.621ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.370ns (logic 1.398ns (31.991%) route 2.972ns (68.009%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.358ns = ( 10.675 - 8.317 ) Source Clock Delay (SCD): 2.814ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.339ns (routing 0.723ns, distribution 1.616ns) Clock Net Delay (Destination): 1.960ns (routing 0.655ns, distribution 1.305ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.339 2.814 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.900 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.409 6.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X118Y194 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 6.532 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.185 6.717 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X118Y195 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.089 6.806 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/O net (fo=7, routed) 0.378 7.184 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X117Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.960 10.675 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.220 10.895 clock uncertainty -0.035 10.860 SLICE_X117Y195 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 10.805 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.805 arrival time -7.184 ------------------------------------------------------------------- slack 3.621 Slack (MET) : 3.621ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.370ns (logic 1.398ns (31.991%) route 2.972ns (68.009%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.358ns = ( 10.675 - 8.317 ) Source Clock Delay (SCD): 2.814ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.339ns (routing 0.723ns, distribution 1.616ns) Clock Net Delay (Destination): 1.960ns (routing 0.655ns, distribution 1.305ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.339 2.814 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.900 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.409 6.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X118Y194 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 6.532 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.185 6.717 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X118Y195 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.089 6.806 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/O net (fo=7, routed) 0.378 7.184 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X117Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.960 10.675 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.220 10.895 clock uncertainty -0.035 10.860 SLICE_X117Y195 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.805 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.805 arrival time -7.184 ------------------------------------------------------------------- slack 3.621 Slack (MET) : 3.643ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.344ns (logic 1.364ns (31.400%) route 2.980ns (68.600%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.237ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.357ns = ( 10.674 - 8.317 ) Source Clock Delay (SCD): 2.814ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.339ns (routing 0.723ns, distribution 1.616ns) Clock Net Delay (Destination): 1.959ns (routing 0.655ns, distribution 1.304ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.339 2.814 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.900 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.409 6.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X118Y194 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 6.532 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.191 6.723 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X118Y196 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.055 6.778 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__8/O net (fo=5, routed) 0.380 7.158 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 SLICE_X117Y196 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.959 10.674 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y196 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.220 10.894 clock uncertainty -0.035 10.859 SLICE_X117Y196 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.801 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 10.801 arrival time -7.158 ------------------------------------------------------------------- slack 3.643 Slack (MET) : 3.645ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.348ns (logic 1.398ns (32.153%) route 2.950ns (67.847%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.360ns = ( 10.677 - 8.317 ) Source Clock Delay (SCD): 2.814ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.339ns (routing 0.723ns, distribution 1.616ns) Clock Net Delay (Destination): 1.962ns (routing 0.655ns, distribution 1.307ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.339 2.814 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.900 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.409 6.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X118Y194 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 6.532 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.185 6.717 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X118Y195 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.089 6.806 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/O net (fo=7, routed) 0.356 7.162 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X117Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.962 10.677 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.220 10.897 clock uncertainty -0.035 10.862 SLICE_X117Y195 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 10.807 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.807 arrival time -7.162 ------------------------------------------------------------------- slack 3.645 Slack (MET) : 3.650ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 4.344ns (logic 1.398ns (32.182%) route 2.946ns (67.818%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.360ns = ( 10.677 - 8.317 ) Source Clock Delay (SCD): 2.814ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.339ns (routing 0.723ns, distribution 1.616ns) Clock Net Delay (Destination): 1.962ns (routing 0.655ns, distribution 1.307ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.339 2.814 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.900 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.409 6.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X118Y194 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 6.532 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/O net (fo=5, routed) 0.185 6.717 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X118Y195 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.089 6.806 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/O net (fo=7, routed) 0.352 7.158 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X117Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.962 10.677 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X117Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.220 10.897 clock uncertainty -0.035 10.862 SLICE_X117Y195 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 10.808 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.808 arrival time -7.158 ------------------------------------------------------------------- slack 3.650 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.034ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[23]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[23]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.168ns (logic 0.048ns (28.571%) route 0.120ns (71.429%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.179ns Source Clock Delay (SCD): 0.971ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.853ns (routing 0.315ns, distribution 0.538ns) Clock Net Delay (Destination): 1.014ns (routing 0.355ns, distribution 0.659ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.971 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X117Y187 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[23]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y187 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.019 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[23]/Q net (fo=1, routed) 0.120 1.139 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0[23] SLICE_X118Y187 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.179 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X118Y187 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[23]/C clock pessimism -0.130 1.049 SLICE_X118Y187 FDCE (Hold_HFF2_SLICEM_C_D) 0.056 1.105 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[23] ------------------------------------------------------------------- required time -1.105 arrival time 1.139 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.094ns (50.811%) route 0.091ns (49.189%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.178ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.837ns (routing 0.315ns, distribution 0.522ns) Clock Net Delay (Destination): 1.013ns (routing 0.355ns, distribution 0.658ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X112Y183 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y183 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.004 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.075 1.079 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in SLICE_X111Y183 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.124 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__7/O net (fo=1, routed) 0.016 1.140 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[10] SLICE_X111Y183 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.013 1.178 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X111Y183 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.130 1.048 SLICE_X111Y183 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.104 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.104 arrival time 1.140 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.104ns (54.737%) route 0.086ns (45.263%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.176ns Source Clock Delay (SCD): 0.949ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.831ns (routing 0.315ns, distribution 0.516ns) Clock Net Delay (Destination): 1.011ns (routing 0.355ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.831 0.949 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X112Y191 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y191 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.998 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.075 1.073 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister[1] SLICE_X111Y191 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.055 1.128 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__7/O net (fo=1, routed) 0.011 1.139 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[18] SLICE_X111Y191 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.011 1.176 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X111Y191 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.130 1.046 SLICE_X111Y191 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.102 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -1.102 arrival time 1.139 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.094ns (50.538%) route 0.092ns (49.462%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.175ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.837ns (routing 0.315ns, distribution 0.522ns) Clock Net Delay (Destination): 1.010ns (routing 0.355ns, distribution 0.655ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X112Y183 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y183 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.004 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.076 1.080 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in SLICE_X111Y183 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.045 1.125 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__7/O net (fo=1, routed) 0.016 1.141 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] SLICE_X111Y183 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.175 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X111Y183 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.130 1.045 SLICE_X111Y183 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.101 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.101 arrival time 1.141 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.079ns (44.886%) route 0.097ns (55.114%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.165ns Source Clock Delay (SCD): 0.960ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.842ns (routing 0.315ns, distribution 0.527ns) Clock Net Delay (Destination): 1.000ns (routing 0.355ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.842 0.960 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y196 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y196 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.008 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[0]/Q net (fo=7, routed) 0.081 1.089 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/timer[0] SLICE_X115Y196 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.031 1.120 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[1]_i_1__8/O net (fo=1, routed) 0.016 1.136 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[1]_i_1__8_n_0 SLICE_X115Y196 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.165 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X115Y196 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[1]/C clock pessimism -0.130 1.035 SLICE_X115Y196 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[1] ------------------------------------------------------------------- required time -1.091 arrival time 1.136 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.175ns Source Clock Delay (SCD): 0.960ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.842ns (routing 0.315ns, distribution 0.527ns) Clock Net Delay (Destination): 1.010ns (routing 0.355ns, distribution 0.655ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.842 0.960 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X111Y192 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y192 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.009 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.034 1.043 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X111Y192 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.088 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__7/O net (fo=1, routed) 0.016 1.104 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] SLICE_X111Y192 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.175 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X111Y192 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.173 1.002 SLICE_X111Y192 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.058 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.058 arrival time 1.104 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[8].rx_data_ngccm_reg[8][25]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[25]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.048ns (25.263%) route 0.142ns (74.737%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.172ns Source Clock Delay (SCD): 0.954ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.836ns (routing 0.315ns, distribution 0.521ns) Clock Net Delay (Destination): 1.007ns (routing 0.355ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.836 0.954 RX_WORDCLK_O[8] SLICE_X110Y193 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][25]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y193 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.002 r SFP_GEN[8].rx_data_ngccm_reg[8][25]/Q net (fo=1, routed) 0.142 1.144 SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[83]_0[17] SLICE_X108Y193 FDCE r SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[25]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.172 SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y193 FDCE r SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[25]/C clock pessimism -0.130 1.042 SLICE_X108Y193 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.098 SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[25] ------------------------------------------------------------------- required time -1.098 arrival time 1.144 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[8].rx_data_ngccm_reg[8][27]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[27]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.048ns (25.263%) route 0.142ns (74.737%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.172ns Source Clock Delay (SCD): 0.954ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.836ns (routing 0.315ns, distribution 0.521ns) Clock Net Delay (Destination): 1.007ns (routing 0.355ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.836 0.954 RX_WORDCLK_O[8] SLICE_X110Y193 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][27]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y193 FDCE (Prop_GFF2_SLICEM_C_Q) 0.048 1.002 r SFP_GEN[8].rx_data_ngccm_reg[8][27]/Q net (fo=1, routed) 0.142 1.144 SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[83]_0[19] SLICE_X108Y193 FDCE r SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[27]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.172 SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y193 FDCE r SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[27]/C clock pessimism -0.130 1.042 SLICE_X108Y193 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.098 SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[27] ------------------------------------------------------------------- required time -1.098 arrival time 1.144 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].rx_data_ngccm_reg[8][52]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.049ns (29.341%) route 0.118ns (70.659%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.965ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.847ns (routing 0.315ns, distribution 0.532ns) Clock Net Delay (Destination): 0.995ns (routing 0.355ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.847 0.965 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X111Y183 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y183 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.014 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.118 1.132 rx_data[8][52] SLICE_X112Y183 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][52]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.995 1.160 RX_WORDCLK_O[8] SLICE_X112Y183 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][52]/C clock pessimism -0.130 1.030 SLICE_X112Y183 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.086 SFP_GEN[8].rx_data_ngccm_reg[8][52] ------------------------------------------------------------------- required time -1.086 arrival time 1.132 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].rx_data_ngccm_reg[8][6]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_10 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.048ns (25.131%) route 0.143ns (74.869%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.832ns (routing 0.315ns, distribution 0.517ns) Clock Net Delay (Destination): 1.004ns (routing 0.355ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.832 0.950 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X112Y187 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y187 FDRE (Prop_HFF2_SLICEM_C_Q) 0.048 0.998 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.143 1.141 rx_data[8][6] SLICE_X111Y187 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.169 RX_WORDCLK_O[8] SLICE_X111Y187 FDCE r SFP_GEN[8].rx_data_ngccm_reg[8][6]/C clock pessimism -0.130 1.039 SLICE_X111Y187 FDCE (Hold_BFF_SLICEL_C_D) 0.056 1.095 SFP_GEN[8].rx_data_ngccm_reg[8][6] ------------------------------------------------------------------- required time -1.095 arrival time 1.141 ------------------------------------------------------------------- slack 0.046 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_10 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y75 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y235 g_clock_rate_din[8].ngccm_status_cnt_reg[8][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y235 g_clock_rate_din[8].ngccm_status_cnt_reg[8][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y235 g_clock_rate_din[8].ngccm_status_cnt_reg[8][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][3]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][4]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y236 g_clock_rate_din[8].ngccm_status_cnt_reg[8][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X108Y195 g_clock_rate_din[8].rx_frameclk_div2_reg[8]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X109Y198 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_11 To Clock: gtwiz_userclk_rx_srcclk_out[0]_11 Setup : 0 Failing Endpoints, Worst Slack 3.153ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.153ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 4.841ns (logic 1.741ns (35.964%) route 3.100ns (64.036%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.318ns = ( 10.635 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.728ns, distribution 1.569ns) Clock Net Delay (Destination): 1.920ns (routing 0.660ns, distribution 1.260ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.933 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.144 6.077 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y205 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.219 6.296 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/O net (fo=5, routed) 0.286 6.582 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X99Y208 LUT4 (Prop_B5LUT_SLICEL_I2_O) 0.272 6.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__8/O net (fo=1, routed) 0.322 7.176 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__8_n_0 SLICE_X99Y207 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.089 7.265 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__8/O net (fo=2, routed) 0.348 7.613 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__8_n_0 SLICE_X99Y205 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.920 10.635 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y205 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.221 10.856 clock uncertainty -0.035 10.821 SLICE_X99Y205 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 10.766 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.766 arrival time -7.613 ------------------------------------------------------------------- slack 3.153 Slack (MET) : 3.167ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 4.830ns (logic 1.741ns (36.046%) route 3.089ns (63.954%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.320ns = ( 10.637 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.728ns, distribution 1.569ns) Clock Net Delay (Destination): 1.922ns (routing 0.660ns, distribution 1.262ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.933 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.144 6.077 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y205 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.219 6.296 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/O net (fo=5, routed) 0.286 6.582 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X99Y208 LUT4 (Prop_B5LUT_SLICEL_I2_O) 0.272 6.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__8/O net (fo=1, routed) 0.322 7.176 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__8_n_0 SLICE_X99Y207 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.089 7.265 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__8/O net (fo=2, routed) 0.337 7.602 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__8_n_0 SLICE_X99Y205 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.922 10.637 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y205 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.221 10.858 clock uncertainty -0.035 10.823 SLICE_X99Y205 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 10.769 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.769 arrival time -7.602 ------------------------------------------------------------------- slack 3.167 Slack (MET) : 3.311ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 4.663ns (logic 1.546ns (33.155%) route 3.117ns (66.845%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.250ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.301ns = ( 10.618 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.728ns, distribution 1.569ns) Clock Net Delay (Destination): 1.903ns (routing 0.660ns, distribution 1.243ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.933 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.144 6.077 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y205 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.219 6.296 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/O net (fo=5, routed) 0.261 6.557 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X99Y207 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.166 6.723 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/O net (fo=7, routed) 0.712 7.435 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X100Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.903 10.618 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X100Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.221 10.840 clock uncertainty -0.035 10.804 SLICE_X100Y208 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.746 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.746 arrival time -7.435 ------------------------------------------------------------------- slack 3.311 Slack (MET) : 3.311ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 4.663ns (logic 1.546ns (33.155%) route 3.117ns (66.845%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.250ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.301ns = ( 10.618 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.728ns, distribution 1.569ns) Clock Net Delay (Destination): 1.903ns (routing 0.660ns, distribution 1.243ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.933 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.144 6.077 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y205 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.219 6.296 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/O net (fo=5, routed) 0.261 6.557 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X99Y207 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.166 6.723 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/O net (fo=7, routed) 0.712 7.435 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X100Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.903 10.618 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X100Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.221 10.840 clock uncertainty -0.035 10.804 SLICE_X100Y208 FDRE (Setup_GFF2_SLICEM_C_CE) -0.058 10.746 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.746 arrival time -7.435 ------------------------------------------------------------------- slack 3.311 Slack (MET) : 3.317ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 4.660ns (logic 1.546ns (33.176%) route 3.114ns (66.824%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.250ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.301ns = ( 10.618 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.728ns, distribution 1.569ns) Clock Net Delay (Destination): 1.903ns (routing 0.660ns, distribution 1.243ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.933 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.144 6.077 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y205 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.219 6.296 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/O net (fo=5, routed) 0.261 6.557 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X99Y207 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.166 6.723 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/O net (fo=7, routed) 0.709 7.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X100Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.903 10.618 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X100Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.221 10.840 clock uncertainty -0.035 10.804 SLICE_X100Y208 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.749 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.749 arrival time -7.432 ------------------------------------------------------------------- slack 3.317 Slack (MET) : 3.317ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 4.660ns (logic 1.546ns (33.176%) route 3.114ns (66.824%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.250ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.301ns = ( 10.618 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.728ns, distribution 1.569ns) Clock Net Delay (Destination): 1.903ns (routing 0.660ns, distribution 1.243ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.933 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.144 6.077 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y205 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.219 6.296 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/O net (fo=5, routed) 0.261 6.557 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X99Y207 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.166 6.723 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/O net (fo=7, routed) 0.709 7.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X100Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.903 10.618 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X100Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.221 10.840 clock uncertainty -0.035 10.804 SLICE_X100Y208 FDRE (Setup_FFF_SLICEM_C_CE) -0.055 10.749 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.749 arrival time -7.432 ------------------------------------------------------------------- slack 3.317 Slack (MET) : 3.317ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 4.660ns (logic 1.546ns (33.176%) route 3.114ns (66.824%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.250ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.301ns = ( 10.618 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.728ns, distribution 1.569ns) Clock Net Delay (Destination): 1.903ns (routing 0.660ns, distribution 1.243ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.933 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.144 6.077 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y205 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.219 6.296 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/O net (fo=5, routed) 0.261 6.557 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X99Y207 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.166 6.723 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/O net (fo=7, routed) 0.709 7.432 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X100Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.903 10.618 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X100Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.221 10.840 clock uncertainty -0.035 10.804 SLICE_X100Y208 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 10.749 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.749 arrival time -7.432 ------------------------------------------------------------------- slack 3.317 Slack (MET) : 3.436ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 4.555ns (logic 1.546ns (33.941%) route 3.009ns (66.059%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.315ns = ( 10.632 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.728ns, distribution 1.569ns) Clock Net Delay (Destination): 1.917ns (routing 0.660ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.933 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.144 6.077 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y205 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.219 6.296 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/O net (fo=5, routed) 0.261 6.557 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X99Y207 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.166 6.723 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/O net (fo=7, routed) 0.604 7.327 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X99Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.917 10.632 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.221 10.854 clock uncertainty -0.035 10.818 SLICE_X99Y208 FDRE (Setup_BFF2_SLICEL_C_CE) -0.055 10.763 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.763 arrival time -7.327 ------------------------------------------------------------------- slack 3.436 Slack (MET) : 3.436ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 4.555ns (logic 1.546ns (33.941%) route 3.009ns (66.059%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.315ns = ( 10.632 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.728ns, distribution 1.569ns) Clock Net Delay (Destination): 1.917ns (routing 0.660ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.933 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.144 6.077 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y205 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.219 6.296 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/O net (fo=5, routed) 0.261 6.557 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X99Y207 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.166 6.723 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__9/O net (fo=7, routed) 0.604 7.327 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X99Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.917 10.632 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y208 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.221 10.854 clock uncertainty -0.035 10.818 SLICE_X99Y208 FDRE (Setup_AFF2_SLICEL_C_CE) -0.055 10.763 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.763 arrival time -7.327 ------------------------------------------------------------------- slack 3.436 Slack (MET) : 3.627ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 4.355ns (logic 1.526ns (35.040%) route 2.829ns (64.960%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.245ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.772ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.297ns (routing 0.728ns, distribution 1.569ns) Clock Net Delay (Destination): 1.908ns (routing 0.660ns, distribution 1.248ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.297 2.772 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.933 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.144 6.077 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y205 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.219 6.296 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__8/O net (fo=5, routed) 0.271 6.567 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X99Y208 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 6.713 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__9/O net (fo=5, routed) 0.414 7.127 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecCorrectHeaders0 SLICE_X99Y209 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.908 10.623 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X99Y209 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.221 10.845 clock uncertainty -0.035 10.809 SLICE_X99Y209 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.754 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 10.754 arrival time -7.127 ------------------------------------------------------------------- slack 3.627 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].rx_data_ngccm_reg[9][82]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.048ns (30.189%) route 0.111ns (69.811%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.146ns Source Clock Delay (SCD): 0.946ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.828ns (routing 0.314ns, distribution 0.514ns) Clock Net Delay (Destination): 0.981ns (routing 0.355ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.946 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X97Y196 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y196 FDRE (Prop_GFF_SLICEM_C_Q) 0.048 0.994 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/Q net (fo=1, routed) 0.111 1.105 rx_data[9][82] SLICE_X96Y196 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][82]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.981 1.146 RX_WORDCLK_O[9] SLICE_X96Y196 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][82]/C clock pessimism -0.132 1.014 SLICE_X96Y196 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.070 SFP_GEN[9].rx_data_ngccm_reg[9][82] ------------------------------------------------------------------- required time -1.070 arrival time 1.105 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.157ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.816ns (routing 0.314ns, distribution 0.502ns) Clock Net Delay (Destination): 0.992ns (routing 0.355ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.816 0.934 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X97Y205 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y205 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 0.983 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.035 1.018 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in SLICE_X97Y204 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.054 1.072 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__8/O net (fo=1, routed) 0.016 1.088 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[12] SLICE_X97Y204 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.992 1.157 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X97Y204 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.163 0.994 SLICE_X97Y204 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.050 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.050 arrival time 1.088 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.113ns (70.625%) route 0.047ns (29.375%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.157ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.816ns (routing 0.314ns, distribution 0.502ns) Clock Net Delay (Destination): 0.992ns (routing 0.355ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.816 0.934 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X97Y205 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y205 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 0.983 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.035 1.018 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in SLICE_X97Y204 LUT3 (Prop_D5LUT_SLICEM_I0_O) 0.064 1.082 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__8/O net (fo=1, routed) 0.012 1.094 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[14] SLICE_X97Y204 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.992 1.157 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X97Y204 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.163 0.994 SLICE_X97Y204 FDRE (Hold_DFF2_SLICEM_C_D) 0.056 1.050 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -1.050 arrival time 1.094 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.093ns (62.838%) route 0.055ns (37.162%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.145ns Source Clock Delay (SCD): 0.930ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.812ns (routing 0.314ns, distribution 0.498ns) Clock Net Delay (Destination): 0.980ns (routing 0.355ns, distribution 0.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.812 0.930 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X98Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y211 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.978 r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/Q net (fo=10, routed) 0.039 1.017 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].cnt_reg[9][7]_0[0] SLICE_X98Y211 LUT6 (Prop_D6LUT_SLICEL_I1_O) 0.045 1.062 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].cnt[9][1]_i_1/O net (fo=1, routed) 0.016 1.078 g_gbt_bank[0].gbtbank/i_gbt_bank_n_345 SLICE_X98Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.145 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X98Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C clock pessimism -0.171 0.974 SLICE_X98Y211 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.030 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1] ------------------------------------------------------------------- required time -1.030 arrival time 1.078 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].rx_data_ngccm_reg[9][46]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.143ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.822ns (routing 0.314ns, distribution 0.508ns) Clock Net Delay (Destination): 0.978ns (routing 0.355ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X99Y195 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y195 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 0.989 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.095 1.084 rx_data[9][46] SLICE_X99Y196 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][46]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.143 RX_WORDCLK_O[9] SLICE_X99Y196 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][46]/C clock pessimism -0.163 0.980 SLICE_X99Y196 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.035 SFP_GEN[9].rx_data_ngccm_reg[9][46] ------------------------------------------------------------------- required time -1.035 arrival time 1.084 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].rx_data_ngccm_reg[9][54]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.049ns (32.886%) route 0.100ns (67.114%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.145ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.822ns (routing 0.314ns, distribution 0.508ns) Clock Net Delay (Destination): 0.980ns (routing 0.355ns, distribution 0.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X100Y192 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X100Y192 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 0.989 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/Q net (fo=1, routed) 0.100 1.089 rx_data[9][54] SLICE_X100Y191 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][54]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.145 RX_WORDCLK_O[9] SLICE_X100Y191 FDCE r SFP_GEN[9].rx_data_ngccm_reg[9][54]/C clock pessimism -0.163 0.982 SLICE_X100Y191 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.037 SFP_GEN[9].rx_data_ngccm_reg[9][54] ------------------------------------------------------------------- required time -1.037 arrival time 1.089 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.103ns (67.320%) route 0.050ns (32.680%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.145ns Source Clock Delay (SCD): 0.930ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.812ns (routing 0.314ns, distribution 0.498ns) Clock Net Delay (Destination): 0.980ns (routing 0.355ns, distribution 0.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.812 0.930 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X98Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y211 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.978 r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/Q net (fo=10, routed) 0.039 1.017 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].cnt_reg[9][7]_0[0] SLICE_X98Y211 LUT5 (Prop_C5LUT_SLICEL_I3_O) 0.055 1.072 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].cnt[9][2]_i_1/O net (fo=1, routed) 0.011 1.083 g_gbt_bank[0].gbtbank/i_gbt_bank_n_344 SLICE_X98Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.145 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X98Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/C clock pessimism -0.171 0.974 SLICE_X98Y211 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.030 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2] ------------------------------------------------------------------- required time -1.030 arrival time 1.083 ------------------------------------------------------------------- slack 0.053 Slack (MET) : 0.053ns (arrival time - required time) Source: SFP_GEN[9].ngccm_status_reg_reg[9][24]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngccm_status_reg_reg[9][24]/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.113ns (logic 0.064ns (56.637%) route 0.049ns (43.363%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.004ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.230ns Clock Net Delay (Source): 1.002ns (routing 0.314ns, distribution 0.688ns) Clock Net Delay (Destination): 1.189ns (routing 0.355ns, distribution 0.834ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.120 RX_WORDCLK_O[9] SLICE_X78Y238 FDPE r SFP_GEN[9].ngccm_status_reg_reg[9][24]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y238 FDPE (Prop_FFF_SLICEL_C_Q) 0.049 1.169 r SFP_GEN[9].ngccm_status_reg_reg[9][24]/Q net (fo=2, routed) 0.037 1.206 SFP_GEN[9].ngCCM_gbt/SFP_GEN[9].ngccm_status_reg_reg[9][24]_0[8] SLICE_X78Y238 LUT2 (Prop_F6LUT_SLICEL_I0_O) 0.015 1.221 r SFP_GEN[9].ngCCM_gbt/SFP_GEN[9].ngccm_status_reg[9][24]_i_2/O net (fo=1, routed) 0.012 1.233 SFP_GEN[9].ngCCM_gbt_n_393 SLICE_X78Y238 FDPE r SFP_GEN[9].ngccm_status_reg_reg[9][24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.354 RX_WORDCLK_O[9] SLICE_X78Y238 FDPE r SFP_GEN[9].ngccm_status_reg_reg[9][24]/C clock pessimism -0.230 1.124 SLICE_X78Y238 FDPE (Hold_FFF_SLICEL_C_D) 0.056 1.180 SFP_GEN[9].ngccm_status_reg_reg[9][24] ------------------------------------------------------------------- required time -1.180 arrival time 1.233 ------------------------------------------------------------------- slack 0.053 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCmd_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.113ns (logic 0.063ns (55.752%) route 0.050ns (44.248%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.004ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.129ns Source Clock Delay (SCD): 0.925ns Clock Pessimism Removal (CPR): 0.200ns Clock Net Delay (Source): 0.807ns (routing 0.314ns, distribution 0.493ns) Clock Net Delay (Destination): 0.964ns (routing 0.355ns, distribution 0.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.807 0.925 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X100Y207 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCmd_reg/C ------------------------------------------------------------------- ------------------- SLICE_X100Y207 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 0.973 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCmd_reg/Q net (fo=10, routed) 0.036 1.009 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCmd_to_bitSlipCtrller_9 SLICE_X100Y207 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.015 1.024 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_inv_i_1__9/O net (fo=1, routed) 0.014 1.038 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr3_out SLICE_X100Y207 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.964 1.129 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X100Y207 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv/C clock pessimism -0.200 0.929 SLICE_X100Y207 FDPE (Hold_GFF_SLICEM_C_D) 0.056 0.985 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv ------------------------------------------------------------------- required time -0.985 arrival time 1.038 ------------------------------------------------------------------- slack 0.053 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_11 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.094ns (50.538%) route 0.092ns (49.462%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.147ns Source Clock Delay (SCD): 0.938ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.820ns (routing 0.314ns, distribution 0.506ns) Clock Net Delay (Destination): 0.982ns (routing 0.355ns, distribution 0.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.820 0.938 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X100Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X100Y194 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 0.987 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.076 1.063 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_35_in SLICE_X99Y194 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.108 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__8/O net (fo=1, routed) 0.016 1.124 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[16] SLICE_X99Y194 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.147 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X99Y194 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.132 1.015 SLICE_X99Y194 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.071 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.071 arrival time 1.124 ------------------------------------------------------------------- slack 0.053 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_11 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y77 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y239 g_clock_rate_din[9].ngccm_status_cnt_reg[9][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y239 g_clock_rate_din[9].ngccm_status_cnt_reg[9][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y238 g_clock_rate_din[9].ngccm_status_cnt_reg[9][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y238 g_clock_rate_din[9].ngccm_status_cnt_reg[9][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y238 g_clock_rate_din[9].ngccm_status_cnt_reg[9][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y238 g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y238 g_clock_rate_din[9].ngccm_status_cnt_reg[9][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y238 g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X95Y205 g_clock_rate_din[9].rx_frameclk_div2_reg[9]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X97Y211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X98Y211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X97Y211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X97Y211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X97Y211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X98Y211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X98Y211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X98Y211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X98Y211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X98Y211 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_2 To Clock: gtwiz_userclk_rx_srcclk_out[0]_2 Setup : 0 Failing Endpoints, Worst Slack 4.186ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.186ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].rx_data_ngccm_reg[11][41]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 3.764ns (logic 0.383ns (10.175%) route 3.381ns (89.825%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.274ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.231ns = ( 10.548 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.833ns (routing 0.565ns, distribution 1.268ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.679 4.533 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X106Y234 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 4.777 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/O net (fo=76, routed) 1.702 6.479 rx_data_ngccm[11] SLICE_X113Y230 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][41]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.833 10.548 RX_WORDCLK_O[11] SLICE_X113Y230 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][41]/C clock pessimism 0.210 10.758 clock uncertainty -0.035 10.723 SLICE_X113Y230 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 10.665 SFP_GEN[11].rx_data_ngccm_reg[11][41] ------------------------------------------------------------------- required time 10.665 arrival time -6.479 ------------------------------------------------------------------- slack 4.186 Slack (MET) : 4.192ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].rx_data_ngccm_reg[11][40]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 3.761ns (logic 0.383ns (10.183%) route 3.378ns (89.817%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.274ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.231ns = ( 10.548 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.833ns (routing 0.565ns, distribution 1.268ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.679 4.533 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X106Y234 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 4.777 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/O net (fo=76, routed) 1.699 6.476 rx_data_ngccm[11] SLICE_X113Y230 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][40]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.833 10.548 RX_WORDCLK_O[11] SLICE_X113Y230 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][40]/C clock pessimism 0.210 10.758 clock uncertainty -0.035 10.723 SLICE_X113Y230 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 10.668 SFP_GEN[11].rx_data_ngccm_reg[11][40] ------------------------------------------------------------------- required time 10.668 arrival time -6.476 ------------------------------------------------------------------- slack 4.192 Slack (MET) : 4.192ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].rx_data_ngccm_reg[11][66]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 3.761ns (logic 0.383ns (10.183%) route 3.378ns (89.817%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.274ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.231ns = ( 10.548 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.833ns (routing 0.565ns, distribution 1.268ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.679 4.533 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X106Y234 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 4.777 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/O net (fo=76, routed) 1.699 6.476 rx_data_ngccm[11] SLICE_X113Y230 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][66]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.833 10.548 RX_WORDCLK_O[11] SLICE_X113Y230 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][66]/C clock pessimism 0.210 10.758 clock uncertainty -0.035 10.723 SLICE_X113Y230 FDCE (Setup_FFF_SLICEM_C_CE) -0.055 10.668 SFP_GEN[11].rx_data_ngccm_reg[11][66] ------------------------------------------------------------------- required time 10.668 arrival time -6.476 ------------------------------------------------------------------- slack 4.192 Slack (MET) : 4.264ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 3.781ns (logic 1.423ns (37.636%) route 2.358ns (62.364%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.182ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.228ns = ( 10.545 - 8.317 ) Source Clock Delay (SCD): 2.620ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.145ns (routing 0.624ns, distribution 1.521ns) Clock Net Delay (Destination): 1.830ns (routing 0.565ns, distribution 1.265ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.145 2.620 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.706 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.362 5.068 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X119Y236 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.239 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.414 5.653 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X117Y237 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.166 5.819 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/O net (fo=7, routed) 0.582 6.401 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X118Y235 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.830 10.545 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X118Y235 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.210 10.756 clock uncertainty -0.035 10.720 SLICE_X118Y235 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 10.665 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.665 arrival time -6.401 ------------------------------------------------------------------- slack 4.264 Slack (MET) : 4.286ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 3.754ns (logic 1.642ns (43.740%) route 2.112ns (56.260%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.222ns = ( 10.539 - 8.317 ) Source Clock Delay (SCD): 2.620ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.145ns (routing 0.624ns, distribution 1.521ns) Clock Net Delay (Destination): 1.824ns (routing 0.565ns, distribution 1.259ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.145 2.620 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.706 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.362 5.068 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X119Y236 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.239 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.315 5.554 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X117Y236 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 5.792 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10/O net (fo=1, routed) 0.159 5.951 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10_n_0 SLICE_X117Y237 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 6.098 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10/O net (fo=2, routed) 0.276 6.374 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10_n_0 SLICE_X118Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.824 10.539 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X118Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.210 10.750 clock uncertainty -0.035 10.714 SLICE_X118Y237 FDCE (Setup_AFF_SLICEM_C_CE) -0.054 10.660 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.660 arrival time -6.374 ------------------------------------------------------------------- slack 4.286 Slack (MET) : 4.286ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 3.754ns (logic 1.642ns (43.740%) route 2.112ns (56.260%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.222ns = ( 10.539 - 8.317 ) Source Clock Delay (SCD): 2.620ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.145ns (routing 0.624ns, distribution 1.521ns) Clock Net Delay (Destination): 1.824ns (routing 0.565ns, distribution 1.259ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.145 2.620 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.706 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.362 5.068 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X119Y236 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.239 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.315 5.554 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X117Y236 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 5.792 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10/O net (fo=1, routed) 0.159 5.951 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10_n_0 SLICE_X117Y237 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 6.098 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10/O net (fo=2, routed) 0.276 6.374 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10_n_0 SLICE_X118Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.824 10.539 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X118Y237 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.210 10.750 clock uncertainty -0.035 10.714 SLICE_X118Y237 FDCE (Setup_CFF_SLICEM_C_CE) -0.054 10.660 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.660 arrival time -6.374 ------------------------------------------------------------------- slack 4.286 Slack (MET) : 4.318ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 3.729ns (logic 1.423ns (38.160%) route 2.306ns (61.840%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.180ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.230ns = ( 10.547 - 8.317 ) Source Clock Delay (SCD): 2.620ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.145ns (routing 0.624ns, distribution 1.521ns) Clock Net Delay (Destination): 1.832ns (routing 0.565ns, distribution 1.267ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.145 2.620 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.706 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.362 5.068 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X119Y236 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.239 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.414 5.653 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X117Y237 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.166 5.819 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/O net (fo=7, routed) 0.530 6.349 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X118Y235 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.832 10.547 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X118Y235 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.210 10.758 clock uncertainty -0.035 10.722 SLICE_X118Y235 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 10.667 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.667 arrival time -6.349 ------------------------------------------------------------------- slack 4.318 Slack (MET) : 4.322ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 3.726ns (logic 1.423ns (38.191%) route 2.303ns (61.809%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.180ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.230ns = ( 10.547 - 8.317 ) Source Clock Delay (SCD): 2.620ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.145ns (routing 0.624ns, distribution 1.521ns) Clock Net Delay (Destination): 1.832ns (routing 0.565ns, distribution 1.267ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.145 2.620 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.706 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.362 5.068 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X119Y236 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 5.239 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/O net (fo=5, routed) 0.414 5.653 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X117Y237 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.166 5.819 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/O net (fo=7, routed) 0.527 6.346 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X118Y235 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.832 10.547 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X118Y235 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.210 10.758 clock uncertainty -0.035 10.722 SLICE_X118Y235 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 10.668 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.668 arrival time -6.346 ------------------------------------------------------------------- slack 4.322 Slack (MET) : 4.349ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].rx_data_ngccm_reg[11][56]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 3.616ns (logic 0.383ns (10.592%) route 3.233ns (89.408%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.259ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.246ns = ( 10.563 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.848ns (routing 0.565ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.679 4.533 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X106Y234 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 4.777 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/O net (fo=76, routed) 1.554 6.331 rx_data_ngccm[11] SLICE_X113Y228 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][56]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.848 10.563 RX_WORDCLK_O[11] SLICE_X113Y228 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][56]/C clock pessimism 0.210 10.773 clock uncertainty -0.035 10.738 SLICE_X113Y228 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 10.680 SFP_GEN[11].rx_data_ngccm_reg[11][56] ------------------------------------------------------------------- required time 10.680 arrival time -6.331 ------------------------------------------------------------------- slack 4.349 Slack (MET) : 4.349ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].rx_data_ngccm_reg[11][60]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 3.616ns (logic 0.383ns (10.592%) route 3.233ns (89.408%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.259ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.246ns = ( 10.563 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.848ns (routing 0.565ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.679 4.533 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X106Y234 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 4.777 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/SFP_GEN[11].rx_data_ngccm[11][83]_i_1/O net (fo=76, routed) 1.554 6.331 rx_data_ngccm[11] SLICE_X113Y228 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][60]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.848 10.563 RX_WORDCLK_O[11] SLICE_X113Y228 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][60]/C clock pessimism 0.210 10.773 clock uncertainty -0.035 10.738 SLICE_X113Y228 FDCE (Setup_FFF2_SLICEM_C_CE) -0.058 10.680 SFP_GEN[11].rx_data_ngccm_reg[11][60] ------------------------------------------------------------------- required time 10.680 arrival time -6.331 ------------------------------------------------------------------- slack 4.349 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.113ns Source Clock Delay (SCD): 0.905ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.787ns (routing 0.265ns, distribution 0.522ns) Clock Net Delay (Destination): 0.948ns (routing 0.303ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.787 0.905 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X114Y235 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y235 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 0.953 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]/Q net (fo=1, routed) 0.094 1.047 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[24] SLICE_X114Y234 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.948 1.113 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X114Y234 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]/C clock pessimism -0.158 0.955 SLICE_X114Y234 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.011 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24] ------------------------------------------------------------------- required time -1.011 arrival time 1.047 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.040ns (arrival time - required time) Source: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[27]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.162ns (logic 0.049ns (30.247%) route 0.113ns (69.753%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.106ns Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.793ns (routing 0.265ns, distribution 0.528ns) Clock Net Delay (Destination): 0.941ns (routing 0.303ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.793 0.911 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y235 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y235 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 0.960 r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[27]/Q net (fo=2, routed) 0.113 1.073 SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/Q[11] SLICE_X106Y235 FDRE r SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.941 1.106 SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y235 FDRE r SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C clock pessimism -0.128 0.978 SLICE_X106Y235 FDRE (Hold_EFF2_SLICEM_C_D) 0.055 1.033 SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11] ------------------------------------------------------------------- required time -1.033 arrival time 1.073 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.102ns (66.234%) route 0.052ns (33.766%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.119ns Source Clock Delay (SCD): 0.907ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.789ns (routing 0.265ns, distribution 0.524ns) Clock Net Delay (Destination): 0.954ns (routing 0.303ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.789 0.907 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X111Y234 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y234 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 0.956 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Q net (fo=2, routed) 0.036 0.992 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_19_in SLICE_X111Y233 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.053 1.045 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__10/O net (fo=1, routed) 0.016 1.061 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[10] SLICE_X111Y233 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.954 1.119 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X111Y233 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.159 0.960 SLICE_X111Y233 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.016 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.016 arrival time 1.061 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].rx_data_ngccm_reg[11][72]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.048ns (30.769%) route 0.108ns (69.231%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.113ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.782ns (routing 0.265ns, distribution 0.517ns) Clock Net Delay (Destination): 0.948ns (routing 0.303ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X113Y227 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y227 FDRE (Prop_CFF2_SLICEM_C_Q) 0.048 0.948 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/Q net (fo=1, routed) 0.108 1.056 rx_data[11][72] SLICE_X113Y228 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][72]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.948 1.113 RX_WORDCLK_O[11] SLICE_X113Y228 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][72]/C clock pessimism -0.158 0.955 SLICE_X113Y228 FDCE (Hold_GFF2_SLICEM_C_D) 0.056 1.011 SFP_GEN[11].rx_data_ngccm_reg[11][72] ------------------------------------------------------------------- required time -1.011 arrival time 1.056 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[11].rx_data_ngccm_reg[11][16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.198ns (logic 0.049ns (24.747%) route 0.149ns (75.252%)) Logic Levels: 0 Clock Path Skew: 0.096ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.122ns Source Clock Delay (SCD): 0.898ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.780ns (routing 0.265ns, distribution 0.515ns) Clock Net Delay (Destination): 0.957ns (routing 0.303ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.780 0.898 RX_WORDCLK_O[11] SLICE_X109Y236 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][16]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y236 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 0.947 r SFP_GEN[11].rx_data_ngccm_reg[11][16]/Q net (fo=1, routed) 0.149 1.096 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[83]_0[8] SLICE_X107Y236 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.122 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y236 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]/C clock pessimism -0.128 0.994 SLICE_X107Y236 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.050 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16] ------------------------------------------------------------------- required time -1.050 arrival time 1.096 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].rx_data_ngccm_reg[11][63]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.048ns (25.000%) route 0.144ns (75.000%)) Logic Levels: 0 Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.111ns Source Clock Delay (SCD): 0.893ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.775ns (routing 0.265ns, distribution 0.510ns) Clock Net Delay (Destination): 0.946ns (routing 0.303ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.775 0.893 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X115Y229 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y229 FDRE (Prop_HFF_SLICEM_C_Q) 0.048 0.941 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/Q net (fo=1, routed) 0.144 1.085 rx_data[11][63] SLICE_X114Y228 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][63]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.946 1.111 RX_WORDCLK_O[11] SLICE_X114Y228 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][63]/C clock pessimism -0.128 0.983 SLICE_X114Y228 FDCE (Hold_EFF_SLICEL_C_D) 0.056 1.039 SFP_GEN[11].rx_data_ngccm_reg[11][63] ------------------------------------------------------------------- required time -1.039 arrival time 1.085 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.094ns (63.946%) route 0.053ns (36.054%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.119ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.788ns (routing 0.265ns, distribution 0.523ns) Clock Net Delay (Destination): 0.954ns (routing 0.303ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X110Y230 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y230 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 0.955 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.037 0.992 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O85[0] SLICE_X110Y230 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__10/O net (fo=1, routed) 0.016 1.053 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] SLICE_X110Y230 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.954 1.119 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X110Y230 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.172 0.947 SLICE_X110Y230 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.003 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.003 arrival time 1.053 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].rx_data_ngccm_reg[11][50]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.049ns (26.923%) route 0.133ns (73.077%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.101ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.265ns, distribution 0.514ns) Clock Net Delay (Destination): 0.936ns (routing 0.303ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X112Y227 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y227 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 0.946 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/Q net (fo=1, routed) 0.133 1.079 rx_data[11][50] SLICE_X111Y227 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][50]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.936 1.101 RX_WORDCLK_O[11] SLICE_X111Y227 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][50]/C clock pessimism -0.128 0.973 SLICE_X111Y227 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.029 SFP_GEN[11].rx_data_ngccm_reg[11][50] ------------------------------------------------------------------- required time -1.029 arrival time 1.079 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.112ns (70.440%) route 0.047ns (29.560%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.119ns Source Clock Delay (SCD): 0.907ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.789ns (routing 0.265ns, distribution 0.524ns) Clock Net Delay (Destination): 0.954ns (routing 0.303ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.789 0.907 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X111Y234 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y234 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 0.956 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Q net (fo=2, routed) 0.036 0.992 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_19_in SLICE_X111Y233 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.063 1.055 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[8]_i_1__10/O net (fo=1, routed) 0.011 1.066 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[8] SLICE_X111Y233 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.954 1.119 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X111Y233 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C clock pessimism -0.159 0.960 SLICE_X111Y233 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.016 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8] ------------------------------------------------------------------- required time -1.016 arrival time 1.066 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: SFP_GEN[11].rx_data_ngccm_reg[11][34]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[34]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.121ns Source Clock Delay (SCD): 0.908ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.790ns (routing 0.265ns, distribution 0.525ns) Clock Net Delay (Destination): 0.956ns (routing 0.303ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.790 0.908 RX_WORDCLK_O[11] SLICE_X108Y235 FDCE r SFP_GEN[11].rx_data_ngccm_reg[11][34]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y235 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.957 r SFP_GEN[11].rx_data_ngccm_reg[11][34]/Q net (fo=1, routed) 0.034 0.991 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[83]_0[26] SLICE_X108Y235 LUT3 (Prop_D5LUT_SLICEL_I1_O) 0.055 1.046 r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40[34]_i_1/O net (fo=1, routed) 0.011 1.057 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40[34]_i_1_n_0 SLICE_X108Y235 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.956 1.121 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y235 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.171 0.950 SLICE_X108Y235 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.006 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.006 arrival time 1.057 ------------------------------------------------------------------- slack 0.051 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_2 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y95 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X105Y234 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X104Y234 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X104Y234 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X104Y235 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X104Y235 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X104Y235 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X105Y235 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X105Y234 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X105Y235 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X105Y235 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X105Y234 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X106Y232 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X106Y232 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X104Y235 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X104Y235 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X104Y235 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X105Y235 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X107Y234 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/READY_O_reg/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X108Y236 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_3 To Clock: gtwiz_userclk_rx_srcclk_out[0]_3 Setup : 0 Failing Endpoints, Worst Slack 2.349ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.038ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.349ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.300ns (logic 1.609ns (30.358%) route 3.691ns (69.642%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.578ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.808ns = ( 11.125 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.234ns, distribution 1.949ns) Clock Net Delay (Destination): 2.410ns (routing 1.125ns, distribution 1.285ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.742 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.715 7.457 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X86Y79 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.223 7.680 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/O net (fo=5, routed) 0.352 8.032 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y80 LUT4 (Prop_D5LUT_SLICEM_I2_O) 0.247 8.279 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0/O net (fo=1, routed) 0.222 8.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0_n_0 SLICE_X85Y80 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.055 8.556 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0/O net (fo=2, routed) 0.402 8.958 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0_n_0 SLICE_X86Y81 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.410 11.125 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y81 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.272 11.397 clock uncertainty -0.035 11.362 SLICE_X86Y81 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.307 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.307 arrival time -8.958 ------------------------------------------------------------------- slack 2.349 Slack (MET) : 2.356ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.296ns (logic 1.609ns (30.381%) route 3.687ns (69.619%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.576ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.810ns = ( 11.127 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.234ns, distribution 1.949ns) Clock Net Delay (Destination): 2.412ns (routing 1.125ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.742 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.715 7.457 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X86Y79 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.223 7.680 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/O net (fo=5, routed) 0.352 8.032 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y80 LUT4 (Prop_D5LUT_SLICEM_I2_O) 0.247 8.279 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0/O net (fo=1, routed) 0.222 8.501 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0_n_0 SLICE_X85Y80 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.055 8.556 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0/O net (fo=2, routed) 0.398 8.954 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0_n_0 SLICE_X86Y81 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.412 11.127 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y81 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.272 11.399 clock uncertainty -0.035 11.364 SLICE_X86Y81 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 11.310 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.310 arrival time -8.954 ------------------------------------------------------------------- slack 2.356 Slack (MET) : 2.596ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.060ns (logic 1.533ns (30.296%) route 3.527ns (69.704%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.571ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.815ns = ( 11.132 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.234ns, distribution 1.949ns) Clock Net Delay (Destination): 2.417ns (routing 1.125ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.742 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.715 7.457 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X86Y79 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.223 7.680 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/O net (fo=5, routed) 0.278 7.958 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y80 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 8.184 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__1/O net (fo=7, routed) 0.534 8.718 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X85Y80 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.417 11.132 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y80 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.272 11.404 clock uncertainty -0.035 11.369 SLICE_X85Y80 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.314 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.314 arrival time -8.718 ------------------------------------------------------------------- slack 2.596 Slack (MET) : 2.596ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.060ns (logic 1.533ns (30.296%) route 3.527ns (69.704%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.571ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.815ns = ( 11.132 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.234ns, distribution 1.949ns) Clock Net Delay (Destination): 2.417ns (routing 1.125ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.742 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.715 7.457 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X86Y79 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.223 7.680 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/O net (fo=5, routed) 0.278 7.958 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y80 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 8.184 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__1/O net (fo=7, routed) 0.534 8.718 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X85Y80 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.417 11.132 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y80 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.272 11.404 clock uncertainty -0.035 11.369 SLICE_X85Y80 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.314 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.314 arrival time -8.718 ------------------------------------------------------------------- slack 2.596 Slack (MET) : 2.599ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.037ns (logic 1.530ns (30.375%) route 3.507ns (69.625%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.591ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.795ns = ( 11.112 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.234ns, distribution 1.949ns) Clock Net Delay (Destination): 2.397ns (routing 1.125ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.742 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.715 7.457 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X86Y79 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.223 7.680 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/O net (fo=5, routed) 0.345 8.025 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y80 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.223 8.248 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__1/O net (fo=5, routed) 0.447 8.695 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 SLICE_X87Y81 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.397 11.112 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X87Y81 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.272 11.384 clock uncertainty -0.035 11.349 SLICE_X87Y81 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.294 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.294 arrival time -8.695 ------------------------------------------------------------------- slack 2.599 Slack (MET) : 2.599ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.037ns (logic 1.530ns (30.375%) route 3.507ns (69.625%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.591ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.795ns = ( 11.112 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.234ns, distribution 1.949ns) Clock Net Delay (Destination): 2.397ns (routing 1.125ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.742 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.715 7.457 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X86Y79 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.223 7.680 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/O net (fo=5, routed) 0.345 8.025 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y80 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.223 8.248 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__1/O net (fo=5, routed) 0.447 8.695 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 SLICE_X87Y81 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.397 11.112 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X87Y81 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.272 11.384 clock uncertainty -0.035 11.349 SLICE_X87Y81 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.294 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.294 arrival time -8.695 ------------------------------------------------------------------- slack 2.599 Slack (MET) : 2.600ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.057ns (logic 1.533ns (30.314%) route 3.524ns (69.686%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.571ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.815ns = ( 11.132 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.234ns, distribution 1.949ns) Clock Net Delay (Destination): 2.417ns (routing 1.125ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.742 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.715 7.457 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X86Y79 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.223 7.680 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/O net (fo=5, routed) 0.278 7.958 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y80 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 8.184 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__1/O net (fo=7, routed) 0.531 8.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X85Y80 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.417 11.132 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y80 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.272 11.404 clock uncertainty -0.035 11.369 SLICE_X85Y80 FDRE (Setup_AFF_SLICEM_C_CE) -0.054 11.315 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.315 arrival time -8.715 ------------------------------------------------------------------- slack 2.600 Slack (MET) : 2.600ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.057ns (logic 1.533ns (30.314%) route 3.524ns (69.686%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.571ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.815ns = ( 11.132 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.234ns, distribution 1.949ns) Clock Net Delay (Destination): 2.417ns (routing 1.125ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.742 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.715 7.457 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X86Y79 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.223 7.680 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/O net (fo=5, routed) 0.278 7.958 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y80 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 8.184 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__1/O net (fo=7, routed) 0.531 8.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X85Y80 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.417 11.132 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y80 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.272 11.404 clock uncertainty -0.035 11.369 SLICE_X85Y80 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.315 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.315 arrival time -8.715 ------------------------------------------------------------------- slack 2.600 Slack (MET) : 2.603ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.034ns (logic 1.530ns (30.393%) route 3.504ns (69.607%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.591ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.795ns = ( 11.112 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.234ns, distribution 1.949ns) Clock Net Delay (Destination): 2.397ns (routing 1.125ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.742 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.715 7.457 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X86Y79 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.223 7.680 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/O net (fo=5, routed) 0.345 8.025 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y80 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.223 8.248 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__1/O net (fo=5, routed) 0.444 8.692 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 SLICE_X87Y81 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.397 11.112 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X87Y81 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.272 11.384 clock uncertainty -0.035 11.349 SLICE_X87Y81 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.295 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.295 arrival time -8.692 ------------------------------------------------------------------- slack 2.603 Slack (MET) : 2.603ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 5.034ns (logic 1.530ns (30.393%) route 3.504ns (69.607%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.591ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.795ns = ( 11.112 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.234ns, distribution 1.949ns) Clock Net Delay (Destination): 2.397ns (routing 1.125ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 4.742 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.715 7.457 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X86Y79 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.223 7.680 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/O net (fo=5, routed) 0.345 8.025 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y80 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.223 8.248 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__1/O net (fo=5, routed) 0.444 8.692 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 SLICE_X87Y81 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.397 11.112 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X87Y81 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.272 11.384 clock uncertainty -0.035 11.349 SLICE_X87Y81 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.295 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.295 arrival time -8.692 ------------------------------------------------------------------- slack 2.603 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.038ns (arrival time - required time) Source: SFP_GEN[1].rx_data_ngccm_reg[1][42]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[42]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.088ns (50.867%) route 0.085ns (49.133%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.401ns Source Clock Delay (SCD): 1.165ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.047ns (routing 0.538ns, distribution 0.509ns) Clock Net Delay (Destination): 1.236ns (routing 0.604ns, distribution 0.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.047 1.165 RX_WORDCLK_O[1] SLICE_X78Y75 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][42]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y75 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.214 r SFP_GEN[1].rx_data_ngccm_reg[1][42]/Q net (fo=1, routed) 0.073 1.287 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[34] SLICE_X80Y75 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.039 1.326 r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[42]_i_1/O net (fo=1, routed) 0.012 1.338 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[42]_i_1_n_0 SLICE_X80Y75 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[42]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.236 1.401 SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y75 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[42]/C clock pessimism -0.157 1.244 SLICE_X80Y75 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.300 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[42] ------------------------------------------------------------------- required time -1.300 arrival time 1.338 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.078ns (48.750%) route 0.082ns (51.250%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.405ns Source Clock Delay (SCD): 1.161ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 1.043ns (routing 0.538ns, distribution 0.505ns) Clock Net Delay (Destination): 1.240ns (routing 0.604ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.043 1.161 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X78Y74 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y74 FDCE (Prop_GFF2_SLICEL_C_Q) 0.048 1.209 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.068 1.277 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in SLICE_X78Y73 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.030 1.307 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__0/O net (fo=1, routed) 0.014 1.321 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X78Y73 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.240 1.405 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X78Y73 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.187 1.218 SLICE_X78Y73 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.274 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.274 arrival time 1.321 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[1].rx_data_ngccm_reg[1][79]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[78]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.103ns (69.595%) route 0.045ns (30.405%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.406ns Source Clock Delay (SCD): 1.165ns Clock Pessimism Removal (CPR): 0.197ns Clock Net Delay (Source): 1.047ns (routing 0.538ns, distribution 0.509ns) Clock Net Delay (Destination): 1.241ns (routing 0.604ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.047 1.165 RX_WORDCLK_O[1] SLICE_X78Y75 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][79]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y75 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.213 r SFP_GEN[1].rx_data_ngccm_reg[1][79]/Q net (fo=1, routed) 0.034 1.247 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[71] SLICE_X78Y75 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.055 1.302 r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[78]_i_1/O net (fo=1, routed) 0.011 1.313 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[78]_i_1_n_0 SLICE_X78Y75 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[78]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.241 1.406 SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y75 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[78]/C clock pessimism -0.197 1.209 SLICE_X78Y75 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.265 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[78] ------------------------------------------------------------------- required time -1.265 arrival time 1.313 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[1].ngccm_rx_down_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].ngccm_rx_down_cnt_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.393ns Source Clock Delay (SCD): 1.163ns Clock Pessimism Removal (CPR): 0.225ns Clock Net Delay (Source): 1.045ns (routing 0.538ns, distribution 0.507ns) Clock Net Delay (Destination): 1.228ns (routing 0.604ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.045 1.163 RX_WORDCLK_O[1] SLICE_X79Y114 FDRE r SFP_GEN[1].ngccm_rx_down_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y114 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 1.212 r SFP_GEN[1].ngccm_rx_down_cnt_reg[1]/Q net (fo=2, routed) 0.033 1.245 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/cntr_din[0] SLICE_X79Y114 LUT4 (Prop_A6LUT_SLICEM_I3_O) 0.015 1.260 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/SFP_GEN[1].ngccm_rx_down_cnt[1]_i_1/O net (fo=1, routed) 0.012 1.272 g_gbt_bank[0].gbtbank_n_122 SLICE_X79Y114 FDRE r SFP_GEN[1].ngccm_rx_down_cnt_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.393 RX_WORDCLK_O[1] SLICE_X79Y114 FDRE r SFP_GEN[1].ngccm_rx_down_cnt_reg[1]/C clock pessimism -0.225 1.168 SLICE_X79Y114 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.224 SFP_GEN[1].ngccm_rx_down_cnt_reg[1] ------------------------------------------------------------------- required time -1.224 arrival time 1.272 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: SFP_GEN[1].rx_data_ngccm_reg[1][46]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[46]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.406ns Source Clock Delay (SCD): 1.165ns Clock Pessimism Removal (CPR): 0.197ns Clock Net Delay (Source): 1.047ns (routing 0.538ns, distribution 0.509ns) Clock Net Delay (Destination): 1.241ns (routing 0.604ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.047 1.165 RX_WORDCLK_O[1] SLICE_X78Y75 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][46]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y75 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.214 r SFP_GEN[1].rx_data_ngccm_reg[1][46]/Q net (fo=1, routed) 0.034 1.248 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[38] SLICE_X78Y75 LUT3 (Prop_D5LUT_SLICEL_I1_O) 0.055 1.303 r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[46]_i_1/O net (fo=1, routed) 0.011 1.314 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[46]_i_1_n_0 SLICE_X78Y75 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[46]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.241 1.406 SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y75 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[46]/C clock pessimism -0.197 1.209 SLICE_X78Y75 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.265 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[46] ------------------------------------------------------------------- required time -1.265 arrival time 1.314 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[34]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.049ns (33.793%) route 0.096ns (66.207%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.389ns Source Clock Delay (SCD): 1.162ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 1.044ns (routing 0.538ns, distribution 0.506ns) Clock Net Delay (Destination): 1.224ns (routing 0.604ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.044 1.162 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X81Y72 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y72 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.211 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]/Q net (fo=1, routed) 0.096 1.307 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[34] SLICE_X81Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.224 1.389 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X81Y71 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[34]/C clock pessimism -0.187 1.202 SLICE_X81Y71 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.258 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[34] ------------------------------------------------------------------- required time -1.258 arrival time 1.307 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: SFP_GEN[1].rx_data_ngccm_reg[1][41]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[40]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.401ns Source Clock Delay (SCD): 1.166ns Clock Pessimism Removal (CPR): 0.196ns Clock Net Delay (Source): 1.048ns (routing 0.538ns, distribution 0.510ns) Clock Net Delay (Destination): 1.236ns (routing 0.604ns, distribution 0.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.048 1.166 RX_WORDCLK_O[1] SLICE_X80Y75 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][41]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y75 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.215 r SFP_GEN[1].rx_data_ngccm_reg[1][41]/Q net (fo=1, routed) 0.035 1.250 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[33] SLICE_X80Y75 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.045 1.295 r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[40]_i_1/O net (fo=1, routed) 0.016 1.311 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 SLICE_X80Y75 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[40]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.236 1.401 SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y75 FDCE r SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[40]/C clock pessimism -0.196 1.205 SLICE_X80Y75 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.261 SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[40] ------------------------------------------------------------------- required time -1.261 arrival time 1.311 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.407ns Source Clock Delay (SCD): 1.175ns Clock Pessimism Removal (CPR): 0.227ns Clock Net Delay (Source): 1.057ns (routing 0.538ns, distribution 0.519ns) Clock Net Delay (Destination): 1.242ns (routing 0.604ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.057 1.175 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X86Y79 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.224 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.035 1.259 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/ready_from_bitSlipCtrller_1 SLICE_X86Y79 LUT3 (Prop_A6LUT_SLICEL_I2_O) 0.015 1.274 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_i_1__0/O net (fo=1, routed) 0.012 1.286 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_i_1__0_n_0 SLICE_X86Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.242 1.407 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/C clock pessimism -0.227 1.180 SLICE_X86Y79 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.236 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.236 arrival time 1.286 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[1].rx_data_ngccm_reg[1][62]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.049ns (25.926%) route 0.140ns (74.074%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.409ns Source Clock Delay (SCD): 1.169ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.051ns (routing 0.538ns, distribution 0.513ns) Clock Net Delay (Destination): 1.244ns (routing 0.604ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.051 1.169 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X79Y71 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y71 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.218 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/Q net (fo=1, routed) 0.140 1.358 rx_data[1][62] SLICE_X78Y71 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][62]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.244 1.409 RX_WORDCLK_O[1] SLICE_X78Y71 FDCE r SFP_GEN[1].rx_data_ngccm_reg[1][62]/C clock pessimism -0.157 1.252 SLICE_X78Y71 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.308 SFP_GEN[1].rx_data_ngccm_reg[1][62] ------------------------------------------------------------------- required time -1.308 arrival time 1.358 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.104ns (54.737%) route 0.086ns (45.263%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.408ns Source Clock Delay (SCD): 1.167ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.049ns (routing 0.538ns, distribution 0.511ns) Clock Net Delay (Destination): 1.243ns (routing 0.604ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.049 1.167 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X79Y72 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y72 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.216 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.075 1.291 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_31_in SLICE_X78Y72 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.055 1.346 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__0/O net (fo=1, routed) 0.011 1.357 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[14] SLICE_X78Y72 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.243 1.408 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X78Y72 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.157 1.251 SLICE_X78Y72 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.307 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -1.307 arrival time 1.357 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_3 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y33 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X80Y81 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X80Y81 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y81 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X80Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X80Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X80Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X80Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/C Low Pulse Width Fast FDPE/C n/a 0.275 4.159 3.884 SLICE_X89Y80 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X82Y81 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y80 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X89Y78 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_4 To Clock: gtwiz_userclk_rx_srcclk_out[0]_4 Setup : 0 Failing Endpoints, Worst Slack 2.428ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.040ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.428ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.244ns (logic 1.544ns (29.443%) route 3.700ns (70.557%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.552ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.687ns = ( 11.004 - 8.317 ) Source Clock Delay (SCD): 3.496ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.021ns (routing 1.094ns, distribution 1.927ns) Clock Net Delay (Destination): 2.289ns (routing 0.997ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.021 3.496 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.582 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.995 7.577 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X84Y90 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.223 7.800 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.205 8.005 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y91 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.235 8.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__2/O net (fo=3, routed) 0.500 8.740 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecFalseHeaders0 SLICE_X83Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.289 11.004 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.257 11.261 clock uncertainty -0.035 11.226 SLICE_X83Y91 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.168 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.168 arrival time -8.740 ------------------------------------------------------------------- slack 2.428 Slack (MET) : 2.434ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.241ns (logic 1.544ns (29.460%) route 3.697ns (70.540%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.552ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.687ns = ( 11.004 - 8.317 ) Source Clock Delay (SCD): 3.496ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.021ns (routing 1.094ns, distribution 1.927ns) Clock Net Delay (Destination): 2.289ns (routing 0.997ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.021 3.496 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.582 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.995 7.577 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X84Y90 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.223 7.800 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.205 8.005 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y91 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.235 8.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__2/O net (fo=3, routed) 0.497 8.737 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecFalseHeaders0 SLICE_X83Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.289 11.004 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.257 11.261 clock uncertainty -0.035 11.226 SLICE_X83Y91 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.171 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.171 arrival time -8.737 ------------------------------------------------------------------- slack 2.434 Slack (MET) : 2.434ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.241ns (logic 1.544ns (29.460%) route 3.697ns (70.540%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.552ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.687ns = ( 11.004 - 8.317 ) Source Clock Delay (SCD): 3.496ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.021ns (routing 1.094ns, distribution 1.927ns) Clock Net Delay (Destination): 2.289ns (routing 0.997ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.021 3.496 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.582 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.995 7.577 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X84Y90 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.223 7.800 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.205 8.005 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y91 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.235 8.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__2/O net (fo=3, routed) 0.497 8.737 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecFalseHeaders0 SLICE_X83Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.289 11.004 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.257 11.261 clock uncertainty -0.035 11.226 SLICE_X83Y91 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.171 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.171 arrival time -8.737 ------------------------------------------------------------------- slack 2.434 Slack (MET) : 2.443ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.219ns (logic 1.398ns (26.787%) route 3.821ns (73.213%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.565ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.674ns = ( 10.991 - 8.317 ) Source Clock Delay (SCD): 3.496ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.021ns (routing 1.094ns, distribution 1.927ns) Clock Net Delay (Destination): 2.276ns (routing 0.997ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.021 3.496 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.582 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.995 7.577 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X84Y90 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.223 7.800 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.187 7.987 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y92 LUT5 (Prop_G6LUT_SLICEL_I3_O) 0.089 8.076 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/O net (fo=7, routed) 0.639 8.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X84Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.991 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.257 11.248 clock uncertainty -0.035 11.213 SLICE_X84Y92 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 11.158 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.158 arrival time -8.715 ------------------------------------------------------------------- slack 2.443 Slack (MET) : 2.460ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.217ns (logic 1.398ns (26.797%) route 3.819ns (73.203%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.550ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.689ns = ( 11.006 - 8.317 ) Source Clock Delay (SCD): 3.496ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.021ns (routing 1.094ns, distribution 1.927ns) Clock Net Delay (Destination): 2.291ns (routing 0.997ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.021 3.496 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.582 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.995 7.577 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X84Y90 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.223 7.800 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.187 7.987 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y92 LUT5 (Prop_G6LUT_SLICEL_I3_O) 0.089 8.076 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/O net (fo=7, routed) 0.637 8.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X83Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.291 11.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.257 11.263 clock uncertainty -0.035 11.228 SLICE_X83Y91 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.173 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.173 arrival time -8.713 ------------------------------------------------------------------- slack 2.460 Slack (MET) : 2.464ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.214ns (logic 1.398ns (26.812%) route 3.816ns (73.188%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.550ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.689ns = ( 11.006 - 8.317 ) Source Clock Delay (SCD): 3.496ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.021ns (routing 1.094ns, distribution 1.927ns) Clock Net Delay (Destination): 2.291ns (routing 0.997ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.021 3.496 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.582 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.995 7.577 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X84Y90 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.223 7.800 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.187 7.987 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y92 LUT5 (Prop_G6LUT_SLICEL_I3_O) 0.089 8.076 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/O net (fo=7, routed) 0.634 8.710 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X83Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.291 11.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.257 11.263 clock uncertainty -0.035 11.228 SLICE_X83Y91 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.174 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.174 arrival time -8.710 ------------------------------------------------------------------- slack 2.464 Slack (MET) : 2.485ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.194ns (logic 1.602ns (30.843%) route 3.592ns (69.157%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.549ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 3.496ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.021ns (routing 1.094ns, distribution 1.927ns) Clock Net Delay (Destination): 2.292ns (routing 0.997ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.021 3.496 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.582 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.995 7.577 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X84Y90 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.223 7.800 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.190 7.990 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y92 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.146 8.136 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1/O net (fo=1, routed) 0.159 8.295 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1_n_0 SLICE_X84Y91 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 8.442 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1/O net (fo=2, routed) 0.248 8.690 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1_n_0 SLICE_X84Y91 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.292 11.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y91 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.257 11.264 clock uncertainty -0.035 11.229 SLICE_X84Y91 FDCE (Setup_BFF_SLICEL_C_CE) -0.054 11.175 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.175 arrival time -8.690 ------------------------------------------------------------------- slack 2.485 Slack (MET) : 2.485ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.194ns (logic 1.602ns (30.843%) route 3.592ns (69.157%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.549ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 3.496ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.021ns (routing 1.094ns, distribution 1.927ns) Clock Net Delay (Destination): 2.292ns (routing 0.997ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.021 3.496 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.582 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.995 7.577 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X84Y90 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.223 7.800 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.190 7.990 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y92 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.146 8.136 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1/O net (fo=1, routed) 0.159 8.295 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1_n_0 SLICE_X84Y91 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 8.442 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1/O net (fo=2, routed) 0.248 8.690 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1_n_0 SLICE_X84Y91 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.292 11.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y91 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.257 11.264 clock uncertainty -0.035 11.229 SLICE_X84Y91 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 11.175 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.175 arrival time -8.690 ------------------------------------------------------------------- slack 2.485 Slack (MET) : 2.511ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.153ns (logic 1.544ns (29.963%) route 3.609ns (70.037%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.563ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.676ns = ( 10.993 - 8.317 ) Source Clock Delay (SCD): 3.496ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.021ns (routing 1.094ns, distribution 1.927ns) Clock Net Delay (Destination): 2.278ns (routing 0.997ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.021 3.496 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.582 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.995 7.577 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X84Y90 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.223 7.800 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.206 8.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y91 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 8.241 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/O net (fo=5, routed) 0.408 8.649 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 SLICE_X84Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.278 10.993 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.257 11.250 clock uncertainty -0.035 11.215 SLICE_X84Y92 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.160 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.160 arrival time -8.649 ------------------------------------------------------------------- slack 2.511 Slack (MET) : 2.511ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 5.153ns (logic 1.544ns (29.963%) route 3.609ns (70.037%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.563ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.676ns = ( 10.993 - 8.317 ) Source Clock Delay (SCD): 3.496ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.021ns (routing 1.094ns, distribution 1.927ns) Clock Net Delay (Destination): 2.278ns (routing 0.997ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.021 3.496 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.582 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.995 7.577 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X84Y90 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.223 7.800 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/O net (fo=5, routed) 0.206 8.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y91 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.235 8.241 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/O net (fo=5, routed) 0.408 8.649 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 SLICE_X84Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.278 10.993 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.257 11.250 clock uncertainty -0.035 11.215 SLICE_X84Y92 FDRE (Setup_BFF2_SLICEL_C_CE) -0.055 11.160 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.160 arrival time -8.649 ------------------------------------------------------------------- slack 2.511 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.094ns (51.934%) route 0.087ns (48.066%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 1.005ns (routing 0.466ns, distribution 0.539ns) Clock Net Delay (Destination): 1.192ns (routing 0.526ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.123 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X78Y84 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y84 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.172 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.073 1.245 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X79Y84 LUT3 (Prop_G6LUT_SLICEM_I0_O) 0.045 1.290 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__1/O net (fo=1, routed) 0.014 1.304 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] SLICE_X79Y84 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.357 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X79Y84 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.149 1.208 SLICE_X79Y84 FDRE (Hold_GFF_SLICEM_C_D) 0.056 1.264 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.264 arrival time 1.304 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.095ns (51.075%) route 0.091ns (48.925%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.349ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.997ns (routing 0.466ns, distribution 0.531ns) Clock Net Delay (Destination): 1.184ns (routing 0.526ns, distribution 0.658ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X75Y82 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y82 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.164 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Q net (fo=2, routed) 0.075 1.239 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_19_in SLICE_X76Y82 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.046 1.285 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__1/O net (fo=1, routed) 0.016 1.301 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[10] SLICE_X76Y82 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.184 1.349 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X76Y82 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.150 1.199 SLICE_X76Y82 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.255 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.255 arrival time 1.301 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.187ns (logic 0.096ns (51.337%) route 0.091ns (48.663%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 1.005ns (routing 0.466ns, distribution 0.539ns) Clock Net Delay (Destination): 1.192ns (routing 0.526ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.123 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X78Y84 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y84 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.172 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.075 1.247 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X79Y84 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.047 1.294 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__1/O net (fo=1, routed) 0.016 1.310 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[0] SLICE_X79Y84 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.357 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X79Y84 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.149 1.208 SLICE_X79Y84 FDRE (Hold_HFF_SLICEM_C_D) 0.056 1.264 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.264 arrival time 1.310 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].rx_data_ngccm_reg[2][78]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.048ns (31.579%) route 0.104ns (68.421%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.125ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 1.007ns (routing 0.466ns, distribution 0.541ns) Clock Net Delay (Destination): 1.193ns (routing 0.526ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.125 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X78Y82 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y82 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.173 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/Q net (fo=1, routed) 0.104 1.277 rx_data[2][78] SLICE_X78Y83 FDCE r SFP_GEN[2].rx_data_ngccm_reg[2][78]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.193 1.358 RX_WORDCLK_O[2] SLICE_X78Y83 FDCE r SFP_GEN[2].rx_data_ngccm_reg[2][78]/C clock pessimism -0.184 1.174 SLICE_X78Y83 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.230 SFP_GEN[2].rx_data_ngccm_reg[2][78] ------------------------------------------------------------------- required time -1.230 arrival time 1.277 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].rx_data_ngccm_reg[2][65]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.048ns (30.769%) route 0.108ns (69.231%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.122ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 1.004ns (routing 0.466ns, distribution 0.538ns) Clock Net Delay (Destination): 1.193ns (routing 0.526ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.122 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y82 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y82 FDRE (Prop_CFF2_SLICEM_C_Q) 0.048 1.170 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/Q net (fo=1, routed) 0.108 1.278 rx_data[2][65] SLICE_X79Y83 FDCE r SFP_GEN[2].rx_data_ngccm_reg[2][65]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.193 1.358 RX_WORDCLK_O[2] SLICE_X79Y83 FDCE r SFP_GEN[2].rx_data_ngccm_reg[2][65]/C clock pessimism -0.184 1.174 SLICE_X79Y83 FDCE (Hold_GFF2_SLICEM_C_D) 0.056 1.230 SFP_GEN[2].rx_data_ngccm_reg[2][65] ------------------------------------------------------------------- required time -1.230 arrival time 1.278 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].rx_data_ngccm_reg[2][69]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.195ns (logic 0.048ns (24.615%) route 0.147ns (75.385%)) Logic Levels: 0 Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.362ns Source Clock Delay (SCD): 1.122ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 1.004ns (routing 0.466ns, distribution 0.538ns) Clock Net Delay (Destination): 1.197ns (routing 0.526ns, distribution 0.671ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.122 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X80Y83 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y83 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 1.170 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.147 1.317 rx_data[2][69] SLICE_X77Y83 FDCE r SFP_GEN[2].rx_data_ngccm_reg[2][69]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.197 1.362 RX_WORDCLK_O[2] SLICE_X77Y83 FDCE r SFP_GEN[2].rx_data_ngccm_reg[2][69]/C clock pessimism -0.149 1.213 SLICE_X77Y83 FDCE (Hold_BFF2_SLICEM_C_D) 0.056 1.269 SFP_GEN[2].rx_data_ngccm_reg[2][69] ------------------------------------------------------------------- required time -1.269 arrival time 1.317 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: SFP_GEN[2].rx_data_ngccm_reg[2][42]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[42]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.089ns (50.568%) route 0.087ns (49.432%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 1.005ns (routing 0.466ns, distribution 0.539ns) Clock Net Delay (Destination): 1.178ns (routing 0.526ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.123 RX_WORDCLK_O[2] SLICE_X79Y85 FDCE r SFP_GEN[2].rx_data_ngccm_reg[2][42]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y85 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.172 r SFP_GEN[2].rx_data_ngccm_reg[2][42]/Q net (fo=1, routed) 0.075 1.247 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[83]_0[34] SLICE_X77Y85 LUT3 (Prop_D5LUT_SLICEM_I1_O) 0.040 1.287 r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40[42]_i_1/O net (fo=1, routed) 0.012 1.299 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40[42]_i_1_n_0 SLICE_X77Y85 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[42]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.343 SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y85 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[42]/C clock pessimism -0.150 1.193 SLICE_X77Y85 FDCE (Hold_DFF2_SLICEM_C_D) 0.056 1.249 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[42] ------------------------------------------------------------------- required time -1.249 arrival time 1.299 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.093ns (51.381%) route 0.088ns (48.619%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.332ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.989ns (routing 0.466ns, distribution 0.523ns) Clock Net Delay (Destination): 1.167ns (routing 0.526ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y93 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y93 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.155 r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/Q net (fo=1, routed) 0.072 1.227 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].cnt_reg[2][0]_0[0] SLICE_X82Y93 LUT2 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.272 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].rx_clken_sr[2][1]_i_1/O net (fo=1, routed) 0.016 1.288 g_gbt_bank[0].gbtbank/i_gbt_bank_n_247 SLICE_X82Y93 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.167 1.332 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X82Y93 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C clock pessimism -0.150 1.182 SLICE_X82Y93 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.238 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1] ------------------------------------------------------------------- required time -1.238 arrival time 1.288 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.103ns Clock Pessimism Removal (CPR): 0.219ns Clock Net Delay (Source): 0.985ns (routing 0.466ns, distribution 0.519ns) Clock Net Delay (Destination): 1.162ns (routing 0.526ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.103 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y92 FDRE (Prop_AFF_SLICEL_C_Q) 0.049 1.152 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/Q net (fo=2, routed) 0.035 1.187 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[4] SLICE_X84Y92 LUT6 (Prop_A6LUT_SLICEL_I5_O) 0.015 1.202 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__2/O net (fo=1, routed) 0.012 1.214 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__2_n_0 SLICE_X84Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.327 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y92 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism -0.219 1.108 SLICE_X84Y92 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.164 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time -1.164 arrival time 1.214 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].rx_data_ngccm_reg[2][24]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.198ns (logic 0.049ns (24.747%) route 0.149ns (75.253%)) Logic Levels: 0 Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.355ns Source Clock Delay (SCD): 1.114ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.996ns (routing 0.466ns, distribution 0.530ns) Clock Net Delay (Destination): 1.190ns (routing 0.526ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.996 1.114 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X76Y91 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y91 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 1.163 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.149 1.312 rx_data[2][24] SLICE_X77Y92 FDCE r SFP_GEN[2].rx_data_ngccm_reg[2][24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.355 RX_WORDCLK_O[2] SLICE_X77Y92 FDCE r SFP_GEN[2].rx_data_ngccm_reg[2][24]/C clock pessimism -0.150 1.205 SLICE_X77Y92 FDCE (Hold_GFF2_SLICEM_C_D) 0.056 1.261 SFP_GEN[2].rx_data_ngccm_reg[2][24] ------------------------------------------------------------------- required time -1.261 arrival time 1.312 ------------------------------------------------------------------- slack 0.051 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_4 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y47 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y116 g_clock_rate_din[2].ngccm_status_cnt_reg[2][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y116 g_clock_rate_din[2].ngccm_status_cnt_reg[2][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y116 g_clock_rate_din[2].ngccm_status_cnt_reg[2][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y116 g_clock_rate_din[2].ngccm_status_cnt_reg[2][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y116 g_clock_rate_din[2].ngccm_status_cnt_reg[2][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y116 g_clock_rate_din[2].ngccm_status_cnt_reg[2][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y119 g_clock_rate_din[2].ngccm_status_cnt_reg[2][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y116 g_clock_rate_din[2].ngccm_status_cnt_reg[2][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y116 g_clock_rate_din[2].ngccm_status_cnt_reg[2][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y116 g_clock_rate_din[2].ngccm_status_cnt_reg[2][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y116 g_clock_rate_din[2].ngccm_status_cnt_reg[2][3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y116 g_clock_rate_din[2].ngccm_status_cnt_reg[2][4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y116 g_clock_rate_din[2].ngccm_status_cnt_reg[2][5]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y84 SFP_GEN[2].rx_data_ngccm_reg[2][48]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y84 SFP_GEN[2].rx_data_ngccm_reg[2][50]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X80Y85 SFP_GEN[2].rx_data_ngccm_reg[2][51]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X78Y83 SFP_GEN[2].rx_data_ngccm_reg[2][52]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X80Y85 SFP_GEN[2].rx_data_ngccm_reg[2][53]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X78Y83 SFP_GEN[2].rx_data_ngccm_reg[2][54]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_5 To Clock: gtwiz_userclk_rx_srcclk_out[0]_5 Setup : 0 Failing Endpoints, Worst Slack 2.044ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.044ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.535ns (logic 1.283ns (23.180%) route 4.252ns (76.820%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.648ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.805ns = ( 11.122 - 8.317 ) Source Clock Delay (SCD): 3.722ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.247ns (routing 1.207ns, distribution 2.040ns) Clock Net Delay (Destination): 2.407ns (routing 1.098ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.247 3.722 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.808 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.142 7.950 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X91Y103 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.146 8.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.595 8.691 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X91Y103 LUT6 (Prop_G6LUT_SLICEL_I1_O) 0.051 8.742 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2/O net (fo=2, routed) 0.515 9.257 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2_n_0 SLICE_X88Y104 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.407 11.122 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y104 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.269 11.392 clock uncertainty -0.035 11.356 SLICE_X88Y104 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.301 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.301 arrival time -9.257 ------------------------------------------------------------------- slack 2.044 Slack (MET) : 2.110ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.470ns (logic 1.283ns (23.455%) route 4.187ns (76.545%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.647ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.806ns = ( 11.123 - 8.317 ) Source Clock Delay (SCD): 3.722ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.247ns (routing 1.207ns, distribution 2.040ns) Clock Net Delay (Destination): 2.408ns (routing 1.098ns, distribution 1.310ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.247 3.722 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.808 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.142 7.950 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X91Y103 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.146 8.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.595 8.691 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X91Y103 LUT6 (Prop_G6LUT_SLICEL_I1_O) 0.051 8.742 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2/O net (fo=2, routed) 0.450 9.192 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2_n_0 SLICE_X89Y104 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.408 11.123 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y104 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.269 11.393 clock uncertainty -0.035 11.357 SLICE_X89Y104 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.302 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.302 arrival time -9.192 ------------------------------------------------------------------- slack 2.110 Slack (MET) : 2.354ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.234ns (logic 1.378ns (26.328%) route 3.856ns (73.672%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.636ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.817ns = ( 11.134 - 8.317 ) Source Clock Delay (SCD): 3.722ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.247ns (routing 1.207ns, distribution 2.040ns) Clock Net Delay (Destination): 2.419ns (routing 1.098ns, distribution 1.321ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.247 3.722 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.808 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.142 7.950 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X91Y103 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.146 8.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.178 8.274 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X91Y104 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.146 8.420 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__3/O net (fo=3, routed) 0.536 8.956 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecFalseHeaders0 SLICE_X91Y104 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.419 11.134 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y104 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.269 11.404 clock uncertainty -0.035 11.368 SLICE_X91Y104 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.310 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.310 arrival time -8.956 ------------------------------------------------------------------- slack 2.354 Slack (MET) : 2.361ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.230ns (logic 1.378ns (26.348%) route 3.852ns (73.652%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.636ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.817ns = ( 11.134 - 8.317 ) Source Clock Delay (SCD): 3.722ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.247ns (routing 1.207ns, distribution 2.040ns) Clock Net Delay (Destination): 2.419ns (routing 1.098ns, distribution 1.321ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.247 3.722 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.808 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.142 7.950 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X91Y103 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.146 8.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.178 8.274 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X91Y104 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.146 8.420 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__3/O net (fo=3, routed) 0.532 8.952 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecFalseHeaders0 SLICE_X91Y104 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.419 11.134 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y104 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.269 11.404 clock uncertainty -0.035 11.368 SLICE_X91Y104 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.313 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.313 arrival time -8.952 ------------------------------------------------------------------- slack 2.361 Slack (MET) : 2.361ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.230ns (logic 1.378ns (26.348%) route 3.852ns (73.652%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.636ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.817ns = ( 11.134 - 8.317 ) Source Clock Delay (SCD): 3.722ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.247ns (routing 1.207ns, distribution 2.040ns) Clock Net Delay (Destination): 2.419ns (routing 1.098ns, distribution 1.321ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.247 3.722 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.808 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.142 7.950 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X91Y103 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.146 8.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.178 8.274 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X91Y104 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.146 8.420 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__3/O net (fo=3, routed) 0.532 8.952 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecFalseHeaders0 SLICE_X91Y104 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.419 11.134 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y104 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.269 11.404 clock uncertainty -0.035 11.368 SLICE_X91Y104 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 11.313 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.313 arrival time -8.952 ------------------------------------------------------------------- slack 2.361 Slack (MET) : 2.425ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.190ns (logic 1.378ns (26.551%) route 3.812ns (73.449%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.612ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.841ns = ( 11.158 - 8.317 ) Source Clock Delay (SCD): 3.722ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.247ns (routing 1.207ns, distribution 2.040ns) Clock Net Delay (Destination): 2.443ns (routing 1.098ns, distribution 1.345ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.247 3.722 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.808 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.142 7.950 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X91Y103 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.146 8.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.178 8.274 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X91Y104 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 8.420 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/O net (fo=5, routed) 0.492 8.912 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 SLICE_X92Y105 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.443 11.158 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y105 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.269 11.427 clock uncertainty -0.035 11.392 SLICE_X92Y105 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.337 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.337 arrival time -8.912 ------------------------------------------------------------------- slack 2.425 Slack (MET) : 2.458ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.140ns (logic 1.378ns (26.809%) route 3.762ns (73.191%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.629ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.824ns = ( 11.141 - 8.317 ) Source Clock Delay (SCD): 3.722ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.247ns (routing 1.207ns, distribution 2.040ns) Clock Net Delay (Destination): 2.426ns (routing 1.098ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.247 3.722 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.808 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.142 7.950 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X91Y103 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.146 8.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.088 8.184 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X91Y103 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 8.330 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/O net (fo=7, routed) 0.532 8.862 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 SLICE_X91Y103 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.426 11.141 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y103 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.269 11.411 clock uncertainty -0.035 11.375 SLICE_X91Y103 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 11.320 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.320 arrival time -8.862 ------------------------------------------------------------------- slack 2.458 Slack (MET) : 2.479ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.138ns (logic 1.378ns (26.820%) route 3.760ns (73.180%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.610ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.843ns = ( 11.160 - 8.317 ) Source Clock Delay (SCD): 3.722ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.247ns (routing 1.207ns, distribution 2.040ns) Clock Net Delay (Destination): 2.445ns (routing 1.098ns, distribution 1.347ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.247 3.722 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.808 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.142 7.950 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X91Y103 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.146 8.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.178 8.274 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X91Y104 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 8.420 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/O net (fo=5, routed) 0.440 8.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 SLICE_X92Y105 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.445 11.160 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y105 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.269 11.429 clock uncertainty -0.035 11.394 SLICE_X92Y105 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.339 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.339 arrival time -8.860 ------------------------------------------------------------------- slack 2.479 Slack (MET) : 2.479ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.138ns (logic 1.378ns (26.820%) route 3.760ns (73.180%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.610ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.843ns = ( 11.160 - 8.317 ) Source Clock Delay (SCD): 3.722ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.247ns (routing 1.207ns, distribution 2.040ns) Clock Net Delay (Destination): 2.445ns (routing 1.098ns, distribution 1.347ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.247 3.722 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.808 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.142 7.950 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X91Y103 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.146 8.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.178 8.274 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X91Y104 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 8.420 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/O net (fo=5, routed) 0.440 8.860 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 SLICE_X92Y105 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.445 11.160 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y105 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.269 11.429 clock uncertainty -0.035 11.394 SLICE_X92Y105 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.339 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.339 arrival time -8.860 ------------------------------------------------------------------- slack 2.479 Slack (MET) : 2.483ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 5.135ns (logic 1.378ns (26.835%) route 3.757ns (73.165%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.610ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.843ns = ( 11.160 - 8.317 ) Source Clock Delay (SCD): 3.722ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.247ns (routing 1.207ns, distribution 2.040ns) Clock Net Delay (Destination): 2.445ns (routing 1.098ns, distribution 1.347ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.247 3.722 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.808 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.142 7.950 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X91Y103 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.146 8.096 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/O net (fo=5, routed) 0.178 8.274 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X91Y104 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 8.420 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/O net (fo=5, routed) 0.437 8.857 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 SLICE_X92Y105 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.445 11.160 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y105 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.269 11.429 clock uncertainty -0.035 11.394 SLICE_X92Y105 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.340 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.340 arrival time -8.857 ------------------------------------------------------------------- slack 2.483 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[35]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[35]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.430ns Source Clock Delay (SCD): 1.189ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.071ns (routing 0.527ns, distribution 0.544ns) Clock Net Delay (Destination): 1.265ns (routing 0.593ns, distribution 0.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.071 1.189 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X84Y99 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[35]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y99 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.237 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[35]/Q net (fo=1, routed) 0.095 1.332 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[35] SLICE_X84Y98 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.265 1.430 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X84Y98 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[35]/C clock pessimism -0.190 1.240 SLICE_X84Y98 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.296 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[35] ------------------------------------------------------------------- required time -1.296 arrival time 1.332 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.040ns (arrival time - required time) Source: SFP_GEN[3].rx_data_ngccm_reg[3][82]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[82]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.157ns (logic 0.048ns (30.573%) route 0.109ns (69.427%)) Logic Levels: 0 Clock Path Skew: 0.061ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.416ns Source Clock Delay (SCD): 1.166ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 1.048ns (routing 0.527ns, distribution 0.521ns) Clock Net Delay (Destination): 1.251ns (routing 0.593ns, distribution 0.658ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.048 1.166 RX_WORDCLK_O[3] SLICE_X80Y100 FDCE r SFP_GEN[3].rx_data_ngccm_reg[3][82]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y100 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.214 r SFP_GEN[3].rx_data_ngccm_reg[3][82]/Q net (fo=1, routed) 0.109 1.323 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]_0[74] SLICE_X80Y102 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[82]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.251 1.416 SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y102 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[82]/C clock pessimism -0.189 1.227 SLICE_X80Y102 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.283 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[82] ------------------------------------------------------------------- required time -1.283 arrival time 1.323 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.080ns (45.714%) route 0.095ns (54.286%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.420ns Source Clock Delay (SCD): 1.189ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.071ns (routing 0.527ns, distribution 0.544ns) Clock Net Delay (Destination): 1.255ns (routing 0.593ns, distribution 0.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.071 1.189 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X84Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y101 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.238 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Q net (fo=28, routed) 0.079 1.317 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] SLICE_X85Y101 LUT5 (Prop_D6LUT_SLICEM_I0_O) 0.031 1.348 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter[2]_i_1__11/O net (fo=1, routed) 0.016 1.364 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter[2] SLICE_X85Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.255 1.420 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X85Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C clock pessimism -0.156 1.264 SLICE_X85Y101 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.320 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] ------------------------------------------------------------------- required time -1.320 arrival time 1.364 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.080ns (45.714%) route 0.095ns (54.286%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.416ns Source Clock Delay (SCD): 1.186ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.068ns (routing 0.527ns, distribution 0.541ns) Clock Net Delay (Destination): 1.251ns (routing 0.593ns, distribution 0.658ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.068 1.186 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y104 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y104 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.234 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=9, routed) 0.079 1.313 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/Q[1] SLICE_X89Y104 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.032 1.345 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[0]_i_1__2/O net (fo=1, routed) 0.016 1.361 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/D[0] SLICE_X89Y104 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.251 1.416 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y104 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism -0.156 1.260 SLICE_X89Y104 FDCE (Hold_HFF_SLICEM_C_D) 0.056 1.316 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time -1.316 arrival time 1.361 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[27]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.048ns (33.103%) route 0.097ns (66.897%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.427ns Source Clock Delay (SCD): 1.192ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.074ns (routing 0.527ns, distribution 0.547ns) Clock Net Delay (Destination): 1.262ns (routing 0.593ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.074 1.192 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X84Y100 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y100 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.240 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]/Q net (fo=1, routed) 0.097 1.337 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[27] SLICE_X84Y98 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.262 1.427 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X84Y98 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[27]/C clock pessimism -0.190 1.237 SLICE_X84Y98 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.292 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[27] ------------------------------------------------------------------- required time -1.292 arrival time 1.337 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].rx_data_ngccm_reg[3][71]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.422ns Source Clock Delay (SCD): 1.187ns Clock Pessimism Removal (CPR): 0.197ns Clock Net Delay (Source): 1.069ns (routing 0.527ns, distribution 0.542ns) Clock Net Delay (Destination): 1.257ns (routing 0.593ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.069 1.187 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X83Y94 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X83Y94 FDRE (Prop_BFF2_SLICEM_C_Q) 0.048 1.235 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/Q net (fo=1, routed) 0.094 1.329 rx_data[3][71] SLICE_X84Y94 FDCE r SFP_GEN[3].rx_data_ngccm_reg[3][71]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.257 1.422 RX_WORDCLK_O[3] SLICE_X84Y94 FDCE r SFP_GEN[3].rx_data_ngccm_reg[3][71]/C clock pessimism -0.197 1.225 SLICE_X84Y94 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.281 SFP_GEN[3].rx_data_ngccm_reg[3][71] ------------------------------------------------------------------- required time -1.281 arrival time 1.329 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.095ns (64.626%) route 0.052ns (35.374%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.414ns Source Clock Delay (SCD): 1.175ns Clock Pessimism Removal (CPR): 0.198ns Clock Net Delay (Source): 1.057ns (routing 0.527ns, distribution 0.530ns) Clock Net Delay (Destination): 1.249ns (routing 0.593ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.057 1.175 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X79Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y101 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.224 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.036 1.260 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_3_in SLICE_X79Y101 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.046 1.306 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__2/O net (fo=1, routed) 0.016 1.322 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] SLICE_X79Y101 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.249 1.414 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X79Y101 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.198 1.216 SLICE_X79Y101 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.272 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.272 arrival time 1.322 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.412ns Source Clock Delay (SCD): 1.175ns Clock Pessimism Removal (CPR): 0.198ns Clock Net Delay (Source): 1.057ns (routing 0.527ns, distribution 0.530ns) Clock Net Delay (Destination): 1.247ns (routing 0.593ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.057 1.175 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X80Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y101 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.224 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.035 1.259 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_5_in SLICE_X80Y101 LUT3 (Prop_H6LUT_SLICEL_I2_O) 0.045 1.304 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__2/O net (fo=1, routed) 0.016 1.320 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] SLICE_X80Y101 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.247 1.412 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X80Y101 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.198 1.214 SLICE_X80Y101 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.270 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.270 arrival time 1.320 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[2]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[3]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.093ns (62.838%) route 0.055ns (37.162%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.449ns Source Clock Delay (SCD): 1.206ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.088ns (routing 0.527ns, distribution 0.561ns) Clock Net Delay (Destination): 1.284ns (routing 0.593ns, distribution 0.691ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.088 1.206 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y105 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y105 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.254 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[2]/Q net (fo=5, routed) 0.039 1.293 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/timer[2] SLICE_X93Y105 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.045 1.338 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer[3]_i_1__3/O net (fo=1, routed) 0.016 1.354 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer[3]_i_1__3_n_0 SLICE_X93Y105 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.284 1.449 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y105 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[3]/C clock pessimism -0.201 1.248 SLICE_X93Y105 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.304 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[3] ------------------------------------------------------------------- required time -1.304 arrival time 1.354 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.427ns Source Clock Delay (SCD): 1.192ns Clock Pessimism Removal (CPR): 0.230ns Clock Net Delay (Source): 1.074ns (routing 0.527ns, distribution 0.547ns) Clock Net Delay (Destination): 1.262ns (routing 0.593ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.074 1.192 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X86Y112 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y112 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.241 r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/Q net (fo=9, routed) 0.035 1.276 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gbtBank_Clk_gen[3].cnt_reg[3][7]_0[3] SLICE_X86Y112 LUT6 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.291 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gbtBank_Clk_gen[3].cnt[3][3]_i_1/O net (fo=1, routed) 0.012 1.303 g_gbt_bank[0].gbtbank/i_gbt_bank_n_253 SLICE_X86Y112 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.262 1.427 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X86Y112 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C clock pessimism -0.230 1.197 SLICE_X86Y112 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.253 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3] ------------------------------------------------------------------- required time -1.253 arrival time 1.303 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_5 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y27 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X86Y112 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X86Y112 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X86Y112 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X86Y112 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X86Y112 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X86Y114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X86Y114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X86Y112 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X86Y112 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X86Y112 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X86Y114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X86Y114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X86Y114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y105 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y105 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y100 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X90Y100 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X85Y99 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X85Y99 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_6 To Clock: gtwiz_userclk_rx_srcclk_out[0]_6 Setup : 0 Failing Endpoints, Worst Slack 2.853ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.044ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.485ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.853ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.435ns (logic 1.396ns (25.685%) route 4.039ns (74.315%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.667ns = ( 10.984 - 8.317 ) Source Clock Delay (SCD): 2.831ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.718ns, distribution 1.638ns) Clock Net Delay (Destination): 2.269ns (routing 0.653ns, distribution 1.616ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.831 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.992 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.185 7.177 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X90Y134 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.267 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.178 7.445 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X90Y135 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.535 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3/O net (fo=1, routed) 0.269 7.804 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3_n_0 SLICE_X90Y136 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.055 7.859 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3/O net (fo=2, routed) 0.407 8.266 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3_n_0 SLICE_X90Y134 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.269 10.984 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y134 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.224 11.209 clock uncertainty -0.035 11.173 SLICE_X90Y134 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 11.119 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.119 arrival time -8.266 ------------------------------------------------------------------- slack 2.853 Slack (MET) : 2.853ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.435ns (logic 1.396ns (25.685%) route 4.039ns (74.315%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.667ns = ( 10.984 - 8.317 ) Source Clock Delay (SCD): 2.831ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.718ns, distribution 1.638ns) Clock Net Delay (Destination): 2.269ns (routing 0.653ns, distribution 1.616ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.831 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.992 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.185 7.177 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X90Y134 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.267 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.178 7.445 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X90Y135 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.535 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3/O net (fo=1, routed) 0.269 7.804 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3_n_0 SLICE_X90Y136 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.055 7.859 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3/O net (fo=2, routed) 0.407 8.266 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3_n_0 SLICE_X90Y134 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.269 10.984 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y134 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.224 11.209 clock uncertainty -0.035 11.173 SLICE_X90Y134 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 11.119 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.119 arrival time -8.266 ------------------------------------------------------------------- slack 2.853 Slack (MET) : 2.958ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.311ns (logic 1.397ns (26.304%) route 3.914ns (73.696%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.649ns = ( 10.966 - 8.317 ) Source Clock Delay (SCD): 2.831ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.718ns, distribution 1.638ns) Clock Net Delay (Destination): 2.251ns (routing 0.653ns, distribution 1.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.831 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.992 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.185 7.177 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X90Y134 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.267 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.200 7.467 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X90Y136 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.613 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__4/O net (fo=3, routed) 0.529 8.142 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 SLICE_X90Y136 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.251 10.966 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y136 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.224 11.191 clock uncertainty -0.035 11.155 SLICE_X90Y136 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.100 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.100 arrival time -8.142 ------------------------------------------------------------------- slack 2.958 Slack (MET) : 2.962ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.308ns (logic 1.397ns (26.319%) route 3.911ns (73.681%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.649ns = ( 10.966 - 8.317 ) Source Clock Delay (SCD): 2.831ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.718ns, distribution 1.638ns) Clock Net Delay (Destination): 2.251ns (routing 0.653ns, distribution 1.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.831 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.992 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.185 7.177 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X90Y134 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.267 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.200 7.467 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X90Y136 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.613 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__4/O net (fo=3, routed) 0.526 8.139 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 SLICE_X90Y136 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.251 10.966 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y136 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.224 11.191 clock uncertainty -0.035 11.155 SLICE_X90Y136 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.101 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.101 arrival time -8.139 ------------------------------------------------------------------- slack 2.962 Slack (MET) : 2.963ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.305ns (logic 1.424ns (26.843%) route 3.881ns (73.157%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.041ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.648ns = ( 10.965 - 8.317 ) Source Clock Delay (SCD): 2.831ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.718ns, distribution 1.638ns) Clock Net Delay (Destination): 2.250ns (routing 0.653ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.831 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.992 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.185 7.177 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X90Y134 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.267 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.189 7.456 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X90Y135 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.629 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/O net (fo=5, routed) 0.507 8.136 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X90Y138 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.250 10.965 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y138 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.224 11.190 clock uncertainty -0.035 11.154 SLICE_X90Y138 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.099 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.099 arrival time -8.136 ------------------------------------------------------------------- slack 2.963 Slack (MET) : 2.963ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.305ns (logic 1.424ns (26.843%) route 3.881ns (73.157%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.041ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.648ns = ( 10.965 - 8.317 ) Source Clock Delay (SCD): 2.831ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.718ns, distribution 1.638ns) Clock Net Delay (Destination): 2.250ns (routing 0.653ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.831 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.992 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.185 7.177 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X90Y134 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.267 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.189 7.456 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X90Y135 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.629 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/O net (fo=5, routed) 0.507 8.136 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X90Y138 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.250 10.965 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y138 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.224 11.190 clock uncertainty -0.035 11.154 SLICE_X90Y138 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.099 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.099 arrival time -8.136 ------------------------------------------------------------------- slack 2.963 Slack (MET) : 2.967ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.302ns (logic 1.424ns (26.858%) route 3.878ns (73.142%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.041ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.648ns = ( 10.965 - 8.317 ) Source Clock Delay (SCD): 2.831ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.718ns, distribution 1.638ns) Clock Net Delay (Destination): 2.250ns (routing 0.653ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.831 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.992 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.185 7.177 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X90Y134 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.267 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.189 7.456 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X90Y135 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.629 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/O net (fo=5, routed) 0.504 8.133 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X90Y138 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.250 10.965 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y138 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.224 11.190 clock uncertainty -0.035 11.154 SLICE_X90Y138 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.100 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.100 arrival time -8.133 ------------------------------------------------------------------- slack 2.967 Slack (MET) : 2.967ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.302ns (logic 1.424ns (26.858%) route 3.878ns (73.142%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.041ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.648ns = ( 10.965 - 8.317 ) Source Clock Delay (SCD): 2.831ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.718ns, distribution 1.638ns) Clock Net Delay (Destination): 2.250ns (routing 0.653ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.831 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.992 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.185 7.177 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X90Y134 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.267 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.189 7.456 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X90Y135 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.629 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/O net (fo=5, routed) 0.504 8.133 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X90Y138 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.250 10.965 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y138 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.224 11.190 clock uncertainty -0.035 11.154 SLICE_X90Y138 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.100 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.100 arrival time -8.133 ------------------------------------------------------------------- slack 2.967 Slack (MET) : 2.977ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.289ns (logic 1.424ns (26.924%) route 3.865ns (73.076%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.039ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.646ns = ( 10.963 - 8.317 ) Source Clock Delay (SCD): 2.831ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.718ns, distribution 1.638ns) Clock Net Delay (Destination): 2.248ns (routing 0.653ns, distribution 1.595ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.831 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.992 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.185 7.177 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X90Y134 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.267 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.189 7.456 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X90Y135 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.629 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/O net (fo=5, routed) 0.491 8.120 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X90Y138 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.248 10.963 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y138 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.224 11.188 clock uncertainty -0.035 11.152 SLICE_X90Y138 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.097 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.097 arrival time -8.120 ------------------------------------------------------------------- slack 2.977 Slack (MET) : 3.053ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 5.219ns (logic 1.306ns (25.024%) route 3.913ns (74.976%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.045ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.652ns = ( 10.969 - 8.317 ) Source Clock Delay (SCD): 2.831ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.718ns, distribution 1.638ns) Clock Net Delay (Destination): 2.254ns (routing 0.653ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.831 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.992 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.185 7.177 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X90Y134 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.267 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/O net (fo=5, routed) 0.204 7.471 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X90Y136 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.055 7.526 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/O net (fo=7, routed) 0.524 8.050 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X91Y133 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.254 10.969 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y133 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.224 11.194 clock uncertainty -0.035 11.158 SLICE_X91Y133 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.103 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.103 arrival time -8.050 ------------------------------------------------------------------- slack 3.053 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].rx_data_ngccm_reg[4][54]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.048ns (27.586%) route 0.126ns (72.414%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.312ns Source Clock Delay (SCD): 1.085ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 0.967ns (routing 0.305ns, distribution 0.662ns) Clock Net Delay (Destination): 1.147ns (routing 0.344ns, distribution 0.803ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.085 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X90Y121 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X90Y121 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.133 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/Q net (fo=1, routed) 0.126 1.259 rx_data[4][54] SLICE_X89Y121 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][54]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.312 RX_WORDCLK_O[4] SLICE_X89Y121 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][54]/C clock pessimism -0.152 1.160 SLICE_X89Y121 FDCE (Hold_FFF2_SLICEM_C_D) 0.055 1.215 SFP_GEN[4].rx_data_ngccm_reg[4][54] ------------------------------------------------------------------- required time -1.215 arrival time 1.259 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].rx_data_ngccm_reg[4][48]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.049ns (26.776%) route 0.134ns (73.224%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.103ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.985ns (routing 0.305ns, distribution 0.680ns) Clock Net Delay (Destination): 1.172ns (routing 0.344ns, distribution 0.828ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.103 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X87Y123 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y123 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 1.152 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.134 1.286 rx_data[4][48] SLICE_X86Y121 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][48]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.337 RX_WORDCLK_O[4] SLICE_X86Y121 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][48]/C clock pessimism -0.151 1.186 SLICE_X86Y121 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.242 SFP_GEN[4].rx_data_ngccm_reg[4][48] ------------------------------------------------------------------- required time -1.242 arrival time 1.286 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.333ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 0.983ns (routing 0.305ns, distribution 0.678ns) Clock Net Delay (Destination): 1.168ns (routing 0.344ns, distribution 0.824ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.101 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X88Y121 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y121 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.150 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.034 1.184 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_13_in SLICE_X88Y121 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.229 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__3/O net (fo=1, routed) 0.016 1.245 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] SLICE_X88Y121 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.168 1.333 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X88Y121 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.190 1.143 SLICE_X88Y121 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.199 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.199 arrival time 1.245 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.048ns (29.814%) route 0.113ns (70.186%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.338ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.177ns Clock Net Delay (Source): 0.984ns (routing 0.305ns, distribution 0.679ns) Clock Net Delay (Destination): 1.173ns (routing 0.344ns, distribution 0.829ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y123 FDCE r SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y123 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.150 r SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6]/Q net (fo=1, routed) 0.113 1.263 SFP_GEN[4].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[3] SLICE_X85Y121 FDRE r SFP_GEN[4].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.173 1.338 SFP_GEN[4].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y121 FDRE r SFP_GEN[4].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C clock pessimism -0.177 1.161 SLICE_X85Y121 FDRE (Hold_AFF2_SLICEM_C_D) 0.056 1.217 SFP_GEN[4].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6] ------------------------------------------------------------------- required time -1.217 arrival time 1.263 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].rx_data_ngccm_reg[4][79]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.048ns (26.087%) route 0.136ns (73.913%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.984ns (routing 0.305ns, distribution 0.679ns) Clock Net Delay (Destination): 1.171ns (routing 0.344ns, distribution 0.827ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X87Y122 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y122 FDRE (Prop_GFF_SLICEM_C_Q) 0.048 1.150 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/Q net (fo=1, routed) 0.136 1.286 rx_data[4][79] SLICE_X85Y122 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][79]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 RX_WORDCLK_O[4] SLICE_X85Y122 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][79]/C clock pessimism -0.151 1.185 SLICE_X85Y122 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.240 SFP_GEN[4].rx_data_ngccm_reg[4][79] ------------------------------------------------------------------- required time -1.240 arrival time 1.286 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].rx_data_ngccm_reg[4][47]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.048ns (26.087%) route 0.136ns (73.913%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.103ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.985ns (routing 0.305ns, distribution 0.680ns) Clock Net Delay (Destination): 1.171ns (routing 0.344ns, distribution 0.827ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.103 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X88Y121 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y121 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.151 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.136 1.287 rx_data[4][47] SLICE_X85Y121 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][47]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 RX_WORDCLK_O[4] SLICE_X85Y121 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][47]/C clock pessimism -0.151 1.185 SLICE_X85Y121 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.240 SFP_GEN[4].rx_data_ngccm_reg[4][47] ------------------------------------------------------------------- required time -1.240 arrival time 1.287 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[33]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[33]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.048ns (33.103%) route 0.097ns (66.897%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.310ns Source Clock Delay (SCD): 1.091ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.973ns (routing 0.305ns, distribution 0.668ns) Clock Net Delay (Destination): 1.145ns (routing 0.344ns, distribution 0.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.973 1.091 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X91Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[33]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y125 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.139 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[33]/Q net (fo=1, routed) 0.097 1.236 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[33] SLICE_X91Y123 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.145 1.310 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X91Y123 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[33]/C clock pessimism -0.178 1.132 SLICE_X91Y123 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.187 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[33] ------------------------------------------------------------------- required time -1.187 arrival time 1.236 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].rx_data_ngccm_reg[4][3]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.048ns (32.877%) route 0.098ns (67.123%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.339ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 0.989ns (routing 0.305ns, distribution 0.684ns) Clock Net Delay (Destination): 1.174ns (routing 0.344ns, distribution 0.830ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X84Y124 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y124 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.155 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.098 1.253 rx_data[4][3] SLICE_X83Y124 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.174 1.339 RX_WORDCLK_O[4] SLICE_X83Y124 FDCE r SFP_GEN[4].rx_data_ngccm_reg[4][3]/C clock pessimism -0.191 1.148 SLICE_X83Y124 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.204 SFP_GEN[4].rx_data_ngccm_reg[4][3] ------------------------------------------------------------------- required time -1.204 arrival time 1.253 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.289ns Source Clock Delay (SCD): 1.073ns Clock Pessimism Removal (CPR): 0.211ns Clock Net Delay (Source): 0.955ns (routing 0.305ns, distribution 0.650ns) Clock Net Delay (Destination): 1.124ns (routing 0.344ns, distribution 0.780ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.955 1.073 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y133 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y133 FDRE (Prop_AFF_SLICEL_C_Q) 0.049 1.122 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Q net (fo=2, routed) 0.035 1.157 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/timer[5] SLICE_X93Y133 LUT6 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.172 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__4/O net (fo=1, routed) 0.012 1.184 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__4_n_0 SLICE_X93Y133 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.124 1.289 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y133 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C clock pessimism -0.211 1.078 SLICE_X93Y133 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.134 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/clkSlipProcess.timer_reg[5] ------------------------------------------------------------------- required time -1.134 arrival time 1.184 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.094ns (63.513%) route 0.054ns (36.486%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.341ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 0.991ns (routing 0.305ns, distribution 0.686ns) Clock Net Delay (Destination): 1.176ns (routing 0.344ns, distribution 0.832ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.109 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X83Y125 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X83Y125 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.158 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.038 1.196 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_7_in SLICE_X83Y125 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.241 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__3/O net (fo=1, routed) 0.016 1.257 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] SLICE_X83Y125 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.176 1.341 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X83Y125 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.191 1.150 SLICE_X83Y125 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.206 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.206 arrival time 1.257 ------------------------------------------------------------------- slack 0.051 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_6 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y57 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X89Y136 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X89Y135 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X89Y136 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X89Y136 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X89Y136 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X88Y135 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X89Y135 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y136 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y136 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y135 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X88Y135 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y135 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y135 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y136 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y136 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y136 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X88Y135 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y135 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y135 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.045 0.485 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.021 0.498 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.021 0.861 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.045 1.283 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_7 To Clock: gtwiz_userclk_rx_srcclk_out[0]_7 Setup : 0 Failing Endpoints, Worst Slack 2.692ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.692ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.591ns (logic 1.590ns (28.439%) route 4.001ns (71.561%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.706ns = ( 11.023 - 8.317 ) Source Clock Delay (SCD): 2.876ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.401ns (routing 0.732ns, distribution 1.669ns) Clock Net Delay (Destination): 2.308ns (routing 0.665ns, distribution 1.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.401 2.876 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.980 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.183 7.163 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X84Y141 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 7.386 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/O net (fo=5, routed) 0.320 7.706 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y141 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.796 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__4/O net (fo=1, routed) 0.084 7.880 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__4_n_0 SLICE_X85Y141 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 8.053 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__4/O net (fo=2, routed) 0.414 8.467 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__4_n_0 SLICE_X83Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.308 11.023 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.226 11.249 clock uncertainty -0.035 11.214 SLICE_X83Y141 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.159 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.159 arrival time -8.467 ------------------------------------------------------------------- slack 2.692 Slack (MET) : 2.692ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.591ns (logic 1.590ns (28.439%) route 4.001ns (71.561%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.706ns = ( 11.023 - 8.317 ) Source Clock Delay (SCD): 2.876ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.401ns (routing 0.732ns, distribution 1.669ns) Clock Net Delay (Destination): 2.308ns (routing 0.665ns, distribution 1.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.401 2.876 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.980 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.183 7.163 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X84Y141 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 7.386 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/O net (fo=5, routed) 0.320 7.706 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y141 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.796 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__4/O net (fo=1, routed) 0.084 7.880 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__4_n_0 SLICE_X85Y141 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 8.053 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__4/O net (fo=2, routed) 0.414 8.467 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__4_n_0 SLICE_X83Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.308 11.023 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.226 11.249 clock uncertainty -0.035 11.214 SLICE_X83Y141 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.159 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.159 arrival time -8.467 ------------------------------------------------------------------- slack 2.692 Slack (MET) : 2.752ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.519ns (logic 1.495ns (27.088%) route 4.024ns (72.912%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.694ns = ( 11.011 - 8.317 ) Source Clock Delay (SCD): 2.876ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.401ns (routing 0.732ns, distribution 1.669ns) Clock Net Delay (Destination): 2.296ns (routing 0.665ns, distribution 1.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.401 2.876 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.980 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.183 7.163 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X84Y141 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 7.386 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/O net (fo=5, routed) 0.326 7.712 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y141 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.168 7.880 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/O net (fo=5, routed) 0.515 8.395 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X84Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.296 11.011 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.226 11.237 clock uncertainty -0.035 11.202 SLICE_X84Y140 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.147 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.147 arrival time -8.395 ------------------------------------------------------------------- slack 2.752 Slack (MET) : 2.757ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.515ns (logic 1.495ns (27.108%) route 4.020ns (72.892%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.694ns = ( 11.011 - 8.317 ) Source Clock Delay (SCD): 2.876ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.401ns (routing 0.732ns, distribution 1.669ns) Clock Net Delay (Destination): 2.296ns (routing 0.665ns, distribution 1.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.401 2.876 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.980 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.183 7.163 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X84Y141 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 7.386 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/O net (fo=5, routed) 0.326 7.712 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y141 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.168 7.880 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/O net (fo=5, routed) 0.511 8.391 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X84Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.296 11.011 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.226 11.237 clock uncertainty -0.035 11.202 SLICE_X84Y140 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 11.148 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.148 arrival time -8.391 ------------------------------------------------------------------- slack 2.757 Slack (MET) : 2.843ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.436ns (logic 1.495ns (27.502%) route 3.941ns (72.498%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.702ns = ( 11.019 - 8.317 ) Source Clock Delay (SCD): 2.876ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.401ns (routing 0.732ns, distribution 1.669ns) Clock Net Delay (Destination): 2.304ns (routing 0.665ns, distribution 1.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.401 2.876 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.980 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.183 7.163 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X84Y141 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 7.386 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/O net (fo=5, routed) 0.326 7.712 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y141 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.168 7.880 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/O net (fo=5, routed) 0.432 8.312 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X85Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.304 11.019 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.226 11.245 clock uncertainty -0.035 11.210 SLICE_X85Y140 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.155 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.155 arrival time -8.312 ------------------------------------------------------------------- slack 2.843 Slack (MET) : 2.843ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.431ns (logic 1.500ns (27.619%) route 3.931ns (72.381%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.700ns = ( 11.017 - 8.317 ) Source Clock Delay (SCD): 2.876ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.401ns (routing 0.732ns, distribution 1.669ns) Clock Net Delay (Destination): 2.302ns (routing 0.665ns, distribution 1.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.401 2.876 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.980 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.183 7.163 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X84Y141 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 7.386 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/O net (fo=5, routed) 0.329 7.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y141 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.173 7.888 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__5/O net (fo=3, routed) 0.419 8.307 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X85Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 11.017 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.226 11.243 clock uncertainty -0.035 11.208 SLICE_X85Y140 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.150 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.150 arrival time -8.307 ------------------------------------------------------------------- slack 2.843 Slack (MET) : 2.847ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.433ns (logic 1.495ns (27.517%) route 3.938ns (72.483%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.702ns = ( 11.019 - 8.317 ) Source Clock Delay (SCD): 2.876ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.401ns (routing 0.732ns, distribution 1.669ns) Clock Net Delay (Destination): 2.304ns (routing 0.665ns, distribution 1.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.401 2.876 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.980 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.183 7.163 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X84Y141 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 7.386 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/O net (fo=5, routed) 0.326 7.712 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y141 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.168 7.880 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/O net (fo=5, routed) 0.429 8.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X85Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.304 11.019 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.226 11.245 clock uncertainty -0.035 11.210 SLICE_X85Y140 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.156 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.156 arrival time -8.309 ------------------------------------------------------------------- slack 2.847 Slack (MET) : 2.847ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.433ns (logic 1.495ns (27.517%) route 3.938ns (72.483%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.702ns = ( 11.019 - 8.317 ) Source Clock Delay (SCD): 2.876ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.401ns (routing 0.732ns, distribution 1.669ns) Clock Net Delay (Destination): 2.304ns (routing 0.665ns, distribution 1.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.401 2.876 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.980 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.183 7.163 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X84Y141 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 7.386 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/O net (fo=5, routed) 0.326 7.712 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y141 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.168 7.880 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__5/O net (fo=5, routed) 0.429 8.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X85Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.304 11.019 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.226 11.245 clock uncertainty -0.035 11.210 SLICE_X85Y140 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.156 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.156 arrival time -8.309 ------------------------------------------------------------------- slack 2.847 Slack (MET) : 2.849ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.428ns (logic 1.500ns (27.634%) route 3.928ns (72.366%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.700ns = ( 11.017 - 8.317 ) Source Clock Delay (SCD): 2.876ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.401ns (routing 0.732ns, distribution 1.669ns) Clock Net Delay (Destination): 2.302ns (routing 0.665ns, distribution 1.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.401 2.876 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.980 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.183 7.163 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X84Y141 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 7.386 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/O net (fo=5, routed) 0.329 7.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y141 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.173 7.888 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__5/O net (fo=3, routed) 0.416 8.304 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X85Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 11.017 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.226 11.243 clock uncertainty -0.035 11.208 SLICE_X85Y140 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.153 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.153 arrival time -8.304 ------------------------------------------------------------------- slack 2.849 Slack (MET) : 2.849ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 5.428ns (logic 1.500ns (27.634%) route 3.928ns (72.366%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.700ns = ( 11.017 - 8.317 ) Source Clock Delay (SCD): 2.876ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.401ns (routing 0.732ns, distribution 1.669ns) Clock Net Delay (Destination): 2.302ns (routing 0.665ns, distribution 1.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.401 2.876 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.980 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.183 7.163 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X84Y141 LUT4 (Prop_D6LUT_SLICEL_I1_O) 0.223 7.386 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__4/O net (fo=5, routed) 0.329 7.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y141 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.173 7.888 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__5/O net (fo=3, routed) 0.416 8.304 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X85Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.302 11.017 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y140 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.226 11.243 clock uncertainty -0.035 11.208 SLICE_X85Y140 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.153 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.153 arrival time -8.304 ------------------------------------------------------------------- slack 2.849 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[24]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[24]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.371ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 1.018ns (routing 0.320ns, distribution 0.698ns) Clock Net Delay (Destination): 1.206ns (routing 0.362ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.136 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X80Y137 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y137 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[24]/Q net (fo=1, routed) 0.095 1.280 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[24] SLICE_X80Y135 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.206 1.371 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X80Y135 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[24]/C clock pessimism -0.183 1.188 SLICE_X80Y135 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.244 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[24] ------------------------------------------------------------------- required time -1.244 arrival time 1.280 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[27]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[27]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.048ns (33.103%) route 0.097ns (66.897%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.368ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 1.018ns (routing 0.320ns, distribution 0.698ns) Clock Net Delay (Destination): 1.203ns (routing 0.362ns, distribution 0.841ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.136 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X80Y137 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y137 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.184 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[27]/Q net (fo=1, routed) 0.097 1.281 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[27] SLICE_X80Y135 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.203 1.368 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X80Y135 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[27]/C clock pessimism -0.183 1.185 SLICE_X80Y135 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.240 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[27] ------------------------------------------------------------------- required time -1.240 arrival time 1.281 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[33]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[33]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.049ns (32.886%) route 0.100ns (67.114%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.368ns Source Clock Delay (SCD): 1.136ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 1.018ns (routing 0.320ns, distribution 0.698ns) Clock Net Delay (Destination): 1.203ns (routing 0.362ns, distribution 0.841ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.136 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X80Y137 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[33]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y137 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.185 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[33]/Q net (fo=1, routed) 0.100 1.285 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[33] SLICE_X80Y135 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.203 1.368 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X80Y135 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[33]/C clock pessimism -0.183 1.185 SLICE_X80Y135 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.240 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[33] ------------------------------------------------------------------- required time -1.240 arrival time 1.285 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][70]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.048ns (31.373%) route 0.105ns (68.627%)) Logic Levels: 0 Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.140ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 1.022ns (routing 0.320ns, distribution 0.702ns) Clock Net Delay (Destination): 1.209ns (routing 0.362ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.140 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X80Y128 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y128 FDRE (Prop_BFF2_SLICEL_C_Q) 0.048 1.188 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.105 1.293 rx_data[5][70] SLICE_X80Y129 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][70]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.209 1.374 RX_WORDCLK_O[5] SLICE_X80Y129 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][70]/C clock pessimism -0.183 1.191 SLICE_X80Y129 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.247 SFP_GEN[5].rx_data_ngccm_reg[5][70] ------------------------------------------------------------------- required time -1.247 arrival time 1.293 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: SFP_GEN[5].rx_data_ngccm_reg[5][45]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[44]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.080ns (45.455%) route 0.096ns (54.545%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.368ns Source Clock Delay (SCD): 1.142ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.024ns (routing 0.320ns, distribution 0.704ns) Clock Net Delay (Destination): 1.203ns (routing 0.362ns, distribution 0.841ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.142 RX_WORDCLK_O[5] SLICE_X77Y128 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][45]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y128 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.191 r SFP_GEN[5].rx_data_ngccm_reg[5][45]/Q net (fo=1, routed) 0.080 1.271 g_gbt_bank[0].gbtbank/RX_Word_rx40_reg[78]_0[21] SLICE_X76Y128 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.031 1.302 r g_gbt_bank[0].gbtbank/RX_Word_rx40[44]_i_1__0/O net (fo=1, routed) 0.016 1.318 SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[83]_0[26] SLICE_X76Y128 FDCE r SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[44]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.203 1.368 SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y128 FDCE r SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[44]/C clock pessimism -0.153 1.215 SLICE_X76Y128 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.271 SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[44] ------------------------------------------------------------------- required time -1.271 arrival time 1.318 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][53]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.049ns (31.410%) route 0.107ns (68.590%)) Logic Levels: 0 Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.140ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 1.022ns (routing 0.320ns, distribution 0.702ns) Clock Net Delay (Destination): 1.209ns (routing 0.362ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.140 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X80Y128 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y128 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.189 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/Q net (fo=1, routed) 0.107 1.296 rx_data[5][53] SLICE_X80Y129 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][53]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.209 1.374 RX_WORDCLK_O[5] SLICE_X80Y129 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][53]/C clock pessimism -0.183 1.191 SLICE_X80Y129 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.247 SFP_GEN[5].rx_data_ngccm_reg[5][53] ------------------------------------------------------------------- required time -1.247 arrival time 1.296 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.094ns (63.946%) route 0.053ns (36.054%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.370ns Source Clock Delay (SCD): 1.134ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.016ns (routing 0.320ns, distribution 0.696ns) Clock Net Delay (Destination): 1.205ns (routing 0.362ns, distribution 0.843ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.134 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X78Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y142 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.183 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.037 1.220 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister[0] SLICE_X78Y142 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.265 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__4/O net (fo=1, routed) 0.016 1.281 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[17] SLICE_X78Y142 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.205 1.370 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X78Y142 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.194 1.176 SLICE_X78Y142 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.232 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.232 arrival time 1.281 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.094ns (63.946%) route 0.053ns (36.054%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.370ns Source Clock Delay (SCD): 1.134ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.016ns (routing 0.320ns, distribution 0.696ns) Clock Net Delay (Destination): 1.205ns (routing 0.362ns, distribution 0.843ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.134 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X78Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y142 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.183 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.037 1.220 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/feedbackRegister[0] SLICE_X78Y142 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.265 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__4/O net (fo=1, routed) 0.016 1.281 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] SLICE_X78Y142 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.205 1.370 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X78Y142 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.194 1.176 SLICE_X78Y142 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.232 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.232 arrival time 1.281 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].rx_data_ngccm_reg[5][20]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.049ns (33.333%) route 0.098ns (66.667%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.368ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.015ns (routing 0.320ns, distribution 0.695ns) Clock Net Delay (Destination): 1.203ns (routing 0.362ns, distribution 0.841ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.133 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X78Y143 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y143 FDRE (Prop_FFF_SLICEL_C_Q) 0.049 1.182 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/Q net (fo=1, routed) 0.098 1.280 rx_data[5][20] SLICE_X77Y143 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.203 1.368 RX_WORDCLK_O[5] SLICE_X77Y143 FDCE r SFP_GEN[5].rx_data_ngccm_reg[5][20]/C clock pessimism -0.194 1.174 SLICE_X77Y143 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.230 SFP_GEN[5].rx_data_ngccm_reg[5][20] ------------------------------------------------------------------- required time -1.230 arrival time 1.280 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.350ns Source Clock Delay (SCD): 1.119ns Clock Pessimism Removal (CPR): 0.226ns Clock Net Delay (Source): 1.001ns (routing 0.320ns, distribution 0.681ns) Clock Net Delay (Destination): 1.185ns (routing 0.362ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.119 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y141 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.168 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.035 1.203 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/ready_from_bitSlipCtrller_5 SLICE_X84Y141 LUT3 (Prop_A6LUT_SLICEL_I2_O) 0.015 1.218 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_i_1__4/O net (fo=1, routed) 0.012 1.230 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_i_1__4_n_0 SLICE_X84Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.350 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/C clock pessimism -0.226 1.124 SLICE_X84Y141 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.180 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.180 arrival time 1.230 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_7 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y51 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y147 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y147 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y146 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y146 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y146 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y146 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X81Y146 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y142 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y142 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y142 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y142 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X80Y145 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X80Y145 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y144 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y144 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X80Y136 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/READY_O_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X80Y136 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y142 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y142 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_8 To Clock: gtwiz_userclk_rx_srcclk_out[0]_8 Setup : 0 Failing Endpoints, Worst Slack 2.280ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.040ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.280ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 6.041ns (logic 1.602ns (26.519%) route 4.439ns (73.481%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.094ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.345ns (routing 0.728ns, distribution 1.617ns) Clock Net Delay (Destination): 2.292ns (routing 0.664ns, distribution 1.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 2.820 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.924 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.266 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X85Y161 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.510 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.521 8.031 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y163 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.088 8.119 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5/O net (fo=1, routed) 0.078 8.197 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5_n_0 SLICE_X84Y163 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 8.363 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5/O net (fo=2, routed) 0.498 8.861 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5_n_0 SLICE_X84Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.292 11.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.224 11.231 clock uncertainty -0.035 11.196 SLICE_X84Y160 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.141 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.141 arrival time -8.861 ------------------------------------------------------------------- slack 2.280 Slack (MET) : 2.280ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 6.041ns (logic 1.602ns (26.519%) route 4.439ns (73.481%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.094ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.345ns (routing 0.728ns, distribution 1.617ns) Clock Net Delay (Destination): 2.292ns (routing 0.664ns, distribution 1.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 2.820 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.924 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.266 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X85Y161 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.510 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.521 8.031 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y163 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.088 8.119 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5/O net (fo=1, routed) 0.078 8.197 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5_n_0 SLICE_X84Y163 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 8.363 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5/O net (fo=2, routed) 0.498 8.861 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5_n_0 SLICE_X84Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.292 11.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.224 11.231 clock uncertainty -0.035 11.196 SLICE_X84Y160 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.141 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.141 arrival time -8.861 ------------------------------------------------------------------- slack 2.280 Slack (MET) : 2.340ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 5.974ns (logic 1.399ns (23.418%) route 4.575ns (76.582%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.087ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.683ns = ( 11.000 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.345ns (routing 0.728ns, distribution 1.617ns) Clock Net Delay (Destination): 2.285ns (routing 0.664ns, distribution 1.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 2.820 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.924 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.266 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X85Y161 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.510 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.655 8.165 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y162 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 8.216 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.578 8.794 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X84Y162 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.285 11.000 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y162 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.224 11.224 clock uncertainty -0.035 11.189 SLICE_X84Y162 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 11.134 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.134 arrival time -8.794 ------------------------------------------------------------------- slack 2.340 Slack (MET) : 2.428ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 5.893ns (logic 1.399ns (23.740%) route 4.494ns (76.260%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.094ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.345ns (routing 0.728ns, distribution 1.617ns) Clock Net Delay (Destination): 2.292ns (routing 0.664ns, distribution 1.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 2.820 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.924 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.266 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X85Y161 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.510 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.655 8.165 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y162 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 8.216 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.497 8.713 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X84Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.292 11.007 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.224 11.231 clock uncertainty -0.035 11.196 SLICE_X84Y161 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 11.141 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.141 arrival time -8.713 ------------------------------------------------------------------- slack 2.428 Slack (MET) : 2.488ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 5.835ns (logic 1.399ns (23.976%) route 4.436ns (76.024%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.692ns = ( 11.009 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.345ns (routing 0.728ns, distribution 1.617ns) Clock Net Delay (Destination): 2.294ns (routing 0.664ns, distribution 1.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 2.820 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.924 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.266 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X85Y161 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.510 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.655 8.165 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y162 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 8.216 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.439 8.655 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X84Y160 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 11.009 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y160 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.224 11.233 clock uncertainty -0.035 11.198 SLICE_X84Y160 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.143 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.143 arrival time -8.655 ------------------------------------------------------------------- slack 2.488 Slack (MET) : 2.493ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 5.830ns (logic 1.399ns (23.997%) route 4.431ns (76.003%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.692ns = ( 11.009 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.345ns (routing 0.728ns, distribution 1.617ns) Clock Net Delay (Destination): 2.294ns (routing 0.664ns, distribution 1.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 2.820 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.924 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.266 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X85Y161 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.510 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.655 8.165 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y162 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 8.216 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.434 8.650 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X84Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 11.009 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.224 11.233 clock uncertainty -0.035 11.198 SLICE_X84Y161 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.143 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.143 arrival time -8.650 ------------------------------------------------------------------- slack 2.493 Slack (MET) : 2.493ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 5.831ns (logic 1.399ns (23.992%) route 4.432ns (76.008%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.692ns = ( 11.009 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.345ns (routing 0.728ns, distribution 1.617ns) Clock Net Delay (Destination): 2.294ns (routing 0.664ns, distribution 1.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 2.820 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.924 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.266 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X85Y161 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.510 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.655 8.165 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y162 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 8.216 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.435 8.651 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X84Y160 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 11.009 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y160 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.224 11.233 clock uncertainty -0.035 11.198 SLICE_X84Y160 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 11.144 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.144 arrival time -8.651 ------------------------------------------------------------------- slack 2.493 Slack (MET) : 2.498ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 5.826ns (logic 1.399ns (24.013%) route 4.427ns (75.987%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.692ns = ( 11.009 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.345ns (routing 0.728ns, distribution 1.617ns) Clock Net Delay (Destination): 2.294ns (routing 0.664ns, distribution 1.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 2.820 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.924 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.266 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X85Y161 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.510 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.655 8.165 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y162 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 8.216 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.430 8.646 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X84Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 11.009 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.224 11.233 clock uncertainty -0.035 11.198 SLICE_X84Y161 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.144 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.144 arrival time -8.646 ------------------------------------------------------------------- slack 2.498 Slack (MET) : 2.498ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 5.826ns (logic 1.399ns (24.013%) route 4.427ns (75.987%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.692ns = ( 11.009 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.345ns (routing 0.728ns, distribution 1.617ns) Clock Net Delay (Destination): 2.294ns (routing 0.664ns, distribution 1.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 2.820 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.924 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.266 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X85Y161 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.510 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.655 8.165 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y162 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 8.216 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.430 8.646 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X84Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 11.009 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.224 11.233 clock uncertainty -0.035 11.198 SLICE_X84Y161 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 11.144 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.144 arrival time -8.646 ------------------------------------------------------------------- slack 2.498 Slack (MET) : 2.734ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 5.582ns (logic 1.566ns (28.054%) route 4.016ns (71.946%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.685ns = ( 11.002 - 8.317 ) Source Clock Delay (SCD): 2.820ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.345ns (routing 0.728ns, distribution 1.617ns) Clock Net Delay (Destination): 2.287ns (routing 0.664ns, distribution 1.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 2.820 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.924 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.342 7.266 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X85Y161 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.510 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/O net (fo=5, routed) 0.406 7.916 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X84Y162 LUT6 (Prop_H6LUT_SLICEL_I0_O) 0.218 8.134 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__6/O net (fo=5, routed) 0.268 8.402 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/consecCorrectHeaders0 SLICE_X84Y162 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.287 11.002 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y162 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.224 11.226 clock uncertainty -0.035 11.191 SLICE_X84Y162 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.136 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.136 arrival time -8.402 ------------------------------------------------------------------- slack 2.734 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].rx_data_ngccm_reg[6][54]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.163ns (logic 0.049ns (30.061%) route 0.114ns (69.939%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.972ns (routing 0.317ns, distribution 0.655ns) Clock Net Delay (Destination): 1.149ns (routing 0.360ns, distribution 0.789ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.090 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X81Y150 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y150 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.139 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/Q net (fo=1, routed) 0.114 1.253 rx_data[6][54] SLICE_X81Y149 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][54]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.149 1.314 RX_WORDCLK_O[6] SLICE_X81Y149 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][54]/C clock pessimism -0.156 1.158 SLICE_X81Y149 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.213 SFP_GEN[6].rx_data_ngccm_reg[6][54] ------------------------------------------------------------------- required time -1.213 arrival time 1.253 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].rx_data_ngccm_reg[6][1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.048ns (30.968%) route 0.107ns (69.032%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.111ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 0.993ns (routing 0.317ns, distribution 0.676ns) Clock Net Delay (Destination): 1.188ns (routing 0.360ns, distribution 0.828ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.111 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X80Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y161 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.107 1.266 rx_data[6][1] SLICE_X80Y162 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 RX_WORDCLK_O[6] SLICE_X80Y162 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][1]/C clock pessimism -0.183 1.170 SLICE_X80Y162 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.226 SFP_GEN[6].rx_data_ngccm_reg[6][1] ------------------------------------------------------------------- required time -1.226 arrival time 1.266 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].rx_data_ngccm_reg[6][3]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.048ns (30.968%) route 0.107ns (69.032%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.111ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 0.993ns (routing 0.317ns, distribution 0.676ns) Clock Net Delay (Destination): 1.188ns (routing 0.360ns, distribution 0.828ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.111 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X80Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y161 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.159 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.107 1.266 rx_data[6][3] SLICE_X80Y162 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 RX_WORDCLK_O[6] SLICE_X80Y162 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][3]/C clock pessimism -0.183 1.170 SLICE_X80Y162 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.226 SFP_GEN[6].rx_data_ngccm_reg[6][3] ------------------------------------------------------------------- required time -1.226 arrival time 1.266 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.166ns (logic 0.079ns (47.590%) route 0.087ns (52.410%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.099ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.981ns (routing 0.317ns, distribution 0.664ns) Clock Net Delay (Destination): 1.157ns (routing 0.360ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.981 1.099 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X78Y152 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y152 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.148 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.073 1.221 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[0] SLICE_X79Y152 LUT3 (Prop_G6LUT_SLICEM_I2_O) 0.030 1.251 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__5/O net (fo=1, routed) 0.014 1.265 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] SLICE_X79Y152 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.322 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X79Y152 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.156 1.166 SLICE_X79Y152 FDRE (Hold_GFF_SLICEM_C_D) 0.056 1.222 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.222 arrival time 1.265 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[86]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[86]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.049ns (32.667%) route 0.101ns (67.333%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.328ns Source Clock Delay (SCD): 1.096ns Clock Pessimism Removal (CPR): 0.182ns Clock Net Delay (Source): 0.978ns (routing 0.317ns, distribution 0.661ns) Clock Net Delay (Destination): 1.163ns (routing 0.360ns, distribution 0.803ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.096 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X85Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[86]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y160 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.145 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[86]/Q net (fo=1, routed) 0.101 1.246 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[86] SLICE_X85Y161 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[86]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.163 1.328 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X85Y161 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[86]/C clock pessimism -0.182 1.146 SLICE_X85Y161 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.201 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[86] ------------------------------------------------------------------- required time -1.201 arrival time 1.246 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.050ns (arrival time - required time) Source: SFP_GEN[6].rx_data_ngccm_reg[6][40]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[40]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.102ns (66.234%) route 0.052ns (33.766%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.991ns (routing 0.317ns, distribution 0.674ns) Clock Net Delay (Destination): 1.178ns (routing 0.360ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.109 RX_WORDCLK_O[6] SLICE_X78Y155 FDCE r SFP_GEN[6].rx_data_ngccm_reg[6][40]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y155 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.158 r SFP_GEN[6].rx_data_ngccm_reg[6][40]/Q net (fo=1, routed) 0.036 1.194 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[83]_0[32] SLICE_X78Y154 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.053 1.247 r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[40]_i_1/O net (fo=1, routed) 0.016 1.263 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 SLICE_X78Y154 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[40]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.343 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y154 FDCE r SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[40]/C clock pessimism -0.186 1.157 SLICE_X78Y154 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.213 SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[40] ------------------------------------------------------------------- required time -1.213 arrival time 1.263 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.192ns Clock Net Delay (Source): 0.991ns (routing 0.317ns, distribution 0.674ns) Clock Net Delay (Destination): 1.172ns (routing 0.360ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.109 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X80Y161 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y161 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.158 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.034 1.192 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X80Y161 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.237 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__5/O net (fo=1, routed) 0.016 1.253 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] SLICE_X80Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.337 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X80Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.192 1.145 SLICE_X80Y161 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.201 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.201 arrival time 1.253 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.114ns (logic 0.064ns (56.140%) route 0.050ns (43.860%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.341ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.229ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.176ns (routing 0.360ns, distribution 0.816ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y161 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.156 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/Q net (fo=3, routed) 0.035 1.191 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/sel0[4] SLICE_X84Y161 LUT6 (Prop_B6LUT_SLICEL_I5_O) 0.015 1.206 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[4]_i_1__6/O net (fo=1, routed) 0.015 1.221 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[4]_i_1__6_n_0 SLICE_X84Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.176 1.341 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y161 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism -0.229 1.112 SLICE_X84Y161 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.168 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time -1.168 arrival time 1.221 ------------------------------------------------------------------- slack 0.053 Slack (MET) : 0.054ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[35]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.048ns (33.103%) route 0.097ns (66.897%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.103ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 0.985ns (routing 0.317ns, distribution 0.668ns) Clock Net Delay (Destination): 1.157ns (routing 0.360ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.103 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X81Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y160 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.151 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]/Q net (fo=1, routed) 0.097 1.248 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[35] SLICE_X81Y158 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.322 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X81Y158 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[35]/C clock pessimism -0.183 1.139 SLICE_X81Y158 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.194 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[35] ------------------------------------------------------------------- required time -1.194 arrival time 1.248 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.054ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.115ns (logic 0.064ns (55.652%) route 0.051ns (44.348%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns Source Clock Delay (SCD): 1.091ns Clock Pessimism Removal (CPR): 0.218ns Clock Net Delay (Source): 0.973ns (routing 0.317ns, distribution 0.656ns) Clock Net Delay (Destination): 1.149ns (routing 0.360ns, distribution 0.789ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.973 1.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y159 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X88Y159 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.140 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/Q net (fo=2, routed) 0.035 1.175 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/rxslide_in[0] SLICE_X88Y159 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.015 1.190 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__5/O net (fo=1, routed) 0.016 1.206 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__5_n_0 SLICE_X88Y159 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.149 1.314 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y159 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C clock pessimism -0.218 1.096 SLICE_X88Y159 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.152 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg ------------------------------------------------------------------- required time -1.152 arrival time 1.206 ------------------------------------------------------------------- slack 0.054 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_8 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y53 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y177 g_clock_rate_din[6].ngccm_status_cnt_reg[6][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y168 g_clock_rate_din[6].rx_frameclk_div2_reg[6]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X79Y164 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X79Y164 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X79Y164 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X82Y159 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X82Y159 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y179 g_clock_rate_din[6].ngccm_status_cnt_reg[6][5]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_9 To Clock: gtwiz_userclk_rx_srcclk_out[0]_9 Setup : 0 Failing Endpoints, Worst Slack 3.532ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.038ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.532ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 4.475ns (logic 1.560ns (34.860%) route 2.915ns (65.140%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.298ns = ( 10.615 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.256ns (routing 0.678ns, distribution 1.578ns) Clock Net Delay (Destination): 1.900ns (routing 0.616ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.256 2.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.815 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.080 5.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X108Y175 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.165 6.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/O net (fo=5, routed) 0.286 6.346 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X108Y174 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.088 6.434 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6/O net (fo=1, routed) 0.269 6.703 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6_n_0 SLICE_X109Y174 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.223 6.926 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6/O net (fo=2, routed) 0.280 7.206 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6_n_0 SLICE_X107Y174 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.900 10.615 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y174 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.213 10.828 clock uncertainty -0.035 10.793 SLICE_X107Y174 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 10.738 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.738 arrival time -7.206 ------------------------------------------------------------------- slack 3.532 Slack (MET) : 3.532ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 4.475ns (logic 1.560ns (34.860%) route 2.915ns (65.140%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.298ns = ( 10.615 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.256ns (routing 0.678ns, distribution 1.578ns) Clock Net Delay (Destination): 1.900ns (routing 0.616ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.256 2.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.815 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.080 5.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X108Y175 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.165 6.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/O net (fo=5, routed) 0.286 6.346 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X108Y174 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.088 6.434 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6/O net (fo=1, routed) 0.269 6.703 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6_n_0 SLICE_X109Y174 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.223 6.926 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6/O net (fo=2, routed) 0.280 7.206 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6_n_0 SLICE_X107Y174 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.900 10.615 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y174 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.213 10.828 clock uncertainty -0.035 10.793 SLICE_X107Y174 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.738 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.738 arrival time -7.206 ------------------------------------------------------------------- slack 3.532 Slack (MET) : 3.712ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 4.279ns (logic 1.475ns (34.471%) route 2.804ns (65.529%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.282ns = ( 10.599 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.256ns (routing 0.678ns, distribution 1.578ns) Clock Net Delay (Destination): 1.884ns (routing 0.616ns, distribution 1.268ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.256 2.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.815 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.080 5.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X108Y175 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.165 6.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/O net (fo=5, routed) 0.199 6.259 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y175 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.485 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/O net (fo=7, routed) 0.525 7.010 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X111Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.884 10.599 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.213 10.812 clock uncertainty -0.035 10.777 SLICE_X111Y174 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 10.722 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.722 arrival time -7.010 ------------------------------------------------------------------- slack 3.712 Slack (MET) : 3.717ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 4.275ns (logic 1.475ns (34.503%) route 2.800ns (65.497%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.236ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.282ns = ( 10.599 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.256ns (routing 0.678ns, distribution 1.578ns) Clock Net Delay (Destination): 1.884ns (routing 0.616ns, distribution 1.268ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.256 2.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.815 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.080 5.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X108Y175 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.165 6.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/O net (fo=5, routed) 0.199 6.259 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y175 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.485 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/O net (fo=7, routed) 0.521 7.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X111Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.884 10.599 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.213 10.812 clock uncertainty -0.035 10.777 SLICE_X111Y174 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 10.723 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.723 arrival time -7.006 ------------------------------------------------------------------- slack 3.717 Slack (MET) : 3.824ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 4.184ns (logic 1.396ns (33.365%) route 2.788ns (66.635%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.299ns = ( 10.616 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.256ns (routing 0.678ns, distribution 1.578ns) Clock Net Delay (Destination): 1.901ns (routing 0.616ns, distribution 1.285ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.256 2.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.815 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.080 5.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X108Y175 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.165 6.060 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/O net (fo=5, routed) 0.189 6.249 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X108Y174 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.396 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__7/O net (fo=5, routed) 0.519 6.915 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecCorrectHeaders0 SLICE_X108Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.901 10.616 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.213 10.829 clock uncertainty -0.035 10.794 SLICE_X108Y174 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.739 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 10.739 arrival time -6.915 ------------------------------------------------------------------- slack 3.824 Slack (MET) : 3.893ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 4.107ns (logic 1.475ns (35.914%) route 2.632ns (64.086%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.291ns = ( 10.608 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.256ns (routing 0.678ns, distribution 1.578ns) Clock Net Delay (Destination): 1.893ns (routing 0.616ns, distribution 1.277ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.256 2.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.815 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.080 5.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X108Y175 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.165 6.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/O net (fo=5, routed) 0.199 6.259 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y175 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.485 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/O net (fo=7, routed) 0.353 6.838 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X109Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.893 10.608 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.213 10.821 clock uncertainty -0.035 10.786 SLICE_X109Y174 FDRE (Setup_AFF2_SLICEM_C_CE) -0.055 10.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.731 arrival time -6.838 ------------------------------------------------------------------- slack 3.893 Slack (MET) : 3.893ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 4.107ns (logic 1.475ns (35.914%) route 2.632ns (64.086%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.291ns = ( 10.608 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.256ns (routing 0.678ns, distribution 1.578ns) Clock Net Delay (Destination): 1.893ns (routing 0.616ns, distribution 1.277ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.256 2.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.815 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.080 5.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X108Y175 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.165 6.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/O net (fo=5, routed) 0.199 6.259 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y175 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.485 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/O net (fo=7, routed) 0.353 6.838 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X109Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.893 10.608 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.213 10.821 clock uncertainty -0.035 10.786 SLICE_X109Y174 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 10.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.731 arrival time -6.838 ------------------------------------------------------------------- slack 3.893 Slack (MET) : 3.897ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 4.104ns (logic 1.475ns (35.941%) route 2.629ns (64.059%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.291ns = ( 10.608 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.256ns (routing 0.678ns, distribution 1.578ns) Clock Net Delay (Destination): 1.893ns (routing 0.616ns, distribution 1.277ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.256 2.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.815 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.080 5.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X108Y175 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.165 6.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/O net (fo=5, routed) 0.199 6.259 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y175 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.485 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/O net (fo=7, routed) 0.350 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X109Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.893 10.608 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.213 10.821 clock uncertainty -0.035 10.786 SLICE_X109Y174 FDRE (Setup_AFF_SLICEM_C_CE) -0.054 10.732 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.732 arrival time -6.835 ------------------------------------------------------------------- slack 3.897 Slack (MET) : 3.897ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 4.104ns (logic 1.475ns (35.941%) route 2.629ns (64.059%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.291ns = ( 10.608 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.256ns (routing 0.678ns, distribution 1.578ns) Clock Net Delay (Destination): 1.893ns (routing 0.616ns, distribution 1.277ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.256 2.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.815 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.080 5.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X108Y175 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.165 6.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/O net (fo=5, routed) 0.199 6.259 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y175 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.485 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/O net (fo=7, routed) 0.350 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X109Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.893 10.608 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.213 10.821 clock uncertainty -0.035 10.786 SLICE_X109Y174 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 10.732 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.732 arrival time -6.835 ------------------------------------------------------------------- slack 3.897 Slack (MET) : 3.897ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 4.104ns (logic 1.475ns (35.941%) route 2.629ns (64.059%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.291ns = ( 10.608 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.256ns (routing 0.678ns, distribution 1.578ns) Clock Net Delay (Destination): 1.893ns (routing 0.616ns, distribution 1.277ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.256 2.731 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.815 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.080 5.895 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X108Y175 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.165 6.060 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/O net (fo=5, routed) 0.199 6.259 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y175 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.485 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__7/O net (fo=7, routed) 0.350 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X109Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.893 10.608 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y174 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.213 10.821 clock uncertainty -0.035 10.786 SLICE_X109Y174 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 10.732 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.732 arrival time -6.835 ------------------------------------------------------------------- slack 3.897 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][52]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.171ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 0.835ns (routing 0.297ns, distribution 0.538ns) Clock Net Delay (Destination): 1.006ns (routing 0.341ns, distribution 0.665ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.835 0.953 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X104Y169 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X104Y169 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.002 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.095 1.097 rx_data[7][52] SLICE_X104Y170 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][52]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.006 1.171 RX_WORDCLK_O[7] SLICE_X104Y170 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][52]/C clock pessimism -0.167 1.004 SLICE_X104Y170 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.059 SFP_GEN[7].rx_data_ngccm_reg[7][52] ------------------------------------------------------------------- required time -1.059 arrival time 1.097 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.196ns (logic 0.100ns (51.020%) route 0.096ns (48.980%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.096ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.180ns Source Clock Delay (SCD): 0.951ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 0.833ns (routing 0.297ns, distribution 0.536ns) Clock Net Delay (Destination): 1.015ns (routing 0.341ns, distribution 0.674ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.833 0.951 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X103Y177 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y177 FDCE (Prop_GFF_SLICEM_C_Q) 0.048 0.999 r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/Q net (fo=1, routed) 0.080 1.079 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gbtBank_Clk_gen[7].cnt_reg[7][0]_0[0] SLICE_X101Y177 LUT2 (Prop_C6LUT_SLICEM_I0_O) 0.052 1.131 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gbtBank_Clk_gen[7].rx_clken_sr[7][1]_i_1/O net (fo=1, routed) 0.016 1.147 g_gbt_bank[0].gbtbank/i_gbt_bank_n_322 SLICE_X101Y177 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.180 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X101Y177 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C clock pessimism -0.133 1.047 SLICE_X101Y177 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.103 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1] ------------------------------------------------------------------- required time -1.103 arrival time 1.147 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.094ns (50.538%) route 0.092ns (49.462%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.172ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 0.835ns (routing 0.297ns, distribution 0.538ns) Clock Net Delay (Destination): 1.007ns (routing 0.341ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.835 0.953 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X97Y175 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y175 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.002 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.076 1.078 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_3_in SLICE_X96Y175 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.123 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__6/O net (fo=1, routed) 0.016 1.139 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] SLICE_X96Y175 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.172 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y175 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.133 1.039 SLICE_X96Y175 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.095 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.095 arrival time 1.139 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[25]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.049ns (34.266%) route 0.094ns (65.734%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns Source Clock Delay (SCD): 1.089ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 0.971ns (routing 0.297ns, distribution 0.674ns) Clock Net Delay (Destination): 1.149ns (routing 0.341ns, distribution 0.808ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.971 1.089 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y171 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[25]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y171 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.138 r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[25]/Q net (fo=2, routed) 0.094 1.232 SFP_GEN[7].ngCCM_gbt/gbt_rx_checker/Q[9] SLICE_X94Y172 FDRE r SFP_GEN[7].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.149 1.314 SFP_GEN[7].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y172 FDRE r SFP_GEN[7].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]/C clock pessimism -0.183 1.131 SLICE_X94Y172 FDRE (Hold_HFF2_SLICEL_C_D) 0.056 1.187 SFP_GEN[7].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9] ------------------------------------------------------------------- required time -1.187 arrival time 1.232 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][31]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.168ns Source Clock Delay (SCD): 0.958ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 0.840ns (routing 0.297ns, distribution 0.543ns) Clock Net Delay (Destination): 1.003ns (routing 0.341ns, distribution 0.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.840 0.958 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y169 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y169 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.007 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.095 1.102 rx_data[7][31] SLICE_X96Y170 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][31]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.168 RX_WORDCLK_O[7] SLICE_X96Y170 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][31]/C clock pessimism -0.168 1.000 SLICE_X96Y170 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.055 SFP_GEN[7].rx_data_ngccm_reg[7][31] ------------------------------------------------------------------- required time -1.055 arrival time 1.102 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.049ns (arrival time - required time) Source: SFP_GEN[7].rx_data_ngccm_reg[7][63]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[62]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.187ns (logic 0.103ns (55.080%) route 0.084ns (44.920%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.835ns (routing 0.297ns, distribution 0.538ns) Clock Net Delay (Destination): 1.004ns (routing 0.341ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.835 0.953 RX_WORDCLK_O[7] SLICE_X103Y169 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][63]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y169 FDCE (Prop_GFF_SLICEM_C_Q) 0.048 1.001 r SFP_GEN[7].rx_data_ngccm_reg[7][63]/Q net (fo=1, routed) 0.073 1.074 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[83]_0[55] SLICE_X102Y169 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.055 1.129 r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[62]_i_1/O net (fo=1, routed) 0.011 1.140 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[62]_i_1_n_0 SLICE_X102Y169 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[62]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.169 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y169 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[62]/C clock pessimism -0.134 1.035 SLICE_X102Y169 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.091 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[62] ------------------------------------------------------------------- required time -1.091 arrival time 1.140 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[32]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[32]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.049ns (33.793%) route 0.096ns (66.207%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.179ns Source Clock Delay (SCD): 0.958ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 0.840ns (routing 0.297ns, distribution 0.543ns) Clock Net Delay (Destination): 1.014ns (routing 0.341ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.840 0.958 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X101Y177 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[32]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y177 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.007 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[32]/Q net (fo=1, routed) 0.096 1.103 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[32] SLICE_X102Y177 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.179 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X102Y177 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[32]/C clock pessimism -0.181 0.998 SLICE_X102Y177 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.054 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[32] ------------------------------------------------------------------- required time -1.054 arrival time 1.103 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.104ns (54.450%) route 0.087ns (45.550%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.172ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 0.835ns (routing 0.297ns, distribution 0.538ns) Clock Net Delay (Destination): 1.007ns (routing 0.341ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.835 0.953 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X97Y175 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y175 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.002 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.076 1.078 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_3_in SLICE_X96Y175 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.055 1.133 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__6/O net (fo=1, routed) 0.011 1.144 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[2] SLICE_X96Y175 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.172 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y175 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.133 1.039 SLICE_X96Y175 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.095 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -1.095 arrival time 1.144 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: SFP_GEN[7].rx_data_ngccm_reg[7][58]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[58]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.104ns (55.319%) route 0.084ns (44.681%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.835ns (routing 0.297ns, distribution 0.538ns) Clock Net Delay (Destination): 1.004ns (routing 0.341ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.835 0.953 RX_WORDCLK_O[7] SLICE_X103Y169 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][58]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y169 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.002 r SFP_GEN[7].rx_data_ngccm_reg[7][58]/Q net (fo=1, routed) 0.073 1.075 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[83]_0[50] SLICE_X102Y169 LUT3 (Prop_D5LUT_SLICEL_I1_O) 0.055 1.130 r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[58]_i_1/O net (fo=1, routed) 0.011 1.141 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[58]_i_1_n_0 SLICE_X102Y169 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[58]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.169 SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y169 FDCE r SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[58]/C clock pessimism -0.134 1.035 SLICE_X102Y169 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.091 SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[58] ------------------------------------------------------------------- required time -1.091 arrival time 1.141 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[7].rx_data_ngccm_reg[7][26]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_9 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.049ns (33.333%) route 0.098ns (66.667%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.959ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 0.841ns (routing 0.297ns, distribution 0.544ns) Clock Net Delay (Destination): 1.004ns (routing 0.341ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.841 0.959 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y170 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y170 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.008 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.098 1.106 rx_data[7][26] SLICE_X96Y172 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][26]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.169 RX_WORDCLK_O[7] SLICE_X96Y172 FDCE r SFP_GEN[7].rx_data_ngccm_reg[7][26]/C clock pessimism -0.168 1.001 SLICE_X96Y172 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.056 SFP_GEN[7].rx_data_ngccm_reg[7][26] ------------------------------------------------------------------- required time -1.056 arrival time 1.106 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_9 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y71 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][3]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][4]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][5]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y177 g_clock_rate_din[7].ngccm_status_cnt_reg[7][7]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X73Y178 g_clock_rate_din[7].rx_wordclk_div2_reg[7]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X94Y176 g_clock_rate_din[7].rx_frameclk_div2_reg[7]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X103Y177 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X103Y178 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X103Y178 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y177 SFP_GEN[7].ngccm_status_reg_reg[7][0]/C High Pulse Width Slow FDPE/C n/a 0.275 4.159 3.884 SLICE_X81Y177 SFP_GEN[7].ngccm_status_reg_reg[7][16]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: txoutclk_out[0]_49 To Clock: txoutclk_out[0]_49 Setup : 0 Failing Endpoints, Worst Slack 0.477ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.032ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.407ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.477ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txgearbox_inst/dataWord_reg[23]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.392ns (logic 0.139ns (5.811%) route 2.253ns (94.189%)) Logic Levels: 0 Clock Path Skew: -0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.325ns = ( 4.444 - 3.119 ) Source Clock Delay (SCD): 1.549ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.074ns (routing 0.114ns, distribution 0.960ns) Clock Net Delay (Destination): 0.927ns (routing 0.097ns, distribution 0.830ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.074 1.549 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.688 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 2.253 3.941 i_tcds2_if/txgearbox_inst/SR[0] SLICE_X140Y47 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[23]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.927 4.444 i_tcds2_if/txgearbox_inst/CLK SLICE_X140Y47 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[23]/C clock pessimism 0.105 4.549 clock uncertainty -0.035 4.514 SLICE_X140Y47 FDRE (Setup_DFF_SLICEL_C_R) -0.096 4.418 i_tcds2_if/txgearbox_inst/dataWord_reg[23] ------------------------------------------------------------------- required time 4.418 arrival time -3.941 ------------------------------------------------------------------- slack 0.477 Slack (MET) : 0.480ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[11]/S (rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.394ns (logic 0.139ns (5.806%) route 2.255ns (94.194%)) Logic Levels: 0 Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.330ns = ( 4.449 - 3.119 ) Source Clock Delay (SCD): 1.549ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.074ns (routing 0.114ns, distribution 0.960ns) Clock Net Delay (Destination): 0.932ns (routing 0.097ns, distribution 0.835ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.074 1.549 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.688 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 2.255 3.943 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/SR[0] SLICE_X141Y47 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[11]/S (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.932 4.449 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK SLICE_X141Y47 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[11]/C clock pessimism 0.105 4.554 clock uncertainty -0.035 4.519 SLICE_X141Y47 FDSE (Setup_DFF_SLICEL_C_S) -0.096 4.423 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[11] ------------------------------------------------------------------- required time 4.423 arrival time -3.943 ------------------------------------------------------------------- slack 0.480 Slack (MET) : 0.480ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[26]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.394ns (logic 0.139ns (5.806%) route 2.255ns (94.194%)) Logic Levels: 0 Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.330ns = ( 4.449 - 3.119 ) Source Clock Delay (SCD): 1.549ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.074ns (routing 0.114ns, distribution 0.960ns) Clock Net Delay (Destination): 0.932ns (routing 0.097ns, distribution 0.835ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.074 1.549 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.688 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 2.255 3.943 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/SR[0] SLICE_X141Y47 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[26]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.932 4.449 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK SLICE_X141Y47 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[26]/C clock pessimism 0.105 4.554 clock uncertainty -0.035 4.519 SLICE_X141Y47 FDRE (Setup_CFF_SLICEL_C_R) -0.096 4.423 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[26] ------------------------------------------------------------------- required time 4.423 arrival time -3.943 ------------------------------------------------------------------- slack 0.480 Slack (MET) : 0.480ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[50]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.394ns (logic 0.139ns (5.806%) route 2.255ns (94.194%)) Logic Levels: 0 Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.330ns = ( 4.449 - 3.119 ) Source Clock Delay (SCD): 1.549ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.074ns (routing 0.114ns, distribution 0.960ns) Clock Net Delay (Destination): 0.932ns (routing 0.097ns, distribution 0.835ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.074 1.549 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.688 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 2.255 3.943 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/SR[0] SLICE_X141Y47 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[50]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.932 4.449 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK SLICE_X141Y47 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[50]/C clock pessimism 0.105 4.554 clock uncertainty -0.035 4.519 SLICE_X141Y47 FDRE (Setup_BFF_SLICEL_C_R) -0.096 4.423 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[50] ------------------------------------------------------------------- required time 4.423 arrival time -3.943 ------------------------------------------------------------------- slack 0.480 Slack (MET) : 0.480ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[28]/S (rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.394ns (logic 0.139ns (5.806%) route 2.255ns (94.194%)) Logic Levels: 0 Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.330ns = ( 4.449 - 3.119 ) Source Clock Delay (SCD): 1.549ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.074ns (routing 0.114ns, distribution 0.960ns) Clock Net Delay (Destination): 0.932ns (routing 0.097ns, distribution 0.835ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.074 1.549 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.688 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 2.255 3.943 i_tcds2_if/txdatapath_inst/UPS/FEC5L1/SR[0] SLICE_X141Y47 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[28]/S (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.932 4.449 i_tcds2_if/txdatapath_inst/UPS/FEC5L1/CLK SLICE_X141Y47 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[28]/C clock pessimism 0.105 4.554 clock uncertainty -0.035 4.519 SLICE_X141Y47 FDSE (Setup_AFF_SLICEL_C_S) -0.096 4.423 i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[28] ------------------------------------------------------------------- required time 4.423 arrival time -3.943 ------------------------------------------------------------------- slack 0.480 Slack (MET) : 0.487ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txgearbox_inst/dataWord_reg[27]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.381ns (logic 0.139ns (5.838%) route 2.242ns (94.162%)) Logic Levels: 0 Clock Path Skew: -0.121ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.323ns = ( 4.442 - 3.119 ) Source Clock Delay (SCD): 1.549ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.074ns (routing 0.114ns, distribution 0.960ns) Clock Net Delay (Destination): 0.925ns (routing 0.097ns, distribution 0.828ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.074 1.549 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.688 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 2.242 3.930 i_tcds2_if/txgearbox_inst/SR[0] SLICE_X140Y47 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[27]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.925 4.442 i_tcds2_if/txgearbox_inst/CLK SLICE_X140Y47 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[27]/C clock pessimism 0.105 4.547 clock uncertainty -0.035 4.512 SLICE_X140Y47 FDRE (Setup_HFF_SLICEL_C_R) -0.095 4.417 i_tcds2_if/txgearbox_inst/dataWord_reg[27] ------------------------------------------------------------------- required time 4.417 arrival time -3.930 ------------------------------------------------------------------- slack 0.487 Slack (MET) : 0.595ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/tx_div_reg[1]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.262ns (logic 0.139ns (6.145%) route 2.123ns (93.855%)) Logic Levels: 0 Clock Path Skew: -0.131ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.313ns = ( 4.432 - 3.119 ) Source Clock Delay (SCD): 1.549ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.074ns (routing 0.114ns, distribution 0.960ns) Clock Net Delay (Destination): 0.915ns (routing 0.097ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.074 1.549 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.688 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 2.123 3.811 i_tcds2_if/tx_reset SLICE_X133Y45 FDRE r i_tcds2_if/tx_div_reg[1]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.915 4.432 i_tcds2_if/txusrclk_out SLICE_X133Y45 FDRE r i_tcds2_if/tx_div_reg[1]/C clock pessimism 0.105 4.537 clock uncertainty -0.035 4.502 SLICE_X133Y45 FDRE (Setup_DFF_SLICEL_C_R) -0.096 4.406 i_tcds2_if/tx_div_reg[1] ------------------------------------------------------------------- required time 4.406 arrival time -3.811 ------------------------------------------------------------------- slack 0.595 Slack (MET) : 0.598ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/tx_div_reg[0]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.262ns (logic 0.139ns (6.145%) route 2.123ns (93.855%)) Logic Levels: 0 Clock Path Skew: -0.131ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.313ns = ( 4.432 - 3.119 ) Source Clock Delay (SCD): 1.549ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.074ns (routing 0.114ns, distribution 0.960ns) Clock Net Delay (Destination): 0.915ns (routing 0.097ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.074 1.549 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.688 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 2.123 3.811 i_tcds2_if/tx_reset SLICE_X133Y45 FDRE r i_tcds2_if/tx_div_reg[0]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.915 4.432 i_tcds2_if/txusrclk_out SLICE_X133Y45 FDRE r i_tcds2_if/tx_div_reg[0]/C clock pessimism 0.105 4.537 clock uncertainty -0.035 4.502 SLICE_X133Y45 FDRE (Setup_CFF2_SLICEL_C_R) -0.093 4.409 i_tcds2_if/tx_div_reg[0] ------------------------------------------------------------------- required time 4.409 arrival time -3.811 ------------------------------------------------------------------- slack 0.598 Slack (MET) : 0.598ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/tx_div_reg[2]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.262ns (logic 0.139ns (6.145%) route 2.123ns (93.855%)) Logic Levels: 0 Clock Path Skew: -0.131ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.313ns = ( 4.432 - 3.119 ) Source Clock Delay (SCD): 1.549ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.074ns (routing 0.114ns, distribution 0.960ns) Clock Net Delay (Destination): 0.915ns (routing 0.097ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.074 1.549 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.688 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 2.123 3.811 i_tcds2_if/tx_reset SLICE_X133Y45 FDRE r i_tcds2_if/tx_div_reg[2]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.915 4.432 i_tcds2_if/txusrclk_out SLICE_X133Y45 FDRE r i_tcds2_if/tx_div_reg[2]/C clock pessimism 0.105 4.537 clock uncertainty -0.035 4.502 SLICE_X133Y45 FDRE (Setup_DFF2_SLICEL_C_R) -0.093 4.409 i_tcds2_if/tx_div_reg[2] ------------------------------------------------------------------- required time 4.409 arrival time -3.811 ------------------------------------------------------------------- slack 0.598 Slack (MET) : 0.621ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[1]/R (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (txoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 2.237ns (logic 0.139ns (6.214%) route 2.098ns (93.786%)) Logic Levels: 0 Clock Path Skew: -0.130ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.314ns = ( 4.433 - 3.119 ) Source Clock Delay (SCD): 1.549ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.074ns (routing 0.114ns, distribution 0.960ns) Clock Net Delay (Destination): 0.916ns (routing 0.097ns, distribution 0.819ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.091 0.091 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 1.074 1.549 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.688 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q net (fo=273, routed) 2.098 3.786 i_tcds2_if/txdatapath_inst/UPS/FEC5L1/SR[0] SLICE_X137Y47 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[1]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 3.119 3.119 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.052 3.171 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 3.517 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.916 4.433 i_tcds2_if/txdatapath_inst/UPS/FEC5L1/CLK SLICE_X137Y47 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[1]/C clock pessimism 0.105 4.538 clock uncertainty -0.035 4.503 SLICE_X137Y47 FDRE (Setup_DFF_SLICEL_C_R) -0.096 4.407 i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[1] ------------------------------------------------------------------- required time 4.407 arrival time -3.786 ------------------------------------------------------------------- slack 0.621 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.032ns (arrival time - required time) Source: i_tcds2_if/prbs_generator/data_o_reg[102]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[44]/D (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.164ns (logic 0.079ns (48.171%) route 0.085ns (51.829%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.673ns Source Clock Delay (SCD): 0.528ns Clock Pessimism Removal (CPR): 0.069ns Clock Net Delay (Source): 0.410ns (routing 0.059ns, distribution 0.351ns) Clock Net Delay (Destination): 0.508ns (routing 0.075ns, distribution 0.433ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.410 0.528 i_tcds2_if/prbs_generator/CLK SLICE_X133Y48 FDRE r i_tcds2_if/prbs_generator/data_o_reg[102]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y48 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 0.577 r i_tcds2_if/prbs_generator/data_o_reg[102]/Q net (fo=1, routed) 0.070 0.647 i_tcds2_if/txdatapath_inst/UPS/FEC5L1/Q[34] SLICE_X134Y48 LUT6 (Prop_B6LUT_SLICEL_I2_O) 0.030 0.677 r i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData[44]_i_1__1/O net (fo=1, routed) 0.015 0.692 i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData[44]_i_1__1_n_0 SLICE_X134Y48 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[44]/D ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.508 0.673 i_tcds2_if/txdatapath_inst/UPS/FEC5L1/CLK SLICE_X134Y48 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[44]/C clock pessimism -0.069 0.604 SLICE_X134Y48 FDRE (Hold_BFF_SLICEL_C_D) 0.056 0.660 i_tcds2_if/txdatapath_inst/UPS/FEC5L1/scrambledData_reg[44] ------------------------------------------------------------------- required time -0.660 arrival time 0.692 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.035ns (arrival time - required time) Source: i_tcds2_if/prbs_generator/node_ff_reg[2]/C (rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/prbs_generator/data_o_reg[136]/D (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.078ns (46.707%) route 0.089ns (53.293%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.673ns Source Clock Delay (SCD): 0.528ns Clock Pessimism Removal (CPR): 0.069ns Clock Net Delay (Source): 0.410ns (routing 0.059ns, distribution 0.351ns) Clock Net Delay (Destination): 0.508ns (routing 0.075ns, distribution 0.433ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.410 0.528 i_tcds2_if/prbs_generator/CLK SLICE_X133Y56 FDSE r i_tcds2_if/prbs_generator/node_ff_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y56 FDSE (Prop_HFF_SLICEL_C_Q) 0.048 0.576 r i_tcds2_if/prbs_generator/node_ff_reg[2]/Q net (fo=47, routed) 0.075 0.651 i_tcds2_if/prbs_generator/node_array[1]_15[1] SLICE_X134Y56 LUT6 (Prop_G6LUT_SLICEL_I1_O) 0.030 0.681 r i_tcds2_if/prbs_generator/data_o[136]_i_1/O net (fo=1, routed) 0.014 0.695 i_tcds2_if/prbs_generator/node_array[134]_23[2] SLICE_X134Y56 FDRE r i_tcds2_if/prbs_generator/data_o_reg[136]/D ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.508 0.673 i_tcds2_if/prbs_generator/CLK SLICE_X134Y56 FDRE r i_tcds2_if/prbs_generator/data_o_reg[136]/C clock pessimism -0.069 0.604 SLICE_X134Y56 FDRE (Hold_GFF_SLICEL_C_D) 0.056 0.660 i_tcds2_if/prbs_generator/data_o_reg[136] ------------------------------------------------------------------- required time -0.660 arrival time 0.695 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.037ns (arrival time - required time) Source: i_tcds2_if/prbs_generator/data_o_reg[119]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData_reg[42]/D (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.166ns (logic 0.079ns (47.590%) route 0.087ns (52.410%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.674ns Source Clock Delay (SCD): 0.532ns Clock Pessimism Removal (CPR): 0.069ns Clock Net Delay (Source): 0.414ns (routing 0.059ns, distribution 0.355ns) Clock Net Delay (Destination): 0.509ns (routing 0.075ns, distribution 0.434ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.414 0.532 i_tcds2_if/prbs_generator/CLK SLICE_X139Y57 FDRE r i_tcds2_if/prbs_generator/data_o_reg[119]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y57 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 0.580 r i_tcds2_if/prbs_generator/data_o_reg[119]/Q net (fo=2, routed) 0.071 0.651 i_tcds2_if/txdatapath_inst/UPS/FEC5H0/Q[2] SLICE_X140Y57 LUT6 (Prop_H6LUT_SLICEL_I1_O) 0.031 0.682 r i_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData[42]_i_1__0/O net (fo=1, routed) 0.016 0.698 i_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData[42]_i_1__0_n_0 SLICE_X140Y57 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData_reg[42]/D ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.509 0.674 i_tcds2_if/txdatapath_inst/UPS/FEC5H0/CLK SLICE_X140Y57 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData_reg[42]/C clock pessimism -0.069 0.605 SLICE_X140Y57 FDRE (Hold_HFF_SLICEL_C_D) 0.056 0.661 i_tcds2_if/txdatapath_inst/UPS/FEC5H0/scrambledData_reg[42] ------------------------------------------------------------------- required time -0.661 arrival time 0.698 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.040ns (arrival time - required time) Source: i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[1]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[40]/D (rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.064ns (41.558%) route 0.090ns (58.442%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.674ns Source Clock Delay (SCD): 0.526ns Clock Pessimism Removal (CPR): 0.090ns Clock Net Delay (Source): 0.408ns (routing 0.059ns, distribution 0.349ns) Clock Net Delay (Destination): 0.509ns (routing 0.075ns, distribution 0.434ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.408 0.526 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK SLICE_X141Y44 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y44 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 0.575 r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[1]/Q net (fo=4, routed) 0.074 0.649 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/tx_frame_data[21] SLICE_X141Y45 LUT6 (Prop_D6LUT_SLICEL_I5_O) 0.015 0.664 r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData[40]_i_1__2/O net (fo=1, routed) 0.016 0.680 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData[40]_i_1__2_n_0 SLICE_X141Y45 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[40]/D ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.509 0.674 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK SLICE_X141Y45 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[40]/C clock pessimism -0.090 0.584 SLICE_X141Y45 FDSE (Hold_DFF_SLICEL_C_D) 0.056 0.640 i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[40] ------------------------------------------------------------------- required time -0.640 arrival time 0.680 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[14]/C (rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[53]/D (rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.063ns (43.151%) route 0.083ns (56.849%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.675ns Source Clock Delay (SCD): 0.536ns Clock Pessimism Removal (CPR): 0.090ns Clock Net Delay (Source): 0.418ns (routing 0.059ns, distribution 0.359ns) Clock Net Delay (Destination): 0.510ns (routing 0.075ns, distribution 0.435ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.418 0.536 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK SLICE_X141Y53 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y53 FDSE (Prop_HFF_SLICEL_C_Q) 0.048 0.584 r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[14]/Q net (fo=6, routed) 0.071 0.655 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[59]_0[11] SLICE_X140Y54 LUT6 (Prop_A6LUT_SLICEL_I5_O) 0.015 0.670 r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[53]_i_1/O net (fo=1, routed) 0.012 0.682 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[53]_i_1_n_0 SLICE_X140Y54 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[53]/D ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.510 0.675 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK SLICE_X140Y54 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[53]/C clock pessimism -0.090 0.585 SLICE_X140Y54 FDSE (Hold_AFF_SLICEL_C_D) 0.056 0.641 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[53] ------------------------------------------------------------------- required time -0.641 arrival time 0.682 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: i_tcds2_if/txgearbox_inst/dataWord_reg[28]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[28] (rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.207ns (logic 0.049ns (23.671%) route 0.158ns (76.329%)) Logic Levels: 0 Clock Path Skew: -0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.601ns Source Clock Delay (SCD): 0.525ns Clock Pessimism Removal (CPR): 0.091ns Clock Net Delay (Source): 0.407ns (routing 0.059ns, distribution 0.348ns) Clock Net Delay (Destination): 0.436ns (routing 0.075ns, distribution 0.361ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.407 0.525 i_tcds2_if/txgearbox_inst/CLK SLICE_X142Y49 FDRE r i_tcds2_if/txgearbox_inst/dataWord_reg[28]/C ------------------------------------------------------------------- ------------------- SLICE_X142Y49 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 0.574 r i_tcds2_if/txgearbox_inst/dataWord_reg[28]/Q net (fo=1, routed) 0.158 0.732 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[28] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[28] ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.436 0.601 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.091 0.510 GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[28]) 0.181 0.691 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -0.691 arrival time 0.732 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: i_tcds2_if/prbs_generator/data_o_reg[192]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[57]/D (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.078ns (46.707%) route 0.089ns (53.293%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.666ns Source Clock Delay (SCD): 0.527ns Clock Pessimism Removal (CPR): 0.069ns Clock Net Delay (Source): 0.409ns (routing 0.059ns, distribution 0.350ns) Clock Net Delay (Destination): 0.501ns (routing 0.075ns, distribution 0.426ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.409 0.527 i_tcds2_if/prbs_generator/CLK SLICE_X137Y51 FDRE r i_tcds2_if/prbs_generator/data_o_reg[192]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y51 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 0.575 r i_tcds2_if/prbs_generator/data_o_reg[192]/Q net (fo=2, routed) 0.077 0.652 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/Q[12] SLICE_X139Y51 LUT6 (Prop_E6LUT_SLICEL_I1_O) 0.030 0.682 r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[57]_i_1__0/O net (fo=1, routed) 0.012 0.694 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[57]_i_1__0_n_0 SLICE_X139Y51 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[57]/D ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.501 0.666 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK SLICE_X139Y51 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[57]/C clock pessimism -0.069 0.597 SLICE_X139Y51 FDRE (Hold_EFF_SLICEL_C_D) 0.056 0.653 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[57] ------------------------------------------------------------------- required time -0.653 arrival time 0.694 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.042ns (arrival time - required time) Source: i_tcds2_if/prbs_generator/data_o_reg[192]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[18]/D (rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.168ns (logic 0.078ns (46.429%) route 0.090ns (53.571%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.666ns Source Clock Delay (SCD): 0.527ns Clock Pessimism Removal (CPR): 0.069ns Clock Net Delay (Source): 0.409ns (routing 0.059ns, distribution 0.350ns) Clock Net Delay (Destination): 0.501ns (routing 0.075ns, distribution 0.426ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.409 0.527 i_tcds2_if/prbs_generator/CLK SLICE_X137Y51 FDRE r i_tcds2_if/prbs_generator/data_o_reg[192]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y51 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 0.575 r i_tcds2_if/prbs_generator/data_o_reg[192]/Q net (fo=2, routed) 0.078 0.653 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/Q[12] SLICE_X139Y51 LUT4 (Prop_F6LUT_SLICEL_I1_O) 0.030 0.683 r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[18]_i_1/O net (fo=1, routed) 0.012 0.695 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[18]_i_1_n_0 SLICE_X139Y51 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[18]/D ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.501 0.666 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK SLICE_X139Y51 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[18]/C clock pessimism -0.069 0.597 SLICE_X139Y51 FDSE (Hold_FFF_SLICEL_C_D) 0.056 0.653 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[18] ------------------------------------------------------------------- required time -0.653 arrival time 0.695 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.042ns (arrival time - required time) Source: i_tcds2_if/prbs_generator/data_o_reg[214]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[40]/D (rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.157ns (logic 0.064ns (40.764%) route 0.093ns (59.236%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.662ns Source Clock Delay (SCD): 0.534ns Clock Pessimism Removal (CPR): 0.069ns Clock Net Delay (Source): 0.416ns (routing 0.059ns, distribution 0.357ns) Clock Net Delay (Destination): 0.497ns (routing 0.075ns, distribution 0.422ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.416 0.534 i_tcds2_if/prbs_generator/CLK SLICE_X135Y53 FDRE r i_tcds2_if/prbs_generator/data_o_reg[214]/C ------------------------------------------------------------------- ------------------- SLICE_X135Y53 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 0.583 r i_tcds2_if/prbs_generator/data_o_reg[214]/Q net (fo=1, routed) 0.077 0.660 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/Q[31] SLICE_X137Y53 LUT6 (Prop_C6LUT_SLICEL_I2_O) 0.015 0.675 r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[40]_i_1/O net (fo=1, routed) 0.016 0.691 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[40]_i_1_n_0 SLICE_X137Y53 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[40]/D ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.497 0.662 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK SLICE_X137Y53 FDSE r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[40]/C clock pessimism -0.069 0.593 SLICE_X137Y53 FDSE (Hold_CFF_SLICEL_C_D) 0.056 0.649 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[40] ------------------------------------------------------------------- required time -0.649 arrival time 0.691 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[28]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[9]/D (rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: txoutclk_out[0]_49 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.079ns (46.471%) route 0.091ns (53.529%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.678ns Source Clock Delay (SCD): 0.538ns Clock Pessimism Removal (CPR): 0.069ns Clock Net Delay (Source): 0.420ns (routing 0.059ns, distribution 0.361ns) Clock Net Delay (Destination): 0.513ns (routing 0.075ns, distribution 0.438ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.018 0.018 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.420 0.538 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK SLICE_X141Y54 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[28]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y54 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 0.587 r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[28]/Q net (fo=7, routed) 0.079 0.666 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[59]_0[23] SLICE_X139Y54 LUT4 (Prop_A6LUT_SLICEL_I2_O) 0.030 0.696 r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[9]_i_1/O net (fo=1, routed) 0.012 0.708 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData[9]_i_1_n_0 SLICE_X139Y54 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[9]/D ------------------------------------------------------------------- ------------------- (clock txoutclk_out[0]_49 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y3 GTHE3_CHANNEL 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=2, routed) 0.035 0.035 i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] BUFG_GT_X1Y9 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=539, routed) 0.513 0.678 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/CLK SLICE_X139Y54 FDRE r i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[9]/C clock pessimism -0.069 0.609 SLICE_X139Y54 FDRE (Hold_AFF_SLICEL_C_D) 0.056 0.665 i_tcds2_if/txdatapath_inst/UPS/FEC5H1/scrambledData_reg[9] ------------------------------------------------------------------- required time -0.665 arrival time 0.708 ------------------------------------------------------------------- slack 0.043 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txoutclk_out[0]_49 Waveform(ns): { 0.000 1.559 } Period(ns): 3.119 Sources: { i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/TXUSRCLK n/a 2.560 3.119 0.559 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Min Period n/a GTHE3_CHANNEL/TXUSRCLK2 n/a 2.560 3.119 0.559 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 3.119 1.532 BUFG_GT_X1Y9 i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X135Y57 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_meta_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X135Y57 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X135Y57 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync1_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X135Y57 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync2_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X135Y57 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X142Y41 i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_meta_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X142Y41 i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_sync_reg/C Low Pulse Width Fast GTHE3_CHANNEL/TXUSRCLK n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/TXUSRCLK2 n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/TXUSRCLK n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/TXUSRCLK2 n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 1.559 1.284 SLICE_X137Y52 i_tcds2_if/prbs_generator/data_o_reg[115]/C Low Pulse Width Slow FDRE/C n/a 0.275 1.559 1.284 SLICE_X133Y53 i_tcds2_if/prbs_generator/data_o_reg[133]/C Low Pulse Width Slow FDRE/C n/a 0.275 1.559 1.284 SLICE_X135Y54 i_tcds2_if/prbs_generator/data_o_reg[141]/C Low Pulse Width Slow FDRE/C n/a 0.275 1.559 1.284 SLICE_X137Y52 i_tcds2_if/prbs_generator/data_o_reg[164]/C Low Pulse Width Slow FDRE/C n/a 0.275 1.559 1.284 SLICE_X137Y53 i_tcds2_if/prbs_generator/data_o_reg[174]/C Low Pulse Width Slow FDRE/C n/a 0.275 1.559 1.284 SLICE_X137Y55 i_tcds2_if/prbs_generator/data_o_reg[186]/C High Pulse Width Slow GTHE3_CHANNEL/TXUSRCLK n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/TXUSRCLK2 n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/TXUSRCLK n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/TXUSRCLK2 n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y57 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_meta_reg/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y57 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_meta_reg/C High Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y57 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y57 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C High Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y57 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync1_reg/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y57 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync1_reg/C Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.020 0.500 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Slow GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.613 0.043 0.570 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Slow GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.864 0.043 0.821 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Max Skew Fast GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.914 0.020 0.894 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_12 To Clock: gtwiz_userclk_rx_srcclk_out[0]_12 Setup : 0 Failing Endpoints, Worst Slack 2.497ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.497ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 5.740ns (logic 1.605ns (27.962%) route 4.135ns (72.038%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.252ns = ( 11.569 - 8.317 ) Source Clock Delay (SCD): 3.533ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.058ns (routing 1.143ns, distribution 1.915ns) Clock Net Delay (Destination): 2.854ns (routing 1.045ns, distribution 1.809ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.058 3.533 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.637 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.384 8.021 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] SLICE_X88Y425 LUT4 (Prop_A6LUT_SLICEL_I1_O) 0.218 8.239 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.184 8.423 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X88Y427 LUT4 (Prop_D5LUT_SLICEL_I2_O) 0.117 8.540 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11/O net (fo=1, routed) 0.137 8.677 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11_n_0 SLICE_X88Y427 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.166 8.843 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11/O net (fo=2, routed) 0.430 9.273 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11_n_0 SLICE_X88Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.854 11.569 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.291 11.860 clock uncertainty -0.035 11.825 SLICE_X88Y425 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.770 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.770 arrival time -9.273 ------------------------------------------------------------------- slack 2.497 Slack (MET) : 2.497ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 5.740ns (logic 1.605ns (27.962%) route 4.135ns (72.038%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.252ns = ( 11.569 - 8.317 ) Source Clock Delay (SCD): 3.533ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.058ns (routing 1.143ns, distribution 1.915ns) Clock Net Delay (Destination): 2.854ns (routing 1.045ns, distribution 1.809ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.058 3.533 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.637 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.384 8.021 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] SLICE_X88Y425 LUT4 (Prop_A6LUT_SLICEL_I1_O) 0.218 8.239 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.184 8.423 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X88Y427 LUT4 (Prop_D5LUT_SLICEL_I2_O) 0.117 8.540 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11/O net (fo=1, routed) 0.137 8.677 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11_n_0 SLICE_X88Y427 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.166 8.843 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11/O net (fo=2, routed) 0.430 9.273 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11_n_0 SLICE_X88Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.854 11.569 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.291 11.860 clock uncertainty -0.035 11.825 SLICE_X88Y425 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.770 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.770 arrival time -9.273 ------------------------------------------------------------------- slack 2.497 Slack (MET) : 2.664ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 5.578ns (logic 1.547ns (27.734%) route 4.031ns (72.266%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.260ns = ( 11.577 - 8.317 ) Source Clock Delay (SCD): 3.533ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.058ns (routing 1.143ns, distribution 1.915ns) Clock Net Delay (Destination): 2.862ns (routing 1.045ns, distribution 1.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.058 3.533 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.637 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.384 8.021 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] SLICE_X88Y425 LUT4 (Prop_A6LUT_SLICEL_I1_O) 0.218 8.239 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.296 8.535 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y427 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.225 8.760 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/O net (fo=5, routed) 0.351 9.111 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.862 11.577 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.291 11.868 clock uncertainty -0.035 11.833 SLICE_X89Y428 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.775 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.775 arrival time -9.111 ------------------------------------------------------------------- slack 2.664 Slack (MET) : 2.664ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 5.578ns (logic 1.547ns (27.734%) route 4.031ns (72.266%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.260ns = ( 11.577 - 8.317 ) Source Clock Delay (SCD): 3.533ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.058ns (routing 1.143ns, distribution 1.915ns) Clock Net Delay (Destination): 2.862ns (routing 1.045ns, distribution 1.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.058 3.533 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.637 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.384 8.021 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] SLICE_X88Y425 LUT4 (Prop_A6LUT_SLICEL_I1_O) 0.218 8.239 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.296 8.535 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y427 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.225 8.760 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/O net (fo=5, routed) 0.351 9.111 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.862 11.577 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.291 11.868 clock uncertainty -0.035 11.833 SLICE_X89Y428 FDRE (Setup_GFF2_SLICEM_C_CE) -0.058 11.775 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.775 arrival time -9.111 ------------------------------------------------------------------- slack 2.664 Slack (MET) : 2.670ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 5.575ns (logic 1.547ns (27.749%) route 4.028ns (72.251%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.260ns = ( 11.577 - 8.317 ) Source Clock Delay (SCD): 3.533ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.058ns (routing 1.143ns, distribution 1.915ns) Clock Net Delay (Destination): 2.862ns (routing 1.045ns, distribution 1.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.058 3.533 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.637 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.384 8.021 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] SLICE_X88Y425 LUT4 (Prop_A6LUT_SLICEL_I1_O) 0.218 8.239 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.296 8.535 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y427 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.225 8.760 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/O net (fo=5, routed) 0.348 9.108 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.862 11.577 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.291 11.868 clock uncertainty -0.035 11.833 SLICE_X89Y428 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.778 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.778 arrival time -9.108 ------------------------------------------------------------------- slack 2.670 Slack (MET) : 2.670ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 5.575ns (logic 1.547ns (27.749%) route 4.028ns (72.251%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.260ns = ( 11.577 - 8.317 ) Source Clock Delay (SCD): 3.533ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.058ns (routing 1.143ns, distribution 1.915ns) Clock Net Delay (Destination): 2.862ns (routing 1.045ns, distribution 1.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.058 3.533 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.637 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.384 8.021 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] SLICE_X88Y425 LUT4 (Prop_A6LUT_SLICEL_I1_O) 0.218 8.239 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.296 8.535 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y427 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.225 8.760 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/O net (fo=5, routed) 0.348 9.108 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.862 11.577 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.291 11.868 clock uncertainty -0.035 11.833 SLICE_X89Y428 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 11.778 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.778 arrival time -9.108 ------------------------------------------------------------------- slack 2.670 Slack (MET) : 2.670ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 5.575ns (logic 1.547ns (27.749%) route 4.028ns (72.251%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.260ns = ( 11.577 - 8.317 ) Source Clock Delay (SCD): 3.533ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.058ns (routing 1.143ns, distribution 1.915ns) Clock Net Delay (Destination): 2.862ns (routing 1.045ns, distribution 1.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.058 3.533 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.637 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.384 8.021 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] SLICE_X88Y425 LUT4 (Prop_A6LUT_SLICEL_I1_O) 0.218 8.239 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.296 8.535 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y427 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.225 8.760 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/O net (fo=5, routed) 0.348 9.108 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.862 11.577 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.291 11.868 clock uncertainty -0.035 11.833 SLICE_X89Y428 FDRE (Setup_FFF_SLICEM_C_CE) -0.055 11.778 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.778 arrival time -9.108 ------------------------------------------------------------------- slack 2.670 Slack (MET) : 2.676ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 5.571ns (logic 1.547ns (27.769%) route 4.024ns (72.231%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.020ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.262ns = ( 11.579 - 8.317 ) Source Clock Delay (SCD): 3.533ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.058ns (routing 1.143ns, distribution 1.915ns) Clock Net Delay (Destination): 2.864ns (routing 1.045ns, distribution 1.819ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.058 3.533 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.637 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.384 8.021 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] SLICE_X88Y425 LUT4 (Prop_A6LUT_SLICEL_I1_O) 0.218 8.239 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.293 8.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y427 LUT6 (Prop_B6LUT_SLICEM_I5_O) 0.225 8.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/O net (fo=3, routed) 0.347 9.104 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecFalseHeaders0 SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.864 11.579 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.291 11.870 clock uncertainty -0.035 11.835 SLICE_X89Y428 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.780 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.780 arrival time -9.104 ------------------------------------------------------------------- slack 2.676 Slack (MET) : 2.680ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 5.568ns (logic 1.547ns (27.784%) route 4.021ns (72.216%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.020ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.262ns = ( 11.579 - 8.317 ) Source Clock Delay (SCD): 3.533ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.058ns (routing 1.143ns, distribution 1.915ns) Clock Net Delay (Destination): 2.864ns (routing 1.045ns, distribution 1.819ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.058 3.533 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.637 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.384 8.021 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] SLICE_X88Y425 LUT4 (Prop_A6LUT_SLICEL_I1_O) 0.218 8.239 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.293 8.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y427 LUT6 (Prop_B6LUT_SLICEM_I5_O) 0.225 8.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/O net (fo=3, routed) 0.344 9.101 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecFalseHeaders0 SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.864 11.579 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.291 11.870 clock uncertainty -0.035 11.835 SLICE_X89Y428 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.781 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.781 arrival time -9.101 ------------------------------------------------------------------- slack 2.680 Slack (MET) : 2.680ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 5.568ns (logic 1.547ns (27.784%) route 4.021ns (72.216%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.020ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.262ns = ( 11.579 - 8.317 ) Source Clock Delay (SCD): 3.533ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.058ns (routing 1.143ns, distribution 1.915ns) Clock Net Delay (Destination): 2.864ns (routing 1.045ns, distribution 1.819ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.058 3.533 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.637 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.384 8.021 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[0] SLICE_X88Y425 LUT4 (Prop_A6LUT_SLICEL_I1_O) 0.218 8.239 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/O net (fo=5, routed) 0.293 8.532 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y427 LUT6 (Prop_B6LUT_SLICEM_I5_O) 0.225 8.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/O net (fo=3, routed) 0.344 9.101 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecFalseHeaders0 SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.864 11.579 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y428 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.291 11.870 clock uncertainty -0.035 11.835 SLICE_X89Y428 FDRE (Setup_AFF_SLICEM_C_CE) -0.054 11.781 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.781 arrival time -9.101 ------------------------------------------------------------------- slack 2.680 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[22]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.429ns (logic 0.122ns (28.438%) route 0.307ns (71.562%)) Logic Levels: 0 Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.732ns Source Clock Delay (SCD): 3.291ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 2.893ns (routing 1.045ns, distribution 1.848ns) Clock Net Delay (Destination): 3.257ns (routing 1.143ns, distribution 2.114ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 0.052 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 0.398 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.893 3.291 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y420 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y420 FDCE (Prop_AFF_SLICEM_C_Q) 0.122 3.413 r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[22]/Q net (fo=5, routed) 0.307 3.720 SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/Q[6] SLICE_X78Y419 FDRE r SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.257 3.732 SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y419 FDRE r SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/C clock pessimism -0.175 3.557 SLICE_X78Y419 FDRE (Hold_GFF2_SLICEL_C_D) 0.128 3.685 SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6] ------------------------------------------------------------------- required time -3.685 arrival time 3.720 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.037ns (arrival time - required time) Source: SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[29]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.049ns (23.445%) route 0.160ns (76.555%)) Logic Levels: 0 Clock Path Skew: 0.117ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.605ns Source Clock Delay (SCD): 1.381ns Clock Pessimism Removal (CPR): 0.107ns Clock Net Delay (Source): 1.263ns (routing 0.484ns, distribution 0.779ns) Clock Net Delay (Destination): 1.440ns (routing 0.544ns, distribution 0.896ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.263 1.381 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y420 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[29]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y420 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.430 r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[29]/Q net (fo=2, routed) 0.160 1.590 SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/Q[13] SLICE_X79Y419 FDRE r SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.440 1.605 SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y419 FDRE r SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/C clock pessimism -0.107 1.498 SLICE_X79Y419 FDRE (Hold_EFF2_SLICEM_C_D) 0.055 1.553 SFP_GEN[12].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13] ------------------------------------------------------------------- required time -1.553 arrival time 1.590 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.039ns (arrival time - required time) Source: SFP_GEN[12].rx_data_ngccm_reg[12][57]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[56]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.113ns (43.462%) route 0.147ns (56.538%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.165ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.603ns Source Clock Delay (SCD): 1.331ns Clock Pessimism Removal (CPR): 0.107ns Clock Net Delay (Source): 1.213ns (routing 0.484ns, distribution 0.729ns) Clock Net Delay (Destination): 1.438ns (routing 0.544ns, distribution 0.894ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.213 1.331 g_gbt_bank[1].gbtbank_n_0 SLICE_X89Y419 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][57]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y419 FDCE (Prop_EFF2_SLICEM_C_Q) 0.048 1.379 r SFP_GEN[12].rx_data_ngccm_reg[12][57]/Q net (fo=1, routed) 0.131 1.510 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[49] SLICE_X90Y420 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.065 1.575 r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[56]_i_1/O net (fo=1, routed) 0.016 1.591 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[56]_i_1_n_0 SLICE_X90Y420 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[56]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.438 1.603 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y420 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[56]/C clock pessimism -0.107 1.496 SLICE_X90Y420 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.552 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[56] ------------------------------------------------------------------- required time -1.552 arrival time 1.591 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.293ns (logic 0.079ns (26.962%) route 0.214ns (73.038%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.626ns Source Clock Delay (SCD): 1.321ns Clock Pessimism Removal (CPR): 0.107ns Clock Net Delay (Source): 1.203ns (routing 0.484ns, distribution 0.719ns) Clock Net Delay (Destination): 1.461ns (routing 0.544ns, distribution 0.917ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.203 1.321 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X90Y418 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X90Y418 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.370 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.198 1.568 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in SLICE_X88Y421 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.030 1.598 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__11/O net (fo=1, routed) 0.016 1.614 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] SLICE_X88Y421 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.461 1.626 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X88Y421 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.107 1.519 SLICE_X88Y421 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.575 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.575 arrival time 1.614 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: SFP_GEN[12].rx_data_ngccm_reg[12][28]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[28]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.048ns (21.818%) route 0.172ns (78.182%)) Logic Levels: 0 Clock Path Skew: 0.124ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.607ns Source Clock Delay (SCD): 1.376ns Clock Pessimism Removal (CPR): 0.107ns Clock Net Delay (Source): 1.258ns (routing 0.484ns, distribution 0.774ns) Clock Net Delay (Destination): 1.442ns (routing 0.544ns, distribution 0.898ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.258 1.376 g_gbt_bank[1].gbtbank_n_0 SLICE_X79Y420 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][28]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y420 FDCE (Prop_GFF2_SLICEM_C_Q) 0.048 1.424 r SFP_GEN[12].rx_data_ngccm_reg[12][28]/Q net (fo=1, routed) 0.172 1.596 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[20] SLICE_X79Y419 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[28]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.442 1.607 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y419 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.107 1.500 SLICE_X79Y419 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.556 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.556 arrival time 1.596 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: SFP_GEN[12].rx_data_ngccm_reg[12][31]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[31]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.124ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.607ns Source Clock Delay (SCD): 1.376ns Clock Pessimism Removal (CPR): 0.107ns Clock Net Delay (Source): 1.258ns (routing 0.484ns, distribution 0.774ns) Clock Net Delay (Destination): 1.442ns (routing 0.544ns, distribution 0.898ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.258 1.376 g_gbt_bank[1].gbtbank_n_0 SLICE_X79Y420 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][31]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y420 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.424 r SFP_GEN[12].rx_data_ngccm_reg[12][31]/Q net (fo=1, routed) 0.173 1.597 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[23] SLICE_X79Y419 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[31]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.442 1.607 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y419 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[31]/C clock pessimism -0.107 1.500 SLICE_X79Y419 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.556 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[31] ------------------------------------------------------------------- required time -1.556 arrival time 1.597 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: SFP_GEN[12].rx_data_ngccm_reg[12][38]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[38]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.215ns (logic 0.129ns (60.000%) route 0.086ns (40.000%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.118ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.592ns Source Clock Delay (SCD): 1.367ns Clock Pessimism Removal (CPR): 0.107ns Clock Net Delay (Source): 1.249ns (routing 0.484ns, distribution 0.765ns) Clock Net Delay (Destination): 1.427ns (routing 0.544ns, distribution 0.883ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.249 1.367 g_gbt_bank[1].gbtbank_n_0 SLICE_X81Y420 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][38]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y420 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.415 r SFP_GEN[12].rx_data_ngccm_reg[12][38]/Q net (fo=1, routed) 0.074 1.489 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[30] SLICE_X81Y419 LUT3 (Prop_H5LUT_SLICEL_I1_O) 0.081 1.570 r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[38]_i_1/O net (fo=1, routed) 0.012 1.582 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[38]_i_1_n_0 SLICE_X81Y419 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[38]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.427 1.592 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y419 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism -0.107 1.485 SLICE_X81Y419 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.541 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time -1.541 arrival time 1.582 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.094ns (51.366%) route 0.089ns (48.634%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.626ns Source Clock Delay (SCD): 1.355ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 1.237ns (routing 0.484ns, distribution 0.753ns) Clock Net Delay (Destination): 1.461ns (routing 0.544ns, distribution 0.917ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.237 1.355 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X89Y421 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y421 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.404 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.073 1.477 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in SLICE_X88Y421 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.522 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__11/O net (fo=1, routed) 0.016 1.538 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] SLICE_X88Y421 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.461 1.626 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X88Y421 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.186 1.440 SLICE_X88Y421 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.496 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.496 arrival time 1.538 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.042ns (arrival time - required time) Source: SFP_GEN[12].rx_data_ngccm_reg[12][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[0]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.283ns (logic 0.120ns (42.403%) route 0.163ns (57.597%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.185ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.638ns Source Clock Delay (SCD): 1.346ns Clock Pessimism Removal (CPR): 0.107ns Clock Net Delay (Source): 1.228ns (routing 0.484ns, distribution 0.744ns) Clock Net Delay (Destination): 1.473ns (routing 0.544ns, distribution 0.929ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.346 g_gbt_bank[1].gbtbank_n_0 SLICE_X83Y419 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][0]/C ------------------------------------------------------------------- ------------------- SLICE_X83Y419 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.395 r SFP_GEN[12].rx_data_ngccm_reg[12][0]/Q net (fo=1, routed) 0.147 1.542 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[0] SLICE_X84Y420 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.071 1.613 r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[0]_i_1/O net (fo=1, routed) 0.016 1.629 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[0]_i_1_n_0 SLICE_X84Y420 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.473 1.638 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y420 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.107 1.531 SLICE_X84Y420 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.587 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.587 arrival time 1.629 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.042ns (arrival time - required time) Source: SFP_GEN[12].rx_data_ngccm_reg[12][41]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[40]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_12 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.095ns (43.182%) route 0.125ns (56.818%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.122ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.601ns Source Clock Delay (SCD): 1.372ns Clock Pessimism Removal (CPR): 0.107ns Clock Net Delay (Source): 1.254ns (routing 0.484ns, distribution 0.770ns) Clock Net Delay (Destination): 1.436ns (routing 0.544ns, distribution 0.892ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.254 1.372 g_gbt_bank[1].gbtbank_n_0 SLICE_X84Y420 FDCE r SFP_GEN[12].rx_data_ngccm_reg[12][41]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y420 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.421 r SFP_GEN[12].rx_data_ngccm_reg[12][41]/Q net (fo=1, routed) 0.109 1.530 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[33] SLICE_X85Y419 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.046 1.576 r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[40]_i_1/O net (fo=1, routed) 0.016 1.592 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 SLICE_X85Y419 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[40]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.436 1.601 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y419 FDCE r SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[40]/C clock pessimism -0.107 1.494 SLICE_X85Y419 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.550 SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[40] ------------------------------------------------------------------- required time -1.550 arrival time 1.592 ------------------------------------------------------------------- slack 0.042 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_12 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y172 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y416 g_clock_rate_din[12].ngccm_status_cnt_reg[12][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y416 g_clock_rate_din[12].ngccm_status_cnt_reg[12][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y414 g_clock_rate_din[12].ngccm_status_cnt_reg[12][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y416 g_clock_rate_din[12].ngccm_status_cnt_reg[12][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X75Y415 g_clock_rate_din[12].ngccm_status_cnt_reg[12][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y416 g_clock_rate_din[12].ngccm_status_cnt_reg[12][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y416 g_clock_rate_din[12].ngccm_status_cnt_reg[12][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y418 g_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[0].rx_data_good_cntr_reg[0][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y418 g_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[0].rx_data_good_cntr_reg[0][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y418 g_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[0].rx_data_good_cntr_reg[0][2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y418 g_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[0].rx_data_good_cntr_reg[0][3]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y418 g_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[0].rx_data_good_cntr_reg[0][4]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X79Y425 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X75Y415 g_clock_rate_din[12].ngccm_status_cnt_reg[12][4]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y418 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y418 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y417 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y417 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X81Y418 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_13 To Clock: gtwiz_userclk_rx_srcclk_out[0]_13 Setup : 0 Failing Endpoints, Worst Slack 3.408ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.040ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.408ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.785ns (logic 1.073ns (22.424%) route 3.712ns (77.576%)) Logic Levels: 5 (LUT4=1 LUT6=4) Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.313ns = ( 10.630 - 8.317 ) Source Clock Delay (SCD): 2.682ns Clock Pessimism Removal (CPR): 0.217ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.207ns (routing 0.723ns, distribution 1.484ns) Clock Net Delay (Destination): 1.915ns (routing 0.658ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.207 2.682 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y553 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]/C ------------------------------------------------------------------- ------------------- SLICE_X104Y553 FDCE (Prop_CFF2_SLICEL_C_Q) 0.139 2.821 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]/Q net (fo=10, routed) 0.890 3.711 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxencdata_s[10]_52[85] SLICE_X112Y558 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 3.863 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_17__21/O net (fo=1, routed) 0.435 4.298 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_17__21_n_0 SLICE_X112Y558 LUT6 (Prop_E6LUT_SLICEM_I2_O) 0.244 4.542 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_3__21/O net (fo=36, routed) 1.359 5.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/s2_from_syndromes[2] SLICE_X119Y568 LUT4 (Prop_C6LUT_SLICEM_I1_O) 0.167 6.068 f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/i___38_i_1__21/O net (fo=22, routed) 0.383 6.451 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_5__21_0 SLICE_X118Y564 LUT6 (Prop_A6LUT_SLICEM_I5_O) 0.146 6.597 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__43/O net (fo=1, routed) 0.610 7.207 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__43_n_0 SLICE_X112Y557 LUT6 (Prop_D6LUT_SLICEM_I3_O) 0.225 7.432 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__43/O net (fo=1, routed) 0.035 7.467 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 SLICE_X112Y557 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.915 10.630 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK SLICE_X112Y557 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C clock pessimism 0.217 10.848 clock uncertainty -0.035 10.812 SLICE_X112Y557 FDRE (Setup_DFF_SLICEM_C_D) 0.063 10.875 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg ------------------------------------------------------------------- required time 10.875 arrival time -7.467 ------------------------------------------------------------------- slack 3.408 Slack (MET) : 3.641ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[94]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.386ns (logic 1.056ns (24.077%) route 3.330ns (75.923%)) Logic Levels: 0 Clock Path Skew: -0.317ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.839ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.364ns (routing 0.723ns, distribution 1.641ns) Clock Net Delay (Destination): 1.909ns (routing 0.658ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.364 2.839 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[12]) 1.056 3.895 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[12] net (fo=6, routed) 3.330 7.225 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/D[14] SLICE_X100Y554 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[94]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.909 10.624 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X100Y554 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[94]/C clock pessimism 0.215 10.839 clock uncertainty -0.035 10.804 SLICE_X100Y554 FDCE (Setup_BFF_SLICEM_C_D) 0.062 10.866 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[94] ------------------------------------------------------------------- required time 10.866 arrival time -7.225 ------------------------------------------------------------------- slack 3.641 Slack (MET) : 3.799ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.113ns (logic 1.630ns (39.630%) route 2.483ns (60.370%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.315ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.309ns = ( 10.626 - 8.317 ) Source Clock Delay (SCD): 2.839ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.364ns (routing 0.723ns, distribution 1.641ns) Clock Net Delay (Destination): 1.911ns (routing 0.658ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.364 2.839 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.938 5.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X107Y559 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.182 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/O net (fo=5, routed) 0.197 6.379 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X107Y560 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.225 6.604 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__22/O net (fo=7, routed) 0.348 6.952 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X108Y559 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.911 10.626 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y559 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.215 10.841 clock uncertainty -0.035 10.806 SLICE_X108Y559 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.751 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.751 arrival time -6.952 ------------------------------------------------------------------- slack 3.799 Slack (MET) : 3.804ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.109ns (logic 1.630ns (39.669%) route 2.479ns (60.331%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.315ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.309ns = ( 10.626 - 8.317 ) Source Clock Delay (SCD): 2.839ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.364ns (routing 0.723ns, distribution 1.641ns) Clock Net Delay (Destination): 1.911ns (routing 0.658ns, distribution 1.253ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.364 2.839 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.938 5.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X107Y559 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.182 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/O net (fo=5, routed) 0.197 6.379 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X107Y560 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.225 6.604 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__22/O net (fo=7, routed) 0.344 6.948 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X108Y559 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.911 10.626 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y559 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.215 10.841 clock uncertainty -0.035 10.806 SLICE_X108Y559 FDRE (Setup_AFF_SLICEL_C_CE) -0.054 10.752 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.752 arrival time -6.948 ------------------------------------------------------------------- slack 3.804 Slack (MET) : 3.813ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.104ns (logic 1.670ns (40.692%) route 2.434ns (59.308%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.313ns = ( 10.630 - 8.317 ) Source Clock Delay (SCD): 2.839ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.364ns (routing 0.723ns, distribution 1.641ns) Clock Net Delay (Destination): 1.915ns (routing 0.658ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.364 2.839 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.938 5.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X107Y559 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.182 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/O net (fo=5, routed) 0.089 6.271 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X107Y559 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.092 6.363 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21/O net (fo=1, routed) 0.086 6.449 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21_n_0 SLICE_X107Y559 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 6.622 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21/O net (fo=2, routed) 0.321 6.943 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21_n_0 SLICE_X107Y559 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.915 10.630 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y559 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.215 10.845 clock uncertainty -0.035 10.810 SLICE_X107Y559 FDCE (Setup_AFF_SLICEM_C_CE) -0.054 10.756 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.756 arrival time -6.943 ------------------------------------------------------------------- slack 3.813 Slack (MET) : 3.813ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.104ns (logic 1.670ns (40.692%) route 2.434ns (59.308%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.313ns = ( 10.630 - 8.317 ) Source Clock Delay (SCD): 2.839ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.364ns (routing 0.723ns, distribution 1.641ns) Clock Net Delay (Destination): 1.915ns (routing 0.658ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.364 2.839 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.938 5.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X107Y559 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.182 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/O net (fo=5, routed) 0.089 6.271 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X107Y559 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.092 6.363 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21/O net (fo=1, routed) 0.086 6.449 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21_n_0 SLICE_X107Y559 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 6.622 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21/O net (fo=2, routed) 0.321 6.943 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21_n_0 SLICE_X107Y559 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.915 10.630 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y559 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.215 10.845 clock uncertainty -0.035 10.810 SLICE_X107Y559 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 10.756 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.756 arrival time -6.943 ------------------------------------------------------------------- slack 3.813 Slack (MET) : 3.815ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[61]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.230ns (logic 1.086ns (25.674%) route 3.144ns (74.326%)) Logic Levels: 0 Clock Path Skew: -0.300ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.324ns = ( 10.641 - 8.317 ) Source Clock Delay (SCD): 2.839ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.364ns (routing 0.723ns, distribution 1.641ns) Clock Net Delay (Destination): 1.926ns (routing 0.658ns, distribution 1.268ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.364 2.839 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.925 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.144 7.069 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/D[1] SLICE_X101Y555 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[61]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.641 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X101Y555 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[61]/C clock pessimism 0.215 10.856 clock uncertainty -0.035 10.821 SLICE_X101Y555 FDCE (Setup_HFF_SLICEM_C_D) 0.063 10.884 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[61] ------------------------------------------------------------------- required time 10.884 arrival time -7.069 ------------------------------------------------------------------- slack 3.815 Slack (MET) : 3.821ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.086ns (logic 1.555ns (38.057%) route 2.531ns (61.943%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.317ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.839ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.364ns (routing 0.723ns, distribution 1.641ns) Clock Net Delay (Destination): 1.909ns (routing 0.658ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.364 2.839 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.938 5.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X107Y559 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.182 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/O net (fo=5, routed) 0.171 6.353 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X107Y560 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.150 6.503 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__22/O net (fo=3, routed) 0.422 6.925 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 SLICE_X108Y559 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.909 10.624 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y559 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.215 10.839 clock uncertainty -0.035 10.804 SLICE_X108Y559 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.746 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.746 arrival time -6.925 ------------------------------------------------------------------- slack 3.821 Slack (MET) : 3.828ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.082ns (logic 1.555ns (38.094%) route 2.527ns (61.906%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.317ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.839ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.364ns (routing 0.723ns, distribution 1.641ns) Clock Net Delay (Destination): 1.909ns (routing 0.658ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.364 2.839 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.938 5.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X107Y559 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.182 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/O net (fo=5, routed) 0.171 6.353 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X107Y560 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.150 6.503 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__22/O net (fo=3, routed) 0.418 6.921 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 SLICE_X108Y559 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.909 10.624 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y559 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.215 10.839 clock uncertainty -0.035 10.804 SLICE_X108Y559 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.749 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 10.749 arrival time -6.921 ------------------------------------------------------------------- slack 3.828 Slack (MET) : 3.828ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.082ns (logic 1.555ns (38.094%) route 2.527ns (61.906%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.317ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.839ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.364ns (routing 0.723ns, distribution 1.641ns) Clock Net Delay (Destination): 1.909ns (routing 0.658ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.364 2.839 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.938 5.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X107Y559 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.182 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/O net (fo=5, routed) 0.171 6.353 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X107Y560 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.150 6.503 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__22/O net (fo=3, routed) 0.418 6.921 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 SLICE_X108Y559 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.909 10.624 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y559 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.215 10.839 clock uncertainty -0.035 10.804 SLICE_X108Y559 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 10.749 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 10.749 arrival time -6.921 ------------------------------------------------------------------- slack 3.828 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.040ns (arrival time - required time) Source: SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[30]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.166ns (logic 0.049ns (29.518%) route 0.117ns (70.482%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.942ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.824ns (routing 0.318ns, distribution 0.506ns) Clock Net Delay (Destination): 0.977ns (routing 0.359ns, distribution 0.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.942 SFP_GEN[22].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X97Y541 FDCE r SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[30]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y541 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 0.991 r SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[30]/Q net (fo=2, routed) 0.117 1.108 SFP_GEN[22].ngCCM_gbt/gbt_rx_checker/Q[14] SLICE_X96Y540 FDRE r SFP_GEN[22].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.142 SFP_GEN[22].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y540 FDRE r SFP_GEN[22].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C clock pessimism -0.130 1.012 SLICE_X96Y540 FDRE (Hold_FFF_SLICEL_C_D) 0.056 1.068 SFP_GEN[22].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14] ------------------------------------------------------------------- required time -1.068 arrival time 1.108 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.946ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.828ns (routing 0.318ns, distribution 0.510ns) Clock Net Delay (Destination): 0.997ns (routing 0.359ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.946 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X98Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y545 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.995 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.034 1.029 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in SLICE_X98Y545 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.074 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__21/O net (fo=1, routed) 0.016 1.090 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[0] SLICE_X98Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X98Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.174 0.988 SLICE_X98Y545 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.044 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.044 arrival time 1.090 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[22].rx_data_ngccm_reg[22][5]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[4]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.080ns (47.059%) route 0.090ns (52.941%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.946ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.828ns (routing 0.318ns, distribution 0.510ns) Clock Net Delay (Destination): 0.977ns (routing 0.359ns, distribution 0.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.946 g_gbt_bank[1].gbtbank_n_124 SLICE_X98Y544 FDCE r SFP_GEN[22].rx_data_ngccm_reg[22][5]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y544 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.995 r SFP_GEN[22].rx_data_ngccm_reg[22][5]/Q net (fo=1, routed) 0.074 1.069 SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[83]_0[5] SLICE_X96Y544 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.031 1.100 r SFP_GEN[22].ngCCM_gbt/RX_Word_rx40[4]_i_1/O net (fo=1, routed) 0.016 1.116 SFP_GEN[22].ngCCM_gbt/RX_Word_rx40[4]_i_1_n_0 SLICE_X96Y544 FDCE r SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.142 SFP_GEN[22].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y544 FDCE r SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[4]/C clock pessimism -0.130 1.012 SLICE_X96Y544 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.068 SFP_GEN[22].ngCCM_gbt/RX_Word_rx40_reg[4] ------------------------------------------------------------------- required time -1.068 arrival time 1.116 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.088ns (50.286%) route 0.087ns (49.714%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.141ns Source Clock Delay (SCD): 0.942ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.824ns (routing 0.318ns, distribution 0.506ns) Clock Net Delay (Destination): 0.976ns (routing 0.359ns, distribution 0.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.942 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y553 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y553 FDCE (Prop_FFF2_SLICEL_C_Q) 0.048 0.990 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[3]/Q net (fo=11, routed) 0.075 1.065 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/Q[3] SLICE_X106Y553 LUT5 (Prop_H5LUT_SLICEM_I1_O) 0.040 1.105 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/decoder/RX_ISDATA_FLAG_O0/O net (fo=1, routed) 0.012 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_I SLICE_X106Y553 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.976 1.141 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK SLICE_X106Y553 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.130 1.011 SLICE_X106Y553 FDCE (Hold_HFF2_SLICEM_C_D) 0.056 1.067 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.067 arrival time 1.117 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.946ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.828ns (routing 0.318ns, distribution 0.510ns) Clock Net Delay (Destination): 0.997ns (routing 0.359ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.946 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X98Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y545 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.995 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.034 1.029 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in SLICE_X98Y545 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.055 1.084 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__21/O net (fo=1, routed) 0.011 1.095 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] SLICE_X98Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X98Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.174 0.988 SLICE_X98Y545 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.044 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -1.044 arrival time 1.095 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].rx_data_ngccm_reg[22][31]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.049ns (33.333%) route 0.098ns (66.667%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.143ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.162ns Clock Net Delay (Source): 0.822ns (routing 0.318ns, distribution 0.504ns) Clock Net Delay (Destination): 0.978ns (routing 0.359ns, distribution 0.619ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X99Y547 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y547 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 0.989 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.098 1.087 rx_data[22][31] SLICE_X99Y545 FDCE r SFP_GEN[22].rx_data_ngccm_reg[22][31]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.143 g_gbt_bank[1].gbtbank_n_124 SLICE_X99Y545 FDCE r SFP_GEN[22].rx_data_ngccm_reg[22][31]/C clock pessimism -0.162 0.981 SLICE_X99Y545 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.036 SFP_GEN[22].rx_data_ngccm_reg[22][31] ------------------------------------------------------------------- required time -1.036 arrival time 1.087 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.113ns (logic 0.064ns (56.637%) route 0.049ns (43.363%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.144ns Source Clock Delay (SCD): 0.939ns Clock Pessimism Removal (CPR): 0.200ns Clock Net Delay (Source): 0.821ns (routing 0.318ns, distribution 0.503ns) Clock Net Delay (Destination): 0.979ns (routing 0.359ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.821 0.939 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X96Y547 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y547 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 0.988 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/Q net (fo=5, routed) 0.037 1.025 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt_reg[10][7]_0[7] SLICE_X96Y547 LUT6 (Prop_A6LUT_SLICEL_I4_O) 0.015 1.040 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt[10][7]_i_2__0/O net (fo=1, routed) 0.012 1.052 g_gbt_bank[1].gbtbank/i_gbt_bank_n_366 SLICE_X96Y547 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.979 1.144 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X96Y547 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C clock pessimism -0.200 0.944 SLICE_X96Y547 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.000 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7] ------------------------------------------------------------------- required time -1.000 arrival time 1.052 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.942ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.824ns (routing 0.318ns, distribution 0.506ns) Clock Net Delay (Destination): 0.986ns (routing 0.359ns, distribution 0.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.942 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X102Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y546 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.991 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.034 1.025 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_21_in SLICE_X102Y546 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.070 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__21/O net (fo=1, routed) 0.016 1.086 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[11] SLICE_X102Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X102Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.173 0.978 SLICE_X102Y546 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.034 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.034 arrival time 1.086 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.114ns (logic 0.064ns (56.140%) route 0.050ns (43.860%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.144ns Source Clock Delay (SCD): 0.939ns Clock Pessimism Removal (CPR): 0.200ns Clock Net Delay (Source): 0.821ns (routing 0.318ns, distribution 0.503ns) Clock Net Delay (Destination): 0.979ns (routing 0.359ns, distribution 0.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.821 0.939 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X96Y547 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y547 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 0.988 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/Q net (fo=6, routed) 0.035 1.023 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt_reg[10][7]_0[6] SLICE_X96Y547 LUT5 (Prop_B6LUT_SLICEL_I0_O) 0.015 1.038 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt[10][6]_i_1__0/O net (fo=1, routed) 0.015 1.053 g_gbt_bank[1].gbtbank/i_gbt_bank_n_367 SLICE_X96Y547 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.979 1.144 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X96Y547 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C clock pessimism -0.200 0.944 SLICE_X96Y547 FDCE (Hold_BFF_SLICEL_C_D) 0.056 1.000 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6] ------------------------------------------------------------------- required time -1.000 arrival time 1.053 ------------------------------------------------------------------- slack 0.053 Slack (MET) : 0.054ns (arrival time - required time) Source: SFP_GEN[22].ngCCM_gbt/pwr_good_pre_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_13 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.205ns (logic 0.113ns (55.122%) route 0.092ns (44.878%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.095ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.329ns Source Clock Delay (SCD): 1.082ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 0.964ns (routing 0.318ns, distribution 0.646ns) Clock Net Delay (Destination): 1.164ns (routing 0.359ns, distribution 0.805ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.964 1.082 SFP_GEN[22].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y540 FDCE r SFP_GEN[22].ngCCM_gbt/pwr_good_pre_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y540 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.131 r SFP_GEN[22].ngCCM_gbt/pwr_good_pre_reg/Q net (fo=1, routed) 0.076 1.207 SFP_GEN[22].ngCCM_gbt/pwr_good_pre SLICE_X91Y540 LUT4 (Prop_C6LUT_SLICEL_I1_O) 0.064 1.271 r SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_i_1__42/O net (fo=1, routed) 0.016 1.287 SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_i_1__42_n_0 SLICE_X91Y540 FDRE r SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.164 1.329 SFP_GEN[22].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y540 FDRE r SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_reg/C clock pessimism -0.152 1.177 SLICE_X91Y540 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.233 SFP_GEN[22].ngCCM_gbt/pwr_good_cnt_reg ------------------------------------------------------------------- required time -1.233 arrival time 1.287 ------------------------------------------------------------------- slack 0.054 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_13 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y219 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X82Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X96Y541 g_clock_rate_din[22].rx_frameclk_div2_reg[22]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X82Y540 g_clock_rate_din[22].rx_test_comm_cnt_reg[22]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X91Y540 SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X91Y540 SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X91Y540 SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][5]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y540 g_clock_rate_din[22].ngccm_status_cnt_reg[22][6]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_14 To Clock: gtwiz_userclk_rx_srcclk_out[0]_14 Setup : 0 Failing Endpoints, Worst Slack 3.158ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.039ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.158ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.761ns (logic 1.618ns (33.984%) route 3.143ns (66.016%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.308ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.916ns = ( 11.233 - 8.317 ) Source Clock Delay (SCD): 3.510ns Clock Pessimism Removal (CPR): 0.286ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.035ns (routing 1.148ns, distribution 1.887ns) Clock Net Delay (Destination): 2.518ns (routing 1.049ns, distribution 1.469ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.035 3.510 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.671 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.199 6.870 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y565 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.235 7.105 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.386 7.491 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X100Y563 LUT4 (Prop_D5LUT_SLICEM_I2_O) 0.171 7.662 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22/O net (fo=1, routed) 0.217 7.879 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22_n_0 SLICE_X100Y563 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.051 7.930 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22/O net (fo=2, routed) 0.341 8.271 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22_n_0 SLICE_X100Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.518 11.233 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X100Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.286 11.520 clock uncertainty -0.035 11.484 SLICE_X100Y565 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.429 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.429 arrival time -8.271 ------------------------------------------------------------------- slack 3.158 Slack (MET) : 3.158ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.761ns (logic 1.618ns (33.984%) route 3.143ns (66.016%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.308ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.916ns = ( 11.233 - 8.317 ) Source Clock Delay (SCD): 3.510ns Clock Pessimism Removal (CPR): 0.286ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.035ns (routing 1.148ns, distribution 1.887ns) Clock Net Delay (Destination): 2.518ns (routing 1.049ns, distribution 1.469ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.035 3.510 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.671 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.199 6.870 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y565 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.235 7.105 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.386 7.491 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X100Y563 LUT4 (Prop_D5LUT_SLICEM_I2_O) 0.171 7.662 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22/O net (fo=1, routed) 0.217 7.879 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22_n_0 SLICE_X100Y563 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.051 7.930 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22/O net (fo=2, routed) 0.341 8.271 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22_n_0 SLICE_X100Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.518 11.233 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X100Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.286 11.520 clock uncertainty -0.035 11.484 SLICE_X100Y565 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.429 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.429 arrival time -8.271 ------------------------------------------------------------------- slack 3.158 Slack (MET) : 3.218ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[94]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.650ns (logic 0.946ns (20.344%) route 3.704ns (79.656%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.477ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.916ns = ( 11.233 - 8.317 ) Source Clock Delay (SCD): 3.690ns Clock Pessimism Removal (CPR): 0.297ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.215ns (routing 1.148ns, distribution 2.067ns) Clock Net Delay (Destination): 2.518ns (routing 1.049ns, distribution 1.469ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.215 3.690 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X94Y569 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[94]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y569 FDCE (Prop_FFF2_SLICEL_C_Q) 0.138 3.828 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[94]/Q net (fo=11, routed) 0.474 4.302 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxencdata_s[11]_51[25] SLICE_X94Y569 LUT6 (Prop_G6LUT_SLICEL_I4_O) 0.218 4.520 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___51_i_12__22/O net (fo=1, routed) 0.497 5.017 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___51_i_12__22_n_0 SLICE_X91Y570 LUT6 (Prop_E6LUT_SLICEL_I0_O) 0.219 5.236 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___51_i_2__22/O net (fo=43, routed) 2.351 7.587 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[92]_0[0] SLICE_X110Y566 LUT4 (Prop_C6LUT_SLICEM_I1_O) 0.146 7.733 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_3__22/O net (fo=1, routed) 0.347 8.080 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_3__22_n_0 SLICE_X109Y566 LUT6 (Prop_H6LUT_SLICEM_I2_O) 0.225 8.305 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__46/O net (fo=1, routed) 0.035 8.340 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg_3 SLICE_X109Y566 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.518 11.233 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/CLK SLICE_X109Y566 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C clock pessimism 0.297 11.530 clock uncertainty -0.035 11.495 SLICE_X109Y566 FDRE (Setup_HFF_SLICEM_C_D) 0.063 11.558 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg ------------------------------------------------------------------- required time 11.558 arrival time -8.340 ------------------------------------------------------------------- slack 3.218 Slack (MET) : 3.308ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[80]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.539ns (logic 1.045ns (23.023%) route 3.494ns (76.977%)) Logic Levels: 5 (LUT4=1 LUT6=4) Clock Path Skew: -0.497ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.923ns = ( 11.240 - 8.317 ) Source Clock Delay (SCD): 3.717ns Clock Pessimism Removal (CPR): 0.297ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.242ns (routing 1.148ns, distribution 2.094ns) Clock Net Delay (Destination): 2.525ns (routing 1.049ns, distribution 1.476ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.242 3.717 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X89Y568 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[80]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y568 FDCE (Prop_EFF2_SLICEM_C_Q) 0.138 3.855 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[80]/Q net (fo=11, routed) 0.578 4.433 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/Q[32] SLICE_X86Y566 LUT6 (Prop_C6LUT_SLICEL_I1_O) 0.165 4.598 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_5__22/O net (fo=1, routed) 0.371 4.969 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_5__22_n_0 SLICE_X85Y567 LUT6 (Prop_C6LUT_SLICEM_I0_O) 0.224 5.193 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_1__22/O net (fo=33, routed) 2.077 7.270 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/s1_from_syndromes[0] SLICE_X101Y561 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.224 7.494 f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__22/O net (fo=1, routed) 0.274 7.768 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__22_n_0 SLICE_X99Y561 LUT6 (Prop_G6LUT_SLICEL_I4_O) 0.147 7.915 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__45/O net (fo=1, routed) 0.161 8.076 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__45_n_0 SLICE_X99Y562 LUT6 (Prop_B6LUT_SLICEL_I3_O) 0.147 8.223 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__45/O net (fo=1, routed) 0.033 8.256 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 SLICE_X99Y562 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.525 11.240 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK SLICE_X99Y562 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C clock pessimism 0.297 11.537 clock uncertainty -0.035 11.502 SLICE_X99Y562 FDRE (Setup_BFF_SLICEL_C_D) 0.062 11.564 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg ------------------------------------------------------------------- required time 11.564 arrival time -8.256 ------------------------------------------------------------------- slack 3.308 Slack (MET) : 3.347ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[0]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 5.027ns (logic 1.104ns (21.961%) route 3.923ns (78.039%)) Logic Levels: 0 Clock Path Skew: 0.029ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.246ns = ( 11.563 - 8.317 ) Source Clock Delay (SCD): 3.510ns Clock Pessimism Removal (CPR): 0.293ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.035ns (routing 1.148ns, distribution 1.887ns) Clock Net Delay (Destination): 2.848ns (routing 1.049ns, distribution 1.799ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.035 3.510 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.614 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.923 8.537 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[0] SLICE_X89Y568 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.848 11.563 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X89Y568 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[0]/C clock pessimism 0.293 11.857 clock uncertainty -0.035 11.821 SLICE_X89Y568 FDCE (Setup_HFF_SLICEM_C_D) 0.063 11.884 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[0] ------------------------------------------------------------------- required time 11.884 arrival time -8.537 ------------------------------------------------------------------- slack 3.347 Slack (MET) : 3.415ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.938ns (logic 1.086ns (21.993%) route 3.852ns (78.007%)) Logic Levels: 0 Clock Path Skew: 0.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.225ns = ( 11.542 - 8.317 ) Source Clock Delay (SCD): 3.510ns Clock Pessimism Removal (CPR): 0.293ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.035ns (routing 1.148ns, distribution 1.887ns) Clock Net Delay (Destination): 2.827ns (routing 1.049ns, distribution 1.778ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.035 3.510 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.596 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.852 8.448 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[1] SLICE_X93Y568 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.827 11.542 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X93Y568 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]/C clock pessimism 0.293 11.836 clock uncertainty -0.035 11.800 SLICE_X93Y568 FDCE (Setup_HFF_SLICEL_C_D) 0.063 11.863 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61] ------------------------------------------------------------------- required time 11.863 arrival time -8.448 ------------------------------------------------------------------- slack 3.415 Slack (MET) : 3.462ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[80]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.914ns (logic 1.104ns (22.466%) route 3.810ns (77.534%)) Logic Levels: 0 Clock Path Skew: 0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.248ns = ( 11.565 - 8.317 ) Source Clock Delay (SCD): 3.510ns Clock Pessimism Removal (CPR): 0.293ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.035ns (routing 1.148ns, distribution 1.887ns) Clock Net Delay (Destination): 2.850ns (routing 1.049ns, distribution 1.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.035 3.510 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.614 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.810 8.424 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[0] SLICE_X89Y568 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[80]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.850 11.565 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X89Y568 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[80]/C clock pessimism 0.293 11.859 clock uncertainty -0.035 11.823 SLICE_X89Y568 FDCE (Setup_DFF_SLICEM_C_D) 0.063 11.886 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[80] ------------------------------------------------------------------- required time 11.886 arrival time -8.424 ------------------------------------------------------------------- slack 3.462 Slack (MET) : 3.469ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.443ns (logic 1.542ns (34.706%) route 2.901ns (65.294%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.911ns = ( 11.228 - 8.317 ) Source Clock Delay (SCD): 3.510ns Clock Pessimism Removal (CPR): 0.287ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.035ns (routing 1.148ns, distribution 1.887ns) Clock Net Delay (Destination): 2.513ns (routing 1.049ns, distribution 1.464ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.035 3.510 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.671 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.199 6.870 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y565 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.235 7.105 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.168 7.273 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X99Y564 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.146 7.419 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__23/O net (fo=3, routed) 0.534 7.953 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X99Y563 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.513 11.228 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X99Y563 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.287 11.515 clock uncertainty -0.035 11.480 SLICE_X99Y563 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.422 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.422 arrival time -7.953 ------------------------------------------------------------------- slack 3.469 Slack (MET) : 3.470ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[63]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.878ns (logic 1.161ns (23.801%) route 3.717ns (76.199%)) Logic Levels: 0 Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.220ns = ( 11.537 - 8.317 ) Source Clock Delay (SCD): 3.510ns Clock Pessimism Removal (CPR): 0.293ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.035ns (routing 1.148ns, distribution 1.887ns) Clock Net Delay (Destination): 2.822ns (routing 1.049ns, distribution 1.773ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.035 3.510 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.671 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.717 8.388 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[3] SLICE_X94Y568 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[63]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.822 11.537 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X94Y568 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[63]/C clock pessimism 0.293 11.831 clock uncertainty -0.035 11.795 SLICE_X94Y568 FDCE (Setup_HFF_SLICEL_C_D) 0.063 11.858 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[63] ------------------------------------------------------------------- required time 11.858 arrival time -8.388 ------------------------------------------------------------------- slack 3.470 Slack (MET) : 3.476ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 4.439ns (logic 1.542ns (34.738%) route 2.897ns (65.262%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.911ns = ( 11.228 - 8.317 ) Source Clock Delay (SCD): 3.510ns Clock Pessimism Removal (CPR): 0.287ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.035ns (routing 1.148ns, distribution 1.887ns) Clock Net Delay (Destination): 2.513ns (routing 1.049ns, distribution 1.464ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.035 3.510 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.671 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.199 6.870 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X99Y565 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.235 7.105 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/O net (fo=5, routed) 0.168 7.273 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X99Y564 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.146 7.419 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__23/O net (fo=3, routed) 0.530 7.949 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X99Y563 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.513 11.228 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X99Y563 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.287 11.515 clock uncertainty -0.035 11.480 SLICE_X99Y563 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.425 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.425 arrival time -7.949 ------------------------------------------------------------------- slack 3.476 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].rx_data_ngccm_reg[23][1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.048ns (31.579%) route 0.104ns (68.421%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.619ns Source Clock Delay (SCD): 1.349ns Clock Pessimism Removal (CPR): 0.212ns Clock Net Delay (Source): 1.231ns (routing 0.485ns, distribution 0.746ns) Clock Net Delay (Destination): 1.454ns (routing 0.546ns, distribution 0.908ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.231 1.349 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X87Y563 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y563 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.397 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.104 1.501 rx_data[23][1] SLICE_X87Y561 FDCE r SFP_GEN[23].rx_data_ngccm_reg[23][1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.454 1.619 g_gbt_bank[1].gbtbank_n_134 SLICE_X87Y561 FDCE r SFP_GEN[23].rx_data_ngccm_reg[23][1]/C clock pessimism -0.212 1.407 SLICE_X87Y561 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.462 SFP_GEN[23].rx_data_ngccm_reg[23][1] ------------------------------------------------------------------- required time -1.462 arrival time 1.501 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[23].rx_data_ngccm_reg[23][68]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.102ns (66.234%) route 0.052ns (33.766%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.611ns Source Clock Delay (SCD): 1.346ns Clock Pessimism Removal (CPR): 0.213ns Clock Net Delay (Source): 1.228ns (routing 0.485ns, distribution 0.743ns) Clock Net Delay (Destination): 1.446ns (routing 0.546ns, distribution 0.900ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.346 g_gbt_bank[1].gbtbank_n_134 SLICE_X91Y560 FDCE r SFP_GEN[23].rx_data_ngccm_reg[23][68]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y560 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.395 r SFP_GEN[23].rx_data_ngccm_reg[23][68]/Q net (fo=1, routed) 0.036 1.431 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[83]_0[60] SLICE_X91Y559 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.053 1.484 r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[68]_i_1/O net (fo=1, routed) 0.016 1.500 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[68]_i_1_n_0 SLICE_X91Y559 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.446 1.611 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y559 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]/C clock pessimism -0.213 1.398 SLICE_X91Y559 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.454 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68] ------------------------------------------------------------------- required time -1.454 arrival time 1.500 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: SFP_GEN[23].rx_data_ngccm_reg[23][32]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[32]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.622ns Source Clock Delay (SCD): 1.359ns Clock Pessimism Removal (CPR): 0.212ns Clock Net Delay (Source): 1.241ns (routing 0.485ns, distribution 0.756ns) Clock Net Delay (Destination): 1.457ns (routing 0.546ns, distribution 0.911ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.241 1.359 g_gbt_bank[1].gbtbank_n_134 SLICE_X87Y561 FDCE r SFP_GEN[23].rx_data_ngccm_reg[23][32]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y561 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.408 r SFP_GEN[23].rx_data_ngccm_reg[23][32]/Q net (fo=1, routed) 0.035 1.443 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[83]_0[24] SLICE_X87Y560 LUT3 (Prop_D6LUT_SLICEM_I1_O) 0.054 1.497 r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[32]_i_1/O net (fo=1, routed) 0.016 1.513 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[32]_i_1_n_0 SLICE_X87Y560 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[32]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.457 1.622 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X87Y560 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.212 1.410 SLICE_X87Y560 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.466 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.466 arrival time 1.513 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[23].rx_data_ngccm_reg[23][44]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.624ns Source Clock Delay (SCD): 1.360ns Clock Pessimism Removal (CPR): 0.223ns Clock Net Delay (Source): 1.242ns (routing 0.485ns, distribution 0.757ns) Clock Net Delay (Destination): 1.459ns (routing 0.546ns, distribution 0.913ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.242 1.360 g_gbt_bank[1].gbtbank_n_134 SLICE_X87Y558 FDCE r SFP_GEN[23].rx_data_ngccm_reg[23][44]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y558 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.409 r SFP_GEN[23].rx_data_ngccm_reg[23][44]/Q net (fo=1, routed) 0.035 1.444 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[83]_0[36] SLICE_X87Y558 LUT3 (Prop_C6LUT_SLICEM_I1_O) 0.045 1.489 r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[44]_i_1/O net (fo=1, routed) 0.016 1.505 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[44]_i_1_n_0 SLICE_X87Y558 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.459 1.624 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X87Y558 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]/C clock pessimism -0.223 1.401 SLICE_X87Y558 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.457 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44] ------------------------------------------------------------------- required time -1.457 arrival time 1.505 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[23].ngccm_status_reg_reg[23][23]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngccm_status_reg_reg[23][23]/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.621ns Source Clock Delay (SCD): 1.364ns Clock Pessimism Removal (CPR): 0.252ns Clock Net Delay (Source): 1.246ns (routing 0.485ns, distribution 0.761ns) Clock Net Delay (Destination): 1.456ns (routing 0.546ns, distribution 0.910ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.246 1.364 g_gbt_bank[1].gbtbank_n_134 SLICE_X73Y531 FDPE r SFP_GEN[23].ngccm_status_reg_reg[23][23]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y531 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.413 r SFP_GEN[23].ngccm_status_reg_reg[23][23]/Q net (fo=2, routed) 0.033 1.446 SFP_GEN[23].ngCCM_gbt/SFP_GEN[23].ngccm_status_reg_reg[23][24]_0[7] SLICE_X73Y531 LUT2 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.461 r SFP_GEN[23].ngCCM_gbt/SFP_GEN[23].ngccm_status_reg[23][23]_i_1/O net (fo=1, routed) 0.012 1.473 SFP_GEN[23].ngCCM_gbt_n_394 SLICE_X73Y531 FDPE r SFP_GEN[23].ngccm_status_reg_reg[23][23]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.456 1.621 g_gbt_bank[1].gbtbank_n_134 SLICE_X73Y531 FDPE r SFP_GEN[23].ngccm_status_reg_reg[23][23]/C clock pessimism -0.252 1.369 SLICE_X73Y531 FDPE (Hold_AFF_SLICEM_C_D) 0.056 1.425 SFP_GEN[23].ngccm_status_reg_reg[23][23] ------------------------------------------------------------------- required time -1.425 arrival time 1.473 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.094ns (65.734%) route 0.049ns (34.266%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.604ns Source Clock Delay (SCD): 1.343ns Clock Pessimism Removal (CPR): 0.224ns Clock Net Delay (Source): 1.225ns (routing 0.485ns, distribution 0.740ns) Clock Net Delay (Destination): 1.439ns (routing 0.546ns, distribution 0.893ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.343 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X91Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y563 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.392 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Q net (fo=2, routed) 0.037 1.429 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_9_in SLICE_X91Y563 LUT3 (Prop_E6LUT_SLICEL_I0_O) 0.045 1.474 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__22/O net (fo=1, routed) 0.012 1.486 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] SLICE_X91Y563 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.439 1.604 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X91Y563 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.224 1.380 SLICE_X91Y563 FDRE (Hold_EFF_SLICEL_C_D) 0.056 1.436 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.436 arrival time 1.486 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.425ns Source Clock Delay (SCD): 1.189ns Clock Pessimism Removal (CPR): 0.231ns Clock Net Delay (Source): 1.071ns (routing 0.485ns, distribution 0.586ns) Clock Net Delay (Destination): 1.260ns (routing 0.546ns, distribution 0.714ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.071 1.189 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/CLK SLICE_X99Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X99Y565 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.238 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.035 1.273 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/ready_from_bitSlipCtrller_11 SLICE_X99Y565 LUT3 (Prop_A6LUT_SLICEL_I2_O) 0.015 1.288 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_i_1__22/O net (fo=1, routed) 0.012 1.300 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_i_1__22_n_0 SLICE_X99Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.260 1.425 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/CLK SLICE_X99Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg/C clock pessimism -0.231 1.194 SLICE_X99Y565 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.250 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.250 arrival time 1.300 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.094ns (63.513%) route 0.054ns (36.486%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.608ns Source Clock Delay (SCD): 1.343ns Clock Pessimism Removal (CPR): 0.224ns Clock Net Delay (Source): 1.225ns (routing 0.485ns, distribution 0.740ns) Clock Net Delay (Destination): 1.443ns (routing 0.546ns, distribution 0.897ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.343 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X90Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X90Y563 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.392 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.038 1.430 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in SLICE_X90Y563 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__22/O net (fo=1, routed) 0.016 1.491 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] SLICE_X90Y563 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.443 1.608 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X90Y563 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.224 1.384 SLICE_X90Y563 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.440 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.440 arrival time 1.491 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.052ns (arrival time - required time) Source: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[27]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.049ns (32.886%) route 0.100ns (67.114%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.611ns Source Clock Delay (SCD): 1.354ns Clock Pessimism Removal (CPR): 0.216ns Clock Net Delay (Source): 1.236ns (routing 0.485ns, distribution 0.751ns) Clock Net Delay (Destination): 1.446ns (routing 0.546ns, distribution 0.900ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.236 1.354 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y561 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y561 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.403 r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[27]/Q net (fo=2, routed) 0.100 1.503 SFP_GEN[23].ngCCM_gbt/gbt_rx_checker/Q[11] SLICE_X84Y559 FDRE r SFP_GEN[23].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.446 1.611 SFP_GEN[23].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y559 FDRE r SFP_GEN[23].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C clock pessimism -0.216 1.395 SLICE_X84Y559 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.451 SFP_GEN[23].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11] ------------------------------------------------------------------- required time -1.451 arrival time 1.503 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_14 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.604ns Source Clock Delay (SCD): 1.343ns Clock Pessimism Removal (CPR): 0.224ns Clock Net Delay (Source): 1.225ns (routing 0.485ns, distribution 0.740ns) Clock Net Delay (Destination): 1.439ns (routing 0.546ns, distribution 0.893ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.225 1.343 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X91Y563 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y563 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.392 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.035 1.427 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_13_in SLICE_X91Y563 LUT3 (Prop_H6LUT_SLICEL_I2_O) 0.045 1.472 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__22/O net (fo=1, routed) 0.016 1.488 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[5] SLICE_X91Y563 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.439 1.604 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X91Y563 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.224 1.380 SLICE_X91Y563 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.436 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.436 arrival time 1.488 ------------------------------------------------------------------- slack 0.052 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_14 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y222 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X73Y531 g_clock_rate_din[23].ngccm_status_cnt_reg[23][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X73Y531 g_clock_rate_din[23].ngccm_status_cnt_reg[23][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X73Y531 g_clock_rate_din[23].ngccm_status_cnt_reg[23][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X73Y531 g_clock_rate_din[23].ngccm_status_cnt_reg[23][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X73Y531 g_clock_rate_din[23].ngccm_status_cnt_reg[23][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X73Y531 g_clock_rate_din[23].ngccm_status_cnt_reg[23][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X72Y531 g_clock_rate_din[23].ngccm_status_cnt_reg[23][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X87Y563 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X87Y563 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X87Y563 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X87Y563 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X87Y563 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X91Y563 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X72Y531 g_clock_rate_din[23].ngccm_status_cnt_reg[23][6]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X72Y531 g_clock_rate_din[23].ngccm_status_cnt_reg[23][7]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X72Y531 g_clock_rate_din[23].rx_test_comm_cnt_reg[23]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X72Y475 g_clock_rate_din[23].rx_wordclk_div2_reg[23]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X97Y569 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X97Y568 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y39 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_15 To Clock: gtwiz_userclk_rx_srcclk_out[0]_15 Setup : 0 Failing Endpoints, Worst Slack 3.354ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.354ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.639ns (logic 1.719ns (37.055%) route 2.920ns (62.945%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.674ns = ( 10.991 - 8.317 ) Source Clock Delay (SCD): 3.154ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.679ns (routing 1.082ns, distribution 1.597ns) Clock Net Delay (Destination): 2.276ns (routing 0.990ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.679 3.154 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.315 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.221 6.536 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y444 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.774 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.275 7.049 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y446 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.150 7.199 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12/O net (fo=1, routed) 0.081 7.280 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12_n_0 SLICE_X109Y446 LUT6 (Prop_E6LUT_SLICEM_I5_O) 0.170 7.450 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12/O net (fo=2, routed) 0.343 7.793 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12_n_0 SLICE_X109Y444 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.991 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y444 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.246 11.237 clock uncertainty -0.035 11.202 SLICE_X109Y444 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.147 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.147 arrival time -7.793 ------------------------------------------------------------------- slack 3.354 Slack (MET) : 3.354ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.639ns (logic 1.719ns (37.055%) route 2.920ns (62.945%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.674ns = ( 10.991 - 8.317 ) Source Clock Delay (SCD): 3.154ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.679ns (routing 1.082ns, distribution 1.597ns) Clock Net Delay (Destination): 2.276ns (routing 0.990ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.679 3.154 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.315 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.221 6.536 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y444 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.774 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.275 7.049 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y446 LUT4 (Prop_B6LUT_SLICEM_I2_O) 0.150 7.199 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12/O net (fo=1, routed) 0.081 7.280 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12_n_0 SLICE_X109Y446 LUT6 (Prop_E6LUT_SLICEM_I5_O) 0.170 7.450 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12/O net (fo=2, routed) 0.343 7.793 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12_n_0 SLICE_X109Y444 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.276 10.991 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y444 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.246 11.237 clock uncertainty -0.035 11.202 SLICE_X109Y444 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.147 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.147 arrival time -7.793 ------------------------------------------------------------------- slack 3.354 Slack (MET) : 3.367ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.627ns (logic 1.642ns (35.487%) route 2.985ns (64.513%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.675ns = ( 10.992 - 8.317 ) Source Clock Delay (SCD): 3.154ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.679ns (routing 1.082ns, distribution 1.597ns) Clock Net Delay (Destination): 2.277ns (routing 0.990ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.679 3.154 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.315 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.221 6.536 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y444 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.774 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.299 7.073 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y446 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 7.316 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/O net (fo=7, routed) 0.465 7.781 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X109Y445 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.277 10.992 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y445 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.246 11.238 clock uncertainty -0.035 11.203 SLICE_X109Y445 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.148 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.148 arrival time -7.781 ------------------------------------------------------------------- slack 3.367 Slack (MET) : 3.367ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.627ns (logic 1.642ns (35.487%) route 2.985ns (64.513%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.675ns = ( 10.992 - 8.317 ) Source Clock Delay (SCD): 3.154ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.679ns (routing 1.082ns, distribution 1.597ns) Clock Net Delay (Destination): 2.277ns (routing 0.990ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.679 3.154 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.315 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.221 6.536 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y444 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.774 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.299 7.073 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y446 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 7.316 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/O net (fo=7, routed) 0.465 7.781 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X109Y445 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.277 10.992 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y445 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.246 11.238 clock uncertainty -0.035 11.203 SLICE_X109Y445 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.148 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.148 arrival time -7.781 ------------------------------------------------------------------- slack 3.367 Slack (MET) : 3.371ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.624ns (logic 1.642ns (35.510%) route 2.982ns (64.490%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.675ns = ( 10.992 - 8.317 ) Source Clock Delay (SCD): 3.154ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.679ns (routing 1.082ns, distribution 1.597ns) Clock Net Delay (Destination): 2.277ns (routing 0.990ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.679 3.154 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.315 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.221 6.536 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y444 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.774 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.299 7.073 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y446 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 7.316 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/O net (fo=7, routed) 0.462 7.778 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X109Y445 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.277 10.992 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y445 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.246 11.238 clock uncertainty -0.035 11.203 SLICE_X109Y445 FDRE (Setup_AFF_SLICEM_C_CE) -0.054 11.149 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.149 arrival time -7.778 ------------------------------------------------------------------- slack 3.371 Slack (MET) : 3.371ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.624ns (logic 1.642ns (35.510%) route 2.982ns (64.490%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.675ns = ( 10.992 - 8.317 ) Source Clock Delay (SCD): 3.154ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.679ns (routing 1.082ns, distribution 1.597ns) Clock Net Delay (Destination): 2.277ns (routing 0.990ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.679 3.154 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.315 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.221 6.536 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y444 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.774 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.299 7.073 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y446 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 7.316 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/O net (fo=7, routed) 0.462 7.778 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X109Y445 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.277 10.992 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y445 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.246 11.238 clock uncertainty -0.035 11.203 SLICE_X109Y445 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.149 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.149 arrival time -7.778 ------------------------------------------------------------------- slack 3.371 Slack (MET) : 3.371ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.624ns (logic 1.642ns (35.510%) route 2.982ns (64.490%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.675ns = ( 10.992 - 8.317 ) Source Clock Delay (SCD): 3.154ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.679ns (routing 1.082ns, distribution 1.597ns) Clock Net Delay (Destination): 2.277ns (routing 0.990ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.679 3.154 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.315 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.221 6.536 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y444 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.774 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.299 7.073 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y446 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 7.316 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/O net (fo=7, routed) 0.462 7.778 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X109Y445 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.277 10.992 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y445 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.246 11.238 clock uncertainty -0.035 11.203 SLICE_X109Y445 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.149 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.149 arrival time -7.778 ------------------------------------------------------------------- slack 3.371 Slack (MET) : 3.407ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.602ns (logic 1.642ns (35.680%) route 2.960ns (64.320%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 3.154ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.679ns (routing 1.082ns, distribution 1.597ns) Clock Net Delay (Destination): 2.292ns (routing 0.990ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.679 3.154 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.315 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.221 6.536 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y444 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.774 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.299 7.073 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y446 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 7.316 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/O net (fo=7, routed) 0.440 7.756 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X108Y447 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.292 11.007 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y447 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.246 11.253 clock uncertainty -0.035 11.218 SLICE_X108Y447 FDRE (Setup_BFF2_SLICEL_C_CE) -0.055 11.163 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.163 arrival time -7.756 ------------------------------------------------------------------- slack 3.407 Slack (MET) : 3.412ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.598ns (logic 1.642ns (35.711%) route 2.956ns (64.289%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 3.154ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.679ns (routing 1.082ns, distribution 1.597ns) Clock Net Delay (Destination): 2.292ns (routing 0.990ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.679 3.154 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.315 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.221 6.536 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y444 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.774 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.299 7.073 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X109Y446 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 7.316 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/O net (fo=7, routed) 0.436 7.752 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X108Y447 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.292 11.007 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y447 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.246 11.253 clock uncertainty -0.035 11.218 SLICE_X108Y447 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 11.164 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.164 arrival time -7.752 ------------------------------------------------------------------- slack 3.412 Slack (MET) : 3.493ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 4.497ns (logic 1.452ns (32.288%) route 3.045ns (67.712%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.237ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.671ns = ( 10.988 - 8.317 ) Source Clock Delay (SCD): 3.154ns Clock Pessimism Removal (CPR): 0.246ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.679ns (routing 1.082ns, distribution 1.597ns) Clock Net Delay (Destination): 2.273ns (routing 0.990ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.679 3.154 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.315 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.221 6.536 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X108Y444 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.774 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/O net (fo=5, routed) 0.316 7.090 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X108Y445 LUT6 (Prop_H6LUT_SLICEL_I0_O) 0.053 7.143 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/O net (fo=5, routed) 0.508 7.651 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 SLICE_X112Y446 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.273 10.988 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X112Y446 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.246 11.234 clock uncertainty -0.035 11.199 SLICE_X112Y446 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.144 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.144 arrival time -7.651 ------------------------------------------------------------------- slack 3.493 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.064ns (41.026%) route 0.092ns (58.974%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.352ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.983ns (routing 0.459ns, distribution 0.524ns) Clock Net Delay (Destination): 1.187ns (routing 0.521ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.101 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y445 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y445 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.149 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/Q net (fo=6, routed) 0.076 1.225 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnt[1] SLICE_X107Y444 LUT6 (Prop_D6LUT_SLICEM_I2_O) 0.016 1.241 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_inv_i_1__13/O net (fo=1, routed) 0.016 1.257 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr3_out SLICE_X107Y444 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.187 1.352 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y444 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv/C clock pessimism -0.186 1.166 SLICE_X107Y444 FDPE (Hold_DFF_SLICEM_C_D) 0.056 1.222 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv ------------------------------------------------------------------- required time -1.222 arrival time 1.257 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.094ns (51.087%) route 0.090ns (48.913%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.355ns Source Clock Delay (SCD): 1.108ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.990ns (routing 0.459ns, distribution 0.531ns) Clock Net Delay (Destination): 1.190ns (routing 0.521ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.108 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X112Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y438 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.157 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.075 1.232 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X111Y438 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.045 1.277 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__12/O net (fo=1, routed) 0.015 1.292 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[1] SLICE_X111Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.355 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X111Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.155 1.200 SLICE_X111Y438 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.256 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.256 arrival time 1.292 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.049ns (27.222%) route 0.131ns (72.778%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.351ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.991ns (routing 0.459ns, distribution 0.532ns) Clock Net Delay (Destination): 1.186ns (routing 0.521ns, distribution 0.665ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.109 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y441 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y441 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.158 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/Q net (fo=1, routed) 0.131 1.289 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[30] SLICE_X108Y441 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.186 1.351 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y441 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]/C clock pessimism -0.155 1.196 SLICE_X108Y441 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.252 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30] ------------------------------------------------------------------- required time -1.252 arrival time 1.289 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[13].rx_data_ngccm_reg[13][43]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.187ns (logic 0.048ns (25.668%) route 0.139ns (74.332%)) Logic Levels: 0 Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.991ns (routing 0.459ns, distribution 0.532ns) Clock Net Delay (Destination): 1.192ns (routing 0.521ns, distribution 0.671ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.109 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X113Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y436 FDRE (Prop_GFF_SLICEM_C_Q) 0.048 1.157 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.139 1.296 rx_data[13][43] SLICE_X111Y436 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][43]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.357 g_gbt_bank[1].gbtbank_n_34 SLICE_X111Y436 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][43]/C clock pessimism -0.155 1.202 SLICE_X111Y436 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.258 SFP_GEN[13].rx_data_ngccm_reg[13][43] ------------------------------------------------------------------- required time -1.258 arrival time 1.296 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.187ns (logic 0.103ns (55.080%) route 0.084ns (44.920%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.355ns Source Clock Delay (SCD): 1.108ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.990ns (routing 0.459ns, distribution 0.531ns) Clock Net Delay (Destination): 1.190ns (routing 0.521ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.108 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X112Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y438 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.156 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.073 1.229 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[1] SLICE_X111Y438 LUT3 (Prop_C5LUT_SLICEL_I2_O) 0.055 1.284 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__12/O net (fo=1, routed) 0.011 1.295 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[18] SLICE_X111Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.355 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X111Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.155 1.200 SLICE_X111Y438 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.256 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -1.256 arrival time 1.295 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.094ns (51.087%) route 0.090ns (48.913%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.352ns Source Clock Delay (SCD): 1.108ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.990ns (routing 0.459ns, distribution 0.531ns) Clock Net Delay (Destination): 1.187ns (routing 0.521ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.108 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X112Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y438 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.157 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.074 1.231 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_29_in SLICE_X111Y438 LUT3 (Prop_H6LUT_SLICEL_I2_O) 0.045 1.276 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__12/O net (fo=1, routed) 0.016 1.292 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[13] SLICE_X111Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.187 1.352 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X111Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.155 1.197 SLICE_X111Y438 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.253 arrival time 1.292 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[13].rx_data_ngccm_reg[13][37]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.049ns (32.886%) route 0.100ns (67.114%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.117ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.999ns (routing 0.459ns, distribution 0.540ns) Clock Net Delay (Destination): 1.192ns (routing 0.521ns, distribution 0.671ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X108Y437 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y437 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.166 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/Q net (fo=1, routed) 0.100 1.266 rx_data[13][37] SLICE_X108Y435 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][37]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.357 g_gbt_bank[1].gbtbank_n_34 SLICE_X108Y435 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][37]/C clock pessimism -0.186 1.171 SLICE_X108Y435 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.226 SFP_GEN[13].rx_data_ngccm_reg[13][37] ------------------------------------------------------------------- required time -1.226 arrival time 1.266 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[21]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.064ns (42.105%) route 0.088ns (57.895%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.998ns (routing 0.459ns, distribution 0.539ns) Clock Net Delay (Destination): 1.189ns (routing 0.521ns, distribution 0.668ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y442 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/Q net (fo=29, routed) 0.072 1.237 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] SLICE_X108Y441 LUT5 (Prop_D6LUT_SLICEL_I2_O) 0.015 1.252 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[21]_i_1__11/O net (fo=1, routed) 0.016 1.268 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg00[21] SLICE_X108Y441 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[21]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.354 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y441 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[21]/C clock pessimism -0.186 1.168 SLICE_X108Y441 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.224 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[21] ------------------------------------------------------------------- required time -1.224 arrival time 1.268 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[13].rx_data_ngccm_reg[13][54]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.049ns (32.026%) route 0.104ns (67.974%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.997ns (routing 0.459ns, distribution 0.538ns) Clock Net Delay (Destination): 1.188ns (routing 0.521ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X114Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y438 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.164 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/Q net (fo=1, routed) 0.104 1.268 rx_data[13][54] SLICE_X114Y437 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][54]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.353 g_gbt_bank[1].gbtbank_n_34 SLICE_X114Y437 FDCE r SFP_GEN[13].rx_data_ngccm_reg[13][54]/C clock pessimism -0.186 1.167 SLICE_X114Y437 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.223 SFP_GEN[13].rx_data_ngccm_reg[13][54] ------------------------------------------------------------------- required time -1.223 arrival time 1.268 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_15 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.104ns (54.737%) route 0.086ns (45.263%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.352ns Source Clock Delay (SCD): 1.108ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.990ns (routing 0.459ns, distribution 0.531ns) Clock Net Delay (Destination): 1.187ns (routing 0.521ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.108 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X112Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y438 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.157 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.074 1.231 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_29_in SLICE_X111Y438 LUT3 (Prop_H5LUT_SLICEL_I0_O) 0.055 1.286 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__12/O net (fo=1, routed) 0.012 1.298 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[15] SLICE_X111Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.187 1.352 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X111Y438 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.155 1.197 SLICE_X111Y438 FDRE (Hold_HFF2_SLICEL_C_D) 0.056 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -1.253 arrival time 1.298 ------------------------------------------------------------------- slack 0.045 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_15 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y191 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y416 g_clock_rate_din[13].ngccm_status_cnt_reg[13][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y416 g_clock_rate_din[13].ngccm_status_cnt_reg[13][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y416 g_clock_rate_din[13].ngccm_status_cnt_reg[13][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y416 g_clock_rate_din[13].ngccm_status_cnt_reg[13][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y416 g_clock_rate_din[13].ngccm_status_cnt_reg[13][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X79Y416 g_clock_rate_din[13].ngccm_status_cnt_reg[13][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X86Y422 g_clock_rate_din[13].ngccm_status_cnt_reg[13][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y416 g_clock_rate_din[13].ngccm_status_cnt_reg[13][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y416 g_clock_rate_din[13].ngccm_status_cnt_reg[13][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y416 g_clock_rate_din[13].ngccm_status_cnt_reg[13][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y416 g_clock_rate_din[13].ngccm_status_cnt_reg[13][3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y416 g_clock_rate_din[13].ngccm_status_cnt_reg[13][4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X79Y416 g_clock_rate_din[13].ngccm_status_cnt_reg[13][5]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X86Y422 g_clock_rate_din[13].ngccm_status_cnt_reg[13][6]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X86Y422 g_clock_rate_din[13].rx_test_comm_cnt_reg[13]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X100Y434 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X101Y434 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X101Y435 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X101Y435 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_16 To Clock: gtwiz_userclk_rx_srcclk_out[0]_16 Setup : 0 Failing Endpoints, Worst Slack 1.858ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.033ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.858ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 6.413ns (logic 1.745ns (27.210%) route 4.668ns (72.790%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.699ns = ( 11.016 - 8.317 ) Source Clock Delay (SCD): 2.882ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.407ns (routing 0.732ns, distribution 1.675ns) Clock Net Delay (Destination): 2.301ns (routing 0.665ns, distribution 1.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.407 2.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.043 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.880 7.923 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X89Y434 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 8.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.298 8.465 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y433 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.167 8.632 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13/O net (fo=1, routed) 0.084 8.716 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13_n_0 SLICE_X89Y433 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 8.889 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13/O net (fo=2, routed) 0.406 9.295 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13_n_0 SLICE_X89Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.301 11.016 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.226 11.242 clock uncertainty -0.035 11.207 SLICE_X89Y434 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 11.153 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.153 arrival time -9.295 ------------------------------------------------------------------- slack 1.858 Slack (MET) : 1.858ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 6.413ns (logic 1.745ns (27.210%) route 4.668ns (72.790%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.699ns = ( 11.016 - 8.317 ) Source Clock Delay (SCD): 2.882ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.407ns (routing 0.732ns, distribution 1.675ns) Clock Net Delay (Destination): 2.301ns (routing 0.665ns, distribution 1.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.407 2.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.043 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.880 7.923 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X89Y434 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 8.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.298 8.465 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y433 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.167 8.632 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13/O net (fo=1, routed) 0.084 8.716 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13_n_0 SLICE_X89Y433 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 8.889 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13/O net (fo=2, routed) 0.406 9.295 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13_n_0 SLICE_X89Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.301 11.016 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.226 11.242 clock uncertainty -0.035 11.207 SLICE_X89Y434 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 11.153 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.153 arrival time -9.295 ------------------------------------------------------------------- slack 1.858 Slack (MET) : 1.942ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 6.305ns (logic 1.628ns (25.821%) route 4.677ns (74.179%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.020ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.676ns = ( 10.993 - 8.317 ) Source Clock Delay (SCD): 2.882ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.407ns (routing 0.732ns, distribution 1.675ns) Clock Net Delay (Destination): 2.278ns (routing 0.665ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.407 2.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.043 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.880 7.923 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X89Y434 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 8.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.322 8.489 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y433 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.223 8.712 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/O net (fo=7, routed) 0.475 9.187 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X90Y434 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.278 10.993 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y434 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.226 11.219 clock uncertainty -0.035 11.184 SLICE_X90Y434 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.129 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.129 arrival time -9.187 ------------------------------------------------------------------- slack 1.942 Slack (MET) : 1.946ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 6.302ns (logic 1.628ns (25.833%) route 4.674ns (74.167%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.020ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.676ns = ( 10.993 - 8.317 ) Source Clock Delay (SCD): 2.882ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.407ns (routing 0.732ns, distribution 1.675ns) Clock Net Delay (Destination): 2.278ns (routing 0.665ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.407 2.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.043 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.880 7.923 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X89Y434 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 8.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.322 8.489 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y433 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.223 8.712 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/O net (fo=7, routed) 0.472 9.184 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X90Y434 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.278 10.993 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y434 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.226 11.219 clock uncertainty -0.035 11.184 SLICE_X90Y434 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.130 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.130 arrival time -9.184 ------------------------------------------------------------------- slack 1.946 Slack (MET) : 1.985ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 6.284ns (logic 1.628ns (25.907%) route 4.656ns (74.093%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.698ns = ( 11.015 - 8.317 ) Source Clock Delay (SCD): 2.882ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.407ns (routing 0.732ns, distribution 1.675ns) Clock Net Delay (Destination): 2.300ns (routing 0.665ns, distribution 1.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.407 2.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.043 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.880 7.923 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X89Y434 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 8.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.322 8.489 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y433 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.223 8.712 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/O net (fo=7, routed) 0.454 9.166 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X89Y435 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.300 11.015 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y435 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.226 11.241 clock uncertainty -0.035 11.206 SLICE_X89Y435 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.151 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.151 arrival time -9.166 ------------------------------------------------------------------- slack 1.985 Slack (MET) : 1.989ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 6.281ns (logic 1.628ns (25.919%) route 4.653ns (74.081%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.698ns = ( 11.015 - 8.317 ) Source Clock Delay (SCD): 2.882ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.407ns (routing 0.732ns, distribution 1.675ns) Clock Net Delay (Destination): 2.300ns (routing 0.665ns, distribution 1.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.407 2.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.043 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.880 7.923 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X89Y434 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 8.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.322 8.489 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y433 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.223 8.712 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/O net (fo=7, routed) 0.451 9.163 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X89Y435 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.300 11.015 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y435 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.226 11.241 clock uncertainty -0.035 11.206 SLICE_X89Y435 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.152 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.152 arrival time -9.163 ------------------------------------------------------------------- slack 1.989 Slack (MET) : 1.989ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 6.281ns (logic 1.628ns (25.919%) route 4.653ns (74.081%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.698ns = ( 11.015 - 8.317 ) Source Clock Delay (SCD): 2.882ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.407ns (routing 0.732ns, distribution 1.675ns) Clock Net Delay (Destination): 2.300ns (routing 0.665ns, distribution 1.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.407 2.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.043 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.880 7.923 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X89Y434 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 8.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.322 8.489 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y433 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.223 8.712 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/O net (fo=7, routed) 0.451 9.163 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X89Y435 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.300 11.015 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y435 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.226 11.241 clock uncertainty -0.035 11.206 SLICE_X89Y435 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.152 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.152 arrival time -9.163 ------------------------------------------------------------------- slack 1.989 Slack (MET) : 2.086ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 6.179ns (logic 1.628ns (26.347%) route 4.551ns (73.653%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.041ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 2.882ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.407ns (routing 0.732ns, distribution 1.675ns) Clock Net Delay (Destination): 2.299ns (routing 0.665ns, distribution 1.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.407 2.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.043 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.880 7.923 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X89Y434 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 8.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.322 8.489 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y433 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.223 8.712 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/O net (fo=7, routed) 0.349 9.061 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X89Y435 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.299 11.014 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y435 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.226 11.240 clock uncertainty -0.035 11.205 SLICE_X89Y435 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.147 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.147 arrival time -9.061 ------------------------------------------------------------------- slack 2.086 Slack (MET) : 2.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 6.096ns (logic 1.628ns (26.706%) route 4.468ns (73.294%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 2.882ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.407ns (routing 0.732ns, distribution 1.675ns) Clock Net Delay (Destination): 2.292ns (routing 0.665ns, distribution 1.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.407 2.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.043 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.880 7.923 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X89Y434 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 8.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.322 8.489 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y433 LUT5 (Prop_G6LUT_SLICEM_I3_O) 0.223 8.712 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/O net (fo=7, routed) 0.266 8.978 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X89Y433 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.292 11.007 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y433 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.226 11.233 clock uncertainty -0.035 11.198 SLICE_X89Y433 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.143 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.143 arrival time -8.978 ------------------------------------------------------------------- slack 2.165 Slack (MET) : 2.166ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 6.085ns (logic 1.648ns (27.083%) route 4.437ns (72.917%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.680ns = ( 10.997 - 8.317 ) Source Clock Delay (SCD): 2.882ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.407ns (routing 0.732ns, distribution 1.675ns) Clock Net Delay (Destination): 2.282ns (routing 0.665ns, distribution 1.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.407 2.882 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 4.043 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.880 7.923 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X89Y434 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 8.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/O net (fo=5, routed) 0.194 8.361 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X89Y433 LUT6 (Prop_B6LUT_SLICEM_I5_O) 0.243 8.604 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__14/O net (fo=3, routed) 0.363 8.967 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecFalseHeaders0 SLICE_X88Y432 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.282 10.997 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X88Y432 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.226 11.223 clock uncertainty -0.035 11.188 SLICE_X88Y432 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.133 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.133 arrival time -8.967 ------------------------------------------------------------------- slack 2.166 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[28]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 1.026ns (routing 0.320ns, distribution 0.706ns) Clock Net Delay (Destination): 1.216ns (routing 0.362ns, distribution 0.854ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.144 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y437 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y437 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.192 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]/Q net (fo=1, routed) 0.094 1.286 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[28] SLICE_X80Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.216 1.381 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[28]/C clock pessimism -0.184 1.197 SLICE_X80Y438 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[28] ------------------------------------------------------------------- required time -1.253 arrival time 1.286 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[29]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 1.026ns (routing 0.320ns, distribution 0.706ns) Clock Net Delay (Destination): 1.216ns (routing 0.362ns, distribution 0.854ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.144 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y437 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y437 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.193 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]/Q net (fo=1, routed) 0.095 1.288 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[29] SLICE_X80Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.216 1.381 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[29]/C clock pessimism -0.184 1.197 SLICE_X80Y438 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[29] ------------------------------------------------------------------- required time -1.253 arrival time 1.288 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.204ns (logic 0.063ns (30.882%) route 0.141ns (69.118%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.109ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.382ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.002ns (routing 0.320ns, distribution 0.682ns) Clock Net Delay (Destination): 1.217ns (routing 0.362ns, distribution 0.855ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.120 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y437 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y437 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.168 f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Q net (fo=28, routed) 0.125 1.293 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] SLICE_X80Y437 LUT5 (Prop_C6LUT_SLICEL_I0_O) 0.015 1.308 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[38]_i_1__12/O net (fo=1, routed) 0.016 1.324 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg00[38] SLICE_X80Y437 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.382 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y437 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]/C clock pessimism -0.153 1.229 SLICE_X80Y437 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.285 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38] ------------------------------------------------------------------- required time -1.285 arrival time 1.324 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.205ns (logic 0.063ns (30.732%) route 0.142ns (69.268%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.109ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.382ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.002ns (routing 0.320ns, distribution 0.682ns) Clock Net Delay (Destination): 1.217ns (routing 0.362ns, distribution 0.855ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.120 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y437 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y437 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.168 f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Q net (fo=28, routed) 0.126 1.294 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] SLICE_X80Y437 LUT5 (Prop_D6LUT_SLICEL_I0_O) 0.015 1.309 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[36]_i_1__12/O net (fo=1, routed) 0.016 1.325 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg00[36] SLICE_X80Y437 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.217 1.382 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y437 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/C clock pessimism -0.153 1.229 SLICE_X80Y437 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.285 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36] ------------------------------------------------------------------- required time -1.285 arrival time 1.325 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.080ns (46.784%) route 0.091ns (53.216%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.350ns Source Clock Delay (SCD): 1.124ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.006ns (routing 0.320ns, distribution 0.686ns) Clock Net Delay (Destination): 1.185ns (routing 0.362ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.006 1.124 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X81Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y429 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.173 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.075 1.248 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_35_in SLICE_X82Y429 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.031 1.279 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__13/O net (fo=1, routed) 0.016 1.295 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[16] SLICE_X82Y429 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.350 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X82Y429 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.153 1.197 SLICE_X82Y429 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.253 arrival time 1.295 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[14].rx_data_ngccm_reg[14][55]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.049ns (32.237%) route 0.103ns (67.763%)) Logic Levels: 0 Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.355ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.005ns (routing 0.320ns, distribution 0.685ns) Clock Net Delay (Destination): 1.190ns (routing 0.362ns, distribution 0.828ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.123 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X83Y430 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X83Y430 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 1.172 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.103 1.275 rx_data[14][55] SLICE_X83Y428 FDCE r SFP_GEN[14].rx_data_ngccm_reg[14][55]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.355 g_gbt_bank[1].gbtbank_n_44 SLICE_X83Y428 FDCE r SFP_GEN[14].rx_data_ngccm_reg[14][55]/C clock pessimism -0.181 1.174 SLICE_X83Y428 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.229 SFP_GEN[14].rx_data_ngccm_reg[14][55] ------------------------------------------------------------------- required time -1.229 arrival time 1.275 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.089ns (50.568%) route 0.087ns (49.432%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.350ns Source Clock Delay (SCD): 1.124ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.006ns (routing 0.320ns, distribution 0.686ns) Clock Net Delay (Destination): 1.185ns (routing 0.362ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.006 1.124 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X81Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y429 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.173 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.075 1.248 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_35_in SLICE_X82Y429 LUT3 (Prop_D5LUT_SLICEM_I0_O) 0.040 1.288 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__13/O net (fo=1, routed) 0.012 1.300 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[18] SLICE_X82Y429 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.350 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X82Y429 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.153 1.197 SLICE_X82Y429 FDRE (Hold_DFF2_SLICEM_C_D) 0.056 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -1.253 arrival time 1.300 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.384ns Source Clock Delay (SCD): 1.149ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.031ns (routing 0.320ns, distribution 0.711ns) Clock Net Delay (Destination): 1.219ns (routing 0.362ns, distribution 0.857ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.031 1.149 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X77Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y436 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.198 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.035 1.233 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_21_in SLICE_X77Y436 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.278 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__13/O net (fo=1, routed) 0.016 1.294 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] SLICE_X77Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.219 1.384 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X77Y436 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.194 1.190 SLICE_X77Y436 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.246 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.246 arrival time 1.294 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/psAddress_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.080ns (42.553%) route 0.108ns (57.447%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.980ns (routing 0.320ns, distribution 0.660ns) Clock Net Delay (Destination): 1.171ns (routing 0.362ns, distribution 0.809ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.098 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/psAddress_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X90Y434 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.146 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/psAddress_reg[2]/Q net (fo=8, routed) 0.092 1.238 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/psAddress[2] SLICE_X89Y434 LUT6 (Prop_H6LUT_SLICEM_I3_O) 0.032 1.270 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd_i_1__13/O net (fo=1, routed) 0.016 1.286 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd SLICE_X89Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd_reg/C clock pessimism -0.154 1.182 SLICE_X89Y434 FDCE (Hold_HFF_SLICEM_C_D) 0.056 1.238 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCmd_reg ------------------------------------------------------------------- required time -1.238 arrival time 1.286 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_16 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.374ns Source Clock Delay (SCD): 1.144ns Clock Pessimism Removal (CPR): 0.225ns Clock Net Delay (Source): 1.026ns (routing 0.320ns, distribution 0.706ns) Clock Net Delay (Destination): 1.209ns (routing 0.362ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.144 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y435 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.193 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/Q net (fo=9, routed) 0.033 1.226 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].cnt_reg[2][7]_0[3] SLICE_X79Y435 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.241 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].cnt[2][3]_i_1__0/O net (fo=1, routed) 0.012 1.253 g_gbt_bank[1].gbtbank/i_gbt_bank_n_250 SLICE_X79Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.209 1.374 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/C clock pessimism -0.225 1.149 SLICE_X79Y435 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.205 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3] ------------------------------------------------------------------- required time -1.205 arrival time 1.253 ------------------------------------------------------------------- slack 0.048 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_16 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y171 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y421 g_clock_rate_din[14].ngccm_status_cnt_reg[14][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y421 g_clock_rate_din[14].ngccm_status_cnt_reg[14][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y425 g_clock_rate_din[14].ngccm_status_cnt_reg[14][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][5]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X71Y451 g_clock_rate_din[14].rx_wordclk_div2_reg[14]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X71Y451 g_clock_rate_din[14].rx_wordclk_div2_reg[14]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y421 g_clock_rate_din[14].ngccm_status_cnt_reg[14][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y421 g_clock_rate_din[14].ngccm_status_cnt_reg[14][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y422 g_clock_rate_din[14].ngccm_status_cnt_reg[14][5]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_17 To Clock: gtwiz_userclk_rx_srcclk_out[0]_17 Setup : 0 Failing Endpoints, Worst Slack 3.270ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.485ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.270ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][66]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.615ns (logic 0.286ns (6.197%) route 4.329ns (93.803%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.342ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.375ns = ( 10.692 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.977ns (routing 0.664ns, distribution 1.313ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.592 5.664 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 5.811 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/O net (fo=76, routed) 1.737 7.548 rx_data_ngccm[15] SLICE_X114Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][66]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.977 10.692 g_gbt_bank[1].gbtbank_n_54 SLICE_X114Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][66]/C clock pessimism 0.216 10.908 clock uncertainty -0.035 10.873 SLICE_X114Y426 FDCE (Setup_AFF2_SLICEL_C_CE) -0.055 10.818 SFP_GEN[15].rx_data_ngccm_reg[15][66] ------------------------------------------------------------------- required time 10.818 arrival time -7.548 ------------------------------------------------------------------- slack 3.270 Slack (MET) : 3.270ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][70]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.615ns (logic 0.286ns (6.197%) route 4.329ns (93.803%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.342ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.375ns = ( 10.692 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.977ns (routing 0.664ns, distribution 1.313ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.592 5.664 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 5.811 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/O net (fo=76, routed) 1.737 7.548 rx_data_ngccm[15] SLICE_X114Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][70]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.977 10.692 g_gbt_bank[1].gbtbank_n_54 SLICE_X114Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][70]/C clock pessimism 0.216 10.908 clock uncertainty -0.035 10.873 SLICE_X114Y426 FDCE (Setup_BFF2_SLICEL_C_CE) -0.055 10.818 SFP_GEN[15].rx_data_ngccm_reg[15][70] ------------------------------------------------------------------- required time 10.818 arrival time -7.548 ------------------------------------------------------------------- slack 3.270 Slack (MET) : 3.271ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][65]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.616ns (logic 0.286ns (6.196%) route 4.330ns (93.804%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.337ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.380ns = ( 10.697 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.982ns (routing 0.664ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.592 5.664 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 5.811 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/O net (fo=76, routed) 1.738 7.549 rx_data_ngccm[15] SLICE_X115Y425 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][65]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.982 10.697 g_gbt_bank[1].gbtbank_n_54 SLICE_X115Y425 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][65]/C clock pessimism 0.216 10.913 clock uncertainty -0.035 10.878 SLICE_X115Y425 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 10.820 SFP_GEN[15].rx_data_ngccm_reg[15][65] ------------------------------------------------------------------- required time 10.820 arrival time -7.549 ------------------------------------------------------------------- slack 3.271 Slack (MET) : 3.271ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][69]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.616ns (logic 0.286ns (6.196%) route 4.330ns (93.804%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.337ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.380ns = ( 10.697 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.982ns (routing 0.664ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.592 5.664 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 5.811 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/O net (fo=76, routed) 1.738 7.549 rx_data_ngccm[15] SLICE_X115Y425 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][69]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.982 10.697 g_gbt_bank[1].gbtbank_n_54 SLICE_X115Y425 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][69]/C clock pessimism 0.216 10.913 clock uncertainty -0.035 10.878 SLICE_X115Y425 FDCE (Setup_FFF2_SLICEM_C_CE) -0.058 10.820 SFP_GEN[15].rx_data_ngccm_reg[15][69] ------------------------------------------------------------------- required time 10.820 arrival time -7.549 ------------------------------------------------------------------- slack 3.271 Slack (MET) : 3.271ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][73]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.616ns (logic 0.286ns (6.196%) route 4.330ns (93.804%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.337ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.380ns = ( 10.697 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.982ns (routing 0.664ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.592 5.664 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 5.811 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/O net (fo=76, routed) 1.738 7.549 rx_data_ngccm[15] SLICE_X115Y425 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][73]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.982 10.697 g_gbt_bank[1].gbtbank_n_54 SLICE_X115Y425 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][73]/C clock pessimism 0.216 10.913 clock uncertainty -0.035 10.878 SLICE_X115Y425 FDCE (Setup_GFF2_SLICEM_C_CE) -0.058 10.820 SFP_GEN[15].rx_data_ngccm_reg[15][73] ------------------------------------------------------------------- required time 10.820 arrival time -7.549 ------------------------------------------------------------------- slack 3.271 Slack (MET) : 3.271ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][77]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.618ns (logic 0.286ns (6.193%) route 4.332ns (93.807%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.338ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.379ns = ( 10.696 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.981ns (routing 0.664ns, distribution 1.317ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.592 5.664 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 5.811 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/O net (fo=76, routed) 1.740 7.551 rx_data_ngccm[15] SLICE_X113Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][77]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.981 10.696 g_gbt_bank[1].gbtbank_n_54 SLICE_X113Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][77]/C clock pessimism 0.216 10.912 clock uncertainty -0.035 10.877 SLICE_X113Y426 FDCE (Setup_AFF2_SLICEM_C_CE) -0.055 10.822 SFP_GEN[15].rx_data_ngccm_reg[15][77] ------------------------------------------------------------------- required time 10.822 arrival time -7.551 ------------------------------------------------------------------- slack 3.271 Slack (MET) : 3.271ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][41]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.589ns (logic 0.286ns (6.232%) route 4.303ns (93.768%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.368ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.349ns = ( 10.666 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.951ns (routing 0.664ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.592 5.664 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 5.811 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/O net (fo=76, routed) 1.711 7.522 rx_data_ngccm[15] SLICE_X109Y425 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][41]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.951 10.666 g_gbt_bank[1].gbtbank_n_54 SLICE_X109Y425 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][41]/C clock pessimism 0.216 10.882 clock uncertainty -0.035 10.847 SLICE_X109Y425 FDCE (Setup_AFF_SLICEM_C_CE) -0.054 10.793 SFP_GEN[15].rx_data_ngccm_reg[15][41] ------------------------------------------------------------------- required time 10.793 arrival time -7.522 ------------------------------------------------------------------- slack 3.271 Slack (MET) : 3.275ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][75]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.615ns (logic 0.286ns (6.197%) route 4.329ns (93.803%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.338ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.379ns = ( 10.696 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.981ns (routing 0.664ns, distribution 1.317ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.592 5.664 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 5.811 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/O net (fo=76, routed) 1.737 7.548 rx_data_ngccm[15] SLICE_X113Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][75]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.981 10.696 g_gbt_bank[1].gbtbank_n_54 SLICE_X113Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][75]/C clock pessimism 0.216 10.912 clock uncertainty -0.035 10.877 SLICE_X113Y426 FDCE (Setup_AFF_SLICEM_C_CE) -0.054 10.823 SFP_GEN[15].rx_data_ngccm_reg[15][75] ------------------------------------------------------------------- required time 10.823 arrival time -7.548 ------------------------------------------------------------------- slack 3.275 Slack (MET) : 3.275ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][64]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.611ns (logic 0.286ns (6.203%) route 4.325ns (93.797%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.342ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.375ns = ( 10.692 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.977ns (routing 0.664ns, distribution 1.313ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.592 5.664 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 5.811 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/O net (fo=76, routed) 1.733 7.544 rx_data_ngccm[15] SLICE_X114Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][64]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.977 10.692 g_gbt_bank[1].gbtbank_n_54 SLICE_X114Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][64]/C clock pessimism 0.216 10.908 clock uncertainty -0.035 10.873 SLICE_X114Y426 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 10.819 SFP_GEN[15].rx_data_ngccm_reg[15][64] ------------------------------------------------------------------- required time 10.819 arrival time -7.544 ------------------------------------------------------------------- slack 3.275 Slack (MET) : 3.275ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][68]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 4.611ns (logic 0.286ns (6.203%) route 4.325ns (93.797%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.342ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.375ns = ( 10.692 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.977ns (routing 0.664ns, distribution 1.313ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.592 5.664 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 5.811 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[15].rx_data_ngccm[15][83]_i_1/O net (fo=76, routed) 1.733 7.544 rx_data_ngccm[15] SLICE_X114Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][68]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.977 10.692 g_gbt_bank[1].gbtbank_n_54 SLICE_X114Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][68]/C clock pessimism 0.216 10.908 clock uncertainty -0.035 10.873 SLICE_X114Y426 FDCE (Setup_BFF_SLICEL_C_CE) -0.054 10.819 SFP_GEN[15].rx_data_ngccm_reg[15][68] ------------------------------------------------------------------- required time 10.819 arrival time -7.544 ------------------------------------------------------------------- slack 3.275 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.179ns (logic 0.093ns (51.955%) route 0.086ns (48.045%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.192ns Source Clock Delay (SCD): 0.970ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.852ns (routing 0.317ns, distribution 0.535ns) Clock Net Delay (Destination): 1.027ns (routing 0.360ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.970 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X114Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y425 FDCE (Prop_GFF2_SLICEL_C_Q) 0.048 1.018 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.074 1.092 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_7_in SLICE_X115Y425 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.045 1.137 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__14/O net (fo=1, routed) 0.012 1.149 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[4] SLICE_X115Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.027 1.192 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X115Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.134 1.058 SLICE_X115Y425 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.114 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.114 arrival time 1.149 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.094ns (51.366%) route 0.089ns (48.634%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.192ns Source Clock Delay (SCD): 0.970ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.852ns (routing 0.317ns, distribution 0.535ns) Clock Net Delay (Destination): 1.027ns (routing 0.360ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.970 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X114Y425 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y425 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.019 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.073 1.092 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_7_in SLICE_X115Y425 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.137 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__14/O net (fo=1, routed) 0.016 1.153 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] SLICE_X115Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.027 1.192 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X115Y425 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.134 1.058 SLICE_X115Y425 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.114 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.114 arrival time 1.153 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][66]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.048ns (26.229%) route 0.135ns (73.770%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.190ns Source Clock Delay (SCD): 0.971ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.853ns (routing 0.317ns, distribution 0.536ns) Clock Net Delay (Destination): 1.025ns (routing 0.360ns, distribution 0.665ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.971 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X115Y426 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y426 FDRE (Prop_CFF2_SLICEM_C_Q) 0.048 1.019 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.135 1.154 rx_data[15][66] SLICE_X114Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][66]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.190 g_gbt_bank[1].gbtbank_n_54 SLICE_X114Y426 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][66]/C clock pessimism -0.134 1.056 SLICE_X114Y426 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.112 SFP_GEN[15].rx_data_ngccm_reg[15][66] ------------------------------------------------------------------- required time -1.112 arrival time 1.154 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.095ns (49.223%) route 0.098ns (50.777%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.187ns Source Clock Delay (SCD): 0.959ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.841ns (routing 0.317ns, distribution 0.524ns) Clock Net Delay (Destination): 1.022ns (routing 0.360ns, distribution 0.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.841 0.959 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X109Y424 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y424 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.008 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.082 1.090 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in SLICE_X110Y424 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.046 1.136 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__14/O net (fo=1, routed) 0.016 1.152 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X110Y424 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.187 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X110Y424 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.134 1.053 SLICE_X110Y424 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.109 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.109 arrival time 1.152 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[29]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[29]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.049ns (27.528%) route 0.129ns (72.472%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.949ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.831ns (routing 0.317ns, distribution 0.514ns) Clock Net Delay (Destination): 0.997ns (routing 0.360ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.831 0.949 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[29]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y429 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 0.998 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[29]/Q net (fo=1, routed) 0.129 1.127 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[29] SLICE_X105Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[29]/C clock pessimism -0.134 1.028 SLICE_X105Y429 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.084 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[29] ------------------------------------------------------------------- required time -1.084 arrival time 1.127 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.167ns Source Clock Delay (SCD): 0.949ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.831ns (routing 0.317ns, distribution 0.514ns) Clock Net Delay (Destination): 1.002ns (routing 0.360ns, distribution 0.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.831 0.949 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X104Y424 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X104Y424 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.998 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.034 1.032 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in SLICE_X104Y424 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.077 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__14/O net (fo=1, routed) 0.016 1.093 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] SLICE_X104Y424 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.167 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X104Y424 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.174 0.993 SLICE_X104Y424 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.049 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.049 arrival time 1.093 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.191ns Source Clock Delay (SCD): 0.970ns Clock Pessimism Removal (CPR): 0.177ns Clock Net Delay (Source): 0.852ns (routing 0.317ns, distribution 0.535ns) Clock Net Delay (Destination): 1.026ns (routing 0.360ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.970 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X114Y424 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y424 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.019 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.034 1.053 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in SLICE_X114Y424 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.098 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__14/O net (fo=1, routed) 0.016 1.114 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] SLICE_X114Y424 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.191 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X114Y424 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.177 1.014 SLICE_X114Y424 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.070 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.070 arrival time 1.114 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[30]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[30]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.048ns (26.374%) route 0.134ns (73.626%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.163ns Source Clock Delay (SCD): 0.946ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.828ns (routing 0.317ns, distribution 0.511ns) Clock Net Delay (Destination): 0.998ns (routing 0.360ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.946 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y428 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[30]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y428 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 0.994 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[30]/Q net (fo=1, routed) 0.134 1.128 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[30] SLICE_X105Y428 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.163 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y428 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[30]/C clock pessimism -0.134 1.029 SLICE_X105Y428 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.084 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[30] ------------------------------------------------------------------- required time -1.084 arrival time 1.128 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][52]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.049ns (31.410%) route 0.107ns (68.590%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.191ns Source Clock Delay (SCD): 0.972ns Clock Pessimism Removal (CPR): 0.165ns Clock Net Delay (Source): 0.854ns (routing 0.317ns, distribution 0.537ns) Clock Net Delay (Destination): 1.026ns (routing 0.360ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.854 0.972 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X114Y424 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y424 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.021 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.107 1.128 rx_data[15][52] SLICE_X114Y425 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][52]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.191 g_gbt_bank[1].gbtbank_n_54 SLICE_X114Y425 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][52]/C clock pessimism -0.165 1.026 SLICE_X114Y425 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.082 SFP_GEN[15].rx_data_ngccm_reg[15][52] ------------------------------------------------------------------- required time -1.082 arrival time 1.128 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[15].rx_data_ngccm_reg[15][76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_17 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.049ns (31.410%) route 0.107ns (68.590%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.188ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.165ns Clock Net Delay (Source): 0.851ns (routing 0.317ns, distribution 0.534ns) Clock Net Delay (Destination): 1.023ns (routing 0.360ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.851 0.969 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X111Y424 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y424 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.018 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.107 1.125 rx_data[15][76] SLICE_X111Y423 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.188 g_gbt_bank[1].gbtbank_n_54 SLICE_X111Y423 FDCE r SFP_GEN[15].rx_data_ngccm_reg[15][76]/C clock pessimism -0.165 1.023 SLICE_X111Y423 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.079 SFP_GEN[15].rx_data_ngccm_reg[15][76] ------------------------------------------------------------------- required time -1.079 arrival time 1.125 ------------------------------------------------------------------- slack 0.046 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_17 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y173 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][3]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][4]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X80Y422 g_clock_rate_din[15].ngccm_status_cnt_reg[15][5]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X102Y421 g_clock_rate_din[15].rx_frameclk_div2_reg[15]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X103Y424 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X103Y424 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X105Y421 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X105Y421 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X105Y422 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.045 0.485 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.021 0.498 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.021 0.861 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.045 1.283 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_18 To Clock: gtwiz_userclk_rx_srcclk_out[0]_18 Setup : 0 Failing Endpoints, Worst Slack 2.699ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.033ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.699ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[101]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 5.684ns (logic 1.086ns (19.106%) route 4.598ns (80.894%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.628ns = ( 10.945 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.725ns, distribution 1.621ns) Clock Net Delay (Destination): 2.230ns (routing 0.657ns, distribution 1.573ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.907 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 4.598 8.505 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[1] SLICE_X90Y511 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[101]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.230 10.945 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y511 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[101]/C clock pessimism 0.227 11.172 clock uncertainty -0.035 11.137 SLICE_X90Y511 FDCE (Setup_DFF2_SLICEM_C_D) 0.067 11.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[101] ------------------------------------------------------------------- required time 11.204 arrival time -8.505 ------------------------------------------------------------------- slack 2.699 Slack (MET) : 2.772ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[61]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 5.607ns (logic 1.086ns (19.369%) route 4.521ns (80.631%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.628ns = ( 10.945 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.725ns, distribution 1.621ns) Clock Net Delay (Destination): 2.230ns (routing 0.657ns, distribution 1.573ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.907 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 4.521 8.428 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[1] SLICE_X90Y511 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[61]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.230 10.945 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y511 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[61]/C clock pessimism 0.227 11.172 clock uncertainty -0.035 11.137 SLICE_X90Y511 FDCE (Setup_DFF_SLICEM_C_D) 0.063 11.200 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[61] ------------------------------------------------------------------- required time 11.200 arrival time -8.428 ------------------------------------------------------------------- slack 2.772 Slack (MET) : 2.927ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[21]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 5.477ns (logic 1.330ns (24.283%) route 4.147ns (75.717%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.653ns = ( 10.970 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.725ns, distribution 1.621ns) Clock Net Delay (Destination): 2.255ns (routing 0.657ns, distribution 1.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.907 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 4.112 8.019 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[1] SLICE_X90Y507 LUT5 (Prop_D6LUT_SLICEM_I3_O) 0.244 8.263 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[21]_i_1__21/O net (fo=1, routed) 0.035 8.298 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg00[21] SLICE_X90Y507 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[21]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.255 10.970 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y507 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[21]/C clock pessimism 0.227 11.197 clock uncertainty -0.035 11.162 SLICE_X90Y507 FDCE (Setup_DFF_SLICEM_C_D) 0.063 11.225 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[21] ------------------------------------------------------------------- required time 11.225 arrival time -8.298 ------------------------------------------------------------------- slack 2.927 Slack (MET) : 3.062ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 5.189ns (logic 1.587ns (30.584%) route 3.602ns (69.416%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.023ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.617ns = ( 10.934 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.725ns, distribution 1.621ns) Clock Net Delay (Destination): 2.219ns (routing 0.657ns, distribution 1.562ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.907 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.756 6.663 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X95Y492 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 6.834 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/O net (fo=5, routed) 0.104 6.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y492 LUT4 (Prop_B5LUT_SLICEM_I2_O) 0.184 7.122 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15/O net (fo=1, routed) 0.242 7.364 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15_n_0 SLICE_X95Y494 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.510 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15/O net (fo=2, routed) 0.500 8.010 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15_n_0 SLICE_X95Y494 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.219 10.934 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X95Y494 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.227 11.161 clock uncertainty -0.035 11.126 SLICE_X95Y494 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 11.072 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.072 arrival time -8.010 ------------------------------------------------------------------- slack 3.062 Slack (MET) : 3.062ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 5.189ns (logic 1.587ns (30.584%) route 3.602ns (69.416%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.023ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.617ns = ( 10.934 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.725ns, distribution 1.621ns) Clock Net Delay (Destination): 2.219ns (routing 0.657ns, distribution 1.562ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.907 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.756 6.663 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X95Y492 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.171 6.834 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/O net (fo=5, routed) 0.104 6.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y492 LUT4 (Prop_B5LUT_SLICEM_I2_O) 0.184 7.122 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15/O net (fo=1, routed) 0.242 7.364 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15_n_0 SLICE_X95Y494 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.510 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15/O net (fo=2, routed) 0.500 8.010 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15_n_0 SLICE_X95Y494 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.219 10.934 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X95Y494 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.227 11.161 clock uncertainty -0.035 11.126 SLICE_X95Y494 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 11.072 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.072 arrival time -8.010 ------------------------------------------------------------------- slack 3.062 Slack (MET) : 3.194ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 5.199ns (logic 1.086ns (20.889%) route 4.113ns (79.111%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.642ns = ( 10.959 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.725ns, distribution 1.621ns) Clock Net Delay (Destination): 2.244ns (routing 0.657ns, distribution 1.587ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.907 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 4.113 8.020 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[1] SLICE_X91Y505 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.244 10.959 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X91Y505 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]/C clock pessimism 0.227 11.186 clock uncertainty -0.035 11.151 SLICE_X91Y505 FDCE (Setup_HFF_SLICEL_C_D) 0.063 11.214 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81] ------------------------------------------------------------------- required time 11.214 arrival time -8.020 ------------------------------------------------------------------- slack 3.194 Slack (MET) : 3.206ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[60]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 5.172ns (logic 1.104ns (21.346%) route 4.068ns (78.654%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.627ns = ( 10.944 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.725ns, distribution 1.621ns) Clock Net Delay (Destination): 2.229ns (routing 0.657ns, distribution 1.572ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.925 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 4.068 7.993 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[0] SLICE_X90Y512 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[60]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.229 10.944 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y512 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[60]/C clock pessimism 0.227 11.171 clock uncertainty -0.035 11.136 SLICE_X90Y512 FDCE (Setup_HFF_SLICEM_C_D) 0.063 11.199 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[60] ------------------------------------------------------------------- required time 11.199 arrival time -7.993 ------------------------------------------------------------------- slack 3.206 Slack (MET) : 3.371ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 5.014ns (logic 1.090ns (21.739%) route 3.924ns (78.261%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.633ns = ( 10.950 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.725ns, distribution 1.621ns) Clock Net Delay (Destination): 2.235ns (routing 0.657ns, distribution 1.578ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[8]) 1.090 3.911 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[8] net (fo=6, routed) 3.924 7.835 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[10] SLICE_X92Y504 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.235 10.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y504 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/C clock pessimism 0.227 11.177 clock uncertainty -0.035 11.142 SLICE_X92Y504 FDCE (Setup_GFF_SLICEM_C_D) 0.064 11.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90] ------------------------------------------------------------------- required time 11.206 arrival time -7.835 ------------------------------------------------------------------- slack 3.371 Slack (MET) : 3.414ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[100]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 4.964ns (logic 1.104ns (22.240%) route 3.860ns (77.760%)) Logic Levels: 0 Clock Path Skew: 0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.943 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.725ns, distribution 1.621ns) Clock Net Delay (Destination): 2.228ns (routing 0.657ns, distribution 1.571ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.925 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.860 7.785 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[0] SLICE_X90Y511 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[100]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.228 10.943 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y511 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[100]/C clock pessimism 0.227 11.170 clock uncertainty -0.035 11.135 SLICE_X90Y511 FDCE (Setup_HFF2_SLICEM_C_D) 0.064 11.199 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[100] ------------------------------------------------------------------- required time 11.199 arrival time -7.785 ------------------------------------------------------------------- slack 3.414 Slack (MET) : 3.424ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 4.956ns (logic 1.086ns (21.913%) route 3.870ns (78.087%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.629ns = ( 10.946 - 8.317 ) Source Clock Delay (SCD): 2.821ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.346ns (routing 0.725ns, distribution 1.621ns) Clock Net Delay (Destination): 2.231ns (routing 0.657ns, distribution 1.574ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.346 2.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.907 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.870 7.777 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[1] SLICE_X93Y505 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.946 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X93Y505 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]/C clock pessimism 0.227 11.173 clock uncertainty -0.035 11.138 SLICE_X93Y505 FDCE (Setup_DFF_SLICEL_C_D) 0.063 11.201 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41] ------------------------------------------------------------------- required time 11.201 arrival time -7.777 ------------------------------------------------------------------- slack 3.424 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.151ns (logic 0.064ns (42.384%) route 0.087ns (57.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.958ns (routing 0.315ns, distribution 0.643ns) Clock Net Delay (Destination): 1.151ns (routing 0.355ns, distribution 0.796ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.958 1.076 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X87Y507 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y507 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.125 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.075 1.200 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/feedbackRegister[1] SLICE_X87Y506 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.215 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[20]_i_2__15/O net (fo=1, routed) 0.012 1.227 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[1] SLICE_X87Y506 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.151 1.316 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X87Y506 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.178 1.138 SLICE_X87Y506 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.194 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.194 arrival time 1.227 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.101ns (67.333%) route 0.049ns (32.667%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.310ns Source Clock Delay (SCD): 1.078ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 0.960ns (routing 0.315ns, distribution 0.645ns) Clock Net Delay (Destination): 1.145ns (routing 0.355ns, distribution 0.790ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.078 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X85Y509 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y509 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.033 1.160 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_21_in SLICE_X85Y508 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.052 1.212 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__15/O net (fo=1, routed) 0.016 1.228 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] SLICE_X85Y508 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.145 1.310 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X85Y508 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.179 1.131 SLICE_X85Y508 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.187 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.187 arrival time 1.228 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.101ns (65.161%) route 0.054ns (34.839%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.321ns Source Clock Delay (SCD): 1.086ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 0.968ns (routing 0.315ns, distribution 0.653ns) Clock Net Delay (Destination): 1.156ns (routing 0.355ns, distribution 0.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.968 1.086 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X86Y508 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y508 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.135 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.038 1.173 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in SLICE_X86Y507 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.052 1.225 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__15/O net (fo=1, routed) 0.016 1.241 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] SLICE_X86Y507 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.321 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X86Y507 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.179 1.142 SLICE_X86Y507 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.198 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.198 arrival time 1.241 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[16].rx_data_ngccm_reg[16][33]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[32]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.096ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 0.978ns (routing 0.315ns, distribution 0.663ns) Clock Net Delay (Destination): 1.162ns (routing 0.355ns, distribution 0.807ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.096 g_gbt_bank[1].gbtbank_n_64 SLICE_X86Y503 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][33]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y503 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.145 r SFP_GEN[16].rx_data_ngccm_reg[16][33]/Q net (fo=1, routed) 0.034 1.179 SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[83]_0[25] SLICE_X86Y503 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.224 r SFP_GEN[16].ngCCM_gbt/RX_Word_rx40[32]_i_1/O net (fo=1, routed) 0.016 1.240 SFP_GEN[16].ngCCM_gbt/RX_Word_rx40[32]_i_1_n_0 SLICE_X86Y503 FDCE r SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[32]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.327 SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X86Y503 FDCE r SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.187 1.140 SLICE_X86Y503 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.196 SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.196 arrival time 1.240 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.063ns (43.448%) route 0.082ns (56.552%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.284ns Source Clock Delay (SCD): 1.065ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.947ns (routing 0.315ns, distribution 0.632ns) Clock Net Delay (Destination): 1.119ns (routing 0.355ns, distribution 0.764ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.947 1.065 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y493 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y493 FDCE (Prop_FFF2_SLICEL_C_Q) 0.048 1.113 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]/Q net (fo=5, routed) 0.070 1.183 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg_n_0_[2] SLICE_X94Y492 LUT3 (Prop_F6LUT_SLICEL_I0_O) 0.015 1.198 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__15/O net (fo=1, routed) 0.012 1.210 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__15_n_0 SLICE_X94Y492 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.119 1.284 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y492 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C clock pessimism -0.176 1.108 SLICE_X94Y492 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.164 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/RX_BITSLIPCMD_o_reg ------------------------------------------------------------------- required time -1.164 arrival time 1.210 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.112ns (71.795%) route 0.044ns (28.205%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.310ns Source Clock Delay (SCD): 1.078ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 0.960ns (routing 0.315ns, distribution 0.645ns) Clock Net Delay (Destination): 1.145ns (routing 0.355ns, distribution 0.790ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.078 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X85Y509 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y509 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.127 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.033 1.160 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_21_in SLICE_X85Y508 LUT3 (Prop_C5LUT_SLICEM_I2_O) 0.063 1.223 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__15/O net (fo=1, routed) 0.011 1.234 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[9] SLICE_X85Y508 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.145 1.310 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X85Y508 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C clock pessimism -0.179 1.131 SLICE_X85Y508 FDRE (Hold_CFF2_SLICEM_C_D) 0.056 1.187 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9] ------------------------------------------------------------------- required time -1.187 arrival time 1.234 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].rx_data_ngccm_reg[16][53]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.049ns (34.266%) route 0.094ns (65.734%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.278ns Source Clock Delay (SCD): 1.061ns Clock Pessimism Removal (CPR): 0.177ns Clock Net Delay (Source): 0.943ns (routing 0.315ns, distribution 0.628ns) Clock Net Delay (Destination): 1.113ns (routing 0.355ns, distribution 0.758ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.943 1.061 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X94Y501 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y501 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.110 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/Q net (fo=1, routed) 0.094 1.204 rx_data[16][53] SLICE_X94Y500 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][53]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.113 1.278 g_gbt_bank[1].gbtbank_n_64 SLICE_X94Y500 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][53]/C clock pessimism -0.177 1.101 SLICE_X94Y500 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.156 SFP_GEN[16].rx_data_ngccm_reg[16][53] ------------------------------------------------------------------- required time -1.156 arrival time 1.204 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.079ns (47.305%) route 0.088ns (52.695%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.958ns (routing 0.315ns, distribution 0.643ns) Clock Net Delay (Destination): 1.151ns (routing 0.355ns, distribution 0.796ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.958 1.076 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X87Y507 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y507 FDCE (Prop_EFF2_SLICEM_C_Q) 0.048 1.124 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.072 1.196 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X87Y506 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.031 1.227 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__15/O net (fo=1, routed) 0.016 1.243 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] SLICE_X87Y506 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.151 1.316 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X87Y506 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.178 1.138 SLICE_X87Y506 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.194 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.194 arrival time 1.243 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.165ns (logic 0.080ns (48.485%) route 0.085ns (51.515%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.958ns (routing 0.315ns, distribution 0.643ns) Clock Net Delay (Destination): 1.149ns (routing 0.355ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.958 1.076 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X87Y507 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y507 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.124 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.069 1.193 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_3_in SLICE_X87Y506 LUT3 (Prop_H6LUT_SLICEM_I2_O) 0.032 1.225 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__15/O net (fo=1, routed) 0.016 1.241 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[0] SLICE_X87Y506 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.149 1.314 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X87Y506 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.178 1.136 SLICE_X87Y506 FDRE (Hold_HFF_SLICEM_C_D) 0.056 1.192 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.192 arrival time 1.241 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: SFP_GEN[16].rx_data_ngccm_reg[16][1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[0]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_18 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.095ns (64.626%) route 0.052ns (35.374%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.321ns Source Clock Delay (SCD): 1.094ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.976ns (routing 0.315ns, distribution 0.661ns) Clock Net Delay (Destination): 1.156ns (routing 0.355ns, distribution 0.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.976 1.094 g_gbt_bank[1].gbtbank_n_64 SLICE_X87Y503 FDCE r SFP_GEN[16].rx_data_ngccm_reg[16][1]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y503 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.143 r SFP_GEN[16].rx_data_ngccm_reg[16][1]/Q net (fo=1, routed) 0.036 1.179 SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[83]_0[1] SLICE_X87Y503 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.046 1.225 r SFP_GEN[16].ngCCM_gbt/RX_Word_rx40[0]_i_1/O net (fo=1, routed) 0.016 1.241 SFP_GEN[16].ngCCM_gbt/RX_Word_rx40[0]_i_1_n_0 SLICE_X87Y503 FDCE r SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.321 SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X87Y503 FDCE r SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.186 1.135 SLICE_X87Y503 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.191 SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.191 arrival time 1.241 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_18 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y196 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X74Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X74Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X74Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X74Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X74Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X74Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y481 g_clock_rate_din[16].ngccm_status_cnt_reg[16][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X74Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X74Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X74Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X74Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X74Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X74Y480 g_clock_rate_din[16].ngccm_status_cnt_reg[16][5]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X94Y485 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X94Y485 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X88Y509 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X88Y506 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X88Y506 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X88Y506 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_19 To Clock: gtwiz_userclk_rx_srcclk_out[0]_19 Setup : 0 Failing Endpoints, Worst Slack 2.878ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.042ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.878ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 5.451ns (logic 1.552ns (28.472%) route 3.899ns (71.528%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.102ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 2.796ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.723ns, distribution 1.598ns) Clock Net Delay (Destination): 2.272ns (routing 0.655ns, distribution 1.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.796 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.981 6.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X84Y504 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 7.161 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.312 7.473 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y505 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.168 7.641 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/O net (fo=3, routed) 0.606 8.247 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X85Y505 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.272 10.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X85Y505 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.228 11.215 clock uncertainty -0.035 11.180 SLICE_X85Y505 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.125 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.125 arrival time -8.247 ------------------------------------------------------------------- slack 2.878 Slack (MET) : 2.882ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 5.448ns (logic 1.552ns (28.488%) route 3.896ns (71.512%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.102ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 2.796ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.723ns, distribution 1.598ns) Clock Net Delay (Destination): 2.272ns (routing 0.655ns, distribution 1.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.796 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.981 6.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X84Y504 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 7.161 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.312 7.473 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y505 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.168 7.641 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/O net (fo=3, routed) 0.603 8.244 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X85Y505 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.272 10.987 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X85Y505 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.228 11.215 clock uncertainty -0.035 11.180 SLICE_X85Y505 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.126 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.126 arrival time -8.244 ------------------------------------------------------------------- slack 2.882 Slack (MET) : 3.025ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 5.320ns (logic 1.628ns (30.601%) route 3.692ns (69.398%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.686ns = ( 11.003 - 8.317 ) Source Clock Delay (SCD): 2.796ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.723ns, distribution 1.598ns) Clock Net Delay (Destination): 2.288ns (routing 0.655ns, distribution 1.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.796 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.981 6.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X84Y504 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 7.161 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.301 7.462 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y504 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.092 7.554 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16/O net (fo=1, routed) 0.082 7.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16_n_0 SLICE_X85Y504 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.152 7.788 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16/O net (fo=2, routed) 0.328 8.116 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16_n_0 SLICE_X86Y504 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.288 11.003 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X86Y504 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.228 11.231 clock uncertainty -0.035 11.196 SLICE_X86Y504 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.141 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.141 arrival time -8.116 ------------------------------------------------------------------- slack 3.025 Slack (MET) : 3.025ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 5.320ns (logic 1.628ns (30.601%) route 3.692ns (69.398%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.118ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.686ns = ( 11.003 - 8.317 ) Source Clock Delay (SCD): 2.796ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.723ns, distribution 1.598ns) Clock Net Delay (Destination): 2.288ns (routing 0.655ns, distribution 1.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.796 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.981 6.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X84Y504 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 7.161 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.301 7.462 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y504 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.092 7.554 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16/O net (fo=1, routed) 0.082 7.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16_n_0 SLICE_X85Y504 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.152 7.788 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16/O net (fo=2, routed) 0.328 8.116 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16_n_0 SLICE_X86Y504 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.288 11.003 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X86Y504 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.228 11.231 clock uncertainty -0.035 11.196 SLICE_X86Y504 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 11.141 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.141 arrival time -8.116 ------------------------------------------------------------------- slack 3.025 Slack (MET) : 3.064ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 5.283ns (logic 1.557ns (29.472%) route 3.726ns (70.528%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.687ns = ( 11.004 - 8.317 ) Source Clock Delay (SCD): 2.796ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.723ns, distribution 1.598ns) Clock Net Delay (Destination): 2.289ns (routing 0.655ns, distribution 1.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.796 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.981 6.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X84Y504 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 7.161 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.317 7.478 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y505 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.651 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/O net (fo=5, routed) 0.428 8.079 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X85Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.289 11.004 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X85Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.228 11.232 clock uncertainty -0.035 11.197 SLICE_X85Y504 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.143 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.143 arrival time -8.079 ------------------------------------------------------------------- slack 3.064 Slack (MET) : 3.064ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 5.283ns (logic 1.557ns (29.472%) route 3.726ns (70.528%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.120ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.688ns = ( 11.005 - 8.317 ) Source Clock Delay (SCD): 2.796ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.723ns, distribution 1.598ns) Clock Net Delay (Destination): 2.290ns (routing 0.655ns, distribution 1.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.796 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.981 6.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X84Y504 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 7.161 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.317 7.478 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y505 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.651 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/O net (fo=5, routed) 0.428 8.079 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X86Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.290 11.005 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X86Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.228 11.233 clock uncertainty -0.035 11.198 SLICE_X86Y504 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.143 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.143 arrival time -8.079 ------------------------------------------------------------------- slack 3.064 Slack (MET) : 3.064ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 5.283ns (logic 1.557ns (29.472%) route 3.726ns (70.528%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.120ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.688ns = ( 11.005 - 8.317 ) Source Clock Delay (SCD): 2.796ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.723ns, distribution 1.598ns) Clock Net Delay (Destination): 2.290ns (routing 0.655ns, distribution 1.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.796 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.981 6.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X84Y504 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 7.161 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.317 7.478 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y505 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.651 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/O net (fo=5, routed) 0.428 8.079 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X86Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.290 11.005 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X86Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.228 11.233 clock uncertainty -0.035 11.198 SLICE_X86Y504 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.143 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.143 arrival time -8.079 ------------------------------------------------------------------- slack 3.064 Slack (MET) : 3.069ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 5.279ns (logic 1.557ns (29.494%) route 3.722ns (70.506%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.120ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.688ns = ( 11.005 - 8.317 ) Source Clock Delay (SCD): 2.796ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.723ns, distribution 1.598ns) Clock Net Delay (Destination): 2.290ns (routing 0.655ns, distribution 1.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.796 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.981 6.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X84Y504 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 7.161 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.317 7.478 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y505 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.651 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/O net (fo=5, routed) 0.424 8.075 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X86Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.290 11.005 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X86Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.228 11.233 clock uncertainty -0.035 11.198 SLICE_X86Y504 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 11.144 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.144 arrival time -8.075 ------------------------------------------------------------------- slack 3.069 Slack (MET) : 3.069ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 5.279ns (logic 1.557ns (29.494%) route 3.722ns (70.506%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.120ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.688ns = ( 11.005 - 8.317 ) Source Clock Delay (SCD): 2.796ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.723ns, distribution 1.598ns) Clock Net Delay (Destination): 2.290ns (routing 0.655ns, distribution 1.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.796 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.981 6.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X84Y504 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 7.161 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.317 7.478 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y505 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 7.651 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__17/O net (fo=5, routed) 0.424 8.075 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 SLICE_X86Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.290 11.005 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X86Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.228 11.233 clock uncertainty -0.035 11.198 SLICE_X86Y504 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.144 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.144 arrival time -8.075 ------------------------------------------------------------------- slack 3.069 Slack (MET) : 3.090ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 5.256ns (logic 1.552ns (29.528%) route 3.704ns (70.472%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.687ns = ( 11.004 - 8.317 ) Source Clock Delay (SCD): 2.796ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.723ns, distribution 1.598ns) Clock Net Delay (Destination): 2.289ns (routing 0.655ns, distribution 1.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.796 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.957 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.981 6.938 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X84Y504 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 7.161 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/O net (fo=5, routed) 0.312 7.473 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X85Y505 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.168 7.641 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/O net (fo=3, routed) 0.411 8.052 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X85Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.289 11.004 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X85Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.228 11.232 clock uncertainty -0.035 11.197 SLICE_X85Y504 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.142 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.142 arrival time -8.052 ------------------------------------------------------------------- slack 3.090 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.368ns Source Clock Delay (SCD): 1.131ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.013ns (routing 0.315ns, distribution 0.698ns) Clock Net Delay (Destination): 1.203ns (routing 0.355ns, distribution 0.848ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.013 1.131 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X79Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y497 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.180 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.035 1.215 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_35_in SLICE_X79Y496 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.054 1.269 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__16/O net (fo=1, routed) 0.016 1.285 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] SLICE_X79Y496 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.203 1.368 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X79Y496 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.181 1.187 SLICE_X79Y496 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.243 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.243 arrival time 1.285 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].rx_data_ngccm_reg[17][5]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.341ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 0.997ns (routing 0.315ns, distribution 0.682ns) Clock Net Delay (Destination): 1.176ns (routing 0.355ns, distribution 0.821ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X81Y497 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y497 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.164 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.095 1.259 rx_data[17][5] SLICE_X81Y495 FDCE r SFP_GEN[17].rx_data_ngccm_reg[17][5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.176 1.341 g_gbt_bank[1].gbtbank_n_74 SLICE_X81Y495 FDCE r SFP_GEN[17].rx_data_ngccm_reg[17][5]/C clock pessimism -0.181 1.160 SLICE_X81Y495 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.216 SFP_GEN[17].rx_data_ngccm_reg[17][5] ------------------------------------------------------------------- required time -1.216 arrival time 1.259 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[32]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[32]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.165ns (logic 0.049ns (29.697%) route 0.116ns (70.303%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.119ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.001ns (routing 0.315ns, distribution 0.686ns) Clock Net Delay (Destination): 1.171ns (routing 0.355ns, distribution 0.816ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.119 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X84Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[32]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y497 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.168 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[32]/Q net (fo=1, routed) 0.116 1.284 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[32] SLICE_X86Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.336 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X86Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[32]/C clock pessimism -0.151 1.185 SLICE_X86Y497 FDCE (Hold_EFF_SLICEL_C_D) 0.056 1.241 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[32] ------------------------------------------------------------------- required time -1.241 arrival time 1.284 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].rx_data_ngccm_reg[17][63]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.049ns (26.630%) route 0.135ns (73.370%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.340ns Source Clock Delay (SCD): 1.105ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 0.987ns (routing 0.315ns, distribution 0.672ns) Clock Net Delay (Destination): 1.175ns (routing 0.355ns, distribution 0.820ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.987 1.105 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X89Y487 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y487 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.154 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/Q net (fo=1, routed) 0.135 1.289 rx_data[17][63] SLICE_X88Y489 FDCE r SFP_GEN[17].rx_data_ngccm_reg[17][63]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.175 1.340 g_gbt_bank[1].gbtbank_n_74 SLICE_X88Y489 FDCE r SFP_GEN[17].rx_data_ngccm_reg[17][63]/C clock pessimism -0.152 1.188 SLICE_X88Y489 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.244 SFP_GEN[17].rx_data_ngccm_reg[17][63] ------------------------------------------------------------------- required time -1.244 arrival time 1.289 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.192ns Clock Net Delay (Source): 1.015ns (routing 0.315ns, distribution 0.700ns) Clock Net Delay (Destination): 1.202ns (routing 0.355ns, distribution 0.847ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X80Y496 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y496 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.182 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.034 1.216 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in SLICE_X80Y496 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.261 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__16/O net (fo=1, routed) 0.016 1.277 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[16] SLICE_X80Y496 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.202 1.367 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X80Y496 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.192 1.175 SLICE_X80Y496 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.231 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.231 arrival time 1.277 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: SFP_GEN[17].rx_data_ngccm_reg[17][61]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.080ns (46.784%) route 0.091ns (53.216%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.325ns Source Clock Delay (SCD): 1.105ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 0.987ns (routing 0.315ns, distribution 0.672ns) Clock Net Delay (Destination): 1.160ns (routing 0.355ns, distribution 0.805ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.987 1.105 g_gbt_bank[1].gbtbank_n_74 SLICE_X89Y488 FDCE r SFP_GEN[17].rx_data_ngccm_reg[17][61]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y488 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.154 r SFP_GEN[17].rx_data_ngccm_reg[17][61]/Q net (fo=1, routed) 0.075 1.229 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[83]_0[53] SLICE_X87Y488 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.031 1.260 r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40[60]_i_1/O net (fo=1, routed) 0.016 1.276 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40[60]_i_1_n_0 SLICE_X87Y488 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.160 1.325 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X87Y488 FDCE r SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]/C clock pessimism -0.152 1.173 SLICE_X87Y488 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.229 SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60] ------------------------------------------------------------------- required time -1.229 arrival time 1.276 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.113ns (70.625%) route 0.047ns (29.375%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.368ns Source Clock Delay (SCD): 1.131ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.013ns (routing 0.315ns, distribution 0.698ns) Clock Net Delay (Destination): 1.203ns (routing 0.355ns, distribution 0.848ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.013 1.131 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X79Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y497 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.180 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.035 1.215 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_35_in SLICE_X79Y496 LUT3 (Prop_D5LUT_SLICEM_I0_O) 0.064 1.279 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__16/O net (fo=1, routed) 0.012 1.291 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[18] SLICE_X79Y496 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.203 1.368 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X79Y496 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.181 1.187 SLICE_X79Y496 FDRE (Hold_DFF2_SLICEM_C_D) 0.056 1.243 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -1.243 arrival time 1.291 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.093ns (62.838%) route 0.055ns (37.162%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.351ns Source Clock Delay (SCD): 1.119ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.001ns (routing 0.315ns, distribution 0.686ns) Clock Net Delay (Destination): 1.186ns (routing 0.355ns, distribution 0.831ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.119 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X84Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y497 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/Q net (fo=5, routed) 0.039 1.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut SLICE_X84Y497 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.251 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter[1]_i_1__21/O net (fo=1, routed) 0.016 1.267 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/cnter[1] SLICE_X84Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.186 1.351 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X84Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C clock pessimism -0.190 1.161 SLICE_X84Y497 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.217 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] ------------------------------------------------------------------- required time -1.217 arrival time 1.267 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.093ns (62.838%) route 0.055ns (37.162%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.351ns Source Clock Delay (SCD): 1.119ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.001ns (routing 0.315ns, distribution 0.686ns) Clock Net Delay (Destination): 1.186ns (routing 0.355ns, distribution 0.831ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.119 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X84Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y497 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.167 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/Q net (fo=5, routed) 0.039 1.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut SLICE_X84Y497 LUT5 (Prop_C6LUT_SLICEL_I1_O) 0.045 1.251 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter[2]_i_1__21/O net (fo=1, routed) 0.016 1.267 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/cnter[2] SLICE_X84Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.186 1.351 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X84Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C clock pessimism -0.190 1.161 SLICE_X84Y497 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.217 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] ------------------------------------------------------------------- required time -1.217 arrival time 1.267 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_19 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.114ns Clock Pessimism Removal (CPR): 0.224ns Clock Net Delay (Source): 0.996ns (routing 0.315ns, distribution 0.681ns) Clock Net Delay (Destination): 1.178ns (routing 0.355ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.996 1.114 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X84Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y504 FDRE (Prop_AFF_SLICEL_C_Q) 0.049 1.163 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/Q net (fo=3, routed) 0.035 1.198 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/sel0[4] SLICE_X84Y504 LUT6 (Prop_A6LUT_SLICEL_I5_O) 0.015 1.213 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[4]_i_1__17/O net (fo=1, routed) 0.012 1.225 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[4]_i_1__17_n_0 SLICE_X84Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.343 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X84Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism -0.224 1.119 SLICE_X84Y504 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.175 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time -1.175 arrival time 1.225 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_19 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y195 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X75Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X75Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X75Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X75Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X75Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X75Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X76Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X75Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X75Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X75Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X75Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][3]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X75Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][4]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X75Y480 g_clock_rate_din[17].ngccm_status_cnt_reg[17][5]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y492 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y497 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y497 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y497 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X83Y497 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X84Y496 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_20 To Clock: gtwiz_userclk_rx_srcclk_out[0]_20 Setup : 0 Failing Endpoints, Worst Slack 1.922ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.039ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.922ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 6.087ns (logic 1.548ns (25.431%) route 4.539ns (74.569%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.770ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.295ns (routing 0.728ns, distribution 1.567ns) Clock Net Delay (Destination): 1.936ns (routing 0.660ns, distribution 1.276ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.295 2.770 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.856 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.584 6.440 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X96Y497 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.238 6.678 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/O net (fo=5, routed) 0.796 7.474 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y498 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.224 7.698 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/O net (fo=7, routed) 1.159 8.857 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X97Y498 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X97Y498 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.221 10.872 clock uncertainty -0.035 10.837 SLICE_X97Y498 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.779 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.779 arrival time -8.857 ------------------------------------------------------------------- slack 1.922 Slack (MET) : 1.928ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 6.084ns (logic 1.548ns (25.444%) route 4.536ns (74.556%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.770ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.295ns (routing 0.728ns, distribution 1.567ns) Clock Net Delay (Destination): 1.936ns (routing 0.660ns, distribution 1.276ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.295 2.770 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.856 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.584 6.440 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X96Y497 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.238 6.678 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/O net (fo=5, routed) 0.796 7.474 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y498 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.224 7.698 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/O net (fo=7, routed) 1.156 8.854 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X97Y498 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X97Y498 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.221 10.872 clock uncertainty -0.035 10.837 SLICE_X97Y498 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.782 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.782 arrival time -8.854 ------------------------------------------------------------------- slack 1.928 Slack (MET) : 2.027ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.979ns (logic 1.548ns (25.891%) route 4.431ns (74.109%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.328ns = ( 10.645 - 8.317 ) Source Clock Delay (SCD): 2.770ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.295ns (routing 0.728ns, distribution 1.567ns) Clock Net Delay (Destination): 1.930ns (routing 0.660ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.295 2.770 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.856 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.584 6.440 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X96Y497 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.238 6.678 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/O net (fo=5, routed) 0.796 7.474 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y498 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.224 7.698 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/O net (fo=7, routed) 1.051 8.749 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X96Y498 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.645 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X96Y498 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.221 10.866 clock uncertainty -0.035 10.831 SLICE_X96Y498 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 10.776 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.776 arrival time -8.749 ------------------------------------------------------------------- slack 2.027 Slack (MET) : 2.027ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.979ns (logic 1.548ns (25.891%) route 4.431ns (74.109%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.328ns = ( 10.645 - 8.317 ) Source Clock Delay (SCD): 2.770ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.295ns (routing 0.728ns, distribution 1.567ns) Clock Net Delay (Destination): 1.930ns (routing 0.660ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.295 2.770 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.856 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.584 6.440 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X96Y497 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.238 6.678 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/O net (fo=5, routed) 0.796 7.474 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y498 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.224 7.698 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/O net (fo=7, routed) 1.051 8.749 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X96Y498 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.645 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X96Y498 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.221 10.866 clock uncertainty -0.035 10.831 SLICE_X96Y498 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.776 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.776 arrival time -8.749 ------------------------------------------------------------------- slack 2.027 Slack (MET) : 2.034ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.975ns (logic 1.548ns (25.908%) route 4.427ns (74.092%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.770ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.295ns (routing 0.728ns, distribution 1.567ns) Clock Net Delay (Destination): 1.932ns (routing 0.660ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.295 2.770 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.856 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.584 6.440 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X96Y497 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.238 6.678 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/O net (fo=5, routed) 0.796 7.474 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y498 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.224 7.698 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/O net (fo=7, routed) 1.047 8.745 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X96Y498 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.932 10.647 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X96Y498 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.221 10.868 clock uncertainty -0.035 10.833 SLICE_X96Y498 FDRE (Setup_AFF_SLICEL_C_CE) -0.054 10.779 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.779 arrival time -8.745 ------------------------------------------------------------------- slack 2.034 Slack (MET) : 2.102ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.891ns (logic 1.548ns (26.277%) route 4.343ns (73.723%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.315ns = ( 10.632 - 8.317 ) Source Clock Delay (SCD): 2.770ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.295ns (routing 0.728ns, distribution 1.567ns) Clock Net Delay (Destination): 1.917ns (routing 0.660ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.295 2.770 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.856 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.584 6.440 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X96Y497 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.238 6.678 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/O net (fo=5, routed) 0.796 7.474 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y498 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.224 7.698 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/O net (fo=7, routed) 0.963 8.661 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X96Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.917 10.632 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X96Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.221 10.854 clock uncertainty -0.035 10.818 SLICE_X96Y504 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.763 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.763 arrival time -8.661 ------------------------------------------------------------------- slack 2.102 Slack (MET) : 2.107ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.887ns (logic 1.548ns (26.295%) route 4.339ns (73.705%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.234ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.315ns = ( 10.632 - 8.317 ) Source Clock Delay (SCD): 2.770ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.295ns (routing 0.728ns, distribution 1.567ns) Clock Net Delay (Destination): 1.917ns (routing 0.660ns, distribution 1.257ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.295 2.770 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.856 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.584 6.440 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X96Y497 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.238 6.678 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/O net (fo=5, routed) 0.796 7.474 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y498 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.224 7.698 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__18/O net (fo=7, routed) 0.959 8.657 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 SLICE_X96Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.917 10.632 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X96Y504 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.221 10.854 clock uncertainty -0.035 10.818 SLICE_X96Y504 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 10.764 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.764 arrival time -8.657 ------------------------------------------------------------------- slack 2.107 Slack (MET) : 2.499ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.805ns (logic 1.625ns (27.993%) route 4.180ns (72.007%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.076ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.618ns = ( 10.935 - 8.317 ) Source Clock Delay (SCD): 2.770ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.295ns (routing 0.728ns, distribution 1.567ns) Clock Net Delay (Destination): 2.220ns (routing 0.660ns, distribution 1.560ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.295 2.770 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.856 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.584 6.440 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X96Y497 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.238 6.678 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/O net (fo=5, routed) 0.931 7.609 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y498 LUT4 (Prop_G6LUT_SLICEM_I2_O) 0.246 7.855 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__17/O net (fo=1, routed) 0.162 8.017 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__17_n_0 SLICE_X95Y497 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.055 8.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__17/O net (fo=2, routed) 0.503 8.575 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__17_n_0 SLICE_X95Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.220 10.935 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X95Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.228 11.163 clock uncertainty -0.035 11.128 SLICE_X95Y497 FDCE (Setup_CFF_SLICEM_C_CE) -0.054 11.074 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.074 arrival time -8.575 ------------------------------------------------------------------- slack 2.499 Slack (MET) : 2.499ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.805ns (logic 1.625ns (27.993%) route 4.180ns (72.007%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.076ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.618ns = ( 10.935 - 8.317 ) Source Clock Delay (SCD): 2.770ns Clock Pessimism Removal (CPR): 0.228ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.295ns (routing 0.728ns, distribution 1.567ns) Clock Net Delay (Destination): 2.220ns (routing 0.660ns, distribution 1.560ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.295 2.770 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.856 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.584 6.440 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X96Y497 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.238 6.678 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__17/O net (fo=5, routed) 0.931 7.609 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X95Y498 LUT4 (Prop_G6LUT_SLICEM_I2_O) 0.246 7.855 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__17/O net (fo=1, routed) 0.162 8.017 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__17_n_0 SLICE_X95Y497 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.055 8.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__17/O net (fo=2, routed) 0.503 8.575 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__17_n_0 SLICE_X95Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.220 10.935 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X95Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.228 11.163 clock uncertainty -0.035 11.128 SLICE_X95Y497 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 11.074 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.074 arrival time -8.575 ------------------------------------------------------------------- slack 2.499 Slack (MET) : 2.943ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[70]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 5.181ns (logic 1.090ns (21.038%) route 4.091ns (78.962%)) Logic Levels: 0 Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.328ns = ( 10.645 - 8.317 ) Source Clock Delay (SCD): 2.770ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.295ns (routing 0.728ns, distribution 1.567ns) Clock Net Delay (Destination): 1.930ns (routing 0.660ns, distribution 1.270ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.295 2.770 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[8]) 1.090 3.860 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[8] net (fo=6, routed) 4.091 7.951 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/D[10] SLICE_X96Y500 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[70]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.645 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X96Y500 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[70]/C clock pessimism 0.221 10.866 clock uncertainty -0.035 10.831 SLICE_X96Y500 FDCE (Setup_CFF_SLICEL_C_D) 0.063 10.894 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[70] ------------------------------------------------------------------- required time 10.894 arrival time -7.951 ------------------------------------------------------------------- slack 2.943 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].rx_data_ngccm_reg[18][51]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.154ns Source Clock Delay (SCD): 0.943ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.825ns (routing 0.314ns, distribution 0.511ns) Clock Net Delay (Destination): 0.989ns (routing 0.355ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.825 0.943 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X102Y482 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y482 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 0.991 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/Q net (fo=1, routed) 0.094 1.085 rx_data[18][51] SLICE_X102Y481 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][51]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.154 g_gbt_bank[1].gbtbank_n_84 SLICE_X102Y481 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][51]/C clock pessimism -0.163 0.991 SLICE_X102Y481 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.046 SFP_GEN[18].rx_data_ngccm_reg[18][51] ------------------------------------------------------------------- required time -1.046 arrival time 1.085 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.172ns (logic 0.080ns (46.512%) route 0.092ns (53.488%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.148ns Source Clock Delay (SCD): 0.943ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.825ns (routing 0.314ns, distribution 0.511ns) Clock Net Delay (Destination): 0.983ns (routing 0.355ns, distribution 0.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.825 0.943 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X100Y483 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X100Y483 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.992 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.076 1.068 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/O84[1] SLICE_X99Y483 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.031 1.099 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__17/O net (fo=1, routed) 0.016 1.115 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] SLICE_X99Y483 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.148 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X99Y483 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.132 1.016 SLICE_X99Y483 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.072 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.072 arrival time 1.115 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.101ns (66.447%) route 0.051ns (33.553%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.165ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.162ns Clock Net Delay (Source): 0.832ns (routing 0.314ns, distribution 0.518ns) Clock Net Delay (Destination): 1.000ns (routing 0.355ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.832 0.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X101Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y484 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 0.999 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.035 1.034 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[0] SLICE_X101Y483 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.052 1.086 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__17/O net (fo=1, routed) 0.016 1.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X101Y483 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.165 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X101Y483 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.162 1.003 SLICE_X101Y483 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.059 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.059 arrival time 1.102 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].rx_data_ngccm_reg[18][18]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.166ns (logic 0.049ns (29.518%) route 0.117ns (70.482%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.286ns Source Clock Delay (SCD): 1.065ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.947ns (routing 0.314ns, distribution 0.633ns) Clock Net Delay (Destination): 1.121ns (routing 0.355ns, distribution 0.766ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.947 1.065 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X95Y484 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y484 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 1.114 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.117 1.231 rx_data[18][18] SLICE_X94Y483 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.121 1.286 g_gbt_bank[1].gbtbank_n_84 SLICE_X94Y483 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][18]/C clock pessimism -0.154 1.132 SLICE_X94Y483 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.188 SFP_GEN[18].rx_data_ngccm_reg[18][18] ------------------------------------------------------------------- required time -1.188 arrival time 1.231 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[18].rx_data_ngccm_reg[18][5]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.049ns (32.026%) route 0.104ns (67.974%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.168ns Source Clock Delay (SCD): 0.951ns Clock Pessimism Removal (CPR): 0.162ns Clock Net Delay (Source): 0.833ns (routing 0.314ns, distribution 0.519ns) Clock Net Delay (Destination): 1.003ns (routing 0.355ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.833 0.951 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X97Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y486 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.104 1.104 rx_data[18][5] SLICE_X97Y484 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.168 g_gbt_bank[1].gbtbank_n_84 SLICE_X97Y484 FDCE r SFP_GEN[18].rx_data_ngccm_reg[18][5]/C clock pessimism -0.162 1.006 SLICE_X97Y484 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.061 SFP_GEN[18].rx_data_ngccm_reg[18][5] ------------------------------------------------------------------- required time -1.061 arrival time 1.104 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.170ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.162ns Clock Net Delay (Source): 0.837ns (routing 0.314ns, distribution 0.523ns) Clock Net Delay (Destination): 1.005ns (routing 0.355ns, distribution 0.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.955 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X97Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y484 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.004 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.035 1.039 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_21_in SLICE_X97Y483 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.054 1.093 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__17/O net (fo=1, routed) 0.016 1.109 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] SLICE_X97Y483 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.170 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X97Y483 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.162 1.008 SLICE_X97Y483 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.064 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.064 arrival time 1.109 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.150ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 0.826ns (routing 0.314ns, distribution 0.512ns) Clock Net Delay (Destination): 0.985ns (routing 0.355ns, distribution 0.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.826 0.944 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/CLK SLICE_X97Y494 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y494 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 0.993 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Q net (fo=2, routed) 0.033 1.026 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/timer[5] SLICE_X97Y494 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__18/O net (fo=1, routed) 0.012 1.053 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__18_n_0 SLICE_X97Y494 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.150 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/CLK SLICE_X97Y494 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C clock pessimism -0.201 0.949 SLICE_X97Y494 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.005 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5] ------------------------------------------------------------------- required time -1.005 arrival time 1.053 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.110ns (logic 0.064ns (58.182%) route 0.046ns (41.818%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.104ns Clock Pessimism Removal (CPR): 0.225ns Clock Net Delay (Source): 0.986ns (routing 0.314ns, distribution 0.672ns) Clock Net Delay (Destination): 1.169ns (routing 0.355ns, distribution 0.814ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.104 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X88Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y480 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.153 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/Q net (fo=9, routed) 0.034 1.187 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt_reg[6][7]_0[3] SLICE_X88Y480 LUT6 (Prop_A6LUT_SLICEL_I2_O) 0.015 1.202 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt[6][4]_i_1__0/O net (fo=1, routed) 0.012 1.214 g_gbt_bank[1].gbtbank/i_gbt_bank_n_309 SLICE_X88Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X88Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/C clock pessimism -0.225 1.109 SLICE_X88Y480 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.165 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4] ------------------------------------------------------------------- required time -1.165 arrival time 1.214 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.094ns (63.513%) route 0.054ns (36.486%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.102ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 0.984ns (routing 0.314ns, distribution 0.670ns) Clock Net Delay (Destination): 1.169ns (routing 0.355ns, distribution 0.814ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.102 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X88Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y480 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.151 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/Q net (fo=10, routed) 0.039 1.190 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt_reg[6][7]_0[0] SLICE_X88Y480 LUT6 (Prop_B6LUT_SLICEL_I1_O) 0.045 1.235 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt[6][3]_i_1__0/O net (fo=1, routed) 0.015 1.250 g_gbt_bank[1].gbtbank/i_gbt_bank_n_310 SLICE_X88Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.334 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X88Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C clock pessimism -0.190 1.144 SLICE_X88Y480 FDCE (Hold_BFF_SLICEL_C_D) 0.056 1.200 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3] ------------------------------------------------------------------- required time -1.200 arrival time 1.250 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_20 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.162ns (logic 0.080ns (49.383%) route 0.082ns (50.617%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.948ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.830ns (routing 0.314ns, distribution 0.516ns) Clock Net Delay (Destination): 1.001ns (routing 0.355ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.830 0.948 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X98Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y485 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.997 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Q net (fo=2, routed) 0.066 1.063 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_19_in SLICE_X98Y484 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.031 1.094 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__17/O net (fo=1, routed) 0.016 1.110 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[10] SLICE_X98Y484 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.001 1.166 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X98Y484 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.163 1.003 SLICE_X98Y484 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.059 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.060 arrival time 1.110 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_20 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y197 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X81Y481 g_clock_rate_din[18].ngccm_status_cnt_reg[18][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][3]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][4]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X77Y480 g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X93Y483 g_clock_rate_din[18].rx_frameclk_div2_reg[18]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X72Y483 g_clock_rate_din[18].rx_wordclk_div2_reg[18]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X88Y480 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X88Y480 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X88Y480 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X100Y489 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y34 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_21 To Clock: gtwiz_userclk_rx_srcclk_out[0]_21 Setup : 0 Failing Endpoints, Worst Slack 3.165ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.037ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.539ns (logic 0.227ns (5.001%) route 4.312ns (94.999%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.523ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.238ns = ( 10.555 - 8.317 ) Source Clock Delay (SCD): 2.981ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.506ns (routing 0.624ns, distribution 1.882ns) Clock Net Delay (Destination): 1.840ns (routing 0.565ns, distribution 1.275ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.506 2.981 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X93Y481 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y481 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.121 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Q net (fo=137, routed) 2.721 5.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X114Y488 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.929 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/O net (fo=76, routed) 1.591 7.520 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X112Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.840 10.555 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X112Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C clock pessimism 0.220 10.775 clock uncertainty -0.035 10.740 SLICE_X112Y486 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 10.685 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8] ------------------------------------------------------------------- required time 10.685 arrival time -7.520 ------------------------------------------------------------------- slack 3.165 Slack (MET) : 3.169ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.536ns (logic 0.227ns (5.004%) route 4.309ns (94.996%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.523ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.238ns = ( 10.555 - 8.317 ) Source Clock Delay (SCD): 2.981ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.506ns (routing 0.624ns, distribution 1.882ns) Clock Net Delay (Destination): 1.840ns (routing 0.565ns, distribution 1.275ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.506 2.981 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X93Y481 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y481 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.121 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Q net (fo=137, routed) 2.721 5.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X114Y488 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.929 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/O net (fo=76, routed) 1.588 7.517 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X112Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.840 10.555 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X112Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism 0.220 10.775 clock uncertainty -0.035 10.740 SLICE_X112Y486 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 10.686 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time 10.686 arrival time -7.517 ------------------------------------------------------------------- slack 3.169 Slack (MET) : 3.403ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.309ns (logic 0.227ns (5.268%) route 4.082ns (94.732%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.512ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.249ns = ( 10.566 - 8.317 ) Source Clock Delay (SCD): 2.981ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.506ns (routing 0.624ns, distribution 1.882ns) Clock Net Delay (Destination): 1.851ns (routing 0.565ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.506 2.981 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X93Y481 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y481 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.121 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Q net (fo=137, routed) 2.721 5.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X114Y488 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.929 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/O net (fo=76, routed) 1.361 7.290 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X108Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.851 10.566 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism 0.220 10.786 clock uncertainty -0.035 10.751 SLICE_X108Y486 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.693 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time 10.693 arrival time -7.290 ------------------------------------------------------------------- slack 3.403 Slack (MET) : 3.403ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.309ns (logic 0.227ns (5.268%) route 4.082ns (94.732%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.512ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.249ns = ( 10.566 - 8.317 ) Source Clock Delay (SCD): 2.981ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.506ns (routing 0.624ns, distribution 1.882ns) Clock Net Delay (Destination): 1.851ns (routing 0.565ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.506 2.981 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X93Y481 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y481 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.121 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Q net (fo=137, routed) 2.721 5.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X114Y488 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.929 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/O net (fo=76, routed) 1.361 7.290 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X108Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.851 10.566 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C clock pessimism 0.220 10.786 clock uncertainty -0.035 10.751 SLICE_X108Y486 FDRE (Setup_GFF2_SLICEL_C_CE) -0.058 10.693 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7] ------------------------------------------------------------------- required time 10.693 arrival time -7.290 ------------------------------------------------------------------- slack 3.403 Slack (MET) : 3.409ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.306ns (logic 0.227ns (5.272%) route 4.079ns (94.728%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.512ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.249ns = ( 10.566 - 8.317 ) Source Clock Delay (SCD): 2.981ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.506ns (routing 0.624ns, distribution 1.882ns) Clock Net Delay (Destination): 1.851ns (routing 0.565ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.506 2.981 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X93Y481 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y481 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.121 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Q net (fo=137, routed) 2.721 5.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X114Y488 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.929 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/O net (fo=76, routed) 1.358 7.287 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X108Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.851 10.566 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism 0.220 10.786 clock uncertainty -0.035 10.751 SLICE_X108Y486 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.696 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time 10.696 arrival time -7.287 ------------------------------------------------------------------- slack 3.409 Slack (MET) : 3.409ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.306ns (logic 0.227ns (5.272%) route 4.079ns (94.728%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.512ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.249ns = ( 10.566 - 8.317 ) Source Clock Delay (SCD): 2.981ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.506ns (routing 0.624ns, distribution 1.882ns) Clock Net Delay (Destination): 1.851ns (routing 0.565ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.506 2.981 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X93Y481 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y481 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.121 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Q net (fo=137, routed) 2.721 5.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X114Y488 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.929 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/O net (fo=76, routed) 1.358 7.287 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X108Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.851 10.566 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y486 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism 0.220 10.786 clock uncertainty -0.035 10.751 SLICE_X108Y486 FDRE (Setup_GFF_SLICEL_C_CE) -0.055 10.696 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time 10.696 arrival time -7.287 ------------------------------------------------------------------- slack 3.409 Slack (MET) : 3.518ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.188ns (logic 0.227ns (5.420%) route 3.961ns (94.580%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.518ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.243ns = ( 10.560 - 8.317 ) Source Clock Delay (SCD): 2.981ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.506ns (routing 0.624ns, distribution 1.882ns) Clock Net Delay (Destination): 1.845ns (routing 0.565ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.506 2.981 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X93Y481 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y481 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.121 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Q net (fo=137, routed) 2.721 5.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X114Y488 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.929 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/O net (fo=76, routed) 1.240 7.169 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X106Y484 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.845 10.560 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X106Y484 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C clock pessimism 0.220 10.780 clock uncertainty -0.035 10.745 SLICE_X106Y484 FDRE (Setup_GFF2_SLICEM_C_CE) -0.058 10.687 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3] ------------------------------------------------------------------- required time 10.687 arrival time -7.169 ------------------------------------------------------------------- slack 3.518 Slack (MET) : 3.518ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.188ns (logic 0.227ns (5.420%) route 3.961ns (94.580%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.518ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.243ns = ( 10.560 - 8.317 ) Source Clock Delay (SCD): 2.981ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.506ns (routing 0.624ns, distribution 1.882ns) Clock Net Delay (Destination): 1.845ns (routing 0.565ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.506 2.981 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X93Y481 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y481 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.121 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Q net (fo=137, routed) 2.721 5.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X114Y488 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.929 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/O net (fo=76, routed) 1.240 7.169 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X106Y484 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.845 10.560 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X106Y484 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism 0.220 10.780 clock uncertainty -0.035 10.745 SLICE_X106Y484 FDRE (Setup_FFF2_SLICEM_C_CE) -0.058 10.687 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time 10.687 arrival time -7.169 ------------------------------------------------------------------- slack 3.518 Slack (MET) : 3.518ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.188ns (logic 0.227ns (5.420%) route 3.961ns (94.580%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.518ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.243ns = ( 10.560 - 8.317 ) Source Clock Delay (SCD): 2.981ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.506ns (routing 0.624ns, distribution 1.882ns) Clock Net Delay (Destination): 1.845ns (routing 0.565ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.506 2.981 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X93Y481 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y481 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.121 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Q net (fo=137, routed) 2.721 5.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X114Y488 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.929 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/O net (fo=76, routed) 1.240 7.169 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X106Y484 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.845 10.560 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X106Y484 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C clock pessimism 0.220 10.780 clock uncertainty -0.035 10.745 SLICE_X106Y484 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.687 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8] ------------------------------------------------------------------- required time 10.687 arrival time -7.169 ------------------------------------------------------------------- slack 3.518 Slack (MET) : 3.524ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 4.185ns (logic 0.227ns (5.424%) route 3.958ns (94.576%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.518ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.243ns = ( 10.560 - 8.317 ) Source Clock Delay (SCD): 2.981ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.506ns (routing 0.624ns, distribution 1.882ns) Clock Net Delay (Destination): 1.845ns (routing 0.565ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.506 2.981 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X93Y481 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C ------------------------------------------------------------------- ------------------- SLICE_X93Y481 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.121 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/Q net (fo=137, routed) 2.721 5.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X114Y488 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.087 5.929 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__18/O net (fo=76, routed) 1.237 7.166 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X106Y484 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.845 10.560 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X106Y484 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism 0.220 10.780 clock uncertainty -0.035 10.745 SLICE_X106Y484 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.690 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time 10.690 arrival time -7.166 ------------------------------------------------------------------- slack 3.524 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.165ns (logic 0.063ns (38.182%) route 0.102ns (61.818%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.106ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.788ns (routing 0.265ns, distribution 0.523ns) Clock Net Delay (Destination): 0.941ns (routing 0.303ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y482 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 0.954 f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.086 1.040 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X109Y482 LUT5 (Prop_C6LUT_SLICEM_I1_O) 0.015 1.055 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[39]_i_2__18/O net (fo=1, routed) 0.016 1.071 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg00[39] SLICE_X109Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.941 1.106 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X109Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[39]/C clock pessimism -0.128 0.978 SLICE_X109Y482 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.034 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[39] ------------------------------------------------------------------- required time -1.034 arrival time 1.071 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.039ns (arrival time - required time) Source: SFP_GEN[19].rx_data_ngccm_reg[19][74]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.104ns (55.319%) route 0.084ns (44.681%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.117ns Source Clock Delay (SCD): 0.896ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.778ns (routing 0.265ns, distribution 0.513ns) Clock Net Delay (Destination): 0.952ns (routing 0.303ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.778 0.896 g_gbt_bank[1].gbtbank_n_94 SLICE_X112Y488 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][74]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y488 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 0.945 r SFP_GEN[19].rx_data_ngccm_reg[19][74]/Q net (fo=1, routed) 0.073 1.018 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[83]_0[66] SLICE_X111Y488 LUT3 (Prop_D5LUT_SLICEL_I1_O) 0.055 1.073 r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[74]_i_1/O net (fo=1, routed) 0.011 1.084 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[74]_i_1_n_0 SLICE_X111Y488 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.952 1.117 SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y488 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]/C clock pessimism -0.128 0.989 SLICE_X111Y488 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.045 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74] ------------------------------------------------------------------- required time -1.045 arrival time 1.084 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.041ns (arrival time - required time) Source: SFP_GEN[19].rx_data_ngccm_reg[19][73]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[72]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.101ns (53.158%) route 0.089ns (46.842%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.117ns Source Clock Delay (SCD): 0.896ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.778ns (routing 0.265ns, distribution 0.513ns) Clock Net Delay (Destination): 0.952ns (routing 0.303ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.778 0.896 g_gbt_bank[1].gbtbank_n_94 SLICE_X112Y488 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][73]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y488 FDCE (Prop_EFF2_SLICEM_C_Q) 0.048 0.944 r SFP_GEN[19].rx_data_ngccm_reg[19][73]/Q net (fo=1, routed) 0.073 1.017 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[83]_0[65] SLICE_X111Y488 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.053 1.070 r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[72]_i_1/O net (fo=1, routed) 0.016 1.086 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[72]_i_1_n_0 SLICE_X111Y488 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[72]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.952 1.117 SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X111Y488 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[72]/C clock pessimism -0.128 0.989 SLICE_X111Y488 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.045 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[72] ------------------------------------------------------------------- required time -1.045 arrival time 1.086 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.079ns (42.935%) route 0.105ns (57.065%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.114ns Source Clock Delay (SCD): 0.899ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.781ns (routing 0.265ns, distribution 0.516ns) Clock Net Delay (Destination): 0.949ns (routing 0.303ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.781 0.899 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X106Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y482 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.948 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/Q net (fo=29, routed) 0.089 1.037 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] SLICE_X107Y482 LUT5 (Prop_C6LUT_SLICEM_I2_O) 0.030 1.067 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter[2]_i_1__19/O net (fo=1, routed) 0.016 1.083 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/cnter[2] SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.949 1.114 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C clock pessimism -0.128 0.986 SLICE_X107Y482 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.042 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] ------------------------------------------------------------------- required time -1.042 arrival time 1.083 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.102ns (53.403%) route 0.089ns (46.597%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.118ns Source Clock Delay (SCD): 0.897ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.779ns (routing 0.265ns, distribution 0.514ns) Clock Net Delay (Destination): 0.953ns (routing 0.303ns, distribution 0.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.779 0.897 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X112Y488 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y488 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 0.946 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.073 1.019 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in SLICE_X111Y487 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.053 1.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__18/O net (fo=1, routed) 0.016 1.088 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X111Y487 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.118 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X111Y487 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.128 0.990 SLICE_X111Y487 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.046 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.046 arrival time 1.088 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.080ns (43.011%) route 0.106ns (56.989%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.114ns Source Clock Delay (SCD): 0.899ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.781ns (routing 0.265ns, distribution 0.516ns) Clock Net Delay (Destination): 0.949ns (routing 0.303ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.781 0.899 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X106Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y482 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.948 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/Q net (fo=29, routed) 0.090 1.038 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] SLICE_X107Y482 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.031 1.069 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter[1]_i_1__19/O net (fo=1, routed) 0.016 1.085 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/cnter[1] SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.949 1.114 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C clock pessimism -0.128 0.986 SLICE_X107Y482 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.042 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] ------------------------------------------------------------------- required time -1.042 arrival time 1.085 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.064ns (41.830%) route 0.089ns (58.170%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.118ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.788ns (routing 0.265ns, distribution 0.523ns) Clock Net Delay (Destination): 0.953ns (routing 0.303ns, distribution 0.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK SLICE_X110Y488 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y488 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 0.955 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/Q net (fo=6, routed) 0.073 1.028 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[0] SLICE_X110Y489 LUT6 (Prop_C6LUT_SLICEM_I1_O) 0.015 1.043 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__19/O net (fo=1, routed) 0.016 1.059 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__19_n_0 SLICE_X110Y489 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.118 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK SLICE_X110Y489 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism -0.159 0.959 SLICE_X110Y489 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.015 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time -1.015 arrival time 1.059 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].rx_data_ngccm_reg[19][78]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.048ns (28.235%) route 0.122ns (71.765%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.099ns Source Clock Delay (SCD): 0.904ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.786ns (routing 0.265ns, distribution 0.521ns) Clock Net Delay (Destination): 0.934ns (routing 0.303ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.786 0.904 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X113Y488 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y488 FDRE (Prop_CFF2_SLICEM_C_Q) 0.048 0.952 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/Q net (fo=1, routed) 0.122 1.074 rx_data[19][78] SLICE_X112Y488 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][78]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.934 1.099 g_gbt_bank[1].gbtbank_n_94 SLICE_X112Y488 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][78]/C clock pessimism -0.128 0.971 SLICE_X112Y488 FDCE (Hold_GFF2_SLICEM_C_D) 0.056 1.027 SFP_GEN[19].rx_data_ngccm_reg[19][78] ------------------------------------------------------------------- required time -1.027 arrival time 1.074 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.080ns (47.337%) route 0.089ns (52.663%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.903ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.785ns (routing 0.265ns, distribution 0.520ns) Clock Net Delay (Destination): 0.932ns (routing 0.303ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.785 0.903 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X114Y488 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y488 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 0.952 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.074 1.026 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in SLICE_X115Y488 LUT3 (Prop_B6LUT_SLICEM_I2_O) 0.031 1.057 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__18/O net (fo=1, routed) 0.015 1.072 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[10] SLICE_X115Y488 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X115Y488 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.128 0.969 SLICE_X115Y488 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.025 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.025 arrival time 1.072 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.049ns (arrival time - required time) Source: SFP_GEN[19].rx_data_ngccm_reg[19][53]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[52]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_21 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.079ns (49.068%) route 0.082ns (50.932%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.110ns Source Clock Delay (SCD): 0.895ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.777ns (routing 0.265ns, distribution 0.512ns) Clock Net Delay (Destination): 0.945ns (routing 0.303ns, distribution 0.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.777 0.895 g_gbt_bank[1].gbtbank_n_94 SLICE_X116Y487 FDCE r SFP_GEN[19].rx_data_ngccm_reg[19][53]/C ------------------------------------------------------------------- ------------------- SLICE_X116Y487 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 0.943 r SFP_GEN[19].rx_data_ngccm_reg[19][53]/Q net (fo=1, routed) 0.066 1.009 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[83]_0[45] SLICE_X116Y486 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.031 1.040 r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[52]_i_1/O net (fo=1, routed) 0.016 1.056 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40[52]_i_1_n_0 SLICE_X116Y486 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[52]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.945 1.110 SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y486 FDCE r SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism -0.159 0.951 SLICE_X116Y486 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.007 SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time -1.007 arrival time 1.056 ------------------------------------------------------------------- slack 0.049 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_21 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y215 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X74Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X74Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X74Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X74Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X74Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X74Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y481 g_clock_rate_din[19].ngccm_status_cnt_reg[19][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X105Y484 g_clock_rate_din[19].rx_frameclk_div2_reg[19]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y480 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y481 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y481 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y481 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/C Low Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X89Y481 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X74Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X74Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X74Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X74Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X74Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X74Y480 g_clock_rate_din[19].ngccm_status_cnt_reg[19][5]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y35 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_22 To Clock: gtwiz_userclk_rx_srcclk_out[0]_22 Setup : 0 Failing Endpoints, Worst Slack 3.569ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.040ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.493ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.569ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.438ns (logic 1.634ns (36.818%) route 2.804ns (63.182%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.205ns = ( 10.522 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.206ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.156ns (routing 0.612ns, distribution 1.544ns) Clock Net Delay (Destination): 1.807ns (routing 0.555ns, distribution 1.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.156 2.631 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.915 5.630 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X112Y542 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.146 5.776 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.389 6.165 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X114Y541 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.237 6.402 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19/O net (fo=1, routed) 0.079 6.481 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19_n_0 SLICE_X114Y541 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.167 6.648 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19/O net (fo=2, routed) 0.421 7.069 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19_n_0 SLICE_X114Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.807 10.522 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X114Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.206 10.728 clock uncertainty -0.035 10.693 SLICE_X114Y542 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 10.638 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.638 arrival time -7.069 ------------------------------------------------------------------- slack 3.569 Slack (MET) : 3.569ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.438ns (logic 1.634ns (36.818%) route 2.804ns (63.182%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.205ns = ( 10.522 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.206ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.156ns (routing 0.612ns, distribution 1.544ns) Clock Net Delay (Destination): 1.807ns (routing 0.555ns, distribution 1.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.156 2.631 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.915 5.630 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X112Y542 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.146 5.776 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.389 6.165 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X114Y541 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.237 6.402 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19/O net (fo=1, routed) 0.079 6.481 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19_n_0 SLICE_X114Y541 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.167 6.648 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19/O net (fo=2, routed) 0.421 7.069 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19_n_0 SLICE_X114Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.807 10.522 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X114Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.206 10.728 clock uncertainty -0.035 10.693 SLICE_X114Y542 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 10.638 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.638 arrival time -7.069 ------------------------------------------------------------------- slack 3.569 Slack (MET) : 3.788ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.221ns (logic 1.319ns (31.249%) route 2.902ns (68.751%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.207ns = ( 10.524 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.206ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.156ns (routing 0.612ns, distribution 1.544ns) Clock Net Delay (Destination): 1.809ns (routing 0.555ns, distribution 1.254ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.156 2.631 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.915 5.630 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X112Y542 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.146 5.776 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.371 6.147 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X114Y541 LUT6 (Prop_A6LUT_SLICEL_I0_O) 0.089 6.236 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/O net (fo=5, routed) 0.616 6.852 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 SLICE_X114Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.809 10.524 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X114Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.206 10.730 clock uncertainty -0.035 10.695 SLICE_X114Y542 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.640 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 10.640 arrival time -6.852 ------------------------------------------------------------------- slack 3.788 Slack (MET) : 3.788ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.221ns (logic 1.319ns (31.249%) route 2.902ns (68.751%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.207ns = ( 10.524 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.206ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.156ns (routing 0.612ns, distribution 1.544ns) Clock Net Delay (Destination): 1.809ns (routing 0.555ns, distribution 1.254ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.156 2.631 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.915 5.630 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X112Y542 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.146 5.776 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.371 6.147 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X114Y541 LUT6 (Prop_A6LUT_SLICEL_I0_O) 0.089 6.236 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/O net (fo=5, routed) 0.616 6.852 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 SLICE_X114Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.809 10.524 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X114Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.206 10.730 clock uncertainty -0.035 10.695 SLICE_X114Y542 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 10.640 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 10.640 arrival time -6.852 ------------------------------------------------------------------- slack 3.788 Slack (MET) : 3.793ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.217ns (logic 1.319ns (31.278%) route 2.898ns (68.722%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.207ns = ( 10.524 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.206ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.156ns (routing 0.612ns, distribution 1.544ns) Clock Net Delay (Destination): 1.809ns (routing 0.555ns, distribution 1.254ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.156 2.631 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.915 5.630 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X112Y542 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.146 5.776 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.371 6.147 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X114Y541 LUT6 (Prop_A6LUT_SLICEL_I0_O) 0.089 6.236 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/O net (fo=5, routed) 0.612 6.848 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 SLICE_X114Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.809 10.524 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X114Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.206 10.730 clock uncertainty -0.035 10.695 SLICE_X114Y542 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 10.641 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 10.641 arrival time -6.848 ------------------------------------------------------------------- slack 3.793 Slack (MET) : 3.793ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.217ns (logic 1.319ns (31.278%) route 2.898ns (68.722%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.207ns = ( 10.524 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.206ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.156ns (routing 0.612ns, distribution 1.544ns) Clock Net Delay (Destination): 1.809ns (routing 0.555ns, distribution 1.254ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.156 2.631 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.915 5.630 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X112Y542 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.146 5.776 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.371 6.147 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X114Y541 LUT6 (Prop_A6LUT_SLICEL_I0_O) 0.089 6.236 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/O net (fo=5, routed) 0.612 6.848 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 SLICE_X114Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.809 10.524 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X114Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.206 10.730 clock uncertainty -0.035 10.695 SLICE_X114Y542 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 10.641 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 10.641 arrival time -6.848 ------------------------------------------------------------------- slack 3.793 Slack (MET) : 3.793ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.217ns (logic 1.319ns (31.278%) route 2.898ns (68.722%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.207ns = ( 10.524 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.206ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.156ns (routing 0.612ns, distribution 1.544ns) Clock Net Delay (Destination): 1.809ns (routing 0.555ns, distribution 1.254ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.156 2.631 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.915 5.630 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X112Y542 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.146 5.776 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.371 6.147 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X114Y541 LUT6 (Prop_A6LUT_SLICEL_I0_O) 0.089 6.236 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/O net (fo=5, routed) 0.612 6.848 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 SLICE_X114Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.809 10.524 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X114Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.206 10.730 clock uncertainty -0.035 10.695 SLICE_X114Y542 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 10.641 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 10.641 arrival time -6.848 ------------------------------------------------------------------- slack 3.793 Slack (MET) : 3.816ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.190ns (logic 1.396ns (33.317%) route 2.794ns (66.683%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.204ns = ( 10.521 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.206ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.156ns (routing 0.612ns, distribution 1.544ns) Clock Net Delay (Destination): 1.806ns (routing 0.555ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.156 2.631 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.915 5.630 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X112Y542 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.146 5.776 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.380 6.156 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X114Y541 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 6.322 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/O net (fo=3, routed) 0.499 6.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 SLICE_X117Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.806 10.521 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X117Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.206 10.727 clock uncertainty -0.035 10.692 SLICE_X117Y542 FDRE (Setup_BFF2_SLICEL_C_CE) -0.055 10.637 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.637 arrival time -6.821 ------------------------------------------------------------------- slack 3.816 Slack (MET) : 3.816ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.190ns (logic 1.396ns (33.317%) route 2.794ns (66.683%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.204ns = ( 10.521 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.206ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.156ns (routing 0.612ns, distribution 1.544ns) Clock Net Delay (Destination): 1.806ns (routing 0.555ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.156 2.631 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.915 5.630 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X112Y542 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.146 5.776 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.380 6.156 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X114Y541 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 6.322 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/O net (fo=3, routed) 0.499 6.821 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 SLICE_X117Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.806 10.521 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X117Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.206 10.727 clock uncertainty -0.035 10.692 SLICE_X117Y542 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.637 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 10.637 arrival time -6.821 ------------------------------------------------------------------- slack 3.816 Slack (MET) : 3.821ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 4.186ns (logic 1.396ns (33.349%) route 2.790ns (66.651%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.204ns = ( 10.521 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.206ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.156ns (routing 0.612ns, distribution 1.544ns) Clock Net Delay (Destination): 1.806ns (routing 0.555ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.156 2.631 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.915 5.630 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X112Y542 LUT4 (Prop_C6LUT_SLICEM_I3_O) 0.146 5.776 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/O net (fo=5, routed) 0.380 6.156 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X114Y541 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.166 6.322 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/O net (fo=3, routed) 0.495 6.817 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 SLICE_X117Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.806 10.521 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X117Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.206 10.727 clock uncertainty -0.035 10.692 SLICE_X117Y542 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 10.638 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 10.638 arrival time -6.817 ------------------------------------------------------------------- slack 3.821 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].rx_data_ngccm_reg[20][39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.098ns Source Clock Delay (SCD): 0.894ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.776ns (routing 0.262ns, distribution 0.514ns) Clock Net Delay (Destination): 0.933ns (routing 0.300ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.776 0.894 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X105Y543 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y543 FDRE (Prop_EFF2_SLICEL_C_Q) 0.048 0.942 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.094 1.036 rx_data[20][39] SLICE_X105Y544 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.933 1.098 g_gbt_bank[1].gbtbank_n_104 SLICE_X105Y544 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][39]/C clock pessimism -0.158 0.940 SLICE_X105Y544 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 0.996 SFP_GEN[20].rx_data_ngccm_reg[20][39] ------------------------------------------------------------------- required time -0.996 arrival time 1.036 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].rx_data_ngccm_reg[20][69]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.048ns (31.373%) route 0.105ns (68.627%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.106ns Source Clock Delay (SCD): 0.894ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 0.776ns (routing 0.262ns, distribution 0.514ns) Clock Net Delay (Destination): 0.941ns (routing 0.300ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.776 0.894 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X114Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y545 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 0.942 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.105 1.047 rx_data[20][69] SLICE_X114Y544 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][69]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.941 1.106 g_gbt_bank[1].gbtbank_n_104 SLICE_X114Y544 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][69]/C clock pessimism -0.157 0.949 SLICE_X114Y544 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.005 SFP_GEN[20].rx_data_ngccm_reg[20][69] ------------------------------------------------------------------- required time -1.005 arrival time 1.047 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].rx_data_ngccm_reg[20][6]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.048ns (28.743%) route 0.119ns (71.257%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.902ns Clock Pessimism Removal (CPR): 0.127ns Clock Net Delay (Source): 0.784ns (routing 0.262ns, distribution 0.522ns) Clock Net Delay (Destination): 0.932ns (routing 0.300ns, distribution 0.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.784 0.902 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y540 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y540 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 0.950 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.119 1.069 rx_data[20][6] SLICE_X109Y540 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 g_gbt_bank[1].gbtbank_n_104 SLICE_X109Y540 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][6]/C clock pessimism -0.127 0.970 SLICE_X109Y540 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.026 SFP_GEN[20].rx_data_ngccm_reg[20][6] ------------------------------------------------------------------- required time -1.026 arrival time 1.069 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].rx_data_ngccm_reg[20][61]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.049ns (32.026%) route 0.104ns (67.974%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.106ns Source Clock Delay (SCD): 0.896ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 0.778ns (routing 0.262ns, distribution 0.516ns) Clock Net Delay (Destination): 0.941ns (routing 0.300ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.778 0.896 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X114Y545 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X114Y545 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 0.945 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/Q net (fo=1, routed) 0.104 1.049 rx_data[20][61] SLICE_X114Y544 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][61]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.941 1.106 g_gbt_bank[1].gbtbank_n_104 SLICE_X114Y544 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][61]/C clock pessimism -0.157 0.949 SLICE_X114Y544 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.005 SFP_GEN[20].rx_data_ngccm_reg[20][61] ------------------------------------------------------------------- required time -1.005 arrival time 1.049 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.104ns (53.886%) route 0.089ns (46.114%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.112ns Source Clock Delay (SCD): 0.893ns Clock Pessimism Removal (CPR): 0.127ns Clock Net Delay (Source): 0.775ns (routing 0.262ns, distribution 0.513ns) Clock Net Delay (Destination): 0.947ns (routing 0.300ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.775 0.893 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X109Y540 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y540 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.942 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.078 1.020 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_7_in SLICE_X108Y540 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.055 1.075 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__19/O net (fo=1, routed) 0.011 1.086 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[2] SLICE_X108Y540 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.947 1.112 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y540 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.127 0.985 SLICE_X108Y540 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.041 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -1.041 arrival time 1.086 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.047ns (arrival time - required time) Source: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.197ns (logic 0.049ns (24.873%) route 0.148ns (75.127%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.128ns Source Clock Delay (SCD): 0.907ns Clock Pessimism Removal (CPR): 0.127ns Clock Net Delay (Source): 0.789ns (routing 0.262ns, distribution 0.527ns) Clock Net Delay (Destination): 0.963ns (routing 0.300ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.789 0.907 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y541 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]/C ------------------------------------------------------------------- ------------------- SLICE_X104Y541 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.956 r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]/Q net (fo=2, routed) 0.148 1.104 SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/Q[14] SLICE_X102Y541 FDRE r SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.963 1.128 SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y541 FDRE r SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C clock pessimism -0.127 1.001 SLICE_X102Y541 FDRE (Hold_FFF_SLICEL_C_D) 0.056 1.057 SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14] ------------------------------------------------------------------- required time -1.057 arrival time 1.104 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].rx_data_ngccm_reg[20][4]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.048ns (28.070%) route 0.123ns (71.930%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.902ns Clock Pessimism Removal (CPR): 0.127ns Clock Net Delay (Source): 0.784ns (routing 0.262ns, distribution 0.522ns) Clock Net Delay (Destination): 0.932ns (routing 0.300ns, distribution 0.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.784 0.902 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y540 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y540 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 0.950 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.123 1.073 rx_data[20][4] SLICE_X109Y540 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 g_gbt_bank[1].gbtbank_n_104 SLICE_X109Y540 FDCE r SFP_GEN[20].rx_data_ngccm_reg[20][4]/C clock pessimism -0.127 0.970 SLICE_X109Y540 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.026 SFP_GEN[20].rx_data_ngccm_reg[20][4] ------------------------------------------------------------------- required time -1.026 arrival time 1.073 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.088ns Source Clock Delay (SCD): 0.888ns Clock Pessimism Removal (CPR): 0.195ns Clock Net Delay (Source): 0.770ns (routing 0.262ns, distribution 0.508ns) Clock Net Delay (Destination): 0.923ns (routing 0.300ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.770 0.888 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK SLICE_X109Y547 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y547 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 0.937 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Q net (fo=2, routed) 0.033 0.970 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/timer[5] SLICE_X109Y547 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.015 0.985 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__20/O net (fo=1, routed) 0.012 0.997 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__20_n_0 SLICE_X109Y547 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.923 1.088 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK SLICE_X109Y547 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C clock pessimism -0.195 0.893 SLICE_X109Y547 FDRE (Hold_AFF_SLICEM_C_D) 0.056 0.949 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5] ------------------------------------------------------------------- required time -0.949 arrival time 0.997 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.162ns (logic 0.079ns (48.765%) route 0.083ns (51.235%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.883ns Clock Pessimism Removal (CPR): 0.158ns Clock Net Delay (Source): 0.765ns (routing 0.262ns, distribution 0.503ns) Clock Net Delay (Destination): 0.932ns (routing 0.300ns, distribution 0.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.765 0.883 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X113Y547 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y547 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 0.932 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.069 1.001 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in SLICE_X113Y546 LUT3 (Prop_G6LUT_SLICEM_I2_O) 0.030 1.031 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__19/O net (fo=1, routed) 0.014 1.045 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X113Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X113Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.158 0.939 SLICE_X113Y546 FDRE (Hold_GFF_SLICEM_C_D) 0.056 0.995 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -0.995 arrival time 1.045 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_22 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.109ns Source Clock Delay (SCD): 0.902ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.784ns (routing 0.262ns, distribution 0.522ns) Clock Net Delay (Destination): 0.944ns (routing 0.300ns, distribution 0.644ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.784 0.902 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y541 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y541 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 0.951 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.035 0.986 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_13_in SLICE_X108Y541 LUT3 (Prop_H6LUT_SLICEL_I2_O) 0.045 1.031 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__19/O net (fo=1, routed) 0.016 1.047 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[5] SLICE_X108Y541 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.944 1.109 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y541 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.170 0.939 SLICE_X108Y541 FDRE (Hold_HFF_SLICEL_C_D) 0.056 0.995 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -0.995 arrival time 1.047 ------------------------------------------------------------------- slack 0.052 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_22 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y239 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X124Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X124Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X93Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X93Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X93Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X95Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X112Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X124Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X124Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X93Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X93Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X93Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X95Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X112Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X112Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X112Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X112Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X117Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[52]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X117Y540 SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[54]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.037 0.493 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.037 1.291 GTHE3_CHANNEL_X1Y36 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_23 To Clock: gtwiz_userclk_rx_srcclk_out[0]_23 Setup : 0 Failing Endpoints, Worst Slack 3.766ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.039ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.494ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.766ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[104]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.427ns (logic 1.148ns (25.932%) route 3.279ns (74.068%)) Logic Levels: 5 (LUT4=1 LUT6=4) Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.526ns = ( 10.843 - 8.317 ) Source Clock Delay (SCD): 2.911ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.436ns (routing 0.721ns, distribution 1.715ns) Clock Net Delay (Destination): 2.128ns (routing 0.657ns, distribution 1.471ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.436 2.911 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X128Y547 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[104]/C ------------------------------------------------------------------- ------------------- SLICE_X128Y547 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.050 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[104]/Q net (fo=9, routed) 0.500 3.550 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxencdata_s[9]_53[15] SLICE_X127Y549 LUT6 (Prop_F6LUT_SLICEL_I3_O) 0.235 3.785 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_5__20/O net (fo=1, routed) 0.497 4.282 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_5__20_n_0 SLICE_X124Y549 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.166 4.448 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_1__20/O net (fo=33, routed) 1.715 6.163 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/s1_from_syndromes[0] SLICE_X131Y546 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.401 f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__20/O net (fo=1, routed) 0.074 6.475 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__20_n_0 SLICE_X131Y546 LUT6 (Prop_G6LUT_SLICEL_I4_O) 0.147 6.622 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__41/O net (fo=1, routed) 0.458 7.080 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__41_n_0 SLICE_X129Y546 LUT6 (Prop_D6LUT_SLICEL_I3_O) 0.223 7.303 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__41/O net (fo=1, routed) 0.035 7.338 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 SLICE_X129Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.128 10.843 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK SLICE_X129Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C clock pessimism 0.233 11.076 clock uncertainty -0.035 11.041 SLICE_X129Y546 FDRE (Setup_DFF_SLICEL_C_D) 0.063 11.104 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg ------------------------------------------------------------------- required time 11.104 arrival time -7.338 ------------------------------------------------------------------- slack 3.766 Slack (MET) : 3.794ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.368ns (logic 1.729ns (39.583%) route 2.639ns (60.417%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.513ns = ( 10.830 - 8.317 ) Source Clock Delay (SCD): 2.812ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.337ns (routing 0.721ns, distribution 1.616ns) Clock Net Delay (Destination): 2.115ns (routing 0.657ns, distribution 1.458ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.337 2.812 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.916 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.584 5.500 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X127Y544 LUT4 (Prop_H6LUT_SLICEL_I1_O) 0.238 5.738 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/O net (fo=5, routed) 0.427 6.165 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X129Y546 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.166 6.331 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__20/O net (fo=1, routed) 0.186 6.517 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__20_n_0 SLICE_X128Y546 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.221 6.738 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__20/O net (fo=2, routed) 0.442 7.180 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__20_n_0 SLICE_X127Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.115 10.830 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X127Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.233 11.063 clock uncertainty -0.035 11.028 SLICE_X127Y546 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 10.974 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.974 arrival time -7.180 ------------------------------------------------------------------- slack 3.794 Slack (MET) : 3.825ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.334ns (logic 1.729ns (39.894%) route 2.605ns (60.106%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.511ns = ( 10.828 - 8.317 ) Source Clock Delay (SCD): 2.812ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.337ns (routing 0.721ns, distribution 1.616ns) Clock Net Delay (Destination): 2.113ns (routing 0.657ns, distribution 1.456ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.337 2.812 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.916 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.584 5.500 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X127Y544 LUT4 (Prop_H6LUT_SLICEL_I1_O) 0.238 5.738 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/O net (fo=5, routed) 0.427 6.165 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X129Y546 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.166 6.331 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__20/O net (fo=1, routed) 0.186 6.517 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__20_n_0 SLICE_X128Y546 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.221 6.738 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__20/O net (fo=2, routed) 0.408 7.146 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__20_n_0 SLICE_X127Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.113 10.828 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X127Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.233 11.061 clock uncertainty -0.035 11.026 SLICE_X127Y546 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 10.971 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.971 arrival time -7.146 ------------------------------------------------------------------- slack 3.825 Slack (MET) : 4.109ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.082ns (logic 1.432ns (35.081%) route 2.650ns (64.919%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.546ns = ( 10.863 - 8.317 ) Source Clock Delay (SCD): 2.812ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.337ns (routing 0.721ns, distribution 1.616ns) Clock Net Delay (Destination): 2.148ns (routing 0.657ns, distribution 1.491ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.337 2.812 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.916 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.584 5.500 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X127Y544 LUT4 (Prop_H6LUT_SLICEL_I1_O) 0.238 5.738 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/O net (fo=5, routed) 0.420 6.158 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X129Y546 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.090 6.248 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/O net (fo=7, routed) 0.646 6.894 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X130Y544 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.148 10.863 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X130Y544 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.233 11.096 clock uncertainty -0.035 11.061 SLICE_X130Y544 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.003 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.003 arrival time -6.894 ------------------------------------------------------------------- slack 4.109 Slack (MET) : 4.116ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.078ns (logic 1.432ns (35.115%) route 2.646ns (64.885%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.546ns = ( 10.863 - 8.317 ) Source Clock Delay (SCD): 2.812ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.337ns (routing 0.721ns, distribution 1.616ns) Clock Net Delay (Destination): 2.148ns (routing 0.657ns, distribution 1.491ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.337 2.812 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.916 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.584 5.500 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X127Y544 LUT4 (Prop_H6LUT_SLICEL_I1_O) 0.238 5.738 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/O net (fo=5, routed) 0.420 6.158 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X129Y546 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.090 6.248 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/O net (fo=7, routed) 0.642 6.890 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X130Y544 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.148 10.863 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X130Y544 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.233 11.096 clock uncertainty -0.035 11.061 SLICE_X130Y544 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.006 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.006 arrival time -6.890 ------------------------------------------------------------------- slack 4.116 Slack (MET) : 4.118ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 4.041ns (logic 1.432ns (35.437%) route 2.609ns (64.563%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.511ns = ( 10.828 - 8.317 ) Source Clock Delay (SCD): 2.812ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.337ns (routing 0.721ns, distribution 1.616ns) Clock Net Delay (Destination): 2.113ns (routing 0.657ns, distribution 1.456ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.337 2.812 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.916 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.584 5.500 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X127Y544 LUT4 (Prop_H6LUT_SLICEL_I1_O) 0.238 5.738 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/O net (fo=5, routed) 0.420 6.158 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X129Y546 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.090 6.248 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/O net (fo=7, routed) 0.605 6.853 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X127Y544 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.113 10.828 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X127Y544 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.233 11.061 clock uncertainty -0.035 11.026 SLICE_X127Y544 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 10.971 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.971 arrival time -6.853 ------------------------------------------------------------------- slack 4.118 Slack (MET) : 4.267ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.899ns (logic 1.432ns (36.727%) route 2.467ns (63.273%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.518ns = ( 10.835 - 8.317 ) Source Clock Delay (SCD): 2.812ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.337ns (routing 0.721ns, distribution 1.616ns) Clock Net Delay (Destination): 2.120ns (routing 0.657ns, distribution 1.463ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.337 2.812 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.916 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.584 5.500 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X127Y544 LUT4 (Prop_H6LUT_SLICEL_I1_O) 0.238 5.738 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/O net (fo=5, routed) 0.420 6.158 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X129Y546 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.090 6.248 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/O net (fo=7, routed) 0.463 6.711 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X128Y544 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.120 10.835 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X128Y544 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.233 11.068 clock uncertainty -0.035 11.033 SLICE_X128Y544 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 10.978 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.978 arrival time -6.711 ------------------------------------------------------------------- slack 4.267 Slack (MET) : 4.272ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.895ns (logic 1.432ns (36.765%) route 2.463ns (63.235%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.518ns = ( 10.835 - 8.317 ) Source Clock Delay (SCD): 2.812ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.337ns (routing 0.721ns, distribution 1.616ns) Clock Net Delay (Destination): 2.120ns (routing 0.657ns, distribution 1.463ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.337 2.812 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.916 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.584 5.500 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X127Y544 LUT4 (Prop_H6LUT_SLICEL_I1_O) 0.238 5.738 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/O net (fo=5, routed) 0.420 6.158 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X129Y546 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.090 6.248 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/O net (fo=7, routed) 0.459 6.707 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X128Y544 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.120 10.835 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X128Y544 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.233 11.068 clock uncertainty -0.035 11.033 SLICE_X128Y544 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 10.979 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.979 arrival time -6.707 ------------------------------------------------------------------- slack 4.272 Slack (MET) : 4.272ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.895ns (logic 1.432ns (36.765%) route 2.463ns (63.235%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.518ns = ( 10.835 - 8.317 ) Source Clock Delay (SCD): 2.812ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.337ns (routing 0.721ns, distribution 1.616ns) Clock Net Delay (Destination): 2.120ns (routing 0.657ns, distribution 1.463ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.337 2.812 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.916 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.584 5.500 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X127Y544 LUT4 (Prop_H6LUT_SLICEL_I1_O) 0.238 5.738 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/O net (fo=5, routed) 0.420 6.158 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X129Y546 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.090 6.248 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__21/O net (fo=7, routed) 0.459 6.707 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X128Y544 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.120 10.835 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X128Y544 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.233 11.068 clock uncertainty -0.035 11.033 SLICE_X128Y544 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 10.979 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.979 arrival time -6.707 ------------------------------------------------------------------- slack 4.272 Slack (MET) : 4.274ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 3.887ns (logic 1.431ns (36.815%) route 2.456ns (63.185%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.063ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.516ns = ( 10.833 - 8.317 ) Source Clock Delay (SCD): 2.812ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.337ns (routing 0.721ns, distribution 1.616ns) Clock Net Delay (Destination): 2.118ns (routing 0.657ns, distribution 1.461ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.337 2.812 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.916 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.584 5.500 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X127Y544 LUT4 (Prop_H6LUT_SLICEL_I1_O) 0.238 5.738 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__20/O net (fo=5, routed) 0.342 6.080 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X128Y545 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.089 6.169 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__21/O net (fo=3, routed) 0.530 6.699 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecFalseHeaders0 SLICE_X128Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.118 10.833 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X128Y546 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.233 11.066 clock uncertainty -0.035 11.031 SLICE_X128Y546 FDRE (Setup_GFF2_SLICEL_C_CE) -0.058 10.973 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.973 arrival time -6.699 ------------------------------------------------------------------- slack 4.274 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.094ns (52.222%) route 0.086ns (47.778%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.226ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.884ns (routing 0.316ns, distribution 0.568ns) Clock Net Delay (Destination): 1.061ns (routing 0.357ns, distribution 0.704ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.884 1.002 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X122Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y549 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.051 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.074 1.125 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/O84[0] SLICE_X123Y549 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.045 1.170 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__20/O net (fo=1, routed) 0.012 1.182 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] SLICE_X123Y549 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.061 1.226 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X123Y549 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.139 1.087 SLICE_X123Y549 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.143 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.143 arrival time 1.182 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.166ns (logic 0.064ns (38.554%) route 0.102ns (61.446%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.939ns Clock Pessimism Removal (CPR): 0.131ns Clock Net Delay (Source): 0.821ns (routing 0.316ns, distribution 0.505ns) Clock Net Delay (Destination): 0.975ns (routing 0.357ns, distribution 0.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.821 0.939 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X97Y542 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C ------------------------------------------------------------------- ------------------- SLICE_X97Y542 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.988 r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/Q net (fo=10, routed) 0.086 1.074 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].cnt_reg[9][7]_0[0] SLICE_X96Y542 LUT6 (Prop_D6LUT_SLICEL_I4_O) 0.015 1.089 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i[9]_i_1__0/O net (fo=1, routed) 0.016 1.105 g_gbt_bank[1].gbtbank/i_gbt_bank_n_154 SLICE_X96Y542 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.140 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X96Y542 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/C clock pessimism -0.131 1.009 SLICE_X96Y542 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.065 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9] ------------------------------------------------------------------- required time -1.065 arrival time 1.105 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[37]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[37]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.226ns Source Clock Delay (SCD): 1.014ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.896ns (routing 0.316ns, distribution 0.580ns) Clock Net Delay (Destination): 1.061ns (routing 0.357ns, distribution 0.704ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.896 1.014 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X125Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[37]/C ------------------------------------------------------------------- ------------------- SLICE_X125Y543 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.062 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[37]/Q net (fo=1, routed) 0.094 1.156 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[37] SLICE_X125Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.061 1.226 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X125Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[37]/C clock pessimism -0.170 1.056 SLICE_X125Y542 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.112 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[37] ------------------------------------------------------------------- required time -1.112 arrival time 1.156 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.094ns (50.811%) route 0.091ns (49.189%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.226ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.884ns (routing 0.316ns, distribution 0.568ns) Clock Net Delay (Destination): 1.061ns (routing 0.357ns, distribution 0.704ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.884 1.002 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X122Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y549 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.051 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.076 1.127 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[0] SLICE_X123Y549 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.045 1.172 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__20/O net (fo=1, routed) 0.015 1.187 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X123Y549 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.061 1.226 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X123Y549 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.139 1.087 SLICE_X123Y549 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.143 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.143 arrival time 1.187 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.094ns (51.648%) route 0.088ns (48.352%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.229ns Source Clock Delay (SCD): 1.009ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.891ns (routing 0.316ns, distribution 0.575ns) Clock Net Delay (Destination): 1.064ns (routing 0.357ns, distribution 0.707ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.891 1.009 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X121Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y542 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.058 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.072 1.130 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X120Y542 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.175 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__20/O net (fo=1, routed) 0.016 1.191 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] SLICE_X120Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.064 1.229 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X120Y542 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.139 1.090 SLICE_X120Y542 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.146 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.146 arrival time 1.191 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.228ns Source Clock Delay (SCD): 1.006ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 0.888ns (routing 0.316ns, distribution 0.572ns) Clock Net Delay (Destination): 1.063ns (routing 0.357ns, distribution 0.706ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.888 1.006 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X120Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X120Y543 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.055 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.034 1.089 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_5_in SLICE_X120Y543 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.134 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__20/O net (fo=1, routed) 0.016 1.150 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] SLICE_X120Y543 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.063 1.228 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X120Y543 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.180 1.048 SLICE_X120Y543 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.104 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.104 arrival time 1.150 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.151ns (logic 0.064ns (42.384%) route 0.087ns (57.616%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.229ns Source Clock Delay (SCD): 1.011ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.893ns (routing 0.316ns, distribution 0.577ns) Clock Net Delay (Destination): 1.064ns (routing 0.357ns, distribution 0.707ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.893 1.011 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/CLK SLICE_X125Y541 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X125Y541 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.060 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[1]/Q net (fo=6, routed) 0.071 1.131 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/timer[1] SLICE_X125Y540 LUT6 (Prop_C6LUT_SLICEL_I5_O) 0.015 1.146 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__21/O net (fo=1, routed) 0.016 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__21_n_0 SLICE_X125Y540 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.064 1.229 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/CLK SLICE_X125Y540 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C clock pessimism -0.170 1.059 SLICE_X125Y540 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.115 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/clkSlipProcess.timer_reg[5] ------------------------------------------------------------------- required time -1.115 arrival time 1.162 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].rx_data_ngccm_reg[21][69]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.226ns Source Clock Delay (SCD): 1.008ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 0.890ns (routing 0.316ns, distribution 0.574ns) Clock Net Delay (Destination): 1.061ns (routing 0.357ns, distribution 0.704ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.890 1.008 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X121Y551 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X121Y551 FDRE (Prop_BFF2_SLICEL_C_Q) 0.048 1.056 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.093 1.149 rx_data[21][69] SLICE_X122Y551 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][69]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.061 1.226 g_gbt_bank[1].gbtbank_n_114 SLICE_X122Y551 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][69]/C clock pessimism -0.180 1.046 SLICE_X122Y551 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.101 SFP_GEN[21].rx_data_ngccm_reg[21][69] ------------------------------------------------------------------- required time -1.101 arrival time 1.149 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[21].rx_data_ngccm_reg[21][73]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[72]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.094ns (65.734%) route 0.049ns (34.266%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.225ns Source Clock Delay (SCD): 1.007ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 0.889ns (routing 0.316ns, distribution 0.573ns) Clock Net Delay (Destination): 1.060ns (routing 0.357ns, distribution 0.703ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.889 1.007 g_gbt_bank[1].gbtbank_n_114 SLICE_X123Y551 FDCE r SFP_GEN[21].rx_data_ngccm_reg[21][73]/C ------------------------------------------------------------------- ------------------- SLICE_X123Y551 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.056 r SFP_GEN[21].rx_data_ngccm_reg[21][73]/Q net (fo=1, routed) 0.033 1.089 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[83]_0[65] SLICE_X123Y551 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.134 r SFP_GEN[21].ngCCM_gbt/RX_Word_rx40[72]_i_1/O net (fo=1, routed) 0.016 1.150 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40[72]_i_1_n_0 SLICE_X123Y551 FDCE r SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[72]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.060 1.225 SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X123Y551 FDCE r SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[72]/C clock pessimism -0.179 1.046 SLICE_X123Y551 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.102 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[72] ------------------------------------------------------------------- required time -1.102 arrival time 1.150 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_23 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.162ns (logic 0.079ns (48.765%) route 0.083ns (51.235%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.226ns Source Clock Delay (SCD): 1.001ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 0.883ns (routing 0.316ns, distribution 0.567ns) Clock Net Delay (Destination): 1.061ns (routing 0.357ns, distribution 0.704ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.883 1.001 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X123Y548 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X123Y548 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.050 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.067 1.117 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_21_in SLICE_X123Y549 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.030 1.147 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__20/O net (fo=1, routed) 0.016 1.163 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] SLICE_X123Y549 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.061 1.226 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X123Y549 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.168 1.058 SLICE_X123Y549 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.114 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.114 arrival time 1.163 ------------------------------------------------------------------- slack 0.049 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_23 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X1Y220 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y540 g_clock_rate_din[21].ngccm_status_cnt_reg[21][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y540 g_clock_rate_din[21].ngccm_status_cnt_reg[21][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y540 g_clock_rate_din[21].ngccm_status_cnt_reg[21][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y540 g_clock_rate_din[21].ngccm_status_cnt_reg[21][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X77Y540 g_clock_rate_din[21].ngccm_status_cnt_reg[21][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y540 g_clock_rate_din[21].ngccm_status_cnt_reg[21][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X78Y540 g_clock_rate_din[21].ngccm_status_cnt_reg[21][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y540 g_clock_rate_din[21].ngccm_status_cnt_reg[21][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y540 g_clock_rate_din[21].ngccm_status_cnt_reg[21][2]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y540 g_clock_rate_din[21].ngccm_status_cnt_reg[21][5]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y540 g_clock_rate_din[21].ngccm_status_cnt_reg[21][6]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X78Y540 g_clock_rate_din[21].ngccm_status_cnt_reg[21][7]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X116Y541 g_clock_rate_din[21].rx_frameclk_div2_reg[21]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X122Y547 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X122Y547 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[72]/C High Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X122Y542 SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X117Y544 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[19]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X117Y544 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[20]/C High Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X117Y544 SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[22]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.036 0.494 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.017 0.502 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.017 0.865 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.036 1.292 GTHE3_CHANNEL_X1Y37 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_24 To Clock: gtwiz_userclk_rx_srcclk_out[0]_24 Setup : 0 Failing Endpoints, Worst Slack 2.638ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.032ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.638ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.427ns (logic 1.372ns (25.281%) route 4.055ns (74.719%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.302ns = ( 10.619 - 8.317 ) Source Clock Delay (SCD): 2.657ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.232ns (routing 0.714ns, distribution 1.518ns) Clock Net Delay (Destination): 1.926ns (routing 0.646ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.232 2.657 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.741 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.232 5.973 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] SLICE_X46Y146 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.238 6.211 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/O net (fo=5, routed) 1.095 7.306 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X48Y142 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.050 7.356 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/O net (fo=7, routed) 0.728 8.084 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 SLICE_X47Y142 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.619 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK SLICE_X47Y142 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.193 10.813 clock uncertainty -0.035 10.777 SLICE_X47Y142 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 10.722 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.722 arrival time -8.084 ------------------------------------------------------------------- slack 2.638 Slack (MET) : 2.991ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].rx_data_ngccm_reg[24][54]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.264ns (logic 0.359ns (6.820%) route 4.905ns (93.180%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.028ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.609ns = ( 10.926 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.233ns (routing 0.646ns, distribution 1.587ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.465 6.386 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y154 LUT6 (Prop_E6LUT_SLICEL_I0_O) 0.219 6.605 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/O net (fo=76, routed) 1.440 8.045 rx_data_ngccm[24] SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][54]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.926 g_gbt_bank[2].gbtbank_n_0 SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][54]/C clock pessimism 0.200 11.126 clock uncertainty -0.035 11.091 SLICE_X55Y158 FDCE (Setup_AFF2_SLICEM_C_CE) -0.055 11.036 SFP_GEN[24].rx_data_ngccm_reg[24][54] ------------------------------------------------------------------- required time 11.036 arrival time -8.045 ------------------------------------------------------------------- slack 2.991 Slack (MET) : 2.991ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].rx_data_ngccm_reg[24][73]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.264ns (logic 0.359ns (6.820%) route 4.905ns (93.180%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.028ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.609ns = ( 10.926 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.233ns (routing 0.646ns, distribution 1.587ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.465 6.386 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y154 LUT6 (Prop_E6LUT_SLICEL_I0_O) 0.219 6.605 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/O net (fo=76, routed) 1.440 8.045 rx_data_ngccm[24] SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][73]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.926 g_gbt_bank[2].gbtbank_n_0 SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][73]/C clock pessimism 0.200 11.126 clock uncertainty -0.035 11.091 SLICE_X55Y158 FDCE (Setup_BFF2_SLICEM_C_CE) -0.055 11.036 SFP_GEN[24].rx_data_ngccm_reg[24][73] ------------------------------------------------------------------- required time 11.036 arrival time -8.045 ------------------------------------------------------------------- slack 2.991 Slack (MET) : 2.991ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].rx_data_ngccm_reg[24][76]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.264ns (logic 0.359ns (6.820%) route 4.905ns (93.180%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.028ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.609ns = ( 10.926 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.233ns (routing 0.646ns, distribution 1.587ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.465 6.386 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y154 LUT6 (Prop_E6LUT_SLICEL_I0_O) 0.219 6.605 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/O net (fo=76, routed) 1.440 8.045 rx_data_ngccm[24] SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][76]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.926 g_gbt_bank[2].gbtbank_n_0 SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][76]/C clock pessimism 0.200 11.126 clock uncertainty -0.035 11.091 SLICE_X55Y158 FDCE (Setup_CFF2_SLICEM_C_CE) -0.055 11.036 SFP_GEN[24].rx_data_ngccm_reg[24][76] ------------------------------------------------------------------- required time 11.036 arrival time -8.045 ------------------------------------------------------------------- slack 2.991 Slack (MET) : 2.995ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].rx_data_ngccm_reg[24][51]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.261ns (logic 0.359ns (6.824%) route 4.902ns (93.176%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.028ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.609ns = ( 10.926 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.233ns (routing 0.646ns, distribution 1.587ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.465 6.386 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y154 LUT6 (Prop_E6LUT_SLICEL_I0_O) 0.219 6.605 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/O net (fo=76, routed) 1.437 8.042 rx_data_ngccm[24] SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][51]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.926 g_gbt_bank[2].gbtbank_n_0 SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][51]/C clock pessimism 0.200 11.126 clock uncertainty -0.035 11.091 SLICE_X55Y158 FDCE (Setup_AFF_SLICEM_C_CE) -0.054 11.037 SFP_GEN[24].rx_data_ngccm_reg[24][51] ------------------------------------------------------------------- required time 11.037 arrival time -8.042 ------------------------------------------------------------------- slack 2.995 Slack (MET) : 2.995ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].rx_data_ngccm_reg[24][72]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.261ns (logic 0.359ns (6.824%) route 4.902ns (93.176%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.028ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.609ns = ( 10.926 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.233ns (routing 0.646ns, distribution 1.587ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.465 6.386 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y154 LUT6 (Prop_E6LUT_SLICEL_I0_O) 0.219 6.605 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/O net (fo=76, routed) 1.437 8.042 rx_data_ngccm[24] SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][72]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.926 g_gbt_bank[2].gbtbank_n_0 SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][72]/C clock pessimism 0.200 11.126 clock uncertainty -0.035 11.091 SLICE_X55Y158 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 11.037 SFP_GEN[24].rx_data_ngccm_reg[24][72] ------------------------------------------------------------------- required time 11.037 arrival time -8.042 ------------------------------------------------------------------- slack 2.995 Slack (MET) : 2.995ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].rx_data_ngccm_reg[24][74]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.261ns (logic 0.359ns (6.824%) route 4.902ns (93.176%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.028ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.609ns = ( 10.926 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.233ns (routing 0.646ns, distribution 1.587ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.465 6.386 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y154 LUT6 (Prop_E6LUT_SLICEL_I0_O) 0.219 6.605 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/O net (fo=76, routed) 1.437 8.042 rx_data_ngccm[24] SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][74]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.926 g_gbt_bank[2].gbtbank_n_0 SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][74]/C clock pessimism 0.200 11.126 clock uncertainty -0.035 11.091 SLICE_X55Y158 FDCE (Setup_CFF_SLICEM_C_CE) -0.054 11.037 SFP_GEN[24].rx_data_ngccm_reg[24][74] ------------------------------------------------------------------- required time 11.037 arrival time -8.042 ------------------------------------------------------------------- slack 2.995 Slack (MET) : 2.995ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].rx_data_ngccm_reg[24][77]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.261ns (logic 0.359ns (6.824%) route 4.902ns (93.176%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.028ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.609ns = ( 10.926 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.233ns (routing 0.646ns, distribution 1.587ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.465 6.386 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y154 LUT6 (Prop_E6LUT_SLICEL_I0_O) 0.219 6.605 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/O net (fo=76, routed) 1.437 8.042 rx_data_ngccm[24] SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][77]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.926 g_gbt_bank[2].gbtbank_n_0 SLICE_X55Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][77]/C clock pessimism 0.200 11.126 clock uncertainty -0.035 11.091 SLICE_X55Y158 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 11.037 SFP_GEN[24].rx_data_ngccm_reg[24][77] ------------------------------------------------------------------- required time 11.037 arrival time -8.042 ------------------------------------------------------------------- slack 2.995 Slack (MET) : 3.005ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].rx_data_ngccm_reg[24][60]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.244ns (logic 0.359ns (6.846%) route 4.885ns (93.154%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.606ns = ( 10.923 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.230ns (routing 0.646ns, distribution 1.584ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.465 6.386 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y154 LUT6 (Prop_E6LUT_SLICEL_I0_O) 0.219 6.605 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/O net (fo=76, routed) 1.420 8.025 rx_data_ngccm[24] SLICE_X59Y159 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][60]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.230 10.923 g_gbt_bank[2].gbtbank_n_0 SLICE_X59Y159 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][60]/C clock pessimism 0.200 11.123 clock uncertainty -0.035 11.088 SLICE_X59Y159 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 11.030 SFP_GEN[24].rx_data_ngccm_reg[24][60] ------------------------------------------------------------------- required time 11.030 arrival time -8.025 ------------------------------------------------------------------- slack 3.005 Slack (MET) : 3.011ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].rx_data_ngccm_reg[24][44]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 5.241ns (logic 0.359ns (6.850%) route 4.882ns (93.150%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.606ns = ( 10.923 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.230ns (routing 0.646ns, distribution 1.584ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.465 6.386 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y154 LUT6 (Prop_E6LUT_SLICEL_I0_O) 0.219 6.605 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[24].rx_data_ngccm[24][83]_i_1/O net (fo=76, routed) 1.417 8.022 rx_data_ngccm[24] SLICE_X59Y159 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][44]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.230 10.923 g_gbt_bank[2].gbtbank_n_0 SLICE_X59Y159 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][44]/C clock pessimism 0.200 11.123 clock uncertainty -0.035 11.088 SLICE_X59Y159 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 11.033 SFP_GEN[24].rx_data_ngccm_reg[24][44] ------------------------------------------------------------------- required time 11.033 arrival time -8.022 ------------------------------------------------------------------- slack 3.011 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.032ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].rx_data_ngccm_reg[24][46]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.049ns (29.341%) route 0.118ns (70.659%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.312ns Source Clock Delay (SCD): 1.084ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.968ns (routing 0.327ns, distribution 0.641ns) Clock Net Delay (Destination): 1.160ns (routing 0.379ns, distribution 0.781ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.968 1.084 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X57Y158 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y158 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.133 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.118 1.251 rx_data[24][46] SLICE_X58Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][46]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.160 1.312 g_gbt_bank[2].gbtbank_n_0 SLICE_X58Y158 FDCE r SFP_GEN[24].rx_data_ngccm_reg[24][46]/C clock pessimism -0.149 1.163 SLICE_X58Y158 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.219 SFP_GEN[24].rx_data_ngccm_reg[24][46] ------------------------------------------------------------------- required time -1.219 arrival time 1.251 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.319ns Source Clock Delay (SCD): 1.085ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 0.969ns (routing 0.327ns, distribution 0.642ns) Clock Net Delay (Destination): 1.167ns (routing 0.379ns, distribution 0.788ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.969 1.085 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y158 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.134 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.036 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_25_in SLICE_X54Y158 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.215 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__23/O net (fo=1, routed) 0.016 1.231 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[13] SLICE_X54Y158 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.167 1.319 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y158 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.190 1.129 SLICE_X54Y158 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.185 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.185 arrival time 1.231 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.325ns Source Clock Delay (SCD): 1.091ns Clock Pessimism Removal (CPR): 0.192ns Clock Net Delay (Source): 0.975ns (routing 0.327ns, distribution 0.648ns) Clock Net Delay (Destination): 1.173ns (routing 0.379ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.091 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X56Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y158 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.140 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.036 1.176 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in SLICE_X56Y158 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.221 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__23/O net (fo=1, routed) 0.016 1.237 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] SLICE_X56Y158 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.173 1.325 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X56Y158 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.192 1.133 SLICE_X56Y158 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.189 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.189 arrival time 1.237 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.957ns Clock Pessimism Removal (CPR): 0.198ns Clock Net Delay (Source): 0.841ns (routing 0.327ns, distribution 0.514ns) Clock Net Delay (Destination): 1.008ns (routing 0.379ns, distribution 0.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.841 0.957 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/CLK SLICE_X47Y141 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y141 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 1.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Q net (fo=2, routed) 0.033 1.039 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/timer[5] SLICE_X47Y141 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.054 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__24/O net (fo=1, routed) 0.012 1.066 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__24_n_0 SLICE_X47Y141 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.160 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/CLK SLICE_X47Y141 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C clock pessimism -0.198 0.962 SLICE_X47Y141 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.018 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5] ------------------------------------------------------------------- required time -1.018 arrival time 1.066 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.063ns (42.282%) route 0.086ns (57.718%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.305ns Source Clock Delay (SCD): 1.080ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 0.964ns (routing 0.327ns, distribution 0.637ns) Clock Net Delay (Destination): 1.153ns (routing 0.379ns, distribution 0.774ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.964 1.080 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X57Y160 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y160 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.128 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.070 1.198 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X57Y159 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.015 1.213 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__23/O net (fo=1, routed) 0.016 1.229 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X57Y159 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.153 1.305 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X57Y159 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.181 1.124 SLICE_X57Y159 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.180 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.180 arrival time 1.229 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.956ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 0.840ns (routing 0.327ns, distribution 0.513ns) Clock Net Delay (Destination): 1.010ns (routing 0.379ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.840 0.956 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/CLK SLICE_X46Y145 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X46Y145 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.005 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.035 1.040 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/ready_from_bitSlipCtrller_0 SLICE_X46Y145 LUT3 (Prop_A6LUT_SLICEL_I2_O) 0.015 1.055 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_i_1__23/O net (fo=1, routed) 0.012 1.067 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_i_1__23_n_0 SLICE_X46Y145 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.162 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/CLK SLICE_X46Y145 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/C clock pessimism -0.201 0.961 SLICE_X46Y145 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.017 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.017 arrival time 1.067 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.139ns (logic 0.093ns (66.906%) route 0.046ns (33.094%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.312ns Source Clock Delay (SCD): 1.089ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 0.973ns (routing 0.327ns, distribution 0.646ns) Clock Net Delay (Destination): 1.160ns (routing 0.379ns, distribution 0.781ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.973 1.089 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y154 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.137 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.034 1.171 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_5_in SLICE_X60Y154 LUT3 (Prop_F6LUT_SLICEL_I2_O) 0.045 1.216 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__23/O net (fo=1, routed) 0.012 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] SLICE_X60Y154 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.160 1.312 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y154 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.190 1.122 SLICE_X60Y154 FDRE (Hold_FFF_SLICEL_C_D) 0.056 1.178 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.178 arrival time 1.228 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.151ns (logic 0.100ns (66.225%) route 0.051ns (33.775%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.325ns Source Clock Delay (SCD): 1.091ns Clock Pessimism Removal (CPR): 0.192ns Clock Net Delay (Source): 0.975ns (routing 0.327ns, distribution 0.648ns) Clock Net Delay (Destination): 1.173ns (routing 0.379ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.091 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X56Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y158 FDCE (Prop_FFF2_SLICEL_C_Q) 0.048 1.139 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.035 1.174 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in SLICE_X56Y158 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.052 1.226 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__23/O net (fo=1, routed) 0.016 1.242 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] SLICE_X56Y158 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.173 1.325 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X56Y158 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.192 1.133 SLICE_X56Y158 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.189 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.189 arrival time 1.242 ------------------------------------------------------------------- slack 0.053 Slack (MET) : 0.053ns (arrival time - required time) Source: SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[26]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.049ns (33.108%) route 0.099ns (66.892%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.302ns Source Clock Delay (SCD): 1.081ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 0.965ns (routing 0.327ns, distribution 0.638ns) Clock Net Delay (Destination): 1.150ns (routing 0.379ns, distribution 0.771ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.965 1.081 SFP_GEN[24].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y155 FDCE r SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y155 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.130 r SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[26]/Q net (fo=2, routed) 0.099 1.229 SFP_GEN[24].ngCCM_gbt/gbt_rx_checker/Q[10] SLICE_X57Y157 FDRE r SFP_GEN[24].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.150 1.302 SFP_GEN[24].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y157 FDRE r SFP_GEN[24].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/C clock pessimism -0.181 1.121 SLICE_X57Y157 FDRE (Hold_EFF2_SLICEL_C_D) 0.055 1.176 SFP_GEN[24].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10] ------------------------------------------------------------------- required time -1.176 arrival time 1.229 ------------------------------------------------------------------- slack 0.053 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_24 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.094ns (66.197%) route 0.048ns (33.803%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.312ns Source Clock Delay (SCD): 1.089ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 0.973ns (routing 0.327ns, distribution 0.646ns) Clock Net Delay (Destination): 1.160ns (routing 0.379ns, distribution 0.781ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.973 1.089 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y154 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.138 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Q net (fo=2, routed) 0.034 1.172 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_19_in SLICE_X60Y154 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.045 1.217 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__23/O net (fo=1, routed) 0.014 1.231 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[10] SLICE_X60Y154 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.160 1.312 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y154 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.190 1.122 SLICE_X60Y154 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.178 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.178 arrival time 1.231 ------------------------------------------------------------------- slack 0.053 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_24 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y57 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y179 g_clock_rate_din[24].ngccm_status_cnt_reg[24][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X55Y179 g_clock_rate_din[24].ngccm_status_cnt_reg[24][6]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X55Y179 g_clock_rate_din[24].rx_test_comm_cnt_reg[24]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X58Y155 SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[20]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X58Y155 SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[22]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X58Y155 SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[24]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X58Y155 SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[25]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y178 g_clock_rate_din[24].ngccm_status_cnt_reg[24][5]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y8 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_25 To Clock: gtwiz_userclk_rx_srcclk_out[0]_25 Setup : 0 Failing Endpoints, Worst Slack 3.291ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.291ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 5.100ns (logic 1.576ns (30.902%) route 3.524ns (69.098%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.164ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.564ns = ( 10.881 - 8.317 ) Source Clock Delay (SCD): 2.596ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.171ns (routing 0.655ns, distribution 1.516ns) Clock Net Delay (Destination): 2.188ns (routing 0.591ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.171 2.596 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.757 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.577 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X50Y272 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.088 6.422 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.328 6.750 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y269 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33/O net (fo=1, routed) 0.207 7.195 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33_n_0 SLICE_X50Y271 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.089 7.284 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33/O net (fo=2, routed) 0.412 7.696 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33_n_0 SLICE_X50Y272 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.188 10.881 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X50Y272 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.196 11.077 clock uncertainty -0.035 11.042 SLICE_X50Y272 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 10.987 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.987 arrival time -7.696 ------------------------------------------------------------------- slack 3.291 Slack (MET) : 3.291ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 5.100ns (logic 1.576ns (30.902%) route 3.524ns (69.098%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.164ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.564ns = ( 10.881 - 8.317 ) Source Clock Delay (SCD): 2.596ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.171ns (routing 0.655ns, distribution 1.516ns) Clock Net Delay (Destination): 2.188ns (routing 0.591ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.171 2.596 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.757 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.577 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X50Y272 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.088 6.422 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.328 6.750 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y269 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.988 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33/O net (fo=1, routed) 0.207 7.195 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33_n_0 SLICE_X50Y271 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.089 7.284 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33/O net (fo=2, routed) 0.412 7.696 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33_n_0 SLICE_X50Y272 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.188 10.881 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X50Y272 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.196 11.077 clock uncertainty -0.035 11.042 SLICE_X50Y272 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 10.987 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.987 arrival time -7.696 ------------------------------------------------------------------- slack 3.291 Slack (MET) : 3.509ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.890ns (logic 1.300ns (26.585%) route 3.590ns (73.415%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.575ns = ( 10.892 - 8.317 ) Source Clock Delay (SCD): 2.596ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.171ns (routing 0.655ns, distribution 1.516ns) Clock Net Delay (Destination): 2.199ns (routing 0.591ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.171 2.596 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.757 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.577 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X50Y272 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.088 6.422 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.194 6.616 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y270 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 6.667 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/O net (fo=7, routed) 0.819 7.486 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X49Y270 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.199 10.892 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X49Y270 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.196 11.088 clock uncertainty -0.035 11.053 SLICE_X49Y270 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.995 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.995 arrival time -7.486 ------------------------------------------------------------------- slack 3.509 Slack (MET) : 3.515ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.887ns (logic 1.300ns (26.601%) route 3.587ns (73.399%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.575ns = ( 10.892 - 8.317 ) Source Clock Delay (SCD): 2.596ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.171ns (routing 0.655ns, distribution 1.516ns) Clock Net Delay (Destination): 2.199ns (routing 0.591ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.171 2.596 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.757 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.577 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X50Y272 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.088 6.422 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.194 6.616 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y270 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 6.667 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/O net (fo=7, routed) 0.816 7.483 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X49Y270 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.199 10.892 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X49Y270 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.196 11.088 clock uncertainty -0.035 11.053 SLICE_X49Y270 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 10.998 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.998 arrival time -7.483 ------------------------------------------------------------------- slack 3.515 Slack (MET) : 3.515ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.887ns (logic 1.300ns (26.601%) route 3.587ns (73.399%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.575ns = ( 10.892 - 8.317 ) Source Clock Delay (SCD): 2.596ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.171ns (routing 0.655ns, distribution 1.516ns) Clock Net Delay (Destination): 2.199ns (routing 0.591ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.171 2.596 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.757 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.577 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X50Y272 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.088 6.422 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.194 6.616 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y270 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 6.667 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/O net (fo=7, routed) 0.816 7.483 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X49Y270 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.199 10.892 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X49Y270 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.196 11.088 clock uncertainty -0.035 11.053 SLICE_X49Y270 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.998 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.998 arrival time -7.483 ------------------------------------------------------------------- slack 3.515 Slack (MET) : 3.555ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.842ns (logic 1.396ns (28.831%) route 3.446ns (71.169%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.570ns = ( 10.887 - 8.317 ) Source Clock Delay (SCD): 2.596ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.171ns (routing 0.655ns, distribution 1.516ns) Clock Net Delay (Destination): 2.194ns (routing 0.591ns, distribution 1.603ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.171 2.596 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.757 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.577 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X50Y272 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.088 6.422 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.192 6.614 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y270 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.761 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/O net (fo=5, routed) 0.677 7.438 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X50Y269 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.194 10.887 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X50Y269 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.196 11.083 clock uncertainty -0.035 11.048 SLICE_X50Y269 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.993 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 10.993 arrival time -7.438 ------------------------------------------------------------------- slack 3.555 Slack (MET) : 3.572ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.822ns (logic 1.300ns (26.960%) route 3.522ns (73.040%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.570ns = ( 10.887 - 8.317 ) Source Clock Delay (SCD): 2.596ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.171ns (routing 0.655ns, distribution 1.516ns) Clock Net Delay (Destination): 2.194ns (routing 0.591ns, distribution 1.603ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.171 2.596 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.757 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.577 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X50Y272 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.088 6.422 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/O net (fo=5, routed) 0.194 6.616 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y270 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.051 6.667 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/O net (fo=7, routed) 0.751 7.418 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X50Y269 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.194 10.887 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK SLICE_X50Y269 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.196 11.083 clock uncertainty -0.035 11.048 SLICE_X50Y269 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.990 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.990 arrival time -7.418 ------------------------------------------------------------------- slack 3.572 Slack (MET) : 3.597ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[34].rx_data_ngccm_reg[34][18]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.683ns (logic 0.383ns (8.179%) route 4.300ns (91.821%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.216ns (routing 0.591ns, distribution 1.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.830 5.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X52Y273 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.944 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[34].rx_data_ngccm[34][83]_i_1/O net (fo=76, routed) 1.470 7.414 rx_data_ngccm[34] SLICE_X59Y279 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][18]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[2].gbtbank_n_124 SLICE_X59Y279 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][18]/C clock pessimism 0.195 11.104 clock uncertainty -0.035 11.069 SLICE_X59Y279 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 11.011 SFP_GEN[34].rx_data_ngccm_reg[34][18] ------------------------------------------------------------------- required time 11.011 arrival time -7.414 ------------------------------------------------------------------- slack 3.597 Slack (MET) : 3.597ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[34].rx_data_ngccm_reg[34][23]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.683ns (logic 0.383ns (8.179%) route 4.300ns (91.821%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.216ns (routing 0.591ns, distribution 1.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.830 5.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X52Y273 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.944 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[34].rx_data_ngccm[34][83]_i_1/O net (fo=76, routed) 1.470 7.414 rx_data_ngccm[34] SLICE_X59Y279 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][23]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[2].gbtbank_n_124 SLICE_X59Y279 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][23]/C clock pessimism 0.195 11.104 clock uncertainty -0.035 11.069 SLICE_X59Y279 FDCE (Setup_FFF2_SLICEM_C_CE) -0.058 11.011 SFP_GEN[34].rx_data_ngccm_reg[34][23] ------------------------------------------------------------------- required time 11.011 arrival time -7.414 ------------------------------------------------------------------- slack 3.597 Slack (MET) : 3.597ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[34].rx_data_ngccm_reg[34][27]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.683ns (logic 0.383ns (8.179%) route 4.300ns (91.821%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.216ns (routing 0.591ns, distribution 1.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.830 5.700 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X52Y273 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.244 5.944 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[34].rx_data_ngccm[34][83]_i_1/O net (fo=76, routed) 1.470 7.414 rx_data_ngccm[34] SLICE_X59Y279 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][27]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[2].gbtbank_n_124 SLICE_X59Y279 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][27]/C clock pessimism 0.195 11.104 clock uncertainty -0.035 11.069 SLICE_X59Y279 FDCE (Setup_GFF2_SLICEM_C_CE) -0.058 11.011 SFP_GEN[34].rx_data_ngccm_reg[34][27] ------------------------------------------------------------------- required time 11.011 arrival time -7.414 ------------------------------------------------------------------- slack 3.597 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.034ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[60]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[60]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.164ns (logic 0.049ns (29.878%) route 0.115ns (70.122%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.311ns Source Clock Delay (SCD): 1.095ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.979ns (routing 0.297ns, distribution 0.682ns) Clock Net Delay (Destination): 1.159ns (routing 0.343ns, distribution 0.816ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.979 1.095 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X54Y286 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[60]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y286 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.144 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[60]/Q net (fo=1, routed) 0.115 1.259 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[60] SLICE_X56Y286 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[60]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.159 1.311 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X56Y286 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[60]/C clock pessimism -0.142 1.169 SLICE_X56Y286 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.225 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[60] ------------------------------------------------------------------- required time -1.225 arrival time 1.259 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[24]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[24]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.049ns (34.507%) route 0.093ns (65.493%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.085ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 0.969ns (routing 0.297ns, distribution 0.672ns) Clock Net Delay (Destination): 1.157ns (routing 0.343ns, distribution 0.814ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.969 1.085 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X54Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y283 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.134 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[24]/Q net (fo=1, routed) 0.093 1.227 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[24] SLICE_X54Y284 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X54Y284 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[24]/C clock pessimism -0.175 1.134 SLICE_X54Y284 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.190 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[24] ------------------------------------------------------------------- required time -1.190 arrival time 1.227 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.164ns (routing 0.343ns, distribution 0.821ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y275 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.137 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.034 1.171 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_5_in SLICE_X54Y275 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.216 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__33/O net (fo=1, routed) 0.016 1.232 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[1] SLICE_X54Y275 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.164 1.316 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y275 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.186 1.130 SLICE_X54Y275 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.186 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.186 arrival time 1.232 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.164ns (routing 0.343ns, distribution 0.821ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y275 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.137 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.037 1.174 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/O85[0] SLICE_X54Y275 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.045 1.219 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__33/O net (fo=1, routed) 0.015 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] SLICE_X54Y275 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.164 1.316 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y275 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.186 1.130 SLICE_X54Y275 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.186 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.186 arrival time 1.234 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.094ns (50.811%) route 0.091ns (49.189%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.312ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.974ns (routing 0.297ns, distribution 0.677ns) Clock Net Delay (Destination): 1.160ns (routing 0.343ns, distribution 0.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y283 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.139 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.075 1.214 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in SLICE_X58Y283 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.259 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__33/O net (fo=1, routed) 0.016 1.275 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] SLICE_X58Y283 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.160 1.312 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X58Y283 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.142 1.170 SLICE_X58Y283 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.226 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.226 arrival time 1.275 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.048ns (27.273%) route 0.128ns (72.727%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.304ns Source Clock Delay (SCD): 1.091ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.975ns (routing 0.297ns, distribution 0.678ns) Clock Net Delay (Destination): 1.152ns (routing 0.343ns, distribution 0.809ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.091 SFP_GEN[34].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y281 FDCE r SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y281 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.139 r SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]/Q net (fo=1, routed) 0.128 1.267 SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[5] SLICE_X56Y281 FDRE r SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.152 1.304 SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y281 FDRE r SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C clock pessimism -0.142 1.162 SLICE_X56Y281 FDRE (Hold_EFF2_SLICEL_C_D) 0.055 1.217 SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34] ------------------------------------------------------------------- required time -1.217 arrival time 1.267 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[36]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[36]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.049ns (26.923%) route 0.133ns (73.077%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.155ns (routing 0.343ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X54Y284 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[36]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y284 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.137 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[36]/Q net (fo=1, routed) 0.133 1.270 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[36] SLICE_X56Y284 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.155 1.307 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X56Y284 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[36]/C clock pessimism -0.142 1.165 SLICE_X56Y284 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.220 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[36] ------------------------------------------------------------------- required time -1.220 arrival time 1.270 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.320ns Source Clock Delay (SCD): 1.096ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.980ns (routing 0.297ns, distribution 0.683ns) Clock Net Delay (Destination): 1.168ns (routing 0.343ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.096 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y283 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.145 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.034 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_11_in SLICE_X60Y283 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.224 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__33/O net (fo=1, routed) 0.016 1.240 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] SLICE_X60Y283 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.168 1.320 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y283 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.186 1.134 SLICE_X60Y283 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.190 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.190 arrival time 1.240 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[34].rx_data_ngccm_reg[34][49]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.048ns (28.402%) route 0.121ns (71.598%)) Logic Levels: 0 Clock Path Skew: 0.063ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.293ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.141ns (routing 0.343ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X53Y277 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y277 FDRE (Prop_HFF2_SLICEM_C_Q) 0.048 1.136 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.121 1.257 rx_data[34][49] SLICE_X52Y277 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][49]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.141 1.293 g_gbt_bank[2].gbtbank_n_124 SLICE_X52Y277 FDCE r SFP_GEN[34].rx_data_ngccm_reg[34][49]/C clock pessimism -0.142 1.151 SLICE_X52Y277 FDCE (Hold_AFF2_SLICEM_C_D) 0.056 1.207 SFP_GEN[34].rx_data_ngccm_reg[34][49] ------------------------------------------------------------------- required time -1.207 arrival time 1.257 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_25 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.164ns (routing 0.343ns, distribution 0.821ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y275 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y275 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.137 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.034 1.171 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_5_in SLICE_X54Y275 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.055 1.226 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__33/O net (fo=1, routed) 0.011 1.237 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[3] SLICE_X54Y275 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.164 1.316 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y275 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C clock pessimism -0.186 1.130 SLICE_X54Y275 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.186 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3] ------------------------------------------------------------------- required time -1.186 arrival time 1.237 ------------------------------------------------------------------- slack 0.051 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_25 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y99 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y273 g_clock_rate_din[34].ngccm_status_cnt_reg[34][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y273 g_clock_rate_din[34].ngccm_status_cnt_reg[34][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y273 g_clock_rate_din[34].ngccm_status_cnt_reg[34][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y273 g_clock_rate_din[34].ngccm_status_cnt_reg[34][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y272 g_clock_rate_din[34].ngccm_status_cnt_reg[34][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y273 g_clock_rate_din[34].ngccm_status_cnt_reg[34][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y280 g_clock_rate_din[34].ngccm_status_cnt_reg[34][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y252 SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y252 SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[50]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y251 SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y273 SFP_GEN[34].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y273 SFP_GEN[34].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y273 SFP_GEN[34].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y273 g_clock_rate_din[34].ngccm_status_cnt_reg[34][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y273 g_clock_rate_din[34].ngccm_status_cnt_reg[34][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y273 g_clock_rate_din[34].ngccm_status_cnt_reg[34][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y273 g_clock_rate_din[34].ngccm_status_cnt_reg[34][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y272 g_clock_rate_din[34].ngccm_status_cnt_reg[34][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y280 SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y18 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_26 To Clock: gtwiz_userclk_rx_srcclk_out[0]_26 Setup : 0 Failing Endpoints, Worst Slack 3.693ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.693ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.371ns (logic 1.698ns (38.847%) route 2.673ns (61.153%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.288ns = ( 10.605 - 8.317 ) Source Clock Delay (SCD): 2.646ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.221ns (routing 0.702ns, distribution 1.519ns) Clock Net Delay (Destination): 1.912ns (routing 0.634ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.221 2.646 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.730 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.769 5.499 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X39Y293 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 5.743 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.407 6.150 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X40Y294 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 6.373 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34/O net (fo=1, routed) 0.074 6.447 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34_n_0 SLICE_X40Y294 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 6.594 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34/O net (fo=2, routed) 0.423 7.017 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34_n_0 SLICE_X40Y292 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.912 10.605 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X40Y292 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.195 10.800 clock uncertainty -0.035 10.765 SLICE_X40Y292 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 10.710 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.710 arrival time -7.017 ------------------------------------------------------------------- slack 3.693 Slack (MET) : 3.693ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.371ns (logic 1.698ns (38.847%) route 2.673ns (61.153%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.288ns = ( 10.605 - 8.317 ) Source Clock Delay (SCD): 2.646ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.221ns (routing 0.702ns, distribution 1.519ns) Clock Net Delay (Destination): 1.912ns (routing 0.634ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.221 2.646 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.730 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.769 5.499 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X39Y293 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 5.743 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.407 6.150 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X40Y294 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.223 6.373 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34/O net (fo=1, routed) 0.074 6.447 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34_n_0 SLICE_X40Y294 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 6.594 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34/O net (fo=2, routed) 0.423 7.017 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34_n_0 SLICE_X40Y292 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.912 10.605 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X40Y292 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.195 10.800 clock uncertainty -0.035 10.765 SLICE_X40Y292 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 10.710 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.710 arrival time -7.017 ------------------------------------------------------------------- slack 3.693 Slack (MET) : 3.899ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.170ns (logic 1.547ns (37.098%) route 2.623ns (62.902%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.155ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.297ns = ( 10.614 - 8.317 ) Source Clock Delay (SCD): 2.646ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.221ns (routing 0.702ns, distribution 1.519ns) Clock Net Delay (Destination): 1.921ns (routing 0.634ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.221 2.646 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.730 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.769 5.499 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X39Y293 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 5.743 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.274 6.017 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X40Y294 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.219 6.236 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__35/O net (fo=7, routed) 0.580 6.816 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X40Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.921 10.614 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X40Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.194 10.809 clock uncertainty -0.035 10.773 SLICE_X40Y294 FDRE (Setup_EFF2_SLICEL_C_CE) -0.058 10.715 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.715 arrival time -6.816 ------------------------------------------------------------------- slack 3.899 Slack (MET) : 3.906ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.166ns (logic 1.547ns (37.134%) route 2.619ns (62.866%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.155ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.297ns = ( 10.614 - 8.317 ) Source Clock Delay (SCD): 2.646ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.221ns (routing 0.702ns, distribution 1.519ns) Clock Net Delay (Destination): 1.921ns (routing 0.634ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.221 2.646 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.730 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.769 5.499 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X39Y293 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 5.743 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.274 6.017 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X40Y294 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.219 6.236 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__35/O net (fo=7, routed) 0.576 6.812 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X40Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.921 10.614 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X40Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.194 10.809 clock uncertainty -0.035 10.773 SLICE_X40Y294 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 10.718 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.718 arrival time -6.812 ------------------------------------------------------------------- slack 3.906 Slack (MET) : 4.042ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.020ns (logic 1.549ns (38.532%) route 2.471ns (61.468%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.289ns = ( 10.606 - 8.317 ) Source Clock Delay (SCD): 2.646ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.221ns (routing 0.702ns, distribution 1.519ns) Clock Net Delay (Destination): 1.913ns (routing 0.634ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.221 2.646 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.730 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.769 5.499 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X39Y293 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 5.743 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.276 6.019 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X40Y294 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.221 6.240 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/O net (fo=3, routed) 0.426 6.666 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X41Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.913 10.606 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X41Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.195 10.801 clock uncertainty -0.035 10.766 SLICE_X41Y294 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.708 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.708 arrival time -6.666 ------------------------------------------------------------------- slack 4.042 Slack (MET) : 4.048ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.017ns (logic 1.549ns (38.561%) route 2.468ns (61.439%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.289ns = ( 10.606 - 8.317 ) Source Clock Delay (SCD): 2.646ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.221ns (routing 0.702ns, distribution 1.519ns) Clock Net Delay (Destination): 1.913ns (routing 0.634ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.221 2.646 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.730 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.769 5.499 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X39Y293 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 5.743 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.276 6.019 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X40Y294 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.221 6.240 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/O net (fo=3, routed) 0.423 6.663 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X41Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.913 10.606 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X41Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.195 10.801 clock uncertainty -0.035 10.766 SLICE_X41Y294 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.711 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 10.711 arrival time -6.663 ------------------------------------------------------------------- slack 4.048 Slack (MET) : 4.048ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.017ns (logic 1.549ns (38.561%) route 2.468ns (61.439%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.289ns = ( 10.606 - 8.317 ) Source Clock Delay (SCD): 2.646ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.221ns (routing 0.702ns, distribution 1.519ns) Clock Net Delay (Destination): 1.913ns (routing 0.634ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.221 2.646 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.730 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.769 5.499 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X39Y293 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 5.743 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.276 6.019 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X40Y294 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.221 6.240 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/O net (fo=3, routed) 0.423 6.663 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 SLICE_X41Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.913 10.606 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X41Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.195 10.801 clock uncertainty -0.035 10.766 SLICE_X41Y294 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 10.711 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 10.711 arrival time -6.663 ------------------------------------------------------------------- slack 4.048 Slack (MET) : 4.063ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.010ns (logic 1.480ns (36.908%) route 2.530ns (63.092%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.298ns = ( 10.615 - 8.317 ) Source Clock Delay (SCD): 2.646ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.221ns (routing 0.702ns, distribution 1.519ns) Clock Net Delay (Destination): 1.922ns (routing 0.634ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.221 2.646 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.730 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.769 5.499 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X39Y293 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 5.743 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.172 5.915 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X39Y294 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 6.067 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/O net (fo=5, routed) 0.589 6.656 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X39Y297 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.922 10.615 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X39Y297 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.194 10.810 clock uncertainty -0.035 10.774 SLICE_X39Y297 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 10.719 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 10.719 arrival time -6.656 ------------------------------------------------------------------- slack 4.063 Slack (MET) : 4.067ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.007ns (logic 1.480ns (36.935%) route 2.527ns (63.065%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.299ns = ( 10.616 - 8.317 ) Source Clock Delay (SCD): 2.646ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.221ns (routing 0.702ns, distribution 1.519ns) Clock Net Delay (Destination): 1.923ns (routing 0.634ns, distribution 1.289ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.221 2.646 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.730 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.769 5.499 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X39Y293 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 5.743 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.172 5.915 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X39Y294 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 6.067 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/O net (fo=5, routed) 0.586 6.653 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X40Y297 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.923 10.616 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X40Y297 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.194 10.811 clock uncertainty -0.035 10.775 SLICE_X40Y297 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.720 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 10.720 arrival time -6.653 ------------------------------------------------------------------- slack 4.067 Slack (MET) : 4.067ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 4.007ns (logic 1.480ns (36.935%) route 2.527ns (63.065%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.298ns = ( 10.615 - 8.317 ) Source Clock Delay (SCD): 2.646ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.221ns (routing 0.702ns, distribution 1.519ns) Clock Net Delay (Destination): 1.922ns (routing 0.634ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.221 2.646 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.730 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.769 5.499 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X39Y293 LUT4 (Prop_D6LUT_SLICEM_I3_O) 0.244 5.743 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/O net (fo=5, routed) 0.172 5.915 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X39Y294 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 6.067 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/O net (fo=5, routed) 0.586 6.653 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 SLICE_X39Y297 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.922 10.615 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X39Y297 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.194 10.810 clock uncertainty -0.035 10.774 SLICE_X39Y297 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 10.720 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 10.720 arrival time -6.653 ------------------------------------------------------------------- slack 4.067 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.078ns (43.094%) route 0.103ns (56.906%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.187ns Source Clock Delay (SCD): 0.968ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.852ns (routing 0.323ns, distribution 0.529ns) Clock Net Delay (Destination): 1.035ns (routing 0.374ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.968 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X45Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y288 FDCE (Prop_CFF2_SLICEL_C_Q) 0.048 1.016 f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Q net (fo=28, routed) 0.087 1.103 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] SLICE_X43Y288 LUT5 (Prop_D6LUT_SLICEL_I0_O) 0.030 1.133 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[25]_i_1__26/O net (fo=1, routed) 0.016 1.149 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[25] SLICE_X43Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.035 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X43Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]/C clock pessimism -0.130 1.057 SLICE_X43Y288 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.113 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25] ------------------------------------------------------------------- required time -1.113 arrival time 1.149 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.078ns (42.857%) route 0.104ns (57.143%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.187ns Source Clock Delay (SCD): 0.968ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.852ns (routing 0.323ns, distribution 0.529ns) Clock Net Delay (Destination): 1.035ns (routing 0.374ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.968 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X45Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y288 FDCE (Prop_CFF2_SLICEL_C_Q) 0.048 1.016 f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Q net (fo=28, routed) 0.088 1.104 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] SLICE_X43Y288 LUT5 (Prop_C6LUT_SLICEL_I0_O) 0.030 1.134 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[26]_i_1__26/O net (fo=1, routed) 0.016 1.150 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[26] SLICE_X43Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.035 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X43Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/C clock pessimism -0.130 1.057 SLICE_X43Y288 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.113 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26] ------------------------------------------------------------------- required time -1.113 arrival time 1.150 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.079ns (47.305%) route 0.088ns (52.695%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.845ns (routing 0.323ns, distribution 0.522ns) Clock Net Delay (Destination): 1.008ns (routing 0.374ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X41Y281 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y281 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.074 1.084 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O84[1] SLICE_X40Y281 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.030 1.114 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__34/O net (fo=1, routed) 0.014 1.128 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] SLICE_X40Y281 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.160 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X40Y281 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.130 1.030 SLICE_X40Y281 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.086 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.086 arrival time 1.128 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].rx_data_ngccm_reg[35][38]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.308ns Source Clock Delay (SCD): 1.086ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.970ns (routing 0.323ns, distribution 0.647ns) Clock Net Delay (Destination): 1.156ns (routing 0.374ns, distribution 0.782ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.970 1.086 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X48Y289 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y289 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.134 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/Q net (fo=1, routed) 0.095 1.229 rx_data[35][38] SLICE_X48Y287 FDCE r SFP_GEN[35].rx_data_ngccm_reg[35][38]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.308 g_gbt_bank[2].gbtbank_n_134 SLICE_X48Y287 FDCE r SFP_GEN[35].rx_data_ngccm_reg[35][38]/C clock pessimism -0.178 1.130 SLICE_X48Y287 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.186 SFP_GEN[35].rx_data_ngccm_reg[35][38] ------------------------------------------------------------------- required time -1.186 arrival time 1.229 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: SFP_GEN[35].rx_data_ngccm_reg[35][49]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[48]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.094ns (50.538%) route 0.092ns (49.462%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.176ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.845ns (routing 0.323ns, distribution 0.522ns) Clock Net Delay (Destination): 1.024ns (routing 0.374ns, distribution 0.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[2].gbtbank_n_134 SLICE_X45Y278 FDCE r SFP_GEN[35].rx_data_ngccm_reg[35][49]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y278 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.010 r SFP_GEN[35].rx_data_ngccm_reg[35][49]/Q net (fo=1, routed) 0.076 1.086 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[83]_0[41] SLICE_X43Y278 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.045 1.131 r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40[48]_i_1/O net (fo=1, routed) 0.016 1.147 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40[48]_i_1_n_0 SLICE_X43Y278 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[48]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.176 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y278 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[48]/C clock pessimism -0.130 1.046 SLICE_X43Y278 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.102 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[48] ------------------------------------------------------------------- required time -1.102 arrival time 1.147 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.063ns (42.857%) route 0.084ns (57.143%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.086ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.970ns (routing 0.323ns, distribution 0.647ns) Clock Net Delay (Destination): 1.157ns (routing 0.374ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.970 1.086 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X48Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y288 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.134 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.069 1.203 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O83[0] SLICE_X48Y289 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.015 1.218 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__34/O net (fo=1, routed) 0.015 1.233 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/I7[0] SLICE_X48Y289 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X48Y289 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.178 1.131 SLICE_X48Y289 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.187 arrival time 1.233 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.161ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.195ns Clock Net Delay (Source): 0.845ns (routing 0.323ns, distribution 0.522ns) Clock Net Delay (Destination): 1.009ns (routing 0.374ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/CLK SLICE_X37Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y294 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 1.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Q net (fo=2, routed) 0.033 1.043 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/timer[5] SLICE_X37Y294 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.058 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__35/O net (fo=1, routed) 0.012 1.070 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__35_n_0 SLICE_X37Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.161 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/CLK SLICE_X37Y294 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C clock pessimism -0.195 0.966 SLICE_X37Y294 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].rxBitSlipControl/clkSlipProcess.timer_reg[5] ------------------------------------------------------------------- required time -1.022 arrival time 1.070 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[35]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.195ns (logic 0.064ns (32.821%) route 0.131ns (67.179%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.188ns Source Clock Delay (SCD): 0.968ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.852ns (routing 0.323ns, distribution 0.529ns) Clock Net Delay (Destination): 1.036ns (routing 0.374ns, distribution 0.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.968 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X45Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y288 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.017 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/Q net (fo=29, routed) 0.119 1.136 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] SLICE_X42Y288 LUT5 (Prop_A6LUT_SLICEM_I2_O) 0.015 1.151 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[35]_i_1__26/O net (fo=1, routed) 0.012 1.163 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[35] SLICE_X42Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[35]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.036 1.188 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X42Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[35]/C clock pessimism -0.130 1.058 SLICE_X42Y288 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.114 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[35] ------------------------------------------------------------------- required time -1.114 arrival time 1.163 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.088ns (50.575%) route 0.086ns (49.425%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.845ns (routing 0.323ns, distribution 0.522ns) Clock Net Delay (Destination): 1.008ns (routing 0.374ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X41Y281 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y281 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.074 1.084 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[1] SLICE_X40Y281 LUT3 (Prop_H5LUT_SLICEL_I2_O) 0.039 1.123 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__34/O net (fo=1, routed) 0.012 1.135 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[18] SLICE_X40Y281 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.160 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X40Y281 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.130 1.030 SLICE_X40Y281 FDRE (Hold_HFF2_SLICEL_C_D) 0.056 1.086 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -1.086 arrival time 1.135 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: SFP_GEN[35].rx_data_ngccm_reg[35][65]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[64]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_26 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.095ns (64.626%) route 0.052ns (35.374%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.180ns Source Clock Delay (SCD): 0.968ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.852ns (routing 0.323ns, distribution 0.529ns) Clock Net Delay (Destination): 1.028ns (routing 0.374ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.968 g_gbt_bank[2].gbtbank_n_134 SLICE_X42Y278 FDCE r SFP_GEN[35].rx_data_ngccm_reg[35][65]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y278 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.017 r SFP_GEN[35].rx_data_ngccm_reg[35][65]/Q net (fo=1, routed) 0.036 1.053 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[83]_0[57] SLICE_X42Y278 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.046 1.099 r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40[64]_i_1/O net (fo=1, routed) 0.016 1.115 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40[64]_i_1_n_0 SLICE_X42Y278 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[64]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.028 1.180 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y278 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[64]/C clock pessimism -0.171 1.009 SLICE_X42Y278 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.065 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[64] ------------------------------------------------------------------- required time -1.065 arrival time 1.115 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_26 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y105 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y273 g_clock_rate_din[35].ngccm_status_cnt_reg[35][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y273 g_clock_rate_din[35].ngccm_status_cnt_reg[35][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y273 g_clock_rate_din[35].ngccm_status_cnt_reg[35][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y273 g_clock_rate_din[35].ngccm_status_cnt_reg[35][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y274 g_clock_rate_din[35].ngccm_status_cnt_reg[35][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y273 g_clock_rate_din[35].ngccm_status_cnt_reg[35][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y282 g_clock_rate_din[35].ngccm_status_cnt_reg[35][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X45Y287 SFP_GEN[35].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X45Y287 SFP_GEN[35].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X41Y291 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X41Y291 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X41Y291 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X41Y291 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][3]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y273 g_clock_rate_din[35].ngccm_status_cnt_reg[35][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y273 g_clock_rate_din[35].ngccm_status_cnt_reg[35][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y273 g_clock_rate_din[35].ngccm_status_cnt_reg[35][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y273 g_clock_rate_din[35].ngccm_status_cnt_reg[35][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y274 g_clock_rate_din[35].ngccm_status_cnt_reg[35][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y273 g_clock_rate_din[35].ngccm_status_cnt_reg[35][5]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y19 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_27 To Clock: gtwiz_userclk_rx_srcclk_out[0]_27 Setup : 0 Failing Endpoints, Worst Slack 3.441ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.441ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][25]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 4.816ns (logic 0.385ns (7.994%) route 4.431ns (92.006%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 2.203ns (routing 0.603ns, distribution 1.600ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.567 5.446 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X44Y167 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.246 5.692 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/O net (fo=76, routed) 1.864 7.556 rx_data_ngccm[25] SLICE_X48Y167 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][25]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[2].gbtbank_n_34 SLICE_X48Y167 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][25]/C clock pessimism 0.194 11.090 clock uncertainty -0.035 11.055 SLICE_X48Y167 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 10.997 SFP_GEN[25].rx_data_ngccm_reg[25][25] ------------------------------------------------------------------- required time 10.997 arrival time -7.556 ------------------------------------------------------------------- slack 3.441 Slack (MET) : 3.447ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][19]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 4.813ns (logic 0.385ns (7.999%) route 4.428ns (92.001%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 2.203ns (routing 0.603ns, distribution 1.600ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.567 5.446 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X44Y167 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.246 5.692 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/O net (fo=76, routed) 1.861 7.553 rx_data_ngccm[25] SLICE_X48Y167 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][19]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[2].gbtbank_n_34 SLICE_X48Y167 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][19]/C clock pessimism 0.194 11.090 clock uncertainty -0.035 11.055 SLICE_X48Y167 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 11.000 SFP_GEN[25].rx_data_ngccm_reg[25][19] ------------------------------------------------------------------- required time 11.000 arrival time -7.553 ------------------------------------------------------------------- slack 3.447 Slack (MET) : 3.447ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][34]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 4.813ns (logic 0.385ns (7.999%) route 4.428ns (92.001%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 2.203ns (routing 0.603ns, distribution 1.600ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.567 5.446 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X44Y167 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.246 5.692 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/O net (fo=76, routed) 1.861 7.553 rx_data_ngccm[25] SLICE_X48Y167 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][34]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[2].gbtbank_n_34 SLICE_X48Y167 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][34]/C clock pessimism 0.194 11.090 clock uncertainty -0.035 11.055 SLICE_X48Y167 FDCE (Setup_FFF_SLICEL_C_CE) -0.055 11.000 SFP_GEN[25].rx_data_ngccm_reg[25][34] ------------------------------------------------------------------- required time 11.000 arrival time -7.553 ------------------------------------------------------------------- slack 3.447 Slack (MET) : 3.481ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 4.670ns (logic 1.562ns (33.448%) route 3.108ns (66.552%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.077ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.320ns = ( 10.637 - 8.317 ) Source Clock Delay (SCD): 2.584ns Clock Pessimism Removal (CPR): 0.187ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.159ns (routing 0.667ns, distribution 1.492ns) Clock Net Delay (Destination): 1.944ns (routing 0.603ns, distribution 1.341ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.159 2.584 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.668 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.396 6.064 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X38Y161 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.146 6.210 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/O net (fo=5, routed) 0.271 6.481 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X38Y160 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.165 6.646 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24/O net (fo=1, routed) 0.078 6.724 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24_n_0 SLICE_X38Y160 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.167 6.891 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24/O net (fo=2, routed) 0.363 7.254 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24_n_0 SLICE_X39Y163 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.944 10.637 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X39Y163 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.187 10.824 clock uncertainty -0.035 10.789 SLICE_X39Y163 FDCE (Setup_CFF_SLICEM_C_CE) -0.054 10.735 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.735 arrival time -7.254 ------------------------------------------------------------------- slack 3.481 Slack (MET) : 3.481ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 4.670ns (logic 1.562ns (33.448%) route 3.108ns (66.552%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.077ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.320ns = ( 10.637 - 8.317 ) Source Clock Delay (SCD): 2.584ns Clock Pessimism Removal (CPR): 0.187ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.159ns (routing 0.667ns, distribution 1.492ns) Clock Net Delay (Destination): 1.944ns (routing 0.603ns, distribution 1.341ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.159 2.584 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.668 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 2.396 6.064 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X38Y161 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.146 6.210 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/O net (fo=5, routed) 0.271 6.481 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X38Y160 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.165 6.646 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24/O net (fo=1, routed) 0.078 6.724 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24_n_0 SLICE_X38Y160 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.167 6.891 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24/O net (fo=2, routed) 0.363 7.254 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24_n_0 SLICE_X39Y163 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.944 10.637 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X39Y163 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.187 10.824 clock uncertainty -0.035 10.789 SLICE_X39Y163 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 10.735 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.735 arrival time -7.254 ------------------------------------------------------------------- slack 3.481 Slack (MET) : 3.584ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][32]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 4.669ns (logic 0.385ns (8.246%) route 4.284ns (91.754%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.029ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.575ns = ( 10.892 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 2.199ns (routing 0.603ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.567 5.446 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X44Y167 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.246 5.692 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/O net (fo=76, routed) 1.717 7.409 rx_data_ngccm[25] SLICE_X49Y166 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][32]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.199 10.892 g_gbt_bank[2].gbtbank_n_34 SLICE_X49Y166 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][32]/C clock pessimism 0.194 11.086 clock uncertainty -0.035 11.051 SLICE_X49Y166 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 10.993 SFP_GEN[25].rx_data_ngccm_reg[25][32] ------------------------------------------------------------------- required time 10.993 arrival time -7.409 ------------------------------------------------------------------- slack 3.584 Slack (MET) : 3.590ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][28]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 4.666ns (logic 0.385ns (8.251%) route 4.281ns (91.749%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.029ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.575ns = ( 10.892 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 2.199ns (routing 0.603ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.567 5.446 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X44Y167 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.246 5.692 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/O net (fo=76, routed) 1.714 7.406 rx_data_ngccm[25] SLICE_X49Y166 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][28]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.199 10.892 g_gbt_bank[2].gbtbank_n_34 SLICE_X49Y166 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][28]/C clock pessimism 0.194 11.086 clock uncertainty -0.035 11.051 SLICE_X49Y166 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 10.996 SFP_GEN[25].rx_data_ngccm_reg[25][28] ------------------------------------------------------------------- required time 10.996 arrival time -7.406 ------------------------------------------------------------------- slack 3.590 Slack (MET) : 3.590ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][35]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 4.666ns (logic 0.385ns (8.251%) route 4.281ns (91.749%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.029ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.575ns = ( 10.892 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 2.199ns (routing 0.603ns, distribution 1.596ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.567 5.446 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X44Y167 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.246 5.692 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/O net (fo=76, routed) 1.714 7.406 rx_data_ngccm[25] SLICE_X49Y166 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][35]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.199 10.892 g_gbt_bank[2].gbtbank_n_34 SLICE_X49Y166 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][35]/C clock pessimism 0.194 11.086 clock uncertainty -0.035 11.051 SLICE_X49Y166 FDCE (Setup_FFF_SLICEM_C_CE) -0.055 10.996 SFP_GEN[25].rx_data_ngccm_reg[25][35] ------------------------------------------------------------------- required time 10.996 arrival time -7.406 ------------------------------------------------------------------- slack 3.590 Slack (MET) : 3.602ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][26]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 4.663ns (logic 0.385ns (8.256%) route 4.278ns (91.744%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.041ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.587ns = ( 10.904 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 2.211ns (routing 0.603ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.567 5.446 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X44Y167 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.246 5.692 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/O net (fo=76, routed) 1.711 7.403 rx_data_ngccm[25] SLICE_X48Y166 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][26]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.211 10.904 g_gbt_bank[2].gbtbank_n_34 SLICE_X48Y166 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][26]/C clock pessimism 0.194 11.098 clock uncertainty -0.035 11.063 SLICE_X48Y166 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 11.005 SFP_GEN[25].rx_data_ngccm_reg[25][26] ------------------------------------------------------------------- required time 11.005 arrival time -7.403 ------------------------------------------------------------------- slack 3.602 Slack (MET) : 3.602ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][37]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 4.663ns (logic 0.385ns (8.256%) route 4.278ns (91.744%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.041ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.587ns = ( 10.904 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 2.211ns (routing 0.603ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.567 5.446 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X44Y167 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.246 5.692 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[25].rx_data_ngccm[25][83]_i_1/O net (fo=76, routed) 1.711 7.403 rx_data_ngccm[25] SLICE_X48Y166 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][37]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.211 10.904 g_gbt_bank[2].gbtbank_n_34 SLICE_X48Y166 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][37]/C clock pessimism 0.194 11.098 clock uncertainty -0.035 11.063 SLICE_X48Y166 FDCE (Setup_FFF2_SLICEL_C_CE) -0.058 11.005 SFP_GEN[25].rx_data_ngccm_reg[25][37] ------------------------------------------------------------------- required time 11.005 arrival time -7.403 ------------------------------------------------------------------- slack 3.602 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][68]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.048ns (30.189%) route 0.111ns (69.811%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.170ns Source Clock Delay (SCD): 0.977ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.861ns (routing 0.301ns, distribution 0.560ns) Clock Net Delay (Destination): 1.018ns (routing 0.348ns, distribution 0.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.861 0.977 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X40Y171 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y171 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.025 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.111 1.136 rx_data[25][68] SLICE_X41Y171 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][68]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.170 g_gbt_bank[2].gbtbank_n_34 SLICE_X41Y171 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][68]/C clock pessimism -0.125 1.045 SLICE_X41Y171 FDCE (Hold_FFF2_SLICEM_C_D) 0.055 1.100 SFP_GEN[25].rx_data_ngccm_reg[25][68] ------------------------------------------------------------------- required time -1.100 arrival time 1.136 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][75]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.049ns (29.341%) route 0.118ns (70.659%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.172ns Source Clock Delay (SCD): 0.976ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.860ns (routing 0.301ns, distribution 0.559ns) Clock Net Delay (Destination): 1.020ns (routing 0.348ns, distribution 0.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.860 0.976 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X40Y170 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y170 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.025 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/Q net (fo=1, routed) 0.118 1.143 rx_data[25][75] SLICE_X41Y170 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][75]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.172 g_gbt_bank[2].gbtbank_n_34 SLICE_X41Y170 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][75]/C clock pessimism -0.125 1.047 SLICE_X41Y170 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.103 SFP_GEN[25].rx_data_ngccm_reg[25][75] ------------------------------------------------------------------- required time -1.103 arrival time 1.143 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].rx_data_ngccm_reg[25][49]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.179ns (logic 0.049ns (27.374%) route 0.130ns (72.626%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.968ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.852ns (routing 0.301ns, distribution 0.551ns) Clock Net Delay (Destination): 1.021ns (routing 0.348ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.968 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X41Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y169 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 1.017 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.130 1.147 rx_data[25][49] SLICE_X42Y169 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][49]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.173 g_gbt_bank[2].gbtbank_n_34 SLICE_X42Y169 FDCE r SFP_GEN[25].rx_data_ngccm_reg[25][49]/C clock pessimism -0.125 1.048 SLICE_X42Y169 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.104 SFP_GEN[25].rx_data_ngccm_reg[25][49] ------------------------------------------------------------------- required time -1.104 arrival time 1.147 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.101ns (52.604%) route 0.091ns (47.396%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.185ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.853ns (routing 0.301ns, distribution 0.552ns) Clock Net Delay (Destination): 1.033ns (routing 0.348ns, distribution 0.685ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X41Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y171 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.017 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.077 1.094 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in SLICE_X40Y171 LUT3 (Prop_G6LUT_SLICEL_I2_O) 0.053 1.147 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__24/O net (fo=1, routed) 0.014 1.161 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X40Y171 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.033 1.185 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X40Y171 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.125 1.060 SLICE_X40Y171 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.116 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.116 arrival time 1.161 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.101ns (52.332%) route 0.092ns (47.668%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.185ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.853ns (routing 0.301ns, distribution 0.552ns) Clock Net Delay (Destination): 1.033ns (routing 0.348ns, distribution 0.685ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X41Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y171 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.018 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.076 1.094 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_29_in SLICE_X40Y171 LUT3 (Prop_H6LUT_SLICEL_I2_O) 0.052 1.146 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__24/O net (fo=1, routed) 0.016 1.162 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[13] SLICE_X40Y171 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.033 1.185 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X40Y171 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.125 1.060 SLICE_X40Y171 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.116 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.116 arrival time 1.162 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.165ns Source Clock Delay (SCD): 0.963ns Clock Pessimism Removal (CPR): 0.197ns Clock Net Delay (Source): 0.847ns (routing 0.301ns, distribution 0.546ns) Clock Net Delay (Destination): 1.013ns (routing 0.348ns, distribution 0.665ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.847 0.963 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X37Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y169 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 1.012 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/Q net (fo=2, routed) 0.033 1.045 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[4] SLICE_X37Y169 LUT6 (Prop_A6LUT_SLICEM_I5_O) 0.015 1.060 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__25/O net (fo=1, routed) 0.012 1.072 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__25_n_0 SLICE_X37Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.013 1.165 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X37Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism -0.197 0.968 SLICE_X37Y169 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.024 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time -1.024 arrival time 1.072 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[35]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.049ns (32.026%) route 0.104ns (67.974%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.177ns Source Clock Delay (SCD): 0.968ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.852ns (routing 0.301ns, distribution 0.551ns) Clock Net Delay (Destination): 1.025ns (routing 0.348ns, distribution 0.677ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.968 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X42Y163 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y163 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.017 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]/Q net (fo=1, routed) 0.104 1.121 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[35] SLICE_X42Y165 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.177 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X42Y165 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[35]/C clock pessimism -0.159 1.018 SLICE_X42Y165 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.073 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[35] ------------------------------------------------------------------- required time -1.073 arrival time 1.121 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.168ns (logic 0.049ns (29.167%) route 0.119ns (70.833%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.161ns Source Clock Delay (SCD): 0.972ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.856ns (routing 0.301ns, distribution 0.555ns) Clock Net Delay (Destination): 1.009ns (routing 0.348ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.856 0.972 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X43Y165 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y165 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.021 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q net (fo=137, routed) 0.119 1.140 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/Q[0] SLICE_X44Y164 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.161 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X44Y164 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism -0.125 1.036 SLICE_X44Y164 FDCE (Hold_EFF_SLICEM_C_D) 0.056 1.092 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time -1.092 arrival time 1.140 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[29]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.049ns (33.562%) route 0.097ns (66.438%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.303ns Source Clock Delay (SCD): 1.085ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.969ns (routing 0.301ns, distribution 0.668ns) Clock Net Delay (Destination): 1.151ns (routing 0.348ns, distribution 0.803ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.969 1.085 SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y168 FDCE r SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[29]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y168 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.134 r SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[29]/Q net (fo=2, routed) 0.097 1.231 SFP_GEN[25].ngCCM_gbt/gbt_rx_checker/Q[13] SLICE_X48Y169 FDRE r SFP_GEN[25].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.151 1.303 SFP_GEN[25].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y169 FDRE r SFP_GEN[25].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/C clock pessimism -0.176 1.127 SLICE_X48Y169 FDRE (Hold_EFF2_SLICEL_C_D) 0.055 1.182 SFP_GEN[25].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13] ------------------------------------------------------------------- required time -1.182 arrival time 1.231 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_27 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.203ns Clock Net Delay (Source): 0.845ns (routing 0.301ns, distribution 0.544ns) Clock Net Delay (Destination): 1.017ns (routing 0.348ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/CLK SLICE_X38Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X38Y161 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.035 1.045 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/ready_from_bitSlipCtrller_1 SLICE_X38Y161 LUT3 (Prop_A6LUT_SLICEL_I2_O) 0.015 1.060 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_i_1__24/O net (fo=1, routed) 0.012 1.072 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_i_1__24_n_0 SLICE_X38Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/CLK SLICE_X38Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg/C clock pessimism -0.203 0.966 SLICE_X38Y161 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.022 arrival time 1.072 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_27 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y51 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y177 g_clock_rate_din[25].ngccm_status_cnt_reg[25][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y177 g_clock_rate_din[25].ngccm_status_cnt_reg[25][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y177 g_clock_rate_din[25].ngccm_status_cnt_reg[25][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y177 g_clock_rate_din[25].ngccm_status_cnt_reg[25][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y177 g_clock_rate_din[25].ngccm_status_cnt_reg[25][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y177 g_clock_rate_din[25].ngccm_status_cnt_reg[25][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X52Y178 g_clock_rate_din[25].ngccm_status_cnt_reg[25][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y178 g_clock_rate_din[25].ngccm_status_cnt_reg[25][6]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y178 g_clock_rate_din[25].rx_test_comm_cnt_reg[25]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y162 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y162 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y162 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y162 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][3]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y162 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y162 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y162 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y162 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y162 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y163 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y9 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_28 To Clock: gtwiz_userclk_rx_srcclk_out[0]_28 Setup : 0 Failing Endpoints, Worst Slack 3.366ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.366ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 4.720ns (logic 1.643ns (34.809%) route 3.077ns (65.191%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.296ns = ( 10.613 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.699ns, distribution 1.502ns) Clock Net Delay (Destination): 1.920ns (routing 0.636ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.787 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.032 5.819 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X38Y153 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.057 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/O net (fo=5, routed) 0.389 6.446 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X37Y152 LUT4 (Prop_D5LUT_SLICEM_I2_O) 0.193 6.639 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__25/O net (fo=1, routed) 0.217 6.856 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__25_n_0 SLICE_X37Y152 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.051 6.907 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__25/O net (fo=2, routed) 0.439 7.346 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__25_n_0 SLICE_X37Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.920 10.613 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X37Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.189 10.802 clock uncertainty -0.035 10.766 SLICE_X37Y153 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 10.712 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.712 arrival time -7.346 ------------------------------------------------------------------- slack 3.366 Slack (MET) : 3.366ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 4.720ns (logic 1.643ns (34.809%) route 3.077ns (65.191%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.296ns = ( 10.613 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.699ns, distribution 1.502ns) Clock Net Delay (Destination): 1.920ns (routing 0.636ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.787 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.032 5.819 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X38Y153 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.057 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/O net (fo=5, routed) 0.389 6.446 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X37Y152 LUT4 (Prop_D5LUT_SLICEM_I2_O) 0.193 6.639 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__25/O net (fo=1, routed) 0.217 6.856 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__25_n_0 SLICE_X37Y152 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.051 6.907 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__25/O net (fo=2, routed) 0.439 7.346 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__25_n_0 SLICE_X37Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.920 10.613 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X37Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.189 10.802 clock uncertainty -0.035 10.766 SLICE_X37Y153 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 10.712 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.712 arrival time -7.346 ------------------------------------------------------------------- slack 3.366 Slack (MET) : 3.528ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 4.541ns (logic 1.625ns (35.785%) route 2.916ns (64.215%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.158ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.279ns = ( 10.596 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.699ns, distribution 1.502ns) Clock Net Delay (Destination): 1.903ns (routing 0.636ns, distribution 1.267ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.787 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.032 5.819 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X38Y153 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.057 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/O net (fo=5, routed) 0.277 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X37Y152 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.560 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/O net (fo=7, routed) 0.607 7.167 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X39Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.903 10.596 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X39Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.189 10.785 clock uncertainty -0.035 10.750 SLICE_X39Y152 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 10.695 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.695 arrival time -7.167 ------------------------------------------------------------------- slack 3.528 Slack (MET) : 3.532ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 4.538ns (logic 1.625ns (35.809%) route 2.913ns (64.191%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.158ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.279ns = ( 10.596 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.699ns, distribution 1.502ns) Clock Net Delay (Destination): 1.903ns (routing 0.636ns, distribution 1.267ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.787 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.032 5.819 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X38Y153 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.057 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/O net (fo=5, routed) 0.277 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X37Y152 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.560 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/O net (fo=7, routed) 0.604 7.164 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X39Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.903 10.596 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X39Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.189 10.785 clock uncertainty -0.035 10.750 SLICE_X39Y152 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 10.696 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.696 arrival time -7.164 ------------------------------------------------------------------- slack 3.532 Slack (MET) : 3.532ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 4.538ns (logic 1.625ns (35.809%) route 2.913ns (64.191%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.158ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.279ns = ( 10.596 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.699ns, distribution 1.502ns) Clock Net Delay (Destination): 1.903ns (routing 0.636ns, distribution 1.267ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.787 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.032 5.819 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X38Y153 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.057 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/O net (fo=5, routed) 0.277 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X37Y152 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.560 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/O net (fo=7, routed) 0.604 7.164 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X39Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.903 10.596 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X39Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.189 10.785 clock uncertainty -0.035 10.750 SLICE_X39Y152 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 10.696 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.696 arrival time -7.164 ------------------------------------------------------------------- slack 3.532 Slack (MET) : 3.571ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 4.506ns (logic 1.625ns (36.063%) route 2.881ns (63.937%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.287ns = ( 10.604 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.699ns, distribution 1.502ns) Clock Net Delay (Destination): 1.911ns (routing 0.636ns, distribution 1.275ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.787 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.032 5.819 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X38Y153 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.057 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/O net (fo=5, routed) 0.277 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X37Y152 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.560 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/O net (fo=7, routed) 0.572 7.132 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X37Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.911 10.604 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X37Y152 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.189 10.793 clock uncertainty -0.035 10.758 SLICE_X37Y152 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 10.703 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.703 arrival time -7.132 ------------------------------------------------------------------- slack 3.571 Slack (MET) : 3.618ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 4.461ns (logic 1.625ns (36.427%) route 2.836ns (63.573%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.289ns = ( 10.606 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.699ns, distribution 1.502ns) Clock Net Delay (Destination): 1.913ns (routing 0.636ns, distribution 1.277ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.787 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.032 5.819 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X38Y153 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.057 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/O net (fo=5, routed) 0.277 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X37Y152 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.560 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/O net (fo=7, routed) 0.527 7.087 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X39Y153 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.913 10.606 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X39Y153 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.189 10.795 clock uncertainty -0.035 10.760 SLICE_X39Y153 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 10.705 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.705 arrival time -7.087 ------------------------------------------------------------------- slack 3.618 Slack (MET) : 3.622ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 4.458ns (logic 1.625ns (36.451%) route 2.833ns (63.549%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.289ns = ( 10.606 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.699ns, distribution 1.502ns) Clock Net Delay (Destination): 1.913ns (routing 0.636ns, distribution 1.277ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.787 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.032 5.819 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X38Y153 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.057 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/O net (fo=5, routed) 0.277 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X37Y152 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.560 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/O net (fo=7, routed) 0.524 7.084 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X39Y153 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.913 10.606 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X39Y153 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.189 10.795 clock uncertainty -0.035 10.760 SLICE_X39Y153 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 10.706 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.706 arrival time -7.084 ------------------------------------------------------------------- slack 3.622 Slack (MET) : 3.731ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 4.346ns (logic 1.625ns (37.391%) route 2.721ns (62.609%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.147ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.290ns = ( 10.607 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.699ns, distribution 1.502ns) Clock Net Delay (Destination): 1.914ns (routing 0.636ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.787 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.032 5.819 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X38Y153 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.057 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/O net (fo=5, routed) 0.277 6.334 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X37Y152 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.226 6.560 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__26/O net (fo=7, routed) 0.412 6.972 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X38Y153 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.914 10.607 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X38Y153 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.189 10.796 clock uncertainty -0.035 10.761 SLICE_X38Y153 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.703 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.703 arrival time -6.972 ------------------------------------------------------------------- slack 3.731 Slack (MET) : 3.875ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 4.204ns (logic 1.551ns (36.893%) route 2.653ns (63.107%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.292ns = ( 10.609 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.699ns, distribution 1.502ns) Clock Net Delay (Destination): 1.916ns (routing 0.636ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.787 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.032 5.819 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X38Y153 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.238 6.057 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__25/O net (fo=5, routed) 0.184 6.241 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X37Y153 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 6.393 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__26/O net (fo=5, routed) 0.437 6.830 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 SLICE_X37Y151 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.916 10.609 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X37Y151 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.189 10.798 clock uncertainty -0.035 10.763 SLICE_X37Y151 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.705 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 10.705 arrival time -6.830 ------------------------------------------------------------------- slack 3.875 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].rx_data_ngccm_reg[26][35]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.165ns (logic 0.048ns (29.091%) route 0.117ns (70.909%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.848ns (routing 0.319ns, distribution 0.529ns) Clock Net Delay (Destination): 1.021ns (routing 0.369ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X43Y137 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y137 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.012 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/Q net (fo=1, routed) 0.117 1.129 rx_data[26][35] SLICE_X44Y137 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][35]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.173 g_gbt_bank[2].gbtbank_n_44 SLICE_X44Y137 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][35]/C clock pessimism -0.130 1.043 SLICE_X44Y137 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.099 SFP_GEN[26].rx_data_ngccm_reg[26][35] ------------------------------------------------------------------- required time -1.099 arrival time 1.129 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.036ns (arrival time - required time) Source: SFP_GEN[26].rx_data_ngccm_reg[26][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.080ns (46.784%) route 0.091ns (53.216%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.171ns Source Clock Delay (SCD): 0.962ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.846ns (routing 0.319ns, distribution 0.527ns) Clock Net Delay (Destination): 1.019ns (routing 0.369ns, distribution 0.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.846 0.962 g_gbt_bank[2].gbtbank_n_44 SLICE_X43Y139 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][0]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y139 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.011 r SFP_GEN[26].rx_data_ngccm_reg[26][0]/Q net (fo=1, routed) 0.075 1.086 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[83]_0[0] SLICE_X44Y139 LUT3 (Prop_D6LUT_SLICEM_I1_O) 0.031 1.117 r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[0]_i_1/O net (fo=1, routed) 0.016 1.133 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[0]_i_1_n_0 SLICE_X44Y139 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.171 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y139 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.130 1.041 SLICE_X44Y139 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.097 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.097 arrival time 1.133 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].rx_data_ngccm_reg[26][48]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.048ns (27.273%) route 0.128ns (72.727%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.171ns Source Clock Delay (SCD): 0.959ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.843ns (routing 0.319ns, distribution 0.524ns) Clock Net Delay (Destination): 1.019ns (routing 0.369ns, distribution 0.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.843 0.959 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X43Y148 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y148 FDRE (Prop_BFF2_SLICEL_C_Q) 0.048 1.007 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.128 1.135 rx_data[26][48] SLICE_X45Y148 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][48]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.171 g_gbt_bank[2].gbtbank_n_44 SLICE_X45Y148 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][48]/C clock pessimism -0.130 1.041 SLICE_X45Y148 FDCE (Hold_GFF_SLICEL_C_D) 0.056 1.097 SFP_GEN[26].rx_data_ngccm_reg[26][48] ------------------------------------------------------------------- required time -1.097 arrival time 1.135 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[23]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[23]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.140ns (logic 0.048ns (34.286%) route 0.092ns (65.714%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.174ns Source Clock Delay (SCD): 0.965ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.849ns (routing 0.319ns, distribution 0.530ns) Clock Net Delay (Destination): 1.022ns (routing 0.369ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.849 0.965 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X43Y144 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[23]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y144 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.013 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[23]/Q net (fo=1, routed) 0.092 1.105 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[23] SLICE_X43Y145 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.174 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X43Y145 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[23]/C clock pessimism -0.163 1.011 SLICE_X43Y145 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.067 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[23] ------------------------------------------------------------------- required time -1.067 arrival time 1.105 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.039ns (arrival time - required time) Source: SFP_GEN[26].rx_data_ngccm_reg[26][57]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[56]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.175ns Source Clock Delay (SCD): 0.952ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 0.836ns (routing 0.319ns, distribution 0.517ns) Clock Net Delay (Destination): 1.023ns (routing 0.369ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.836 0.952 g_gbt_bank[2].gbtbank_n_44 SLICE_X44Y149 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][57]/C ------------------------------------------------------------------- ------------------- SLICE_X44Y149 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.001 r SFP_GEN[26].rx_data_ngccm_reg[26][57]/Q net (fo=1, routed) 0.035 1.036 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[83]_0[49] SLICE_X44Y148 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.054 1.090 r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[56]_i_1/O net (fo=1, routed) 0.016 1.106 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[56]_i_1_n_0 SLICE_X44Y148 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[56]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.175 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y148 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[56]/C clock pessimism -0.164 1.011 SLICE_X44Y148 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.067 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[56] ------------------------------------------------------------------- required time -1.067 arrival time 1.106 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].rx_data_ngccm_reg[26][20]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.048ns (26.519%) route 0.133ns (73.481%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.182ns Source Clock Delay (SCD): 0.967ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.851ns (routing 0.319ns, distribution 0.532ns) Clock Net Delay (Destination): 1.030ns (routing 0.369ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.851 0.967 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X43Y138 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y138 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.015 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/Q net (fo=1, routed) 0.133 1.148 rx_data[26][20] SLICE_X45Y140 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.030 1.182 g_gbt_bank[2].gbtbank_n_44 SLICE_X45Y140 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][20]/C clock pessimism -0.130 1.052 SLICE_X45Y140 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.107 SFP_GEN[26].rx_data_ngccm_reg[26][20] ------------------------------------------------------------------- required time -1.107 arrival time 1.148 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.080ns (46.784%) route 0.091ns (53.216%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.157ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.837ns (routing 0.319ns, distribution 0.518ns) Clock Net Delay (Destination): 1.005ns (routing 0.369ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.953 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X44Y153 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C ------------------------------------------------------------------- ------------------- SLICE_X44Y153 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.002 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/Q net (fo=10, routed) 0.075 1.077 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].cnt_reg[2][7]_0[0] SLICE_X43Y153 LUT6 (Prop_H6LUT_SLICEL_I4_O) 0.031 1.108 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_1__1/O net (fo=1, routed) 0.016 1.124 g_gbt_bank[2].gbtbank/i_gbt_bank_n_147 SLICE_X43Y153 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.157 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X43Y153 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C clock pessimism -0.130 1.027 SLICE_X43Y153 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.083 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2] ------------------------------------------------------------------- required time -1.083 arrival time 1.124 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.063ns (42.568%) route 0.085ns (57.432%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.174ns Source Clock Delay (SCD): 0.962ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.846ns (routing 0.319ns, distribution 0.527ns) Clock Net Delay (Destination): 1.022ns (routing 0.369ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.846 0.962 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X43Y137 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y137 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.071 1.081 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in SLICE_X43Y138 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.015 1.096 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__25/O net (fo=1, routed) 0.014 1.110 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] SLICE_X43Y138 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.174 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X43Y138 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.163 1.011 SLICE_X43Y138 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.067 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.067 arrival time 1.110 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].rx_data_ngccm_reg[26][6]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.168ns Source Clock Delay (SCD): 0.965ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.849ns (routing 0.319ns, distribution 0.530ns) Clock Net Delay (Destination): 1.016ns (routing 0.369ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.849 0.965 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X43Y138 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y138 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.013 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.093 1.106 rx_data[26][6] SLICE_X43Y139 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.168 g_gbt_bank[2].gbtbank_n_44 SLICE_X43Y139 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][6]/C clock pessimism -0.163 1.005 SLICE_X43Y139 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.061 SFP_GEN[26].rx_data_ngccm_reg[26][6] ------------------------------------------------------------------- required time -1.061 arrival time 1.106 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[26].rx_data_ngccm_reg[26][53]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[52]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_28 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.170ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.839ns (routing 0.319ns, distribution 0.520ns) Clock Net Delay (Destination): 1.018ns (routing 0.369ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.839 0.955 g_gbt_bank[2].gbtbank_n_44 SLICE_X43Y149 FDCE r SFP_GEN[26].rx_data_ngccm_reg[26][53]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y149 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.004 r SFP_GEN[26].rx_data_ngccm_reg[26][53]/Q net (fo=1, routed) 0.034 1.038 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[83]_0[45] SLICE_X43Y149 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.083 r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[52]_i_1/O net (fo=1, routed) 0.016 1.099 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[52]_i_1_n_0 SLICE_X43Y149 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[52]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.170 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y149 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism -0.173 0.997 SLICE_X43Y149 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.053 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time -1.053 arrival time 1.099 ------------------------------------------------------------------- slack 0.046 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_28 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y53 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y177 g_clock_rate_din[26].ngccm_status_cnt_reg[26][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y178 g_clock_rate_din[26].ngccm_status_cnt_reg[26][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y177 g_clock_rate_din[26].ngccm_status_cnt_reg[26][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y178 g_clock_rate_din[26].ngccm_status_cnt_reg[26][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y178 g_clock_rate_din[26].ngccm_status_cnt_reg[26][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y178 g_clock_rate_din[26].ngccm_status_cnt_reg[26][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y179 g_clock_rate_din[26].ngccm_status_cnt_reg[26][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y154 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y154 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X44Y147 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X44Y147 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y144 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[23]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y145 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[68]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y153 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y153 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y153 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y153 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y153 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y153 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y10 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_29 To Clock: gtwiz_userclk_rx_srcclk_out[0]_29 Setup : 0 Failing Endpoints, Worst Slack 3.092ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.039ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.092ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.999ns (logic 1.858ns (37.167%) route 3.141ns (62.833%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.428ns = ( 10.745 - 8.317 ) Source Clock Delay (SCD): 2.768ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.343ns (routing 0.804ns, distribution 1.539ns) Clock Net Delay (Destination): 2.052ns (routing 0.721ns, distribution 1.331ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.343 2.768 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.872 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.647 5.519 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X25Y173 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 5.763 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/O net (fo=5, routed) 0.505 6.268 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X26Y175 LUT4 (Prop_B5LUT_SLICEL_I2_O) 0.272 6.540 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26/O net (fo=1, routed) 0.413 6.953 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26_n_0 SLICE_X26Y173 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.238 7.191 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26/O net (fo=2, routed) 0.576 7.767 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26_n_0 SLICE_X25Y173 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.052 10.745 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X25Y173 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.204 10.950 clock uncertainty -0.035 10.914 SLICE_X25Y173 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 10.859 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.859 arrival time -7.767 ------------------------------------------------------------------- slack 3.092 Slack (MET) : 3.092ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.999ns (logic 1.858ns (37.167%) route 3.141ns (62.833%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.428ns = ( 10.745 - 8.317 ) Source Clock Delay (SCD): 2.768ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.343ns (routing 0.804ns, distribution 1.539ns) Clock Net Delay (Destination): 2.052ns (routing 0.721ns, distribution 1.331ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.343 2.768 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.872 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 1.647 5.519 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X25Y173 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 5.763 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/O net (fo=5, routed) 0.505 6.268 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X26Y175 LUT4 (Prop_B5LUT_SLICEL_I2_O) 0.272 6.540 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26/O net (fo=1, routed) 0.413 6.953 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26_n_0 SLICE_X26Y173 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.238 7.191 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26/O net (fo=2, routed) 0.576 7.767 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26_n_0 SLICE_X25Y173 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.052 10.745 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X25Y173 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.204 10.950 clock uncertainty -0.035 10.914 SLICE_X25Y173 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.859 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.859 arrival time -7.767 ------------------------------------------------------------------- slack 3.092 Slack (MET) : 3.936ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.144ns (logic 0.417ns (10.063%) route 3.727ns (89.937%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.428ns = ( 10.745 - 8.317 ) Source Clock Delay (SCD): 2.777ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.352ns (routing 0.804ns, distribution 1.548ns) Clock Net Delay (Destination): 2.052ns (routing 0.721ns, distribution 1.331ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.352 2.777 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y172 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y172 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.917 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 1.477 4.394 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X17Y162 LUT2 (Prop_B5LUT_SLICEM_I1_O) 0.277 4.671 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/O net (fo=76, routed) 2.250 6.921 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X26Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.052 10.745 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X26Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism 0.205 10.950 clock uncertainty -0.035 10.915 SLICE_X26Y169 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.857 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time 10.857 arrival time -6.921 ------------------------------------------------------------------- slack 3.936 Slack (MET) : 3.942ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.141ns (logic 0.417ns (10.070%) route 3.724ns (89.930%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.428ns = ( 10.745 - 8.317 ) Source Clock Delay (SCD): 2.777ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.352ns (routing 0.804ns, distribution 1.548ns) Clock Net Delay (Destination): 2.052ns (routing 0.721ns, distribution 1.331ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.352 2.777 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y172 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y172 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.917 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 1.477 4.394 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X17Y162 LUT2 (Prop_B5LUT_SLICEM_I1_O) 0.277 4.671 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/O net (fo=76, routed) 2.247 6.918 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X26Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.052 10.745 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X26Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism 0.205 10.950 clock uncertainty -0.035 10.915 SLICE_X26Y169 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.860 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time 10.860 arrival time -6.918 ------------------------------------------------------------------- slack 3.942 Slack (MET) : 4.085ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 4.080ns (logic 1.093ns (26.789%) route 2.987ns (73.211%)) Logic Levels: 5 (LUT2=1 LUT4=1 LUT6=3) Clock Path Skew: -0.179ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.493ns = ( 10.810 - 8.317 ) Source Clock Delay (SCD): 2.892ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.467ns (routing 0.804ns, distribution 1.663ns) Clock Net Delay (Destination): 2.117ns (routing 0.721ns, distribution 1.396ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.467 2.892 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X17Y172 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y172 FDCE (Prop_BFF2_SLICEM_C_Q) 0.138 3.030 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[2]/Q net (fo=7, routed) 0.672 3.702 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/Q[2] SLICE_X13Y170 LUT2 (Prop_C5LUT_SLICEM_I1_O) 0.170 3.872 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_6__26/O net (fo=3, routed) 0.546 4.418 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_6__26_n_0 SLICE_X16Y166 LUT6 (Prop_F6LUT_SLICEM_I1_O) 0.245 4.663 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___8_i_1__26/O net (fo=33, routed) 1.094 5.757 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/s1_from_syndromes[0] SLICE_X12Y168 LUT4 (Prop_F6LUT_SLICEL_I2_O) 0.090 5.847 f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__26/O net (fo=1, routed) 0.346 6.193 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__26_n_0 SLICE_X13Y169 LUT6 (Prop_H6LUT_SLICEM_I4_O) 0.225 6.418 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__53/O net (fo=1, routed) 0.295 6.713 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__53_n_0 SLICE_X14Y168 LUT6 (Prop_B6LUT_SLICEM_I3_O) 0.225 6.938 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__53/O net (fo=1, routed) 0.034 6.972 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 SLICE_X14Y168 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.117 10.810 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK SLICE_X14Y168 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C clock pessimism 0.220 11.030 clock uncertainty -0.035 10.995 SLICE_X14Y168 FDRE (Setup_BFF_SLICEM_C_D) 0.062 11.057 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg ------------------------------------------------------------------- required time 11.057 arrival time -6.972 ------------------------------------------------------------------- slack 4.085 Slack (MET) : 4.092ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 3.987ns (logic 0.417ns (10.459%) route 3.570ns (89.541%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.427ns = ( 10.744 - 8.317 ) Source Clock Delay (SCD): 2.777ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.352ns (routing 0.804ns, distribution 1.548ns) Clock Net Delay (Destination): 2.051ns (routing 0.721ns, distribution 1.330ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.352 2.777 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y172 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y172 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.917 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 1.477 4.394 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X17Y162 LUT2 (Prop_B5LUT_SLICEM_I1_O) 0.277 4.671 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/O net (fo=76, routed) 2.093 6.764 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X23Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.051 10.744 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X23Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism 0.205 10.949 clock uncertainty -0.035 10.914 SLICE_X23Y169 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.856 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time 10.856 arrival time -6.764 ------------------------------------------------------------------- slack 4.092 Slack (MET) : 4.092ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 3.987ns (logic 0.417ns (10.459%) route 3.570ns (89.541%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.427ns = ( 10.744 - 8.317 ) Source Clock Delay (SCD): 2.777ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.352ns (routing 0.804ns, distribution 1.548ns) Clock Net Delay (Destination): 2.051ns (routing 0.721ns, distribution 1.330ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.352 2.777 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y172 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y172 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.917 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 1.477 4.394 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X17Y162 LUT2 (Prop_B5LUT_SLICEM_I1_O) 0.277 4.671 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/O net (fo=76, routed) 2.093 6.764 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X23Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.051 10.744 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X23Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C clock pessimism 0.205 10.949 clock uncertainty -0.035 10.914 SLICE_X23Y169 FDRE (Setup_GFF2_SLICEM_C_CE) -0.058 10.856 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3] ------------------------------------------------------------------- required time 10.856 arrival time -6.764 ------------------------------------------------------------------- slack 4.092 Slack (MET) : 4.098ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 3.984ns (logic 0.417ns (10.467%) route 3.567ns (89.533%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.427ns = ( 10.744 - 8.317 ) Source Clock Delay (SCD): 2.777ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.352ns (routing 0.804ns, distribution 1.548ns) Clock Net Delay (Destination): 2.051ns (routing 0.721ns, distribution 1.330ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.352 2.777 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y172 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y172 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.917 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 1.477 4.394 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X17Y162 LUT2 (Prop_B5LUT_SLICEM_I1_O) 0.277 4.671 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/O net (fo=76, routed) 2.090 6.761 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X23Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.051 10.744 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X23Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism 0.205 10.949 clock uncertainty -0.035 10.914 SLICE_X23Y169 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.859 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time 10.859 arrival time -6.761 ------------------------------------------------------------------- slack 4.098 Slack (MET) : 4.098ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 3.984ns (logic 0.417ns (10.467%) route 3.567ns (89.533%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.427ns = ( 10.744 - 8.317 ) Source Clock Delay (SCD): 2.777ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.352ns (routing 0.804ns, distribution 1.548ns) Clock Net Delay (Destination): 2.051ns (routing 0.721ns, distribution 1.330ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.352 2.777 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y172 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y172 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.917 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 1.477 4.394 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X17Y162 LUT2 (Prop_B5LUT_SLICEM_I1_O) 0.277 4.671 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/O net (fo=76, routed) 2.090 6.761 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X23Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.051 10.744 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X23Y169 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism 0.205 10.949 clock uncertainty -0.035 10.914 SLICE_X23Y169 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 10.859 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time 10.859 arrival time -6.761 ------------------------------------------------------------------- slack 4.098 Slack (MET) : 4.103ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 3.982ns (logic 0.417ns (10.472%) route 3.565ns (89.528%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.142ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.430ns = ( 10.747 - 8.317 ) Source Clock Delay (SCD): 2.777ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.352ns (routing 0.804ns, distribution 1.548ns) Clock Net Delay (Destination): 2.054ns (routing 0.721ns, distribution 1.333ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.352 2.777 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y172 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y172 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.917 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=137, routed) 1.477 4.394 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X17Y162 LUT2 (Prop_B5LUT_SLICEM_I1_O) 0.277 4.671 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__26/O net (fo=76, routed) 2.088 6.759 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X23Y170 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.054 10.747 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X23Y170 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C clock pessimism 0.205 10.952 clock uncertainty -0.035 10.917 SLICE_X23Y170 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 10.862 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9] ------------------------------------------------------------------- required time 10.862 arrival time -6.759 ------------------------------------------------------------------- slack 4.103 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.094ns (50.538%) route 0.092ns (49.462%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.960ns (routing 0.382ns, distribution 0.578ns) Clock Net Delay (Destination): 1.166ns (routing 0.446ns, distribution 0.720ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.076 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X18Y163 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X18Y163 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.124 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.077 1.201 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_33_in SLICE_X19Y163 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.046 1.247 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__26/O net (fo=1, routed) 0.015 1.262 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] SLICE_X19Y163 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X19Y163 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.151 1.167 SLICE_X19Y163 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.223 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.223 arrival time 1.262 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].rx_data_ngccm_reg[27][76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.049ns (33.108%) route 0.099ns (66.892%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.317ns Source Clock Delay (SCD): 1.082ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 0.966ns (routing 0.382ns, distribution 0.584ns) Clock Net Delay (Destination): 1.165ns (routing 0.446ns, distribution 0.719ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.966 1.082 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X19Y163 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y163 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.131 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.099 1.230 rx_data[27][76] SLICE_X19Y164 FDCE r SFP_GEN[27].rx_data_ngccm_reg[27][76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.165 1.317 g_gbt_bank[2].gbtbank_n_54 SLICE_X19Y164 FDCE r SFP_GEN[27].rx_data_ngccm_reg[27][76]/C clock pessimism -0.183 1.134 SLICE_X19Y164 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.190 SFP_GEN[27].rx_data_ngccm_reg[27][76] ------------------------------------------------------------------- required time -1.190 arrival time 1.230 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].rx_data_ngccm_reg[27][67]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.298ns Source Clock Delay (SCD): 1.070ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 0.954ns (routing 0.382ns, distribution 0.572ns) Clock Net Delay (Destination): 1.146ns (routing 0.446ns, distribution 0.700ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.954 1.070 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X21Y163 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X21Y163 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.118 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.095 1.213 rx_data[27][67] SLICE_X21Y162 FDCE r SFP_GEN[27].rx_data_ngccm_reg[27][67]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.146 1.298 g_gbt_bank[2].gbtbank_n_54 SLICE_X21Y162 FDCE r SFP_GEN[27].rx_data_ngccm_reg[27][67]/C clock pessimism -0.183 1.115 SLICE_X21Y162 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.171 SFP_GEN[27].rx_data_ngccm_reg[27][67] ------------------------------------------------------------------- required time -1.171 arrival time 1.213 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.158ns (logic 0.078ns (49.367%) route 0.080ns (50.633%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.074ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 0.958ns (routing 0.382ns, distribution 0.576ns) Clock Net Delay (Destination): 1.164ns (routing 0.446ns, distribution 0.718ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.958 1.074 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X18Y165 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X18Y165 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.122 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.068 1.190 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_13_in SLICE_X18Y164 LUT3 (Prop_F6LUT_SLICEL_I2_O) 0.030 1.220 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__26/O net (fo=1, routed) 0.012 1.232 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] SLICE_X18Y164 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.164 1.316 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X18Y164 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.184 1.132 SLICE_X18Y164 FDRE (Hold_FFF_SLICEL_C_D) 0.056 1.188 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.188 arrival time 1.232 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.194ns (logic 0.102ns (52.577%) route 0.092ns (47.423%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.960ns (routing 0.382ns, distribution 0.578ns) Clock Net Delay (Destination): 1.166ns (routing 0.446ns, distribution 0.720ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.076 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X18Y163 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X18Y163 FDCE (Prop_FFF2_SLICEL_C_Q) 0.048 1.124 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.076 1.200 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X19Y163 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.054 1.254 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__26/O net (fo=1, routed) 0.016 1.270 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X19Y163 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X19Y163 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.151 1.167 SLICE_X19Y163 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.223 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.223 arrival time 1.270 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.064ns (42.105%) route 0.088ns (57.895%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.278ns Source Clock Delay (SCD): 1.053ns Clock Pessimism Removal (CPR): 0.177ns Clock Net Delay (Source): 0.937ns (routing 0.382ns, distribution 0.555ns) Clock Net Delay (Destination): 1.126ns (routing 0.446ns, distribution 0.680ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.937 1.053 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X25Y175 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y175 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.102 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[1]/Q net (fo=6, routed) 0.072 1.174 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/timer[1] SLICE_X25Y174 LUT6 (Prop_C6LUT_SLICEM_I5_O) 0.015 1.189 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__27/O net (fo=1, routed) 0.016 1.205 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__27_n_0 SLICE_X25Y174 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.126 1.278 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X25Y174 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C clock pessimism -0.177 1.101 SLICE_X25Y174 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.157 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/clkSlipProcess.timer_reg[5] ------------------------------------------------------------------- required time -1.157 arrival time 1.205 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[23]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.172ns (logic 0.049ns (28.488%) route 0.123ns (71.512%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.255ns Source Clock Delay (SCD): 1.045ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.929ns (routing 0.382ns, distribution 0.547ns) Clock Net Delay (Destination): 1.103ns (routing 0.446ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.929 1.045 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X28Y171 FDCE r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[23]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y171 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.094 r SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[23]/Q net (fo=5, routed) 0.123 1.217 SFP_GEN[27].ngCCM_gbt/gbt_rx_checker/Q[7] SLICE_X29Y171 FDRE r SFP_GEN[27].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.103 1.255 SFP_GEN[27].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X29Y171 FDRE r SFP_GEN[27].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/C clock pessimism -0.142 1.113 SLICE_X29Y171 FDRE (Hold_GFF2_SLICEM_C_D) 0.056 1.169 SFP_GEN[27].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7] ------------------------------------------------------------------- required time -1.169 arrival time 1.217 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.162ns (logic 0.079ns (48.765%) route 0.083ns (51.235%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 0.960ns (routing 0.382ns, distribution 0.578ns) Clock Net Delay (Destination): 1.164ns (routing 0.446ns, distribution 0.718ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.076 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X18Y163 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X18Y163 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.125 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.069 1.194 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_31_in SLICE_X18Y164 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.030 1.224 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__26/O net (fo=1, routed) 0.014 1.238 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[16] SLICE_X18Y164 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.164 1.316 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X18Y164 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.184 1.132 SLICE_X18Y164 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.188 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.188 arrival time 1.238 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.078ns (46.707%) route 0.089ns (53.293%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.061ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.319ns Source Clock Delay (SCD): 1.074ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 0.958ns (routing 0.382ns, distribution 0.576ns) Clock Net Delay (Destination): 1.167ns (routing 0.446ns, distribution 0.721ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.958 1.074 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X18Y165 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X18Y165 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.122 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.073 1.195 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in SLICE_X18Y164 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.030 1.225 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__26/O net (fo=1, routed) 0.016 1.241 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] SLICE_X18Y164 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.167 1.319 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X18Y164 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.184 1.135 SLICE_X18Y164 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.191 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.191 arrival time 1.241 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_29 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.285ns Source Clock Delay (SCD): 1.056ns Clock Pessimism Removal (CPR): 0.224ns Clock Net Delay (Source): 0.940ns (routing 0.382ns, distribution 0.558ns) Clock Net Delay (Destination): 1.133ns (routing 0.446ns, distribution 0.687ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.940 1.056 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X26Y173 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X26Y173 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.105 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.035 1.140 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/ready_from_bitSlipCtrller_3 SLICE_X26Y173 LUT3 (Prop_A6LUT_SLICEL_I2_O) 0.015 1.155 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_i_1__26/O net (fo=1, routed) 0.012 1.167 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_i_1__26_n_0 SLICE_X26Y173 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.133 1.285 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X26Y173 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_reg/C clock pessimism -0.224 1.061 SLICE_X26Y173 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.117 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.117 arrival time 1.167 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_29 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y71 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y176 g_clock_rate_din[27].ngccm_status_cnt_reg[27][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y176 g_clock_rate_din[27].ngccm_status_cnt_reg[27][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y175 g_clock_rate_din[27].ngccm_status_cnt_reg[27][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y175 g_clock_rate_din[27].ngccm_status_cnt_reg[27][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y175 g_clock_rate_din[27].ngccm_status_cnt_reg[27][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y175 g_clock_rate_din[27].ngccm_status_cnt_reg[27][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X52Y178 g_clock_rate_din[27].ngccm_status_cnt_reg[27][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y175 g_clock_rate_din[27].ngccm_status_cnt_reg[27][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y175 g_clock_rate_din[27].ngccm_status_cnt_reg[27][3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y175 g_clock_rate_din[27].ngccm_status_cnt_reg[27][4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y175 g_clock_rate_din[27].ngccm_status_cnt_reg[27][5]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X28Y170 g_clock_rate_din[27].rx_frameclk_div2_reg[27]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y178 g_clock_rate_din[27].rx_wordclk_div2_reg[27]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y178 g_clock_rate_din[27].ngccm_status_cnt_reg[27][6]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y178 g_clock_rate_din[27].rx_test_comm_cnt_reg[27]/C High Pulse Width Slow FDPE/C n/a 0.275 4.159 3.884 SLICE_X27Y167 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X23Y168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X23Y168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X23Y168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y11 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_30 To Clock: gtwiz_userclk_rx_srcclk_out[0]_30 Setup : 0 Failing Endpoints, Worst Slack 3.447ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.447ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.637ns (logic 1.592ns (34.333%) route 3.045ns (65.667%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.716ns = ( 11.033 - 8.317 ) Source Clock Delay (SCD): 3.082ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.657ns (routing 1.111ns, distribution 1.546ns) Clock Net Delay (Destination): 2.340ns (routing 1.016ns, distribution 1.324ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.657 3.082 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.241 6.427 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X42Y192 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.225 6.652 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.279 6.931 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X42Y193 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.021 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27/O net (fo=1, routed) 0.084 7.105 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27_n_0 SLICE_X42Y193 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 7.278 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27/O net (fo=2, routed) 0.441 7.719 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27_n_0 SLICE_X41Y192 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.340 11.033 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y192 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.223 11.257 clock uncertainty -0.035 11.221 SLICE_X41Y192 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.166 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.166 arrival time -7.719 ------------------------------------------------------------------- slack 3.447 Slack (MET) : 3.456ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.631ns (logic 1.592ns (34.377%) route 3.039ns (65.623%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.141ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.718ns = ( 11.035 - 8.317 ) Source Clock Delay (SCD): 3.082ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.657ns (routing 1.111ns, distribution 1.546ns) Clock Net Delay (Destination): 2.342ns (routing 1.016ns, distribution 1.326ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.657 3.082 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.241 6.427 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X42Y192 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.225 6.652 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.279 6.931 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X42Y193 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.090 7.021 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27/O net (fo=1, routed) 0.084 7.105 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27_n_0 SLICE_X42Y193 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 7.278 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27/O net (fo=2, routed) 0.435 7.713 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27_n_0 SLICE_X41Y192 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.342 11.035 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y192 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.223 11.259 clock uncertainty -0.035 11.223 SLICE_X41Y192 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 11.169 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.169 arrival time -7.713 ------------------------------------------------------------------- slack 3.456 Slack (MET) : 3.717ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.361ns (logic 1.477ns (33.868%) route 2.884ns (66.132%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.710ns = ( 11.027 - 8.317 ) Source Clock Delay (SCD): 3.082ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.657ns (routing 1.111ns, distribution 1.546ns) Clock Net Delay (Destination): 2.334ns (routing 1.016ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.657 3.082 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.241 6.427 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X42Y192 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.225 6.652 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.180 6.832 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X42Y193 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.148 6.980 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/O net (fo=7, routed) 0.463 7.443 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X41Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.334 11.027 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.223 11.251 clock uncertainty -0.035 11.215 SLICE_X41Y191 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.160 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.160 arrival time -7.443 ------------------------------------------------------------------- slack 3.717 Slack (MET) : 3.721ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.358ns (logic 1.477ns (33.892%) route 2.881ns (66.108%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.149ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.710ns = ( 11.027 - 8.317 ) Source Clock Delay (SCD): 3.082ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.657ns (routing 1.111ns, distribution 1.546ns) Clock Net Delay (Destination): 2.334ns (routing 1.016ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.657 3.082 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.241 6.427 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X42Y192 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.225 6.652 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.180 6.832 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X42Y193 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.148 6.980 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/O net (fo=7, routed) 0.460 7.440 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X41Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.334 11.027 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.223 11.251 clock uncertainty -0.035 11.215 SLICE_X41Y191 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.161 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.161 arrival time -7.440 ------------------------------------------------------------------- slack 3.721 Slack (MET) : 3.761ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.328ns (logic 1.475ns (34.080%) route 2.853ns (65.920%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.721ns = ( 11.038 - 8.317 ) Source Clock Delay (SCD): 3.082ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.657ns (routing 1.111ns, distribution 1.546ns) Clock Net Delay (Destination): 2.345ns (routing 1.016ns, distribution 1.329ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.657 3.082 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.186 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.241 6.427 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X42Y192 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.225 6.652 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.180 6.832 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X42Y193 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.978 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/O net (fo=5, routed) 0.432 7.410 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X42Y192 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 11.038 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y192 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.223 11.262 clock uncertainty -0.035 11.226 SLICE_X42Y192 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.171 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.171 arrival time -7.410 ------------------------------------------------------------------- slack 3.761 Slack (MET) : 3.761ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.328ns (logic 1.475ns (34.080%) route 2.853ns (65.920%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.721ns = ( 11.038 - 8.317 ) Source Clock Delay (SCD): 3.082ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.657ns (routing 1.111ns, distribution 1.546ns) Clock Net Delay (Destination): 2.345ns (routing 1.016ns, distribution 1.329ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.657 3.082 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.186 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.241 6.427 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X42Y192 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.225 6.652 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.180 6.832 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X42Y193 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.978 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/O net (fo=5, routed) 0.432 7.410 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X42Y192 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 11.038 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y192 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.223 11.262 clock uncertainty -0.035 11.226 SLICE_X42Y192 FDRE (Setup_AFF2_SLICEM_C_CE) -0.055 11.171 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.171 arrival time -7.410 ------------------------------------------------------------------- slack 3.761 Slack (MET) : 3.762ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.320ns (logic 1.475ns (34.144%) route 2.845ns (65.856%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.713ns = ( 11.030 - 8.317 ) Source Clock Delay (SCD): 3.082ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.657ns (routing 1.111ns, distribution 1.546ns) Clock Net Delay (Destination): 2.337ns (routing 1.016ns, distribution 1.321ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.657 3.082 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.186 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.241 6.427 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X42Y192 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.225 6.652 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.180 6.832 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X42Y193 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.978 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/O net (fo=5, routed) 0.424 7.402 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X42Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.337 11.030 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y191 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.223 11.254 clock uncertainty -0.035 11.218 SLICE_X42Y191 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.164 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.164 arrival time -7.402 ------------------------------------------------------------------- slack 3.762 Slack (MET) : 3.765ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.325ns (logic 1.475ns (34.104%) route 2.850ns (65.896%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.721ns = ( 11.038 - 8.317 ) Source Clock Delay (SCD): 3.082ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.657ns (routing 1.111ns, distribution 1.546ns) Clock Net Delay (Destination): 2.345ns (routing 1.016ns, distribution 1.329ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.657 3.082 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.186 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.241 6.427 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X42Y192 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.225 6.652 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.180 6.832 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X42Y193 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.978 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/O net (fo=5, routed) 0.429 7.407 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X42Y192 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 11.038 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y192 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.223 11.262 clock uncertainty -0.035 11.226 SLICE_X42Y192 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.172 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.172 arrival time -7.407 ------------------------------------------------------------------- slack 3.765 Slack (MET) : 3.765ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.325ns (logic 1.475ns (34.104%) route 2.850ns (65.896%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.721ns = ( 11.038 - 8.317 ) Source Clock Delay (SCD): 3.082ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.657ns (routing 1.111ns, distribution 1.546ns) Clock Net Delay (Destination): 2.345ns (routing 1.016ns, distribution 1.329ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.657 3.082 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.186 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.241 6.427 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X42Y192 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.225 6.652 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.180 6.832 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X42Y193 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.146 6.978 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__28/O net (fo=5, routed) 0.429 7.407 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X42Y192 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.345 11.038 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y192 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.223 11.262 clock uncertainty -0.035 11.226 SLICE_X42Y192 FDRE (Setup_AFF_SLICEM_C_CE) -0.054 11.172 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.172 arrival time -7.407 ------------------------------------------------------------------- slack 3.765 Slack (MET) : 3.830ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 4.254ns (logic 1.479ns (34.767%) route 2.775ns (65.233%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.719ns = ( 11.036 - 8.317 ) Source Clock Delay (SCD): 3.082ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.657ns (routing 1.111ns, distribution 1.546ns) Clock Net Delay (Destination): 2.343ns (routing 1.016ns, distribution 1.327ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.657 3.082 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 4.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 2.241 6.427 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X42Y192 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.225 6.652 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/O net (fo=5, routed) 0.182 6.834 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X42Y193 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.150 6.984 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__28/O net (fo=3, routed) 0.352 7.336 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 SLICE_X42Y192 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.343 11.036 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y192 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.223 11.260 clock uncertainty -0.035 11.224 SLICE_X42Y192 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.166 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.166 arrival time -7.336 ------------------------------------------------------------------- slack 3.830 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].rx_data_ngccm_reg[28][73]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.048ns (20.168%) route 0.190ns (79.832%)) Logic Levels: 0 Clock Path Skew: 0.152ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.394ns Source Clock Delay (SCD): 1.138ns Clock Pessimism Removal (CPR): 0.104ns Clock Net Delay (Source): 1.022ns (routing 0.483ns, distribution 0.539ns) Clock Net Delay (Destination): 1.242ns (routing 0.551ns, distribution 0.691ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.022 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X38Y179 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y179 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.186 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.190 1.376 rx_data[28][73] SLICE_X38Y181 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][73]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.242 1.394 g_gbt_bank[2].gbtbank_n_64 SLICE_X38Y181 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][73]/C clock pessimism -0.104 1.290 SLICE_X38Y181 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.346 SFP_GEN[28].rx_data_ngccm_reg[28][73] ------------------------------------------------------------------- required time -1.346 arrival time 1.376 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.095ns (51.351%) route 0.090ns (48.649%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.401ns Source Clock Delay (SCD): 1.156ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.040ns (routing 0.483ns, distribution 0.557ns) Clock Net Delay (Destination): 1.249ns (routing 0.551ns, distribution 0.698ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.156 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X43Y189 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y189 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.205 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.074 1.279 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in SLICE_X44Y189 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.046 1.325 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__27/O net (fo=1, routed) 0.016 1.341 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] SLICE_X44Y189 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.249 1.401 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X44Y189 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.151 1.250 SLICE_X44Y189 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.306 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.306 arrival time 1.341 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].rx_data_ngccm_reg[28][21]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.048ns (30.769%) route 0.108ns (69.231%)) Logic Levels: 0 Clock Path Skew: 0.063ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.401ns Source Clock Delay (SCD): 1.154ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 1.038ns (routing 0.483ns, distribution 0.555ns) Clock Net Delay (Destination): 1.249ns (routing 0.551ns, distribution 0.698ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.038 1.154 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X45Y188 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y188 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.202 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/Q net (fo=1, routed) 0.108 1.310 rx_data[28][21] SLICE_X45Y187 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][21]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.249 1.401 g_gbt_bank[2].gbtbank_n_64 SLICE_X45Y187 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][21]/C clock pessimism -0.184 1.217 SLICE_X45Y187 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.273 SFP_GEN[28].rx_data_ngccm_reg[28][21] ------------------------------------------------------------------- required time -1.273 arrival time 1.310 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.038ns (arrival time - required time) Source: SFP_GEN[28].rx_data_ngccm_reg[28][72]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[72]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.165ns (logic 0.079ns (47.879%) route 0.086ns (52.121%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.159ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.043ns (routing 0.483ns, distribution 0.560ns) Clock Net Delay (Destination): 1.229ns (routing 0.551ns, distribution 0.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.043 1.159 g_gbt_bank[2].gbtbank_n_64 SLICE_X38Y181 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][72]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y181 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.207 r SFP_GEN[28].rx_data_ngccm_reg[28][72]/Q net (fo=1, routed) 0.071 1.278 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[83]_0[64] SLICE_X39Y181 LUT3 (Prop_B6LUT_SLICEM_I1_O) 0.031 1.309 r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40[72]_i_1/O net (fo=1, routed) 0.015 1.324 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40[72]_i_1_n_0 SLICE_X39Y181 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[72]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y181 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[72]/C clock pessimism -0.151 1.230 SLICE_X39Y181 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.286 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[72] ------------------------------------------------------------------- required time -1.286 arrival time 1.324 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.179ns (logic 0.089ns (49.721%) route 0.090ns (50.279%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.151ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.035ns (routing 0.483ns, distribution 0.552ns) Clock Net Delay (Destination): 1.234ns (routing 0.551ns, distribution 0.683ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.035 1.151 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/CLK SLICE_X36Y185 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y185 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.200 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/Q net (fo=3, routed) 0.078 1.278 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/decoder/READY_O SLICE_X37Y185 LUT5 (Prop_D5LUT_SLICEM_I4_O) 0.040 1.318 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/decoder/RX_ISDATA_FLAG_O0/O net (fo=1, routed) 0.012 1.330 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_I SLICE_X37Y185 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/CLK SLICE_X37Y185 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.151 1.235 SLICE_X37Y185 FDCE (Hold_DFF2_SLICEM_C_D) 0.056 1.291 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.291 arrival time 1.330 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.096ns (50.794%) route 0.093ns (49.206%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.399ns Source Clock Delay (SCD): 1.156ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.040ns (routing 0.483ns, distribution 0.557ns) Clock Net Delay (Destination): 1.247ns (routing 0.551ns, distribution 0.696ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.156 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X43Y189 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y189 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.205 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.077 1.282 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in SLICE_X44Y189 LUT3 (Prop_H6LUT_SLICEM_I2_O) 0.047 1.329 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__27/O net (fo=1, routed) 0.016 1.345 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] SLICE_X44Y189 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.247 1.399 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X44Y189 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.151 1.248 SLICE_X44Y189 FDRE (Hold_HFF_SLICEM_C_D) 0.056 1.304 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.304 arrival time 1.345 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.101ns (52.604%) route 0.091ns (47.396%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.394ns Source Clock Delay (SCD): 1.149ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.033ns (routing 0.483ns, distribution 0.550ns) Clock Net Delay (Destination): 1.242ns (routing 0.551ns, distribution 0.691ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.033 1.149 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X39Y180 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y180 FDCE (Prop_EFF2_SLICEM_C_Q) 0.048 1.197 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.076 1.273 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_7_in SLICE_X38Y180 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.053 1.326 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__27/O net (fo=1, routed) 0.015 1.341 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] SLICE_X38Y180 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.242 1.394 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X38Y180 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.151 1.243 SLICE_X38Y180 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.299 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.299 arrival time 1.341 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.104ns (54.450%) route 0.087ns (45.550%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.370ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.014ns (routing 0.483ns, distribution 0.531ns) Clock Net Delay (Destination): 1.218ns (routing 0.551ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X40Y179 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y179 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.076 1.255 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_7_in SLICE_X38Y179 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.055 1.310 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__27/O net (fo=1, routed) 0.011 1.321 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] SLICE_X38Y179 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.370 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X38Y179 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.148 1.222 SLICE_X38Y179 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.278 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -1.278 arrival time 1.321 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.102ns (52.850%) route 0.091ns (47.150%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.370ns Source Clock Delay (SCD): 1.130ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.014ns (routing 0.483ns, distribution 0.531ns) Clock Net Delay (Destination): 1.218ns (routing 0.551ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.130 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X40Y179 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y179 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.179 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.079 1.258 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_7_in SLICE_X38Y179 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.053 1.311 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__27/O net (fo=1, routed) 0.012 1.323 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[4] SLICE_X38Y179 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.370 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X38Y179 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.148 1.222 SLICE_X38Y179 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.278 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.278 arrival time 1.323 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].rx_data_ngccm_reg[28][3]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_30 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.048ns (27.586%) route 0.126ns (72.414%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.381ns Source Clock Delay (SCD): 1.158ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.042ns (routing 0.483ns, distribution 0.559ns) Clock Net Delay (Destination): 1.229ns (routing 0.551ns, distribution 0.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.042 1.158 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X42Y188 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y188 FDRE (Prop_HFF2_SLICEM_C_Q) 0.048 1.206 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/Q net (fo=1, routed) 0.126 1.332 rx_data[28][3] SLICE_X41Y188 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.229 1.381 g_gbt_bank[2].gbtbank_n_64 SLICE_X41Y188 FDCE r SFP_GEN[28].rx_data_ngccm_reg[28][3]/C clock pessimism -0.151 1.230 SLICE_X41Y188 FDCE (Hold_BFF2_SLICEM_C_D) 0.056 1.286 SFP_GEN[28].rx_data_ngccm_reg[28][3] ------------------------------------------------------------------- required time -1.286 arrival time 1.332 ------------------------------------------------------------------- slack 0.046 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_30 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y78 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y236 g_clock_rate_din[28].ngccm_status_cnt_reg[28][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y235 g_clock_rate_din[28].ngccm_status_cnt_reg[28][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y236 g_clock_rate_din[28].ngccm_status_cnt_reg[28][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y235 g_clock_rate_din[28].ngccm_status_cnt_reg[28][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y236 g_clock_rate_din[28].ngccm_status_cnt_reg[28][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y235 g_clock_rate_din[28].ngccm_status_cnt_reg[28][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y237 g_clock_rate_din[28].ngccm_status_cnt_reg[28][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y195 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y195 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X44Y189 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X44Y189 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X44Y189 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X44Y189 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y236 g_clock_rate_din[28].ngccm_status_cnt_reg[28][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y235 g_clock_rate_din[28].ngccm_status_cnt_reg[28][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y236 g_clock_rate_din[28].ngccm_status_cnt_reg[28][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y235 g_clock_rate_din[28].ngccm_status_cnt_reg[28][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y236 g_clock_rate_din[28].ngccm_status_cnt_reg[28][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y235 g_clock_rate_din[28].ngccm_status_cnt_reg[28][5]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y12 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_31 To Clock: gtwiz_userclk_rx_srcclk_out[0]_31 Setup : 0 Failing Endpoints, Worst Slack 3.016ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.016ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 5.060ns (logic 1.556ns (30.751%) route 3.504ns (69.249%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.400ns = ( 10.717 - 8.317 ) Source Clock Delay (SCD): 2.753ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.328ns (routing 0.804ns, distribution 1.524ns) Clock Net Delay (Destination): 2.024ns (routing 0.721ns, distribution 1.303ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.328 2.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.839 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.610 6.449 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X29Y217 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.266 6.959 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X29Y217 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.226 7.185 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__29/O net (fo=3, routed) 0.628 7.813 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X27Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.024 10.717 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X27Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.205 10.922 clock uncertainty -0.035 10.887 SLICE_X27Y216 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.829 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.829 arrival time -7.813 ------------------------------------------------------------------- slack 3.016 Slack (MET) : 3.023ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 5.056ns (logic 1.556ns (30.775%) route 3.500ns (69.225%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.400ns = ( 10.717 - 8.317 ) Source Clock Delay (SCD): 2.753ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.328ns (routing 0.804ns, distribution 1.524ns) Clock Net Delay (Destination): 2.024ns (routing 0.721ns, distribution 1.303ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.328 2.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.839 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.610 6.449 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X29Y217 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.266 6.959 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X29Y217 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.226 7.185 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__29/O net (fo=3, routed) 0.624 7.809 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X27Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.024 10.717 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X27Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.205 10.922 clock uncertainty -0.035 10.887 SLICE_X27Y216 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.832 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 10.832 arrival time -7.809 ------------------------------------------------------------------- slack 3.023 Slack (MET) : 3.126ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.966ns (logic 1.753ns (35.300%) route 3.213ns (64.700%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.413ns = ( 10.730 - 8.317 ) Source Clock Delay (SCD): 2.753ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.328ns (routing 0.804ns, distribution 1.524ns) Clock Net Delay (Destination): 2.037ns (routing 0.721ns, distribution 1.316ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.328 2.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.839 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.610 6.449 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X29Y217 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.200 6.893 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X29Y216 LUT4 (Prop_B5LUT_SLICEM_I2_O) 0.277 7.170 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28/O net (fo=1, routed) 0.146 7.316 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28_n_0 SLICE_X29Y216 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.462 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28/O net (fo=2, routed) 0.257 7.719 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28_n_0 SLICE_X30Y216 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.037 10.730 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X30Y216 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.205 10.935 clock uncertainty -0.035 10.900 SLICE_X30Y216 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 10.845 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.845 arrival time -7.719 ------------------------------------------------------------------- slack 3.126 Slack (MET) : 3.126ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.966ns (logic 1.753ns (35.300%) route 3.213ns (64.700%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.413ns = ( 10.730 - 8.317 ) Source Clock Delay (SCD): 2.753ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.328ns (routing 0.804ns, distribution 1.524ns) Clock Net Delay (Destination): 2.037ns (routing 0.721ns, distribution 1.316ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.328 2.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.839 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.610 6.449 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X29Y217 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.200 6.893 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X29Y216 LUT4 (Prop_B5LUT_SLICEM_I2_O) 0.277 7.170 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28/O net (fo=1, routed) 0.146 7.316 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28_n_0 SLICE_X29Y216 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.462 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28/O net (fo=2, routed) 0.257 7.719 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28_n_0 SLICE_X30Y216 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.037 10.730 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X30Y216 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.205 10.935 clock uncertainty -0.035 10.900 SLICE_X30Y216 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 10.845 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.845 arrival time -7.719 ------------------------------------------------------------------- slack 3.126 Slack (MET) : 3.146ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.933ns (logic 1.556ns (31.543%) route 3.377ns (68.457%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.400ns = ( 10.717 - 8.317 ) Source Clock Delay (SCD): 2.753ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.328ns (routing 0.804ns, distribution 1.524ns) Clock Net Delay (Destination): 2.024ns (routing 0.721ns, distribution 1.303ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.328 2.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.839 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.610 6.449 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X29Y217 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.266 6.959 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X29Y217 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.226 7.185 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__29/O net (fo=3, routed) 0.501 7.686 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X28Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.024 10.717 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X28Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.205 10.922 clock uncertainty -0.035 10.887 SLICE_X28Y216 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 10.832 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 10.832 arrival time -7.686 ------------------------------------------------------------------- slack 3.146 Slack (MET) : 3.187ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.894ns (logic 1.554ns (31.753%) route 3.340ns (68.247%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.402ns = ( 10.719 - 8.317 ) Source Clock Delay (SCD): 2.753ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.328ns (routing 0.804ns, distribution 1.524ns) Clock Net Delay (Destination): 2.026ns (routing 0.721ns, distribution 1.305ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.328 2.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.839 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.610 6.449 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X29Y217 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.333 7.026 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X29Y216 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.224 7.250 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/O net (fo=7, routed) 0.397 7.647 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X27Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.026 10.719 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X27Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.205 10.924 clock uncertainty -0.035 10.889 SLICE_X27Y216 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.834 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.834 arrival time -7.647 ------------------------------------------------------------------- slack 3.187 Slack (MET) : 3.192ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.890ns (logic 1.554ns (31.779%) route 3.336ns (68.221%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.402ns = ( 10.719 - 8.317 ) Source Clock Delay (SCD): 2.753ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.328ns (routing 0.804ns, distribution 1.524ns) Clock Net Delay (Destination): 2.026ns (routing 0.721ns, distribution 1.305ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.328 2.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.839 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.610 6.449 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X29Y217 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.333 7.026 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X29Y216 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.224 7.250 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/O net (fo=7, routed) 0.393 7.643 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X27Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.026 10.719 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X27Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.205 10.924 clock uncertainty -0.035 10.889 SLICE_X27Y216 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 10.835 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.835 arrival time -7.643 ------------------------------------------------------------------- slack 3.192 Slack (MET) : 3.258ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.838ns (logic 1.554ns (32.121%) route 3.284ns (67.879%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.132ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.416ns = ( 10.733 - 8.317 ) Source Clock Delay (SCD): 2.753ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.328ns (routing 0.804ns, distribution 1.524ns) Clock Net Delay (Destination): 2.040ns (routing 0.721ns, distribution 1.319ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.328 2.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.839 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.610 6.449 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X29Y217 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.333 7.026 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X29Y216 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.224 7.250 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/O net (fo=7, routed) 0.341 7.591 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X29Y217 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.040 10.733 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X29Y217 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.205 10.938 clock uncertainty -0.035 10.903 SLICE_X29Y217 FDRE (Setup_AFF_SLICEM_C_CE) -0.054 10.849 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.849 arrival time -7.591 ------------------------------------------------------------------- slack 3.258 Slack (MET) : 3.261ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.813ns (logic 1.554ns (32.288%) route 3.259ns (67.712%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.398ns = ( 10.715 - 8.317 ) Source Clock Delay (SCD): 2.753ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.328ns (routing 0.804ns, distribution 1.524ns) Clock Net Delay (Destination): 2.022ns (routing 0.721ns, distribution 1.301ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.328 2.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.839 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.610 6.449 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X29Y217 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.333 7.026 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X29Y216 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.224 7.250 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/O net (fo=7, routed) 0.316 7.566 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X28Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.022 10.715 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X28Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.205 10.920 clock uncertainty -0.035 10.885 SLICE_X28Y216 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.827 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.827 arrival time -7.566 ------------------------------------------------------------------- slack 3.261 Slack (MET) : 3.267ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 4.810ns (logic 1.554ns (32.308%) route 3.256ns (67.692%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.398ns = ( 10.715 - 8.317 ) Source Clock Delay (SCD): 2.753ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.328ns (routing 0.804ns, distribution 1.524ns) Clock Net Delay (Destination): 2.022ns (routing 0.721ns, distribution 1.301ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.328 2.753 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.839 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.610 6.449 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X29Y217 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/O net (fo=5, routed) 0.333 7.026 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X29Y216 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.224 7.250 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/O net (fo=7, routed) 0.313 7.563 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X28Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.022 10.715 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X28Y216 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.205 10.920 clock uncertainty -0.035 10.885 SLICE_X28Y216 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.830 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.830 arrival time -7.563 ------------------------------------------------------------------- slack 3.267 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.034ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.049ns (34.507%) route 0.093ns (65.493%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.257ns Source Clock Delay (SCD): 1.030ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 0.914ns (routing 0.382ns, distribution 0.532ns) Clock Net Delay (Destination): 1.105ns (routing 0.446ns, distribution 0.659ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.914 1.030 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X36Y216 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y216 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.079 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]/Q net (fo=1, routed) 0.093 1.172 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[21] SLICE_X36Y217 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.105 1.257 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X36Y217 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]/C clock pessimism -0.175 1.082 SLICE_X36Y217 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21] ------------------------------------------------------------------- required time -1.138 arrival time 1.172 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[29].rx_data_ngccm_reg[29][21]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.168ns (logic 0.049ns (29.167%) route 0.119ns (70.833%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.245ns Source Clock Delay (SCD): 1.032ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.916ns (routing 0.382ns, distribution 0.534ns) Clock Net Delay (Destination): 1.093ns (routing 0.446ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.916 1.032 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X34Y222 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y222 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.081 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/Q net (fo=1, routed) 0.119 1.200 rx_data[29][21] SLICE_X35Y222 FDCE r SFP_GEN[29].rx_data_ngccm_reg[29][21]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.093 1.245 g_gbt_bank[2].gbtbank_n_74 SLICE_X35Y222 FDCE r SFP_GEN[29].rx_data_ngccm_reg[29][21]/C clock pessimism -0.143 1.102 SLICE_X35Y222 FDCE (Hold_FFF2_SLICEM_C_D) 0.055 1.157 SFP_GEN[29].rx_data_ngccm_reg[29][21] ------------------------------------------------------------------- required time -1.157 arrival time 1.200 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_rx_rs_err[29].rx_rs_err_cnt_reg[29]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.064ns (33.508%) route 0.127ns (66.492%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.265ns Source Clock Delay (SCD): 1.033ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.917ns (routing 0.382ns, distribution 0.535ns) Clock Net Delay (Destination): 1.113ns (routing 0.446ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.917 1.033 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/CLK SLICE_X34Y224 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y224 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.082 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/Q net (fo=4, routed) 0.111 1.193 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg_0 SLICE_X35Y224 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.015 1.208 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/g_rx_rs_err[29].rx_rs_err_cnt[29]_i_1/O net (fo=1, routed) 0.016 1.224 g_gbt_bank[2].gbtbank_n_195 SLICE_X35Y224 FDRE r g_rx_rs_err[29].rx_rs_err_cnt_reg[29]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.113 1.265 g_gbt_bank[2].gbtbank_n_74 SLICE_X35Y224 FDRE r g_rx_rs_err[29].rx_rs_err_cnt_reg[29]/C clock pessimism -0.142 1.123 SLICE_X35Y224 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.179 g_rx_rs_err[29].rx_rs_err_cnt_reg[29] ------------------------------------------------------------------- required time -1.179 arrival time 1.224 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.259ns Source Clock Delay (SCD): 1.030ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 0.914ns (routing 0.382ns, distribution 0.532ns) Clock Net Delay (Destination): 1.107ns (routing 0.446ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.914 1.030 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X32Y211 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y211 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.079 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.034 1.113 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_11_in SLICE_X32Y211 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.158 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__28/O net (fo=1, routed) 0.016 1.174 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[4] SLICE_X32Y211 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.107 1.259 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X32Y211 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.187 1.072 SLICE_X32Y211 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.128 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.128 arrival time 1.174 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.050ns (arrival time - required time) Source: SFP_GEN[29].rx_data_ngccm_reg[29][44]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[44]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.095ns (64.626%) route 0.052ns (35.374%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.268ns Source Clock Delay (SCD): 1.039ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 0.923ns (routing 0.382ns, distribution 0.541ns) Clock Net Delay (Destination): 1.116ns (routing 0.446ns, distribution 0.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.923 1.039 g_gbt_bank[2].gbtbank_n_74 SLICE_X31Y216 FDCE r SFP_GEN[29].rx_data_ngccm_reg[29][44]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y216 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.088 r SFP_GEN[29].rx_data_ngccm_reg[29][44]/Q net (fo=1, routed) 0.036 1.124 SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[83]_0[36] SLICE_X31Y216 LUT3 (Prop_D6LUT_SLICEM_I1_O) 0.046 1.170 r SFP_GEN[29].ngCCM_gbt/RX_Word_rx40[44]_i_1/O net (fo=1, routed) 0.016 1.186 SFP_GEN[29].ngCCM_gbt/RX_Word_rx40[44]_i_1_n_0 SLICE_X31Y216 FDCE r SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[44]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.116 1.268 SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X31Y216 FDCE r SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[44]/C clock pessimism -0.188 1.080 SLICE_X31Y216 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.136 SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[44] ------------------------------------------------------------------- required time -1.136 arrival time 1.186 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.259ns Source Clock Delay (SCD): 1.030ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 0.914ns (routing 0.382ns, distribution 0.532ns) Clock Net Delay (Destination): 1.107ns (routing 0.446ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.914 1.030 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X32Y211 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y211 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.079 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.034 1.113 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_11_in SLICE_X32Y211 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.055 1.168 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__28/O net (fo=1, routed) 0.011 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[6] SLICE_X32Y211 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.107 1.259 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X32Y211 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism -0.187 1.072 SLICE_X32Y211 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.128 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time -1.128 arrival time 1.179 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.103ns (66.026%) route 0.053ns (33.974%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.262ns Source Clock Delay (SCD): 1.036ns Clock Pessimism Removal (CPR): 0.177ns Clock Net Delay (Source): 0.920ns (routing 0.382ns, distribution 0.538ns) Clock Net Delay (Destination): 1.110ns (routing 0.446ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.920 1.036 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X31Y213 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y213 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.085 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.037 1.122 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in SLICE_X31Y212 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.054 1.176 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__28/O net (fo=1, routed) 0.016 1.192 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[10] SLICE_X31Y212 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.110 1.262 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X31Y212 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.177 1.085 SLICE_X31Y212 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.141 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.141 arrival time 1.192 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr_reg_inv/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.079ns (44.382%) route 0.099ns (55.618%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.254ns Source Clock Delay (SCD): 1.042ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.926ns (routing 0.382ns, distribution 0.544ns) Clock Net Delay (Destination): 1.102ns (routing 0.446ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.926 1.042 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X29Y217 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/C ------------------------------------------------------------------- ------------------- SLICE_X29Y217 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.090 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/Q net (fo=10, routed) 0.083 1.173 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_to_bitSlipCtrller_5 SLICE_X31Y218 LUT6 (Prop_D6LUT_SLICEM_I0_O) 0.031 1.204 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr_inv_i_1__29/O net (fo=1, routed) 0.016 1.220 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr3_out SLICE_X31Y218 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr_reg_inv/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.102 1.254 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X31Y218 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr_reg_inv/C clock pessimism -0.142 1.112 SLICE_X31Y218 FDPE (Hold_DFF_SLICEM_C_D) 0.056 1.168 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/shiftPsAddr_reg_inv ------------------------------------------------------------------- required time -1.168 arrival time 1.220 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.053ns (arrival time - required time) Source: SFP_GEN[29].rx_data_ngccm_reg[29][28]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.179ns (logic 0.048ns (26.816%) route 0.131ns (73.184%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.245ns Source Clock Delay (SCD): 1.032ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.916ns (routing 0.382ns, distribution 0.534ns) Clock Net Delay (Destination): 1.093ns (routing 0.446ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.916 1.032 g_gbt_bank[2].gbtbank_n_74 SLICE_X35Y223 FDCE r SFP_GEN[29].rx_data_ngccm_reg[29][28]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y223 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.080 r SFP_GEN[29].rx_data_ngccm_reg[29][28]/Q net (fo=1, routed) 0.131 1.211 SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[83]_0[20] SLICE_X38Y223 FDCE r SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.093 1.245 SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X38Y223 FDCE r SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.143 1.102 SLICE_X38Y223 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.158 SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.158 arrival time 1.211 ------------------------------------------------------------------- slack 0.053 Slack (MET) : 0.053ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_31 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.151ns (logic 0.093ns (61.589%) route 0.058ns (38.411%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.270ns Source Clock Delay (SCD): 1.040ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 0.924ns (routing 0.382ns, distribution 0.542ns) Clock Net Delay (Destination): 1.118ns (routing 0.446ns, distribution 0.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.924 1.040 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X30Y217 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y217 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.088 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[2]/Q net (fo=8, routed) 0.042 1.130 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress[2] SLICE_X30Y217 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.175 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_i_1__29/O net (fo=1, routed) 0.016 1.191 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_i_1__29_n_0 SLICE_X30Y217 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.118 1.270 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK SLICE_X30Y217 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_reg/C clock pessimism -0.188 1.082 SLICE_X30Y217 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.138 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/headerFlag_s_reg ------------------------------------------------------------------- required time -1.138 arrival time 1.191 ------------------------------------------------------------------- slack 0.053 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_31 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y95 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y238 g_clock_rate_din[29].ngccm_status_cnt_reg[29][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y238 g_clock_rate_din[29].ngccm_status_cnt_reg[29][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y238 g_clock_rate_din[29].ngccm_status_cnt_reg[29][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y238 g_clock_rate_din[29].ngccm_status_cnt_reg[29][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y238 g_clock_rate_din[29].ngccm_status_cnt_reg[29][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y238 g_clock_rate_din[29].ngccm_status_cnt_reg[29][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y238 g_clock_rate_din[29].ngccm_status_cnt_reg[29][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y238 g_clock_rate_din[29].ngccm_status_cnt_reg[29][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y238 g_clock_rate_din[29].ngccm_status_cnt_reg[29][3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y238 g_clock_rate_din[29].ngccm_status_cnt_reg[29][4]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X36Y227 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X36Y227 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X32Y222 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X38Y224 g_clock_rate_din[29].rx_frameclk_div2_reg[29]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X36Y224 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[5].rx_data_good_cntr_reg[5][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X36Y224 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[5].rx_data_good_cntr_reg[5][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X36Y224 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[5].rx_data_good_cntr_reg[5][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X36Y224 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[5].rx_data_good_cntr_reg[5][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X36Y224 g_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[5].rx_data_good_cntr_reg[5][4]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y13 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_32 To Clock: gtwiz_userclk_rx_srcclk_out[0]_32 Setup : 0 Failing Endpoints, Worst Slack 3.761ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.048ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.761ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].ngccm_status_reg_reg[30][21]/CE (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 4.598ns (logic 0.408ns (8.873%) route 4.190ns (91.127%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.652ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.227ns (routing 0.667ns, distribution 1.560ns) Clock Net Delay (Destination): 2.216ns (routing 0.603ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.227 2.652 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y213 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y213 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.792 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.296 6.088 SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X55Y236 LUT2 (Prop_C5LUT_SLICEM_I1_O) 0.268 6.356 r SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/O net (fo=18, routed) 0.894 7.250 rx_test_comm_cnt235_out SLICE_X55Y236 FDPE r SFP_GEN[30].ngccm_status_reg_reg[30][21]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[2].gbtbank_n_84 SLICE_X55Y236 FDPE r SFP_GEN[30].ngccm_status_reg_reg[30][21]/C clock pessimism 0.195 11.104 clock uncertainty -0.035 11.069 SLICE_X55Y236 FDPE (Setup_HFF2_SLICEM_C_CE) -0.058 11.011 SFP_GEN[30].ngccm_status_reg_reg[30][21] ------------------------------------------------------------------- required time 11.011 arrival time -7.250 ------------------------------------------------------------------- slack 3.761 Slack (MET) : 3.761ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].ngccm_status_reg_reg[30][2]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 4.598ns (logic 0.408ns (8.873%) route 4.190ns (91.127%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.652ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.227ns (routing 0.667ns, distribution 1.560ns) Clock Net Delay (Destination): 2.216ns (routing 0.603ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.227 2.652 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y213 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y213 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.792 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.296 6.088 SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X55Y236 LUT2 (Prop_C5LUT_SLICEM_I1_O) 0.268 6.356 r SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/O net (fo=18, routed) 0.894 7.250 rx_test_comm_cnt235_out SLICE_X55Y236 FDCE r SFP_GEN[30].ngccm_status_reg_reg[30][2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[2].gbtbank_n_84 SLICE_X55Y236 FDCE r SFP_GEN[30].ngccm_status_reg_reg[30][2]/C clock pessimism 0.195 11.104 clock uncertainty -0.035 11.069 SLICE_X55Y236 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 11.011 SFP_GEN[30].ngccm_status_reg_reg[30][2] ------------------------------------------------------------------- required time 11.011 arrival time -7.250 ------------------------------------------------------------------- slack 3.761 Slack (MET) : 3.761ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].ngccm_status_reg_reg[30][7]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 4.598ns (logic 0.408ns (8.873%) route 4.190ns (91.127%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.652ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.227ns (routing 0.667ns, distribution 1.560ns) Clock Net Delay (Destination): 2.216ns (routing 0.603ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.227 2.652 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y213 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y213 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.792 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.296 6.088 SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X55Y236 LUT2 (Prop_C5LUT_SLICEM_I1_O) 0.268 6.356 r SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/O net (fo=18, routed) 0.894 7.250 rx_test_comm_cnt235_out SLICE_X55Y236 FDCE r SFP_GEN[30].ngccm_status_reg_reg[30][7]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[2].gbtbank_n_84 SLICE_X55Y236 FDCE r SFP_GEN[30].ngccm_status_reg_reg[30][7]/C clock pessimism 0.195 11.104 clock uncertainty -0.035 11.069 SLICE_X55Y236 FDCE (Setup_FFF2_SLICEM_C_CE) -0.058 11.011 SFP_GEN[30].ngccm_status_reg_reg[30][7] ------------------------------------------------------------------- required time 11.011 arrival time -7.250 ------------------------------------------------------------------- slack 3.761 Slack (MET) : 3.767ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].ngccm_status_reg_reg[30][18]/CE (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 4.595ns (logic 0.408ns (8.879%) route 4.187ns (91.121%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.652ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.227ns (routing 0.667ns, distribution 1.560ns) Clock Net Delay (Destination): 2.216ns (routing 0.603ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.227 2.652 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y213 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y213 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.792 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.296 6.088 SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X55Y236 LUT2 (Prop_C5LUT_SLICEM_I1_O) 0.268 6.356 r SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/O net (fo=18, routed) 0.891 7.247 rx_test_comm_cnt235_out SLICE_X55Y236 FDPE r SFP_GEN[30].ngccm_status_reg_reg[30][18]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[2].gbtbank_n_84 SLICE_X55Y236 FDPE r SFP_GEN[30].ngccm_status_reg_reg[30][18]/C clock pessimism 0.195 11.104 clock uncertainty -0.035 11.069 SLICE_X55Y236 FDPE (Setup_EFF_SLICEM_C_CE) -0.055 11.014 SFP_GEN[30].ngccm_status_reg_reg[30][18] ------------------------------------------------------------------- required time 11.014 arrival time -7.247 ------------------------------------------------------------------- slack 3.767 Slack (MET) : 3.767ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].ngccm_status_reg_reg[30][23]/CE (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 4.595ns (logic 0.408ns (8.879%) route 4.187ns (91.121%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.652ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.227ns (routing 0.667ns, distribution 1.560ns) Clock Net Delay (Destination): 2.216ns (routing 0.603ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.227 2.652 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y213 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y213 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.792 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.296 6.088 SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X55Y236 LUT2 (Prop_C5LUT_SLICEM_I1_O) 0.268 6.356 r SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/O net (fo=18, routed) 0.891 7.247 rx_test_comm_cnt235_out SLICE_X55Y236 FDPE r SFP_GEN[30].ngccm_status_reg_reg[30][23]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[2].gbtbank_n_84 SLICE_X55Y236 FDPE r SFP_GEN[30].ngccm_status_reg_reg[30][23]/C clock pessimism 0.195 11.104 clock uncertainty -0.035 11.069 SLICE_X55Y236 FDPE (Setup_HFF_SLICEM_C_CE) -0.055 11.014 SFP_GEN[30].ngccm_status_reg_reg[30][23] ------------------------------------------------------------------- required time 11.014 arrival time -7.247 ------------------------------------------------------------------- slack 3.767 Slack (MET) : 3.767ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].ngccm_status_reg_reg[30][5]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 4.595ns (logic 0.408ns (8.879%) route 4.187ns (91.121%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.652ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.227ns (routing 0.667ns, distribution 1.560ns) Clock Net Delay (Destination): 2.216ns (routing 0.603ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.227 2.652 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y213 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y213 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.792 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.296 6.088 SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X55Y236 LUT2 (Prop_C5LUT_SLICEM_I1_O) 0.268 6.356 r SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/O net (fo=18, routed) 0.891 7.247 rx_test_comm_cnt235_out SLICE_X55Y236 FDCE r SFP_GEN[30].ngccm_status_reg_reg[30][5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[2].gbtbank_n_84 SLICE_X55Y236 FDCE r SFP_GEN[30].ngccm_status_reg_reg[30][5]/C clock pessimism 0.195 11.104 clock uncertainty -0.035 11.069 SLICE_X55Y236 FDCE (Setup_FFF_SLICEM_C_CE) -0.055 11.014 SFP_GEN[30].ngccm_status_reg_reg[30][5] ------------------------------------------------------------------- required time 11.014 arrival time -7.247 ------------------------------------------------------------------- slack 3.767 Slack (MET) : 3.767ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].ngccm_status_reg_reg[30][8]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 4.595ns (logic 0.408ns (8.879%) route 4.187ns (91.121%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.135ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.652ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.227ns (routing 0.667ns, distribution 1.560ns) Clock Net Delay (Destination): 2.216ns (routing 0.603ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.227 2.652 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y213 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y213 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 2.792 r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.296 6.088 SFP_GEN[30].ngCCM_gbt/RX_CLKEN_O[0] SLICE_X55Y236 LUT2 (Prop_C5LUT_SLICEM_I1_O) 0.268 6.356 r SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_1/O net (fo=18, routed) 0.891 7.247 rx_test_comm_cnt235_out SLICE_X55Y236 FDCE r SFP_GEN[30].ngccm_status_reg_reg[30][8]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[2].gbtbank_n_84 SLICE_X55Y236 FDCE r SFP_GEN[30].ngccm_status_reg_reg[30][8]/C clock pessimism 0.195 11.104 clock uncertainty -0.035 11.069 SLICE_X55Y236 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.014 SFP_GEN[30].ngccm_status_reg_reg[30][8] ------------------------------------------------------------------- required time 11.014 arrival time -7.247 ------------------------------------------------------------------- slack 3.767 Slack (MET) : 3.818ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][66]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 4.463ns (logic 0.285ns (6.386%) route 4.178ns (93.614%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.596ns = ( 10.913 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 2.220ns (routing 0.603ns, distribution 1.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.785 4.660 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 4.806 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 2.393 7.199 rx_data_ngccm[30] SLICE_X49Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][66]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.220 10.913 g_gbt_bank[2].gbtbank_n_84 SLICE_X49Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][66]/C clock pessimism 0.194 11.107 clock uncertainty -0.035 11.072 SLICE_X49Y201 FDCE (Setup_AFF2_SLICEM_C_CE) -0.055 11.017 SFP_GEN[30].rx_data_ngccm_reg[30][66] ------------------------------------------------------------------- required time 11.017 arrival time -7.199 ------------------------------------------------------------------- slack 3.818 Slack (MET) : 3.818ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][70]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 4.463ns (logic 0.285ns (6.386%) route 4.178ns (93.614%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.596ns = ( 10.913 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 2.220ns (routing 0.603ns, distribution 1.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.785 4.660 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 4.806 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 2.393 7.199 rx_data_ngccm[30] SLICE_X49Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][70]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.220 10.913 g_gbt_bank[2].gbtbank_n_84 SLICE_X49Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][70]/C clock pessimism 0.194 11.107 clock uncertainty -0.035 11.072 SLICE_X49Y201 FDCE (Setup_BFF2_SLICEM_C_CE) -0.055 11.017 SFP_GEN[30].rx_data_ngccm_reg[30][70] ------------------------------------------------------------------- required time 11.017 arrival time -7.199 ------------------------------------------------------------------- slack 3.818 Slack (MET) : 3.818ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][73]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 4.463ns (logic 0.285ns (6.386%) route 4.178ns (93.614%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.596ns = ( 10.913 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 2.220ns (routing 0.603ns, distribution 1.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.785 4.660 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.146 4.806 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/O net (fo=76, routed) 2.393 7.199 rx_data_ngccm[30] SLICE_X49Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][73]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.220 10.913 g_gbt_bank[2].gbtbank_n_84 SLICE_X49Y201 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][73]/C clock pessimism 0.194 11.107 clock uncertainty -0.035 11.072 SLICE_X49Y201 FDCE (Setup_CFF2_SLICEM_C_CE) -0.055 11.017 SFP_GEN[30].rx_data_ngccm_reg[30][73] ------------------------------------------------------------------- required time 11.017 arrival time -7.199 ------------------------------------------------------------------- slack 3.818 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.291ns Source Clock Delay (SCD): 1.078ns Clock Pessimism Removal (CPR): 0.208ns Clock Net Delay (Source): 0.962ns (routing 0.301ns, distribution 0.661ns) Clock Net Delay (Destination): 1.139ns (routing 0.348ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.962 1.078 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK SLICE_X49Y200 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X49Y200 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 1.127 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/Q net (fo=4, routed) 0.033 1.160 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/error_detected_msb SLICE_X49Y200 LUT6 (Prop_A6LUT_SLICEM_I5_O) 0.015 1.175 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__59/O net (fo=1, routed) 0.012 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 SLICE_X49Y200 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.139 1.291 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK SLICE_X49Y200 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C clock pessimism -0.208 1.083 SLICE_X49Y200 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.139 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg ------------------------------------------------------------------- required time -1.139 arrival time 1.187 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[37]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[37]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.049ns (25.926%) route 0.140ns (74.074%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.181ns Source Clock Delay (SCD): 0.972ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.856ns (routing 0.301ns, distribution 0.555ns) Clock Net Delay (Destination): 1.029ns (routing 0.348ns, distribution 0.681ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.856 0.972 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y208 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[37]/C ------------------------------------------------------------------- ------------------- SLICE_X44Y208 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.021 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[37]/Q net (fo=1, routed) 0.140 1.161 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[37] SLICE_X43Y208 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.029 1.181 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y208 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[37]/C clock pessimism -0.125 1.056 SLICE_X43Y208 FDCE (Hold_BFF_SLICEL_C_D) 0.056 1.112 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[37] ------------------------------------------------------------------- required time -1.112 arrival time 1.161 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.182ns Source Clock Delay (SCD): 0.972ns Clock Pessimism Removal (CPR): 0.205ns Clock Net Delay (Source): 0.856ns (routing 0.301ns, distribution 0.555ns) Clock Net Delay (Destination): 1.030ns (routing 0.348ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.856 0.972 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y220 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y220 FDRE (Prop_AFF_SLICEL_C_Q) 0.049 1.021 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/Q net (fo=2, routed) 0.035 1.056 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[4] SLICE_X43Y220 LUT6 (Prop_A6LUT_SLICEL_I5_O) 0.015 1.071 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__30/O net (fo=1, routed) 0.012 1.083 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__30_n_0 SLICE_X43Y220 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.030 1.182 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y220 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism -0.205 0.977 SLICE_X43Y220 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.033 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time -1.033 arrival time 1.083 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.164ns Source Clock Delay (SCD): 0.962ns Clock Pessimism Removal (CPR): 0.197ns Clock Net Delay (Source): 0.846ns (routing 0.301ns, distribution 0.545ns) Clock Net Delay (Destination): 1.012ns (routing 0.348ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.846 0.962 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y218 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X43Y218 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.011 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.035 1.046 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/ready_from_bitSlipCtrller_6 SLICE_X43Y218 LUT3 (Prop_A6LUT_SLICEL_I2_O) 0.015 1.061 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_i_1__29/O net (fo=1, routed) 0.012 1.073 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_i_1__29_n_0 SLICE_X43Y218 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.164 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y218 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg/C clock pessimism -0.197 0.967 SLICE_X43Y218 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.023 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.023 arrival time 1.073 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.111ns (logic 0.064ns (57.658%) route 0.047ns (42.342%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.161ns Source Clock Delay (SCD): 0.962ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 0.846ns (routing 0.301ns, distribution 0.545ns) Clock Net Delay (Destination): 1.009ns (routing 0.348ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.846 0.962 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y223 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y223 FDRE (Prop_AFF_SLICEL_C_Q) 0.049 1.011 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Q net (fo=2, routed) 0.035 1.046 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/timer[5] SLICE_X43Y223 LUT6 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.061 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__30/O net (fo=1, routed) 0.012 1.073 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__30_n_0 SLICE_X43Y223 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.161 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y223 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C clock pessimism -0.194 0.967 SLICE_X43Y223 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.023 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/clkSlipProcess.timer_reg[5] ------------------------------------------------------------------- required time -1.023 arrival time 1.073 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[30].rx_data_ngccm_reg[30][32]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.158ns Source Clock Delay (SCD): 0.958ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 0.842ns (routing 0.301ns, distribution 0.541ns) Clock Net Delay (Destination): 1.006ns (routing 0.348ns, distribution 0.658ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.842 0.958 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X46Y210 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y210 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.007 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/Q net (fo=1, routed) 0.095 1.102 rx_data[30][32] SLICE_X46Y211 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][32]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.006 1.158 g_gbt_bank[2].gbtbank_n_84 SLICE_X46Y211 FDCE r SFP_GEN[30].rx_data_ngccm_reg[30][32]/C clock pessimism -0.161 0.997 SLICE_X46Y211 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.052 SFP_GEN[30].rx_data_ngccm_reg[30][32] ------------------------------------------------------------------- required time -1.052 arrival time 1.102 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.063ns (42.568%) route 0.085ns (57.432%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.083ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 0.967ns (routing 0.301ns, distribution 0.666ns) Clock Net Delay (Destination): 1.157ns (routing 0.348ns, distribution 0.809ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.083 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X49Y205 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y205 FDCE (Prop_HFF_SLICEM_C_Q) 0.048 1.131 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.073 1.204 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/O84[0] SLICE_X49Y205 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.219 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__29/O net (fo=1, routed) 0.012 1.231 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] SLICE_X49Y205 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X49Y205 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.185 1.124 SLICE_X49Y205 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.180 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.180 arrival time 1.231 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.151ns (logic 0.104ns (68.874%) route 0.047ns (31.126%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.310ns Source Clock Delay (SCD): 1.081ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 0.965ns (routing 0.301ns, distribution 0.664ns) Clock Net Delay (Destination): 1.158ns (routing 0.348ns, distribution 0.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.965 1.081 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X50Y205 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y205 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.130 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.036 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[1] SLICE_X50Y205 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.055 1.221 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__29/O net (fo=1, routed) 0.011 1.232 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[18] SLICE_X50Y205 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.158 1.310 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X50Y205 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.185 1.125 SLICE_X50Y205 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.181 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -1.181 arrival time 1.232 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.198ns (logic 0.078ns (39.394%) route 0.120ns (60.606%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.182ns Source Clock Delay (SCD): 0.966ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.850ns (routing 0.301ns, distribution 0.549ns) Clock Net Delay (Destination): 1.030ns (routing 0.348ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.850 0.966 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X46Y208 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y208 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.014 f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Q net (fo=28, routed) 0.108 1.122 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] SLICE_X45Y208 LUT5 (Prop_A6LUT_SLICEL_I0_O) 0.030 1.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[20]_i_1__31/O net (fo=1, routed) 0.012 1.164 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg00[20] SLICE_X45Y208 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.030 1.182 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X45Y208 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]/C clock pessimism -0.125 1.057 SLICE_X45Y208 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.113 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20] ------------------------------------------------------------------- required time -1.113 arrival time 1.164 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_32 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.095ns (63.758%) route 0.054ns (36.242%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.083ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 0.967ns (routing 0.301ns, distribution 0.666ns) Clock Net Delay (Destination): 1.157ns (routing 0.348ns, distribution 0.809ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.083 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X49Y205 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y205 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.132 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.038 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in SLICE_X49Y205 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.046 1.216 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__29/O net (fo=1, routed) 0.016 1.232 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] SLICE_X49Y205 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X49Y205 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.185 1.124 SLICE_X49Y205 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.180 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.180 arrival time 1.232 ------------------------------------------------------------------- slack 0.052 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_32 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y75 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y235 g_clock_rate_din[30].ngccm_status_cnt_reg[30][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y235 g_clock_rate_din[30].ngccm_status_cnt_reg[30][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y236 g_clock_rate_din[30].ngccm_status_cnt_reg[30][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y236 g_clock_rate_din[30].ngccm_status_cnt_reg[30][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y236 g_clock_rate_din[30].ngccm_status_cnt_reg[30][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y236 g_clock_rate_din[30].ngccm_status_cnt_reg[30][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y236 g_clock_rate_din[30].ngccm_status_cnt_reg[30][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X58Y219 SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X50Y201 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[72]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X50Y201 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[74]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X46Y215 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C Low Pulse Width Fast FDPE/C n/a 0.275 4.159 3.884 SLICE_X41Y209 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y209 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y221 SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[62]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X58Y219 SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y222 SFP_GEN[30].ngCCM_gbt/RX_Clock_40MHz_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X52Y206 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[44]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X52Y206 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[46]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X52Y205 SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[48]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y14 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_33 To Clock: gtwiz_userclk_rx_srcclk_out[0]_33 Setup : 0 Failing Endpoints, Worst Slack 3.506ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.506ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 4.570ns (logic 1.747ns (38.228%) route 2.823ns (61.772%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.303ns = ( 10.620 - 8.317 ) Source Clock Delay (SCD): 2.643ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.218ns (routing 0.699ns, distribution 1.519ns) Clock Net Delay (Destination): 1.927ns (routing 0.636ns, distribution 1.291ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.218 2.643 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.729 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.996 5.725 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X37Y233 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.969 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.289 6.258 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y234 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.502 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30/O net (fo=1, routed) 0.084 6.586 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30_n_0 SLICE_X35Y234 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 6.759 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30/O net (fo=2, routed) 0.454 7.213 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30_n_0 SLICE_X35Y233 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.927 10.620 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y233 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.188 10.809 clock uncertainty -0.035 10.773 SLICE_X35Y233 FDCE (Setup_CFF_SLICEM_C_CE) -0.054 10.719 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.719 arrival time -7.213 ------------------------------------------------------------------- slack 3.506 Slack (MET) : 3.506ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 4.570ns (logic 1.747ns (38.228%) route 2.823ns (61.772%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.303ns = ( 10.620 - 8.317 ) Source Clock Delay (SCD): 2.643ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.218ns (routing 0.699ns, distribution 1.519ns) Clock Net Delay (Destination): 1.927ns (routing 0.636ns, distribution 1.291ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.218 2.643 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.729 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.996 5.725 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X37Y233 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.969 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.289 6.258 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y234 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.244 6.502 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30/O net (fo=1, routed) 0.084 6.586 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30_n_0 SLICE_X35Y234 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 6.759 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30/O net (fo=2, routed) 0.454 7.213 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30_n_0 SLICE_X35Y233 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.927 10.620 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y233 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.188 10.809 clock uncertainty -0.035 10.773 SLICE_X35Y233 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 10.719 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.719 arrival time -7.213 ------------------------------------------------------------------- slack 3.506 Slack (MET) : 3.681ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 4.407ns (logic 1.476ns (33.492%) route 2.931ns (66.508%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.643ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.218ns (routing 0.699ns, distribution 1.519ns) Clock Net Delay (Destination): 1.940ns (routing 0.636ns, distribution 1.304ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.218 2.643 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.729 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.996 5.725 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X37Y233 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.969 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.288 6.257 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y234 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 6.403 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__31/O net (fo=3, routed) 0.647 7.050 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecFalseHeaders0 SLICE_X36Y234 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.940 10.633 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X36Y234 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.188 10.821 clock uncertainty -0.035 10.786 SLICE_X36Y234 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.731 arrival time -7.050 ------------------------------------------------------------------- slack 3.681 Slack (MET) : 3.686ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 4.403ns (logic 1.476ns (33.523%) route 2.927ns (66.477%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.643ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.218ns (routing 0.699ns, distribution 1.519ns) Clock Net Delay (Destination): 1.940ns (routing 0.636ns, distribution 1.304ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.218 2.643 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.729 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.996 5.725 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X37Y233 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.969 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.288 6.257 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y234 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 6.403 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__31/O net (fo=3, routed) 0.643 7.046 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecFalseHeaders0 SLICE_X36Y234 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.940 10.633 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X36Y234 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.188 10.821 clock uncertainty -0.035 10.786 SLICE_X36Y234 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 10.732 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 10.732 arrival time -7.046 ------------------------------------------------------------------- slack 3.686 Slack (MET) : 3.868ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 4.207ns (logic 1.476ns (35.084%) route 2.731ns (64.916%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.303ns = ( 10.620 - 8.317 ) Source Clock Delay (SCD): 2.643ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.218ns (routing 0.699ns, distribution 1.519ns) Clock Net Delay (Destination): 1.927ns (routing 0.636ns, distribution 1.291ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.218 2.643 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.729 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.996 5.725 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X37Y233 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.969 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.288 6.257 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y234 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.146 6.403 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.447 6.850 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X35Y232 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.927 10.620 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y232 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.188 10.809 clock uncertainty -0.035 10.773 SLICE_X35Y232 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 10.718 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.718 arrival time -6.850 ------------------------------------------------------------------- slack 3.868 Slack (MET) : 3.868ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 4.207ns (logic 1.476ns (35.084%) route 2.731ns (64.916%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.303ns = ( 10.620 - 8.317 ) Source Clock Delay (SCD): 2.643ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.218ns (routing 0.699ns, distribution 1.519ns) Clock Net Delay (Destination): 1.927ns (routing 0.636ns, distribution 1.291ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.218 2.643 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.729 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.996 5.725 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X37Y233 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.969 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.288 6.257 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y234 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.146 6.403 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.447 6.850 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X35Y232 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.927 10.620 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y232 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.188 10.809 clock uncertainty -0.035 10.773 SLICE_X35Y232 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 10.718 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.718 arrival time -6.850 ------------------------------------------------------------------- slack 3.868 Slack (MET) : 3.872ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 4.204ns (logic 1.476ns (35.109%) route 2.728ns (64.891%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.303ns = ( 10.620 - 8.317 ) Source Clock Delay (SCD): 2.643ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.218ns (routing 0.699ns, distribution 1.519ns) Clock Net Delay (Destination): 1.927ns (routing 0.636ns, distribution 1.291ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.218 2.643 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.729 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.996 5.725 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X37Y233 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.969 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.288 6.257 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y234 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.146 6.403 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.444 6.847 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X35Y232 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.927 10.620 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y232 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.188 10.809 clock uncertainty -0.035 10.773 SLICE_X35Y232 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 10.719 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.719 arrival time -6.847 ------------------------------------------------------------------- slack 3.872 Slack (MET) : 3.872ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 4.204ns (logic 1.476ns (35.109%) route 2.728ns (64.891%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.303ns = ( 10.620 - 8.317 ) Source Clock Delay (SCD): 2.643ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.218ns (routing 0.699ns, distribution 1.519ns) Clock Net Delay (Destination): 1.927ns (routing 0.636ns, distribution 1.291ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.218 2.643 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.729 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.996 5.725 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X37Y233 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.969 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.288 6.257 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y234 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.146 6.403 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.444 6.847 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X35Y232 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.927 10.620 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y232 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.188 10.809 clock uncertainty -0.035 10.773 SLICE_X35Y232 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 10.719 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.719 arrival time -6.847 ------------------------------------------------------------------- slack 3.872 Slack (MET) : 3.894ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 4.180ns (logic 1.476ns (35.311%) route 2.704ns (64.689%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.302ns = ( 10.619 - 8.317 ) Source Clock Delay (SCD): 2.643ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.218ns (routing 0.699ns, distribution 1.519ns) Clock Net Delay (Destination): 1.926ns (routing 0.636ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.218 2.643 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.729 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.996 5.725 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X37Y233 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.969 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.288 6.257 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y234 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.146 6.403 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.420 6.823 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X35Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.619 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.188 10.808 clock uncertainty -0.035 10.772 SLICE_X35Y233 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 10.717 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.717 arrival time -6.823 ------------------------------------------------------------------- slack 3.894 Slack (MET) : 3.894ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 4.180ns (logic 1.476ns (35.311%) route 2.704ns (64.689%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.302ns = ( 10.619 - 8.317 ) Source Clock Delay (SCD): 2.643ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.218ns (routing 0.699ns, distribution 1.519ns) Clock Net Delay (Destination): 1.926ns (routing 0.636ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.218 2.643 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.729 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.996 5.725 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X37Y233 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.969 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/O net (fo=5, routed) 0.288 6.257 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X35Y234 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.146 6.403 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/O net (fo=7, routed) 0.420 6.823 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 SLICE_X35Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.619 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y233 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.188 10.808 clock uncertainty -0.035 10.772 SLICE_X35Y233 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.717 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.717 arrival time -6.823 ------------------------------------------------------------------- slack 3.894 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[31].rx_data_ngccm_reg[31][4]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.048ns (29.814%) route 0.113ns (70.186%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.085ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 0.969ns (routing 0.319ns, distribution 0.650ns) Clock Net Delay (Destination): 1.157ns (routing 0.369ns, distribution 0.788ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.969 1.085 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X48Y230 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y230 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.133 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.113 1.246 rx_data[31][4] SLICE_X49Y230 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 g_gbt_bank[2].gbtbank_n_94 SLICE_X49Y230 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][4]/C clock pessimism -0.148 1.161 SLICE_X49Y230 FDCE (Hold_FFF2_SLICEM_C_D) 0.055 1.216 SFP_GEN[31].rx_data_ngccm_reg[31][4] ------------------------------------------------------------------- required time -1.216 arrival time 1.246 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.086ns (50.588%) route 0.084ns (49.412%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.178ns Source Clock Delay (SCD): 0.970ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.854ns (routing 0.319ns, distribution 0.535ns) Clock Net Delay (Destination): 1.026ns (routing 0.369ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.854 0.970 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X44Y237 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X44Y237 FDCE (Prop_BFF2_SLICEM_C_Q) 0.048 1.018 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.073 1.091 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X43Y237 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.038 1.129 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__30/O net (fo=1, routed) 0.011 1.140 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] SLICE_X43Y237 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.178 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X43Y237 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.130 1.048 SLICE_X43Y237 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.104 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -1.104 arrival time 1.140 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[31].rx_data_ngccm_reg[31][79]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.049ns (34.507%) route 0.093ns (65.493%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.178ns Source Clock Delay (SCD): 0.968ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.852ns (routing 0.319ns, distribution 0.533ns) Clock Net Delay (Destination): 1.026ns (routing 0.369ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.968 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X43Y237 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y237 FDRE (Prop_FFF_SLICEL_C_Q) 0.049 1.017 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/Q net (fo=1, routed) 0.093 1.110 rx_data[31][79] SLICE_X43Y238 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][79]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.178 g_gbt_bank[2].gbtbank_n_94 SLICE_X43Y238 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][79]/C clock pessimism -0.163 1.015 SLICE_X43Y238 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.071 SFP_GEN[31].rx_data_ngccm_reg[31][79] ------------------------------------------------------------------- required time -1.071 arrival time 1.110 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[31].rx_data_ngccm_reg[31][69]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.163ns (logic 0.048ns (29.448%) route 0.115ns (70.552%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.968ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.852ns (routing 0.319ns, distribution 0.533ns) Clock Net Delay (Destination): 1.014ns (routing 0.369ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.968 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X43Y234 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y234 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.016 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.115 1.131 rx_data[31][69] SLICE_X44Y234 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][69]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank_n_94 SLICE_X44Y234 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][69]/C clock pessimism -0.130 1.036 SLICE_X44Y234 FDCE (Hold_FFF2_SLICEM_C_D) 0.055 1.091 SFP_GEN[31].rx_data_ngccm_reg[31][69] ------------------------------------------------------------------- required time -1.091 arrival time 1.131 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[31].rx_data_ngccm_reg[31][73]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.178ns Source Clock Delay (SCD): 0.968ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.852ns (routing 0.319ns, distribution 0.533ns) Clock Net Delay (Destination): 1.026ns (routing 0.369ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.968 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X43Y237 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y237 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.016 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.095 1.111 rx_data[31][73] SLICE_X43Y238 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][73]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.178 g_gbt_bank[2].gbtbank_n_94 SLICE_X43Y238 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][73]/C clock pessimism -0.163 1.015 SLICE_X43Y238 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.071 SFP_GEN[31].rx_data_ngccm_reg[31][73] ------------------------------------------------------------------- required time -1.071 arrival time 1.111 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.079ns (46.471%) route 0.091ns (53.529%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.308ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 0.972ns (routing 0.319ns, distribution 0.653ns) Clock Net Delay (Destination): 1.156ns (routing 0.369ns, distribution 0.787ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X49Y230 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y230 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.137 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.075 1.212 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_3_in SLICE_X48Y230 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.030 1.242 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__30/O net (fo=1, routed) 0.016 1.258 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[0] SLICE_X48Y230 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.308 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X48Y230 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.148 1.160 SLICE_X48Y230 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.216 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.216 arrival time 1.258 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.079ns (46.199%) route 0.092ns (53.801%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.308ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 0.972ns (routing 0.319ns, distribution 0.653ns) Clock Net Delay (Destination): 1.156ns (routing 0.369ns, distribution 0.787ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X49Y230 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y230 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.137 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.076 1.213 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in SLICE_X48Y230 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.030 1.243 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__30/O net (fo=1, routed) 0.016 1.259 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] SLICE_X48Y230 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.308 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X48Y230 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.148 1.160 SLICE_X48Y230 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.216 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.216 arrival time 1.259 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[31].rx_data_ngccm_reg[31][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[0]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.080ns (47.059%) route 0.090ns (52.941%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.305ns Source Clock Delay (SCD): 1.087ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 0.971ns (routing 0.319ns, distribution 0.652ns) Clock Net Delay (Destination): 1.153ns (routing 0.369ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.971 1.087 g_gbt_bank[2].gbtbank_n_94 SLICE_X49Y230 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y230 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.136 r SFP_GEN[31].rx_data_ngccm_reg[31][0]/Q net (fo=1, routed) 0.074 1.210 SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[83]_0[0] SLICE_X48Y230 LUT3 (Prop_H6LUT_SLICEL_I1_O) 0.031 1.241 r SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[0]_i_1/O net (fo=1, routed) 0.016 1.257 SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[0]_i_1_n_0 SLICE_X48Y230 FDCE r SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.153 1.305 SFP_GEN[31].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y230 FDCE r SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.148 1.157 SLICE_X48Y230 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.213 SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.213 arrival time 1.257 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[31].rx_data_ngccm_reg[31][37]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[36]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.093ns (50.543%) route 0.091ns (49.457%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.311ns Source Clock Delay (SCD): 1.079ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 0.963ns (routing 0.319ns, distribution 0.644ns) Clock Net Delay (Destination): 1.159ns (routing 0.369ns, distribution 0.790ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.963 1.079 g_gbt_bank[2].gbtbank_n_94 SLICE_X48Y231 FDCE r SFP_GEN[31].rx_data_ngccm_reg[31][37]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y231 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.127 r SFP_GEN[31].rx_data_ngccm_reg[31][37]/Q net (fo=1, routed) 0.075 1.202 SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[83]_0[29] SLICE_X49Y231 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.247 r SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[36]_i_1/O net (fo=1, routed) 0.016 1.263 SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[36]_i_1_n_0 SLICE_X49Y231 FDCE r SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[36]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.159 1.311 SFP_GEN[31].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X49Y231 FDCE r SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.148 1.163 SLICE_X49Y231 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.219 SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -1.219 arrival time 1.263 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_33 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.087ns (50.289%) route 0.086ns (49.711%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.308ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 0.972ns (routing 0.319ns, distribution 0.653ns) Clock Net Delay (Destination): 1.156ns (routing 0.369ns, distribution 0.787ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X49Y230 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y230 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.137 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.075 1.212 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_3_in SLICE_X48Y230 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.038 1.250 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__30/O net (fo=1, routed) 0.011 1.261 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[2] SLICE_X48Y230 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.308 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X48Y230 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.148 1.160 SLICE_X48Y230 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.216 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -1.216 arrival time 1.261 ------------------------------------------------------------------- slack 0.045 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_33 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y77 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y238 g_clock_rate_din[31].ngccm_status_cnt_reg[31][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y238 g_clock_rate_din[31].ngccm_status_cnt_reg[31][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y238 g_clock_rate_din[31].ngccm_status_cnt_reg[31][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y238 g_clock_rate_din[31].ngccm_status_cnt_reg[31][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y237 g_clock_rate_din[31].ngccm_status_cnt_reg[31][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y237 g_clock_rate_din[31].ngccm_status_cnt_reg[31][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y239 g_clock_rate_din[31].ngccm_status_cnt_reg[31][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X48Y232 SFP_GEN[31].rx_data_ngccm_reg[31][32]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X48Y232 SFP_GEN[31].rx_data_ngccm_reg[31][40]/C Low Pulse Width Fast FDPE/C n/a 0.275 4.159 3.884 SLICE_X41Y232 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X41Y239 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X48Y229 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X48Y229 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X49Y237 g_clock_rate_din[31].rx_frameclk_div2_reg[31]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y237 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y237 SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X46Y234 SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[64]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X46Y234 SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[66]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X49Y234 SFP_GEN[31].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[0]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y15 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_34 To Clock: gtwiz_userclk_rx_srcclk_out[0]_34 Setup : 0 Failing Endpoints, Worst Slack 3.279ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.033ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.279ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 5.103ns (logic 1.646ns (32.256%) route 3.457ns (67.744%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.588ns = ( 10.905 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.686ns, distribution 1.520ns) Clock Net Delay (Destination): 2.212ns (routing 0.623ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.573 6.290 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X49Y249 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.224 6.514 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/O net (fo=5, routed) 0.338 6.852 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y251 LUT4 (Prop_H5LUT_SLICEL_I2_O) 0.189 7.041 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__31/O net (fo=1, routed) 0.219 7.260 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__31_n_0 SLICE_X50Y250 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.147 7.407 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__31/O net (fo=2, routed) 0.327 7.734 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__31_n_0 SLICE_X49Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.905 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X49Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.197 11.102 clock uncertainty -0.035 11.067 SLICE_X49Y249 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 11.013 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.013 arrival time -7.734 ------------------------------------------------------------------- slack 3.279 Slack (MET) : 3.279ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 5.103ns (logic 1.646ns (32.256%) route 3.457ns (67.744%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.588ns = ( 10.905 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.686ns, distribution 1.520ns) Clock Net Delay (Destination): 2.212ns (routing 0.623ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.573 6.290 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X49Y249 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.224 6.514 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/O net (fo=5, routed) 0.338 6.852 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y251 LUT4 (Prop_H5LUT_SLICEL_I2_O) 0.189 7.041 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__31/O net (fo=1, routed) 0.219 7.260 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__31_n_0 SLICE_X50Y250 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.147 7.407 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__31/O net (fo=2, routed) 0.327 7.734 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__31_n_0 SLICE_X49Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.905 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X49Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.197 11.102 clock uncertainty -0.035 11.067 SLICE_X49Y249 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 11.013 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.013 arrival time -7.734 ------------------------------------------------------------------- slack 3.279 Slack (MET) : 3.582ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.805ns (logic 1.456ns (30.302%) route 3.349ns (69.698%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.597ns = ( 10.914 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.686ns, distribution 1.520ns) Clock Net Delay (Destination): 2.221ns (routing 0.623ns, distribution 1.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.573 6.290 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X49Y249 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.224 6.514 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/O net (fo=5, routed) 0.257 6.771 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y250 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 6.917 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/O net (fo=7, routed) 0.519 7.436 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X50Y251 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.221 10.914 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X50Y251 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.197 11.111 clock uncertainty -0.035 11.076 SLICE_X50Y251 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.018 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.018 arrival time -7.436 ------------------------------------------------------------------- slack 3.582 Slack (MET) : 3.582ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.805ns (logic 1.456ns (30.302%) route 3.349ns (69.698%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.597ns = ( 10.914 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.686ns, distribution 1.520ns) Clock Net Delay (Destination): 2.221ns (routing 0.623ns, distribution 1.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.573 6.290 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X49Y249 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.224 6.514 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/O net (fo=5, routed) 0.257 6.771 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y250 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 6.917 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/O net (fo=7, routed) 0.519 7.436 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X50Y251 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.221 10.914 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X50Y251 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.197 11.111 clock uncertainty -0.035 11.076 SLICE_X50Y251 FDRE (Setup_GFF2_SLICEL_C_CE) -0.058 11.018 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.018 arrival time -7.436 ------------------------------------------------------------------- slack 3.582 Slack (MET) : 3.590ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.802ns (logic 1.456ns (30.321%) route 3.346ns (69.679%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.168ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.686ns, distribution 1.520ns) Clock Net Delay (Destination): 2.226ns (routing 0.623ns, distribution 1.603ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.573 6.290 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X49Y249 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.224 6.514 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/O net (fo=5, routed) 0.257 6.771 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y250 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 6.917 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/O net (fo=7, routed) 0.516 7.433 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X49Y251 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.226 10.919 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X49Y251 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.197 11.116 clock uncertainty -0.035 11.081 SLICE_X49Y251 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.023 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.023 arrival time -7.433 ------------------------------------------------------------------- slack 3.590 Slack (MET) : 3.596ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.799ns (logic 1.456ns (30.340%) route 3.343ns (69.660%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.168ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.686ns, distribution 1.520ns) Clock Net Delay (Destination): 2.226ns (routing 0.623ns, distribution 1.603ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.573 6.290 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X49Y249 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.224 6.514 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/O net (fo=5, routed) 0.257 6.771 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y250 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 6.917 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/O net (fo=7, routed) 0.513 7.430 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X49Y251 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.226 10.919 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X49Y251 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.197 11.116 clock uncertainty -0.035 11.081 SLICE_X49Y251 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.026 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.026 arrival time -7.430 ------------------------------------------------------------------- slack 3.596 Slack (MET) : 3.711ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].rx_data_ngccm_reg[32][59]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.530ns (logic 0.385ns (8.499%) route 4.145ns (91.501%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.686ns, distribution 1.670ns) Clock Net Delay (Destination): 2.226ns (routing 0.623ns, distribution 1.603ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y249 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.920 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.969 5.889 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X52Y253 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.246 6.135 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/O net (fo=76, routed) 1.176 7.311 rx_data_ngccm[32] SLICE_X58Y248 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][59]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.226 10.919 g_gbt_bank[2].gbtbank_n_104 SLICE_X58Y248 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][59]/C clock pessimism 0.196 11.115 clock uncertainty -0.035 11.080 SLICE_X58Y248 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 11.022 SFP_GEN[32].rx_data_ngccm_reg[32][59] ------------------------------------------------------------------- required time 11.022 arrival time -7.311 ------------------------------------------------------------------- slack 3.711 Slack (MET) : 3.717ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].rx_data_ngccm_reg[32][57]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.527ns (logic 0.385ns (8.505%) route 4.142ns (91.495%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.686ns, distribution 1.670ns) Clock Net Delay (Destination): 2.226ns (routing 0.623ns, distribution 1.603ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y249 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.920 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.969 5.889 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X52Y253 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.246 6.135 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/O net (fo=76, routed) 1.173 7.308 rx_data_ngccm[32] SLICE_X58Y248 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][57]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.226 10.919 g_gbt_bank[2].gbtbank_n_104 SLICE_X58Y248 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][57]/C clock pessimism 0.196 11.115 clock uncertainty -0.035 11.080 SLICE_X58Y248 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 11.025 SFP_GEN[32].rx_data_ngccm_reg[32][57] ------------------------------------------------------------------- required time 11.025 arrival time -7.308 ------------------------------------------------------------------- slack 3.717 Slack (MET) : 3.760ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.625ns (logic 1.456ns (31.481%) route 3.169ns (68.519%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.158ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.686ns, distribution 1.520ns) Clock Net Delay (Destination): 2.216ns (routing 0.623ns, distribution 1.593ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.573 6.290 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X49Y249 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.224 6.514 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/O net (fo=5, routed) 0.257 6.771 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y250 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 6.917 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/O net (fo=7, routed) 0.339 7.256 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X50Y250 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X50Y250 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.197 11.106 clock uncertainty -0.035 11.071 SLICE_X50Y250 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.016 arrival time -7.256 ------------------------------------------------------------------- slack 3.760 Slack (MET) : 3.765ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.621ns (logic 1.456ns (31.508%) route 3.165ns (68.492%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.158ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.686ns, distribution 1.520ns) Clock Net Delay (Destination): 2.216ns (routing 0.623ns, distribution 1.593ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.573 6.290 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X49Y249 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.224 6.514 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__31/O net (fo=5, routed) 0.257 6.771 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X50Y250 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 6.917 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__32/O net (fo=7, routed) 0.335 7.252 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X50Y250 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X50Y250 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.197 11.106 clock uncertainty -0.035 11.071 SLICE_X50Y250 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 11.017 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.017 arrival time -7.252 ------------------------------------------------------------------- slack 3.765 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].rx_data_ngccm_reg[32][7]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.048ns (29.814%) route 0.113ns (70.186%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.313ns Source Clock Delay (SCD): 1.095ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.979ns (routing 0.315ns, distribution 0.664ns) Clock Net Delay (Destination): 1.161ns (routing 0.364ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.979 1.095 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X54Y243 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y243 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 1.143 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.113 1.256 rx_data[32][7] SLICE_X56Y243 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.161 1.313 g_gbt_bank[2].gbtbank_n_104 SLICE_X56Y243 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][7]/C clock pessimism -0.146 1.167 SLICE_X56Y243 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.223 SFP_GEN[32].rx_data_ngccm_reg[32][7] ------------------------------------------------------------------- required time -1.223 arrival time 1.256 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.035ns (arrival time - required time) Source: SFP_GEN[32].rx_data_ngccm_reg[32][46]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[46]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.087ns (50.877%) route 0.084ns (49.123%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.092ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.976ns (routing 0.315ns, distribution 0.661ns) Clock Net Delay (Destination): 1.166ns (routing 0.364ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.976 1.092 g_gbt_bank[2].gbtbank_n_104 SLICE_X56Y251 FDCE r SFP_GEN[32].rx_data_ngccm_reg[32][46]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y251 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.141 r SFP_GEN[32].rx_data_ngccm_reg[32][46]/Q net (fo=1, routed) 0.072 1.213 SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[83]_0[38] SLICE_X54Y251 LUT3 (Prop_G5LUT_SLICEL_I1_O) 0.038 1.251 r SFP_GEN[32].ngCCM_gbt/RX_Word_rx40[46]_i_1/O net (fo=1, routed) 0.012 1.263 SFP_GEN[32].ngCCM_gbt/RX_Word_rx40[46]_i_1_n_0 SLICE_X54Y251 FDCE r SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[46]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.318 SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y251 FDCE r SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[46]/C clock pessimism -0.146 1.172 SLICE_X54Y251 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.228 SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[46] ------------------------------------------------------------------- required time -1.228 arrival time 1.263 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.091ns Clock Pessimism Removal (CPR): 0.177ns Clock Net Delay (Source): 0.975ns (routing 0.315ns, distribution 0.660ns) Clock Net Delay (Destination): 1.166ns (routing 0.364ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.091 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X50Y246 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y246 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.139 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]/Q net (fo=1, routed) 0.094 1.233 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0[39] SLICE_X50Y245 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X50Y245 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[39]/C clock pessimism -0.177 1.141 SLICE_X50Y245 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.197 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[39] ------------------------------------------------------------------- required time -1.197 arrival time 1.233 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.036ns (arrival time - required time) Source: SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.179ns (logic 0.048ns (26.816%) route 0.131ns (73.184%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.331ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.982ns (routing 0.315ns, distribution 0.667ns) Clock Net Delay (Destination): 1.179ns (routing 0.364ns, distribution 0.815ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.098 SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y244 FDCE r SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y244 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.146 r SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]/Q net (fo=1, routed) 0.131 1.277 SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[6] SLICE_X54Y244 FDRE r SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.179 1.331 SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y244 FDRE r SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C clock pessimism -0.146 1.185 SLICE_X54Y244 FDRE (Hold_BFF2_SLICEL_C_D) 0.056 1.241 SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36] ------------------------------------------------------------------- required time -1.241 arrival time 1.277 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.094ns (50.811%) route 0.091ns (49.189%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.319ns Source Clock Delay (SCD): 1.085ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.969ns (routing 0.315ns, distribution 0.654ns) Clock Net Delay (Destination): 1.167ns (routing 0.364ns, distribution 0.803ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.969 1.085 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK SLICE_X48Y251 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y251 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.134 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/Q net (fo=5, routed) 0.079 1.213 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg_n_0_[0] SLICE_X50Y251 LUT3 (Prop_A6LUT_SLICEL_I1_O) 0.045 1.258 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_i_1__31/O net (fo=1, routed) 0.012 1.270 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_i_1__31_n_0 SLICE_X50Y251 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.167 1.319 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK SLICE_X50Y251 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/C clock pessimism -0.146 1.173 SLICE_X50Y251 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.229 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.229 arrival time 1.270 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.080ns (45.455%) route 0.096ns (54.545%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.095ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.979ns (routing 0.315ns, distribution 0.664ns) Clock Net Delay (Destination): 1.166ns (routing 0.364ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.979 1.095 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X58Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y249 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.144 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.080 1.224 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_31_in SLICE_X59Y249 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.031 1.255 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__31/O net (fo=1, routed) 0.016 1.271 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[16] SLICE_X59Y249 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X59Y249 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.146 1.172 SLICE_X59Y249 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.228 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.228 arrival time 1.271 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.063ns (42.857%) route 0.084ns (57.143%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.323ns Source Clock Delay (SCD): 1.099ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.983ns (routing 0.315ns, distribution 0.668ns) Clock Net Delay (Destination): 1.171ns (routing 0.364ns, distribution 0.807ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.099 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X57Y250 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y250 FDCE (Prop_GFF_SLICEL_C_Q) 0.048 1.147 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.072 1.219 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/O84[0] SLICE_X57Y249 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.234 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__31/O net (fo=1, routed) 0.012 1.246 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] SLICE_X57Y249 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.323 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X57Y249 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.178 1.145 SLICE_X57Y249 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.201 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.201 arrival time 1.246 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.331ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 0.982ns (routing 0.315ns, distribution 0.667ns) Clock Net Delay (Destination): 1.179ns (routing 0.364ns, distribution 0.815ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.098 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X54Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y244 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.147 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.036 1.183 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in SLICE_X54Y244 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.228 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__31/O net (fo=1, routed) 0.016 1.244 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] SLICE_X54Y244 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.179 1.331 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X54Y244 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.189 1.142 SLICE_X54Y244 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.198 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.198 arrival time 1.244 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.330ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 0.984ns (routing 0.315ns, distribution 0.669ns) Clock Net Delay (Destination): 1.178ns (routing 0.364ns, distribution 0.814ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.100 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X53Y244 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y244 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.149 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.035 1.184 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_29_in SLICE_X53Y244 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.045 1.229 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__31/O net (fo=1, routed) 0.016 1.245 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] SLICE_X53Y244 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.330 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X53Y244 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.189 1.141 SLICE_X53Y244 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.197 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.197 arrival time 1.245 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[27]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[27]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_34 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.093ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 0.977ns (routing 0.315ns, distribution 0.662ns) Clock Net Delay (Destination): 1.166ns (routing 0.364ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.093 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X49Y247 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y247 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.141 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[27]/Q net (fo=1, routed) 0.094 1.235 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0[27] SLICE_X50Y247 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.318 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X50Y247 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[27]/C clock pessimism -0.187 1.131 SLICE_X50Y247 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[27] ------------------------------------------------------------------- required time -1.187 arrival time 1.235 ------------------------------------------------------------------- slack 0.048 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_34 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y101 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y262 g_clock_rate_din[32].ngccm_status_cnt_reg[32][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y262 g_clock_rate_din[32].ngccm_status_cnt_reg[32][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y253 SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y253 SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y252 SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y252 SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[17]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y252 SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[19]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y253 SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[3]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][5]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y263 g_clock_rate_din[32].ngccm_status_cnt_reg[32][6]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X56Y263 g_clock_rate_din[32].rx_test_comm_cnt_reg[32]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y16 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_35 To Clock: gtwiz_userclk_rx_srcclk_out[0]_35 Setup : 0 Failing Endpoints, Worst Slack 4.492ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.031ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.492ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.562ns (logic 1.639ns (46.013%) route 1.923ns (53.987%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.173ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.261ns = ( 10.578 - 8.317 ) Source Clock Delay (SCD): 2.624ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.199ns (routing 0.686ns, distribution 1.513ns) Clock Net Delay (Destination): 1.885ns (routing 0.623ns, distribution 1.262ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.199 2.624 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.336 5.121 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X28Y255 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.224 5.345 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.086 5.431 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X28Y255 LUT4 (Prop_A6LUT_SLICEM_I2_O) 0.089 5.520 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32/O net (fo=1, routed) 0.175 5.695 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32_n_0 SLICE_X27Y254 LUT6 (Prop_C6LUT_SLICEL_I5_O) 0.165 5.860 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32/O net (fo=2, routed) 0.326 6.186 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32_n_0 SLICE_X27Y255 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.885 10.578 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X27Y255 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.190 10.768 clock uncertainty -0.035 10.733 SLICE_X27Y255 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 10.678 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.678 arrival time -6.186 ------------------------------------------------------------------- slack 4.492 Slack (MET) : 4.492ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.562ns (logic 1.639ns (46.013%) route 1.923ns (53.987%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.173ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.261ns = ( 10.578 - 8.317 ) Source Clock Delay (SCD): 2.624ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.199ns (routing 0.686ns, distribution 1.513ns) Clock Net Delay (Destination): 1.885ns (routing 0.623ns, distribution 1.262ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.199 2.624 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.336 5.121 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X28Y255 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.224 5.345 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.086 5.431 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X28Y255 LUT4 (Prop_A6LUT_SLICEM_I2_O) 0.089 5.520 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32/O net (fo=1, routed) 0.175 5.695 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32_n_0 SLICE_X27Y254 LUT6 (Prop_C6LUT_SLICEL_I5_O) 0.165 5.860 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32/O net (fo=2, routed) 0.326 6.186 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32_n_0 SLICE_X27Y255 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.885 10.578 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X27Y255 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.190 10.768 clock uncertainty -0.035 10.733 SLICE_X27Y255 FDCE (Setup_HFF_SLICEL_C_CE) -0.055 10.678 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.678 arrival time -6.186 ------------------------------------------------------------------- slack 4.492 Slack (MET) : 4.501ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.685ns (logic 1.161ns (31.506%) route 2.524ns (68.494%)) Logic Levels: 0 Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.275ns = ( 10.592 - 8.317 ) Source Clock Delay (SCD): 2.624ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.199ns (routing 0.686ns, distribution 1.513ns) Clock Net Delay (Destination): 1.899ns (routing 0.623ns, distribution 1.276ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.199 2.624 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 2.524 6.309 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[3] SLICE_X29Y246 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.899 10.592 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X29Y246 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]/C clock pessimism 0.190 10.782 clock uncertainty -0.035 10.747 SLICE_X29Y246 FDCE (Setup_AFF_SLICEM_C_D) 0.063 10.810 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103] ------------------------------------------------------------------- required time 10.810 arrival time -6.309 ------------------------------------------------------------------- slack 4.501 Slack (MET) : 4.503ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[97]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.721ns (logic 1.133ns (30.449%) route 2.588ns (69.551%)) Logic Levels: 5 (LUT4=1 LUT5=1 LUT6=3) Clock Path Skew: -0.121ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.311ns = ( 10.628 - 8.317 ) Source Clock Delay (SCD): 2.622ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.197ns (routing 0.686ns, distribution 1.511ns) Clock Net Delay (Destination): 1.935ns (routing 0.623ns, distribution 1.312ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.197 2.622 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X32Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[97]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y249 FDCE (Prop_AFF2_SLICEL_C_Q) 0.139 2.761 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[97]/Q net (fo=9, routed) 0.527 3.288 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxencdata_s[9]_53[22] SLICE_X33Y254 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.146 3.434 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___42_i_16__32/O net (fo=1, routed) 0.361 3.795 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___42_i_16__32_n_0 SLICE_X33Y257 LUT5 (Prop_E6LUT_SLICEL_I2_O) 0.235 4.030 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___42_i_8__32/O net (fo=24, routed) 1.158 5.188 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/s3_from_syndromes[2] SLICE_X33Y249 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.411 f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__32/O net (fo=1, routed) 0.158 5.569 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_12__32_n_0 SLICE_X33Y250 LUT6 (Prop_F6LUT_SLICEL_I4_O) 0.146 5.715 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__65/O net (fo=1, routed) 0.349 6.064 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__65_n_0 SLICE_X35Y250 LUT6 (Prop_H6LUT_SLICEM_I3_O) 0.244 6.308 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__65/O net (fo=1, routed) 0.035 6.343 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 SLICE_X35Y250 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.935 10.628 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK SLICE_X35Y250 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C clock pessimism 0.190 10.818 clock uncertainty -0.035 10.783 SLICE_X35Y250 FDRE (Setup_HFF_SLICEM_C_D) 0.063 10.846 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg ------------------------------------------------------------------- required time 10.846 arrival time -6.343 ------------------------------------------------------------------- slack 4.503 Slack (MET) : 4.509ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.548ns (logic 1.474ns (41.545%) route 2.074ns (58.455%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.264ns = ( 10.581 - 8.317 ) Source Clock Delay (SCD): 2.624ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.199ns (routing 0.686ns, distribution 1.513ns) Clock Net Delay (Destination): 1.888ns (routing 0.623ns, distribution 1.265ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.199 2.624 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.336 5.121 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X28Y255 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.224 5.345 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.266 5.611 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X27Y254 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.089 5.700 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/O net (fo=7, routed) 0.472 6.172 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X27Y253 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.888 10.581 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X27Y253 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.190 10.771 clock uncertainty -0.035 10.736 SLICE_X27Y253 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.681 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.681 arrival time -6.172 ------------------------------------------------------------------- slack 4.509 Slack (MET) : 4.509ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.548ns (logic 1.474ns (41.545%) route 2.074ns (58.455%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.264ns = ( 10.581 - 8.317 ) Source Clock Delay (SCD): 2.624ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.199ns (routing 0.686ns, distribution 1.513ns) Clock Net Delay (Destination): 1.888ns (routing 0.623ns, distribution 1.265ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.199 2.624 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.336 5.121 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X28Y255 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.224 5.345 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.266 5.611 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X27Y254 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.089 5.700 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/O net (fo=7, routed) 0.472 6.172 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X27Y253 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.888 10.581 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X27Y253 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.190 10.771 clock uncertainty -0.035 10.736 SLICE_X27Y253 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 10.681 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.681 arrival time -6.172 ------------------------------------------------------------------- slack 4.509 Slack (MET) : 4.514ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.544ns (logic 1.474ns (41.591%) route 2.070ns (58.409%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.264ns = ( 10.581 - 8.317 ) Source Clock Delay (SCD): 2.624ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.199ns (routing 0.686ns, distribution 1.513ns) Clock Net Delay (Destination): 1.888ns (routing 0.623ns, distribution 1.265ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.199 2.624 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.336 5.121 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X28Y255 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.224 5.345 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.266 5.611 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X27Y254 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.089 5.700 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/O net (fo=7, routed) 0.468 6.168 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X27Y253 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.888 10.581 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X27Y253 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.190 10.771 clock uncertainty -0.035 10.736 SLICE_X27Y253 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 10.682 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.682 arrival time -6.168 ------------------------------------------------------------------- slack 4.514 Slack (MET) : 4.514ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.544ns (logic 1.474ns (41.591%) route 2.070ns (58.409%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.264ns = ( 10.581 - 8.317 ) Source Clock Delay (SCD): 2.624ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.199ns (routing 0.686ns, distribution 1.513ns) Clock Net Delay (Destination): 1.888ns (routing 0.623ns, distribution 1.265ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.199 2.624 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.336 5.121 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X28Y255 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.224 5.345 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.266 5.611 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X27Y254 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.089 5.700 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/O net (fo=7, routed) 0.468 6.168 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 SLICE_X27Y253 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.888 10.581 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X27Y253 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.190 10.771 clock uncertainty -0.035 10.736 SLICE_X27Y253 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 10.682 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.682 arrival time -6.168 ------------------------------------------------------------------- slack 4.514 Slack (MET) : 4.517ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.543ns (logic 1.531ns (43.212%) route 2.012ns (56.788%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.164ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.270ns = ( 10.587 - 8.317 ) Source Clock Delay (SCD): 2.624ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.199ns (routing 0.686ns, distribution 1.513ns) Clock Net Delay (Destination): 1.894ns (routing 0.623ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.199 2.624 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.336 5.121 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X28Y255 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.224 5.345 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.187 5.532 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X27Y255 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.146 5.678 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__33/O net (fo=3, routed) 0.489 6.167 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecFalseHeaders0 SLICE_X27Y254 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.894 10.587 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X27Y254 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.190 10.777 clock uncertainty -0.035 10.742 SLICE_X27Y254 FDRE (Setup_FFF2_SLICEL_C_CE) -0.058 10.684 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 10.684 arrival time -6.167 ------------------------------------------------------------------- slack 4.517 Slack (MET) : 4.595ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 3.470ns (logic 1.531ns (44.121%) route 1.939ns (55.879%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.272ns = ( 10.589 - 8.317 ) Source Clock Delay (SCD): 2.624ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.199ns (routing 0.686ns, distribution 1.513ns) Clock Net Delay (Destination): 1.896ns (routing 0.623ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.199 2.624 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.785 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 1.336 5.121 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X28Y255 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.224 5.345 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/O net (fo=5, routed) 0.187 5.532 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X27Y255 LUT6 (Prop_E6LUT_SLICEL_I5_O) 0.146 5.678 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__33/O net (fo=3, routed) 0.416 6.094 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecFalseHeaders0 SLICE_X27Y254 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.896 10.589 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X27Y254 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.190 10.779 clock uncertainty -0.035 10.744 SLICE_X27Y254 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.689 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 10.689 arrival time -6.094 ------------------------------------------------------------------- slack 4.595 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].rx_data_ngccm_reg[33][48]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.141ns (logic 0.048ns (34.043%) route 0.093ns (65.957%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.172ns Source Clock Delay (SCD): 0.958ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.842ns (routing 0.315ns, distribution 0.527ns) Clock Net Delay (Destination): 1.020ns (routing 0.364ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.842 0.958 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X36Y262 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y262 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 1.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.093 1.099 rx_data[33][48] SLICE_X36Y261 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][48]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.172 g_gbt_bank[2].gbtbank_n_114 SLICE_X36Y261 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][48]/C clock pessimism -0.160 1.012 SLICE_X36Y261 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.068 SFP_GEN[33].rx_data_ngccm_reg[33][48] ------------------------------------------------------------------- required time -1.068 arrival time 1.099 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].rx_data_ngccm_reg[33][7]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.048ns (26.374%) route 0.134ns (73.626%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.177ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.848ns (routing 0.315ns, distribution 0.533ns) Clock Net Delay (Destination): 1.025ns (routing 0.364ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X37Y250 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y250 FDRE (Prop_HFF2_SLICEM_C_Q) 0.048 1.012 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.134 1.146 rx_data[33][7] SLICE_X36Y250 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.025 1.177 g_gbt_bank[2].gbtbank_n_114 SLICE_X36Y250 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][7]/C clock pessimism -0.128 1.049 SLICE_X36Y250 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.105 SFP_GEN[33].rx_data_ngccm_reg[33][7] ------------------------------------------------------------------- required time -1.105 arrival time 1.146 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.094ns (51.648%) route 0.088ns (48.352%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.845ns (routing 0.315ns, distribution 0.530ns) Clock Net Delay (Destination): 1.021ns (routing 0.364ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X37Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y260 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.076 1.086 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X36Y260 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.045 1.131 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__32/O net (fo=1, routed) 0.012 1.143 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] SLICE_X36Y260 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.173 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X36Y260 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.128 1.045 SLICE_X36Y260 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.101 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.101 arrival time 1.143 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.095ns (50.532%) route 0.093ns (49.468%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.179ns Source Clock Delay (SCD): 0.962ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.846ns (routing 0.315ns, distribution 0.531ns) Clock Net Delay (Destination): 1.027ns (routing 0.364ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.846 0.962 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X36Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y258 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.011 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.077 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in SLICE_X37Y258 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.046 1.134 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__32/O net (fo=1, routed) 0.016 1.150 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[12] SLICE_X37Y258 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.027 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X37Y258 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.128 1.051 SLICE_X37Y258 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.107 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.107 arrival time 1.150 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].rx_data_ngccm_reg[33][49]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.048ns (30.769%) route 0.108ns (69.231%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.172ns Source Clock Delay (SCD): 0.958ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.842ns (routing 0.315ns, distribution 0.527ns) Clock Net Delay (Destination): 1.020ns (routing 0.364ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.842 0.958 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X36Y262 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y262 FDRE (Prop_EFF2_SLICEL_C_Q) 0.048 1.006 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.108 1.114 rx_data[33][49] SLICE_X36Y261 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][49]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.172 g_gbt_bank[2].gbtbank_n_114 SLICE_X36Y261 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][49]/C clock pessimism -0.160 1.012 SLICE_X36Y261 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.068 SFP_GEN[33].rx_data_ngccm_reg[33][49] ------------------------------------------------------------------- required time -1.068 arrival time 1.114 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.176ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.848ns (routing 0.315ns, distribution 0.533ns) Clock Net Delay (Destination): 1.024ns (routing 0.364ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X35Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y258 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.013 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.035 1.048 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X35Y258 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.093 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__32/O net (fo=1, routed) 0.016 1.109 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[0] SLICE_X35Y258 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.176 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X35Y258 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.171 1.005 SLICE_X35Y258 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.061 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.061 arrival time 1.109 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.179ns Source Clock Delay (SCD): 0.967ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.851ns (routing 0.315ns, distribution 0.536ns) Clock Net Delay (Destination): 1.027ns (routing 0.364ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.851 0.967 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X37Y258 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y258 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.016 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.035 1.051 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in SLICE_X37Y258 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.045 1.096 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__32/O net (fo=1, routed) 0.016 1.112 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X37Y258 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.027 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X37Y258 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.171 1.008 SLICE_X37Y258 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.064 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.064 arrival time 1.112 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[33].rx_data_ngccm_reg[33][76]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.182ns Source Clock Delay (SCD): 0.970ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.854ns (routing 0.315ns, distribution 0.539ns) Clock Net Delay (Destination): 1.030ns (routing 0.364ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.854 0.970 g_gbt_bank[2].gbtbank_n_114 SLICE_X39Y257 FDCE r SFP_GEN[33].rx_data_ngccm_reg[33][76]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y257 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.019 r SFP_GEN[33].rx_data_ngccm_reg[33][76]/Q net (fo=1, routed) 0.035 1.054 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[83]_0[68] SLICE_X39Y257 LUT3 (Prop_C6LUT_SLICEM_I1_O) 0.045 1.099 r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[76]_i_1/O net (fo=1, routed) 0.016 1.115 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[76]_i_1_n_0 SLICE_X39Y257 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.030 1.182 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y257 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[76]/C clock pessimism -0.171 1.011 SLICE_X39Y257 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.067 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[76] ------------------------------------------------------------------- required time -1.067 arrival time 1.115 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.176ns Source Clock Delay (SCD): 0.963ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.847ns (routing 0.315ns, distribution 0.532ns) Clock Net Delay (Destination): 1.024ns (routing 0.364ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.847 0.963 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X36Y257 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y257 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.012 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.037 1.049 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/O85[1] SLICE_X36Y257 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.045 1.094 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__32/O net (fo=1, routed) 0.015 1.109 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[1] SLICE_X36Y257 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.176 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X36Y257 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.171 1.005 SLICE_X36Y257 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.061 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.061 arrival time 1.109 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_35 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.065ns (37.143%) route 0.110ns (62.857%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.159ns Source Clock Delay (SCD): 0.960ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.844ns (routing 0.315ns, distribution 0.529ns) Clock Net Delay (Destination): 1.007ns (routing 0.364ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.844 0.960 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X35Y253 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y253 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.009 f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Q net (fo=28, routed) 0.094 1.103 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] SLICE_X34Y252 LUT5 (Prop_H6LUT_SLICEM_I0_O) 0.016 1.119 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[36]_i_1__28/O net (fo=1, routed) 0.016 1.135 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg00[36] SLICE_X34Y252 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.159 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X34Y252 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]/C clock pessimism -0.128 1.031 SLICE_X34Y252 FDCE (Hold_HFF_SLICEM_C_D) 0.056 1.087 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36] ------------------------------------------------------------------- required time -1.087 arrival time 1.135 ------------------------------------------------------------------- slack 0.048 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_35 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y102 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y266 g_clock_rate_din[33].ngccm_status_cnt_reg[33][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y266 g_clock_rate_din[33].ngccm_status_cnt_reg[33][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y266 g_clock_rate_din[33].ngccm_status_cnt_reg[33][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y266 g_clock_rate_din[33].ngccm_status_cnt_reg[33][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y266 g_clock_rate_din[33].ngccm_status_cnt_reg[33][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y266 g_clock_rate_din[33].ngccm_status_cnt_reg[33][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y269 g_clock_rate_din[33].ngccm_status_cnt_reg[33][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X42Y253 SFP_GEN[33].ngCCM_gbt/RX_Clock_40MHz_reg/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X39Y251 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[0]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X39Y251 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[2]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X39Y251 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X39Y251 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X35Y251 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[4]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X40Y255 SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X40Y255 SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X34Y261 SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X34Y261 SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[60]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X34Y261 SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[62]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X34Y261 SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[64]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y17 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_36 To Clock: gtwiz_userclk_rx_srcclk_out[0]_36 Setup : 0 Failing Endpoints, Worst Slack 4.051ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.032ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.051ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][6]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.884ns (logic 0.229ns (5.896%) route 3.655ns (94.104%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.799ns = ( 11.116 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.423ns (routing 1.095ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.743 5.207 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X38Y414 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.090 5.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.912 7.209 rx_data_ngccm[36] SLICE_X40Y424 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.423 11.116 g_gbt_bank[3].gbtbank_n_0 SLICE_X40Y424 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][6]/C clock pessimism 0.237 11.354 clock uncertainty -0.035 11.318 SLICE_X40Y424 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 11.260 SFP_GEN[36].rx_data_ngccm_reg[36][6] ------------------------------------------------------------------- required time 11.260 arrival time -7.209 ------------------------------------------------------------------- slack 4.051 Slack (MET) : 4.057ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][4]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.881ns (logic 0.229ns (5.901%) route 3.652ns (94.099%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.799ns = ( 11.116 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.423ns (routing 1.095ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.743 5.207 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X38Y414 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.090 5.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.909 7.206 rx_data_ngccm[36] SLICE_X40Y424 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.423 11.116 g_gbt_bank[3].gbtbank_n_0 SLICE_X40Y424 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][4]/C clock pessimism 0.237 11.354 clock uncertainty -0.035 11.318 SLICE_X40Y424 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 11.263 SFP_GEN[36].rx_data_ngccm_reg[36][4] ------------------------------------------------------------------- required time 11.263 arrival time -7.206 ------------------------------------------------------------------- slack 4.057 Slack (MET) : 4.073ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][36]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.865ns (logic 0.229ns (5.925%) route 3.636ns (94.075%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.799ns = ( 11.116 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.423ns (routing 1.095ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.743 5.207 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X38Y414 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.090 5.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.893 7.190 rx_data_ngccm[36] SLICE_X43Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][36]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.423 11.116 g_gbt_bank[3].gbtbank_n_0 SLICE_X43Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][36]/C clock pessimism 0.237 11.354 clock uncertainty -0.035 11.318 SLICE_X43Y426 FDCE (Setup_AFF2_SLICEL_C_CE) -0.055 11.263 SFP_GEN[36].rx_data_ngccm_reg[36][36] ------------------------------------------------------------------- required time 11.263 arrival time -7.190 ------------------------------------------------------------------- slack 4.073 Slack (MET) : 4.078ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][35]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.861ns (logic 0.229ns (5.931%) route 3.632ns (94.069%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.799ns = ( 11.116 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.423ns (routing 1.095ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.743 5.207 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X38Y414 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.090 5.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.889 7.186 rx_data_ngccm[36] SLICE_X43Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][35]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.423 11.116 g_gbt_bank[3].gbtbank_n_0 SLICE_X43Y426 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][35]/C clock pessimism 0.237 11.354 clock uncertainty -0.035 11.318 SLICE_X43Y426 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 11.264 SFP_GEN[36].rx_data_ngccm_reg[36][35] ------------------------------------------------------------------- required time 11.264 arrival time -7.186 ------------------------------------------------------------------- slack 4.078 Slack (MET) : 4.111ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.831ns (logic 0.229ns (5.978%) route 3.602ns (94.022%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.285ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.803ns = ( 11.120 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.427ns (routing 1.095ns, distribution 1.332ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.743 5.207 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X38Y414 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.090 5.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.859 7.156 rx_data_ngccm[36] SLICE_X38Y423 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.427 11.120 g_gbt_bank[3].gbtbank_n_0 SLICE_X38Y423 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][1]/C clock pessimism 0.237 11.358 clock uncertainty -0.035 11.322 SLICE_X38Y423 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 11.267 SFP_GEN[36].rx_data_ngccm_reg[36][1] ------------------------------------------------------------------- required time 11.267 arrival time -7.156 ------------------------------------------------------------------- slack 4.111 Slack (MET) : 4.133ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][2]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.810ns (logic 0.229ns (6.010%) route 3.581ns (93.989%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.281ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.807ns = ( 11.124 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.431ns (routing 1.095ns, distribution 1.336ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.743 5.207 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X38Y414 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.090 5.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.838 7.135 rx_data_ngccm[36] SLICE_X40Y423 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.431 11.124 g_gbt_bank[3].gbtbank_n_0 SLICE_X40Y423 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][2]/C clock pessimism 0.237 11.362 clock uncertainty -0.035 11.326 SLICE_X40Y423 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 11.268 SFP_GEN[36].rx_data_ngccm_reg[36][2] ------------------------------------------------------------------- required time 11.268 arrival time -7.135 ------------------------------------------------------------------- slack 4.133 Slack (MET) : 4.133ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][7]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.810ns (logic 0.229ns (6.010%) route 3.581ns (93.989%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.281ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.807ns = ( 11.124 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.431ns (routing 1.095ns, distribution 1.336ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.743 5.207 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X38Y414 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.090 5.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.838 7.135 rx_data_ngccm[36] SLICE_X40Y423 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][7]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.431 11.124 g_gbt_bank[3].gbtbank_n_0 SLICE_X40Y423 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][7]/C clock pessimism 0.237 11.362 clock uncertainty -0.035 11.326 SLICE_X40Y423 FDCE (Setup_FFF2_SLICEL_C_CE) -0.058 11.268 SFP_GEN[36].rx_data_ngccm_reg[36][7] ------------------------------------------------------------------- required time 11.268 arrival time -7.135 ------------------------------------------------------------------- slack 4.133 Slack (MET) : 4.134ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][19]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.799ns (logic 0.229ns (6.028%) route 3.570ns (93.972%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.291ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.797ns = ( 11.114 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.421ns (routing 1.095ns, distribution 1.326ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.743 5.207 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X38Y414 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.090 5.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.827 7.124 rx_data_ngccm[36] SLICE_X43Y425 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][19]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.421 11.114 g_gbt_bank[3].gbtbank_n_0 SLICE_X43Y425 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][19]/C clock pessimism 0.237 11.352 clock uncertainty -0.035 11.316 SLICE_X43Y425 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 11.258 SFP_GEN[36].rx_data_ngccm_reg[36][19] ------------------------------------------------------------------- required time 11.258 arrival time -7.124 ------------------------------------------------------------------- slack 4.134 Slack (MET) : 4.134ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][21]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.799ns (logic 0.229ns (6.028%) route 3.570ns (93.972%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.291ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.797ns = ( 11.114 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.421ns (routing 1.095ns, distribution 1.326ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.743 5.207 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X38Y414 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.090 5.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.827 7.124 rx_data_ngccm[36] SLICE_X43Y425 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][21]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.421 11.114 g_gbt_bank[3].gbtbank_n_0 SLICE_X43Y425 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][21]/C clock pessimism 0.237 11.352 clock uncertainty -0.035 11.316 SLICE_X43Y425 FDCE (Setup_FFF2_SLICEL_C_CE) -0.058 11.258 SFP_GEN[36].rx_data_ngccm_reg[36][21] ------------------------------------------------------------------- required time 11.258 arrival time -7.124 ------------------------------------------------------------------- slack 4.134 Slack (MET) : 4.134ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][24]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 3.799ns (logic 0.229ns (6.028%) route 3.570ns (93.972%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.291ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.797ns = ( 11.114 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.421ns (routing 1.095ns, distribution 1.326ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.743 5.207 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X38Y414 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.090 5.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/O net (fo=76, routed) 1.827 7.124 rx_data_ngccm[36] SLICE_X43Y425 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][24]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.421 11.114 g_gbt_bank[3].gbtbank_n_0 SLICE_X43Y425 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][24]/C clock pessimism 0.237 11.352 clock uncertainty -0.035 11.316 SLICE_X43Y425 FDCE (Setup_GFF2_SLICEL_C_CE) -0.058 11.258 SFP_GEN[36].rx_data_ngccm_reg[36][24] ------------------------------------------------------------------- required time 11.258 arrival time -7.124 ------------------------------------------------------------------- slack 4.134 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.032ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.171ns (logic 0.080ns (46.784%) route 0.091ns (53.216%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.436ns Source Clock Delay (SCD): 1.192ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 1.076ns (routing 0.544ns, distribution 0.532ns) Clock Net Delay (Destination): 1.284ns (routing 0.626ns, distribution 0.658ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.076 1.192 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X38Y417 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y417 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.241 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.075 1.316 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X39Y417 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.031 1.347 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__35/O net (fo=1, routed) 0.016 1.363 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] SLICE_X39Y417 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.284 1.436 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X39Y417 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.161 1.275 SLICE_X39Y417 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.331 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.331 arrival time 1.363 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.103ns (66.883%) route 0.051ns (33.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.459ns Source Clock Delay (SCD): 1.200ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.084ns (routing 0.544ns, distribution 0.540ns) Clock Net Delay (Destination): 1.307ns (routing 0.626ns, distribution 0.681ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.084 1.200 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X42Y427 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y427 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.249 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.035 1.284 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X42Y426 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.054 1.338 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__35/O net (fo=1, routed) 0.016 1.354 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] SLICE_X42Y426 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.307 1.459 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X42Y426 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.194 1.265 SLICE_X42Y426 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.321 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.321 arrival time 1.354 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.034ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.163ns (logic 0.063ns (38.650%) route 0.100ns (61.350%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.436ns Source Clock Delay (SCD): 1.199ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 1.083ns (routing 0.544ns, distribution 0.539ns) Clock Net Delay (Destination): 1.284ns (routing 0.626ns, distribution 0.658ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.083 1.199 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X44Y421 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.247 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/Q net (fo=14, routed) 0.084 1.331 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gbtBank_Clk_gen[0].cnt_reg[0][5] SLICE_X42Y421 LUT6 (Prop_C6LUT_SLICEM_I3_O) 0.015 1.346 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gbtBank_Clk_gen[0].cnt[0][1]_i_1__2/O net (fo=1, routed) 0.016 1.362 g_gbt_bank[3].gbtbank/i_gbt_bank_n_223 SLICE_X42Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.284 1.436 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/C clock pessimism -0.164 1.272 SLICE_X42Y421 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.328 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1] ------------------------------------------------------------------- required time -1.328 arrival time 1.362 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.088ns (50.286%) route 0.087ns (49.714%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.441ns Source Clock Delay (SCD): 1.198ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.082ns (routing 0.544ns, distribution 0.538ns) Clock Net Delay (Destination): 1.289ns (routing 0.626ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.082 1.198 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X38Y415 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y415 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.246 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[8]/Q net (fo=2, routed) 0.075 1.321 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_15_in SLICE_X39Y415 LUT3 (Prop_H5LUT_SLICEM_I2_O) 0.040 1.361 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__35/O net (fo=1, routed) 0.012 1.373 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[6] SLICE_X39Y415 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.289 1.441 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X39Y415 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism -0.160 1.281 SLICE_X39Y415 FDRE (Hold_HFF2_SLICEM_C_D) 0.056 1.337 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time -1.337 arrival time 1.373 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][31]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.447ns Source Clock Delay (SCD): 1.204ns Clock Pessimism Removal (CPR): 0.194ns Clock Net Delay (Source): 1.088ns (routing 0.544ns, distribution 0.544ns) Clock Net Delay (Destination): 1.295ns (routing 0.626ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.088 1.204 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X43Y424 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y424 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.252 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.094 1.346 rx_data[36][31] SLICE_X43Y423 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][31]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.295 1.447 g_gbt_bank[3].gbtbank_n_0 SLICE_X43Y423 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][31]/C clock pessimism -0.194 1.253 SLICE_X43Y423 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.309 SFP_GEN[36].rx_data_ngccm_reg[36][31] ------------------------------------------------------------------- required time -1.309 arrival time 1.346 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][5]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.048ns (30.769%) route 0.108ns (69.231%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.464ns Source Clock Delay (SCD): 1.209ns Clock Pessimism Removal (CPR): 0.196ns Clock Net Delay (Source): 1.093ns (routing 0.544ns, distribution 0.549ns) Clock Net Delay (Destination): 1.312ns (routing 0.626ns, distribution 0.686ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.093 1.209 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X40Y422 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y422 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.257 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.108 1.365 rx_data[36][5] SLICE_X40Y423 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.312 1.464 g_gbt_bank[3].gbtbank_n_0 SLICE_X40Y423 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][5]/C clock pessimism -0.196 1.268 SLICE_X40Y423 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.324 SFP_GEN[36].rx_data_ngccm_reg[36][5] ------------------------------------------------------------------- required time -1.324 arrival time 1.365 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.042ns (arrival time - required time) Source: SFP_GEN[36].rx_data_ngccm_reg[36][1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[0]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.094ns (50.811%) route 0.091ns (49.189%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.467ns Source Clock Delay (SCD): 1.216ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 1.100ns (routing 0.544ns, distribution 0.556ns) Clock Net Delay (Destination): 1.315ns (routing 0.626ns, distribution 0.689ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.100 1.216 g_gbt_bank[3].gbtbank_n_0 SLICE_X38Y423 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][1]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.265 r SFP_GEN[36].rx_data_ngccm_reg[36][1]/Q net (fo=1, routed) 0.075 1.340 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[83]_0[1] SLICE_X40Y423 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.385 r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40[0]_i_1/O net (fo=1, routed) 0.016 1.401 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40[0]_i_1_n_0 SLICE_X40Y423 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.315 1.467 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X40Y423 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.164 1.303 SLICE_X40Y423 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.359 SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.359 arrival time 1.401 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].rx_data_ngccm_reg[36][71]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.177ns (logic 0.048ns (27.119%) route 0.129ns (72.881%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.437ns Source Clock Delay (SCD): 1.200ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 1.084ns (routing 0.544ns, distribution 0.540ns) Clock Net Delay (Destination): 1.285ns (routing 0.626ns, distribution 0.659ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.084 1.200 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X38Y415 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y415 FDRE (Prop_BFF2_SLICEL_C_Q) 0.048 1.248 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/Q net (fo=1, routed) 0.129 1.377 rx_data[36][71] SLICE_X36Y415 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][71]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.285 1.437 g_gbt_bank[3].gbtbank_n_0 SLICE_X36Y415 FDCE r SFP_GEN[36].rx_data_ngccm_reg[36][71]/C clock pessimism -0.160 1.277 SLICE_X36Y415 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.333 SFP_GEN[36].rx_data_ngccm_reg[36][71] ------------------------------------------------------------------- required time -1.333 arrival time 1.377 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.064ns (42.953%) route 0.085ns (57.047%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.459ns Source Clock Delay (SCD): 1.215ns Clock Pessimism Removal (CPR): 0.196ns Clock Net Delay (Source): 1.099ns (routing 0.544ns, distribution 0.555ns) Clock Net Delay (Destination): 1.307ns (routing 0.626ns, distribution 0.681ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.099 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X40Y424 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y424 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.264 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.070 1.334 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/feedbackRegister[0] SLICE_X40Y425 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.015 1.349 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__35/O net (fo=1, routed) 0.015 1.364 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] SLICE_X40Y425 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.307 1.459 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X40Y425 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.196 1.263 SLICE_X40Y425 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.319 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.319 arrival time 1.364 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_36 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.048ns (28.235%) route 0.122ns (71.765%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.441ns Source Clock Delay (SCD): 1.208ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 1.092ns (routing 0.544ns, distribution 0.548ns) Clock Net Delay (Destination): 1.289ns (routing 0.626ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.092 1.208 SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y423 FDCE r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y423 FDCE (Prop_CFF2_SLICEL_C_Q) 0.048 1.256 r SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]/Q net (fo=2, routed) 0.122 1.378 SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/Q[11] SLICE_X44Y423 FDRE r SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.289 1.441 SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y423 FDRE r SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C clock pessimism -0.164 1.277 SLICE_X44Y423 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.333 SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11] ------------------------------------------------------------------- required time -1.333 arrival time 1.378 ------------------------------------------------------------------- slack 0.045 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_36 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y191 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y415 g_clock_rate_din[36].ngccm_status_cnt_reg[36][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X52Y414 g_clock_rate_din[36].ngccm_status_cnt_reg[36][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X52Y414 g_clock_rate_din[36].ngccm_status_cnt_reg[36][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X52Y414 g_clock_rate_din[36].ngccm_status_cnt_reg[36][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X52Y414 g_clock_rate_din[36].ngccm_status_cnt_reg[36][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y415 g_clock_rate_din[36].ngccm_status_cnt_reg[36][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y416 g_clock_rate_din[36].ngccm_status_cnt_reg[36][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X40Y425 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X40Y425 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X40Y425 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X40Y425 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X40Y425 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X40Y425 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y416 g_clock_rate_din[36].ngccm_status_cnt_reg[36][6]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y416 g_clock_rate_din[36].rx_test_comm_cnt_reg[36]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X21Y403 SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X42Y414 SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X42Y414 SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X42Y414 SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y28 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_37 To Clock: gtwiz_userclk_rx_srcclk_out[0]_37 Setup : 0 Failing Endpoints, Worst Slack 2.458ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.031ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.504ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.458ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.940ns (logic 1.640ns (27.609%) route 4.300ns (72.391%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.697ns, distribution 1.504ns) Clock Net Delay (Destination): 2.226ns (routing 0.634ns, distribution 1.592ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.730 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.258 6.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X62Y566 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.232 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.432 7.664 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X62Y565 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.146 7.810 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45/O net (fo=1, routed) 0.159 7.969 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45_n_0 SLICE_X62Y564 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 8.115 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45/O net (fo=2, routed) 0.451 8.566 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45_n_0 SLICE_X62Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.226 10.919 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.194 11.113 clock uncertainty -0.035 11.078 SLICE_X62Y565 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 11.024 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.024 arrival time -8.566 ------------------------------------------------------------------- slack 2.458 Slack (MET) : 2.458ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.940ns (logic 1.640ns (27.609%) route 4.300ns (72.391%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.602ns = ( 10.919 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.697ns, distribution 1.504ns) Clock Net Delay (Destination): 2.226ns (routing 0.634ns, distribution 1.592ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.730 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.258 6.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X62Y566 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.232 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.432 7.664 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X62Y565 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.146 7.810 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45/O net (fo=1, routed) 0.159 7.969 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45_n_0 SLICE_X62Y564 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 8.115 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45/O net (fo=2, routed) 0.451 8.566 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45_n_0 SLICE_X62Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.226 10.919 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.194 11.113 clock uncertainty -0.035 11.078 SLICE_X62Y565 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 11.024 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.024 arrival time -8.566 ------------------------------------------------------------------- slack 2.458 Slack (MET) : 2.760ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.645ns (logic 1.593ns (28.220%) route 4.052ns (71.780%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.177ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.609ns = ( 10.926 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.697ns, distribution 1.504ns) Clock Net Delay (Destination): 2.233ns (routing 0.634ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.730 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.258 6.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X62Y566 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.232 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.259 7.491 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X62Y566 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.245 7.736 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/O net (fo=5, routed) 0.535 8.271 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X62Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.233 10.926 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C clock pessimism 0.194 11.120 clock uncertainty -0.035 11.085 SLICE_X62Y566 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.031 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4] ------------------------------------------------------------------- required time 11.031 arrival time -8.271 ------------------------------------------------------------------- slack 2.760 Slack (MET) : 2.760ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.645ns (logic 1.593ns (28.220%) route 4.052ns (71.780%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.178ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.610ns = ( 10.927 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.697ns, distribution 1.504ns) Clock Net Delay (Destination): 2.234ns (routing 0.634ns, distribution 1.600ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.730 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.258 6.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X62Y566 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.232 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.259 7.491 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X62Y566 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.245 7.736 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/O net (fo=5, routed) 0.535 8.271 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.234 10.927 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.194 11.121 clock uncertainty -0.035 11.086 SLICE_X63Y566 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.031 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.031 arrival time -8.271 ------------------------------------------------------------------- slack 2.760 Slack (MET) : 2.760ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.645ns (logic 1.593ns (28.220%) route 4.052ns (71.780%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.178ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.610ns = ( 10.927 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.697ns, distribution 1.504ns) Clock Net Delay (Destination): 2.234ns (routing 0.634ns, distribution 1.600ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.730 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.258 6.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X62Y566 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.232 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.259 7.491 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X62Y566 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.245 7.736 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/O net (fo=5, routed) 0.535 8.271 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.234 10.927 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.194 11.121 clock uncertainty -0.035 11.086 SLICE_X63Y566 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.031 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.031 arrival time -8.271 ------------------------------------------------------------------- slack 2.760 Slack (MET) : 2.765ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.641ns (logic 1.593ns (28.240%) route 4.048ns (71.760%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.178ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.610ns = ( 10.927 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.697ns, distribution 1.504ns) Clock Net Delay (Destination): 2.234ns (routing 0.634ns, distribution 1.600ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.730 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.258 6.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X62Y566 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.232 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.259 7.491 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X62Y566 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.245 7.736 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/O net (fo=5, routed) 0.531 8.267 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.234 10.927 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C clock pessimism 0.194 11.121 clock uncertainty -0.035 11.086 SLICE_X63Y566 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 11.032 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0] ------------------------------------------------------------------- required time 11.032 arrival time -8.267 ------------------------------------------------------------------- slack 2.765 Slack (MET) : 2.765ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.641ns (logic 1.593ns (28.240%) route 4.048ns (71.760%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.178ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.610ns = ( 10.927 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.697ns, distribution 1.504ns) Clock Net Delay (Destination): 2.234ns (routing 0.634ns, distribution 1.600ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.730 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.258 6.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X62Y566 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.232 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.259 7.491 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X62Y566 LUT6 (Prop_F6LUT_SLICEM_I0_O) 0.245 7.736 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/O net (fo=5, routed) 0.531 8.267 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.234 10.927 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C clock pessimism 0.194 11.121 clock uncertainty -0.035 11.086 SLICE_X63Y566 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.032 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2] ------------------------------------------------------------------- required time 11.032 arrival time -8.267 ------------------------------------------------------------------- slack 2.765 Slack (MET) : 2.901ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.499ns (logic 1.592ns (28.951%) route 3.907ns (71.049%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.608ns = ( 10.925 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.697ns, distribution 1.504ns) Clock Net Delay (Destination): 2.232ns (routing 0.634ns, distribution 1.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.730 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.258 6.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X62Y566 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.232 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.214 7.446 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X62Y564 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 7.690 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/O net (fo=7, routed) 0.435 8.125 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.232 10.925 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.194 11.119 clock uncertainty -0.035 11.084 SLICE_X63Y566 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 11.026 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.026 arrival time -8.125 ------------------------------------------------------------------- slack 2.901 Slack (MET) : 2.901ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.499ns (logic 1.592ns (28.951%) route 3.907ns (71.049%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.608ns = ( 10.925 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.697ns, distribution 1.504ns) Clock Net Delay (Destination): 2.232ns (routing 0.634ns, distribution 1.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.730 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.258 6.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X62Y566 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.232 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.214 7.446 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X62Y564 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 7.690 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/O net (fo=7, routed) 0.435 8.125 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.232 10.925 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.194 11.119 clock uncertainty -0.035 11.084 SLICE_X63Y566 FDRE (Setup_GFF2_SLICEL_C_CE) -0.058 11.026 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.026 arrival time -8.125 ------------------------------------------------------------------- slack 2.901 Slack (MET) : 2.908ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 5.495ns (logic 1.592ns (28.972%) route 3.903ns (71.028%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.608ns = ( 10.925 - 8.317 ) Source Clock Delay (SCD): 2.626ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.201ns (routing 0.697ns, distribution 1.504ns) Clock Net Delay (Destination): 2.232ns (routing 0.634ns, distribution 1.598ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 2.626 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0]) 1.104 3.730 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0] net (fo=10, routed) 3.258 6.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] SLICE_X62Y566 LUT4 (Prop_D6LUT_SLICEM_I1_O) 0.244 7.232 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/O net (fo=5, routed) 0.214 7.446 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X62Y564 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.244 7.690 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/O net (fo=7, routed) 0.431 8.121 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.232 10.925 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y566 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.194 11.119 clock uncertainty -0.035 11.084 SLICE_X63Y566 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 11.029 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.029 arrival time -8.121 ------------------------------------------------------------------- slack 2.908 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.031ns (arrival time - required time) Source: SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[25]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.164ns (logic 0.049ns (29.878%) route 0.115ns (70.122%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.320ns Source Clock Delay (SCD): 1.096ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.980ns (routing 0.318ns, distribution 0.662ns) Clock Net Delay (Destination): 1.168ns (routing 0.368ns, distribution 0.800ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.096 SFP_GEN[46].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y560 FDCE r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[25]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y560 FDCE (Prop_AFF2_SLICEM_C_Q) 0.049 1.145 r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[25]/Q net (fo=2, routed) 0.115 1.260 SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/Q[9] SLICE_X65Y560 FDRE r SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.168 1.320 SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y560 FDRE r SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9]/C clock pessimism -0.147 1.173 SLICE_X65Y560 FDRE (Hold_GFF_SLICEM_C_D) 0.056 1.229 SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[9] ------------------------------------------------------------------- required time -1.229 arrival time 1.260 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.037ns (arrival time - required time) Source: SFP_GEN[46].rx_data_ngccm_reg[46][42]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[42]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.087ns (50.289%) route 0.086ns (49.711%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.321ns Source Clock Delay (SCD): 1.094ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.978ns (routing 0.318ns, distribution 0.660ns) Clock Net Delay (Destination): 1.169ns (routing 0.368ns, distribution 0.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.094 g_gbt_bank[3].gbtbank_n_124 SLICE_X68Y566 FDCE r SFP_GEN[46].rx_data_ngccm_reg[46][42]/C ------------------------------------------------------------------- ------------------- SLICE_X68Y566 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.143 r SFP_GEN[46].rx_data_ngccm_reg[46][42]/Q net (fo=1, routed) 0.075 1.218 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[83]_0[34] SLICE_X66Y566 LUT3 (Prop_D5LUT_SLICEL_I1_O) 0.038 1.256 r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[42]_i_1/O net (fo=1, routed) 0.011 1.267 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[42]_i_1_n_0 SLICE_X66Y566 FDCE r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[42]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.169 1.321 SFP_GEN[46].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X66Y566 FDCE r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[42]/C clock pessimism -0.147 1.174 SLICE_X66Y566 FDCE (Hold_DFF2_SLICEL_C_D) 0.056 1.230 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[42] ------------------------------------------------------------------- required time -1.230 arrival time 1.267 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[46].rx_data_ngccm_reg[46][32]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.049ns (29.341%) route 0.118ns (70.659%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.310ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.974ns (routing 0.318ns, distribution 0.656ns) Clock Net Delay (Destination): 1.158ns (routing 0.368ns, distribution 0.790ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X63Y567 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y567 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/Q net (fo=1, routed) 0.118 1.257 rx_data[46][32] SLICE_X64Y567 FDCE r SFP_GEN[46].rx_data_ngccm_reg[46][32]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.158 1.310 g_gbt_bank[3].gbtbank_n_124 SLICE_X64Y567 FDCE r SFP_GEN[46].rx_data_ngccm_reg[46][32]/C clock pessimism -0.147 1.163 SLICE_X64Y567 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.219 SFP_GEN[46].rx_data_ngccm_reg[46][32] ------------------------------------------------------------------- required time -1.219 arrival time 1.257 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.040ns (arrival time - required time) Source: SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.049ns (30.435%) route 0.112ns (69.565%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.308ns Source Clock Delay (SCD): 1.096ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.980ns (routing 0.318ns, distribution 0.662ns) Clock Net Delay (Destination): 1.156ns (routing 0.368ns, distribution 0.788ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.096 SFP_GEN[46].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y560 FDCE r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y560 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.145 r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[18]/Q net (fo=5, routed) 0.112 1.257 SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/Q[2] SLICE_X63Y559 FDRE r SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.308 SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y559 FDRE r SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/C clock pessimism -0.147 1.161 SLICE_X63Y559 FDRE (Hold_FFF_SLICEL_C_D) 0.056 1.217 SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2] ------------------------------------------------------------------- required time -1.217 arrival time 1.257 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.479ns (logic 0.229ns (47.808%) route 0.250ns (52.192%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.312ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.131ns Source Clock Delay (SCD): 2.608ns Clock Pessimism Removal (CPR): 0.211ns Clock Net Delay (Source): 2.232ns (routing 0.634ns, distribution 1.598ns) Clock Net Delay (Destination): 2.706ns (routing 0.697ns, distribution 2.009ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 0.030 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 0.376 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.232 2.608 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X70Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y565 FDCE (Prop_EFF_SLICEM_C_Q) 0.123 2.731 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.215 2.946 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_25_in SLICE_X71Y567 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.106 3.052 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__45/O net (fo=1, routed) 0.035 3.087 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[11] SLICE_X71Y567 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.706 3.131 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X71Y567 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.211 2.920 SLICE_X71Y567 FDRE (Hold_CFF_SLICEM_C_D) 0.127 3.047 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -3.047 arrival time 3.087 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[37]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[37]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.049ns (27.528%) route 0.129ns (72.472%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.974ns (routing 0.318ns, distribution 0.656ns) Clock Net Delay (Destination): 1.164ns (routing 0.368ns, distribution 0.796ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y573 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[37]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y573 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[37]/Q net (fo=1, routed) 0.129 1.268 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[37] SLICE_X63Y573 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.164 1.316 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X63Y573 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[37]/C clock pessimism -0.147 1.169 SLICE_X63Y573 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.225 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[37] ------------------------------------------------------------------- required time -1.225 arrival time 1.268 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.005ns (routing 0.318ns, distribution 0.687ns) Clock Net Delay (Destination): 1.204ns (routing 0.368ns, distribution 0.836ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y568 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y568 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.170 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.034 1.204 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in SLICE_X72Y568 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.249 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__45/O net (fo=1, routed) 0.016 1.265 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] SLICE_X72Y568 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.204 1.356 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y568 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.191 1.165 SLICE_X72Y568 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.221 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -1.221 arrival time 1.265 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[46].rx_data_ngccm_reg[46][78]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[78]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.453ns (logic 0.269ns (59.382%) route 0.184ns (40.618%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.279ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.100ns Source Clock Delay (SCD): 2.610ns Clock Pessimism Removal (CPR): 0.211ns Clock Net Delay (Source): 2.234ns (routing 0.634ns, distribution 1.600ns) Clock Net Delay (Destination): 2.675ns (routing 0.697ns, distribution 1.978ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 0.030 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 0.376 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.234 2.610 g_gbt_bank[3].gbtbank_n_124 SLICE_X70Y565 FDCE r SFP_GEN[46].rx_data_ngccm_reg[46][78]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y565 FDCE (Prop_CFF2_SLICEM_C_Q) 0.123 2.733 r SFP_GEN[46].rx_data_ngccm_reg[46][78]/Q net (fo=1, routed) 0.156 2.889 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[83]_0[70] SLICE_X71Y565 LUT3 (Prop_H5LUT_SLICEM_I1_O) 0.146 3.035 r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[78]_i_1/O net (fo=1, routed) 0.028 3.063 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[78]_i_1_n_0 SLICE_X71Y565 FDCE r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[78]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.675 3.100 SFP_GEN[46].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X71Y565 FDCE r SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[78]/C clock pessimism -0.211 2.889 SLICE_X71Y565 FDCE (Hold_HFF2_SLICEM_C_D) 0.128 3.017 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[78] ------------------------------------------------------------------- required time -3.017 arrival time 3.063 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.191ns Clock Net Delay (Source): 1.005ns (routing 0.318ns, distribution 0.687ns) Clock Net Delay (Destination): 1.204ns (routing 0.368ns, distribution 0.836ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.121 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y568 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y568 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.170 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.034 1.204 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in SLICE_X72Y568 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.055 1.259 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__45/O net (fo=1, routed) 0.011 1.270 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] SLICE_X72Y568 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.204 1.356 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X72Y568 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.191 1.165 SLICE_X72Y568 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.221 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -1.221 arrival time 1.270 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_37 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.088ns (45.833%) route 0.104ns (54.167%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.325ns Source Clock Delay (SCD): 1.092ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.976ns (routing 0.318ns, distribution 0.658ns) Clock Net Delay (Destination): 1.173ns (routing 0.368ns, distribution 0.805ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.976 1.092 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X65Y570 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y570 FDCE (Prop_BFF2_SLICEM_C_Q) 0.048 1.140 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.092 1.232 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_7_in SLICE_X65Y569 LUT3 (Prop_D5LUT_SLICEM_I2_O) 0.040 1.272 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__45/O net (fo=1, routed) 0.012 1.284 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[2] SLICE_X65Y569 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.173 1.325 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X65Y569 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.147 1.178 SLICE_X65Y569 FDRE (Hold_DFF2_SLICEM_C_D) 0.056 1.234 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -1.234 arrival time 1.284 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_37 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y221 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y540 g_clock_rate_din[46].ngccm_status_cnt_reg[46][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y540 g_clock_rate_din[46].ngccm_status_cnt_reg[46][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y541 g_clock_rate_din[46].ngccm_status_cnt_reg[46][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y540 g_clock_rate_din[46].ngccm_status_cnt_reg[46][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y540 g_clock_rate_din[46].ngccm_status_cnt_reg[46][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X64Y540 g_clock_rate_din[46].ngccm_status_cnt_reg[46][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X70Y540 g_clock_rate_din[46].ngccm_status_cnt_reg[46][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y540 g_clock_rate_din[46].ngccm_status_cnt_reg[46][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y540 g_clock_rate_din[46].ngccm_status_cnt_reg[46][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y540 g_clock_rate_din[46].ngccm_status_cnt_reg[46][3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y540 g_clock_rate_din[46].ngccm_status_cnt_reg[46][4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y540 g_clock_rate_din[46].ngccm_status_cnt_reg[46][5]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X64Y541 g_clock_rate_din[46].ngccm_status_cnt_reg[46][7]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X66Y543 SFP_GEN[46].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X64Y564 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[16]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X64Y564 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[19]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X64Y564 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[20]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X64Y564 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[21]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X65Y560 SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[22]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.026 0.504 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.014 0.505 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.014 0.868 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.026 1.302 GTHE3_CHANNEL_X0Y38 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_38 To Clock: gtwiz_userclk_rx_srcclk_out[0]_38 Setup : 0 Failing Endpoints, Worst Slack 3.225ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.032ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.225ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.306ns (logic 1.086ns (20.467%) route 4.220ns (79.533%)) Logic Levels: 0 Clock Path Skew: 0.186ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.594ns = ( 10.911 - 8.317 ) Source Clock Delay (SCD): 2.600ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.175ns (routing 0.691ns, distribution 1.484ns) Clock Net Delay (Destination): 2.218ns (routing 0.628ns, distribution 1.590ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.175 2.600 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.686 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 4.220 7.906 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[1] SLICE_X61Y596 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.218 10.911 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X61Y596 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61]/C clock pessimism 0.192 11.103 clock uncertainty -0.035 11.068 SLICE_X61Y596 FDCE (Setup_HFF_SLICEM_C_D) 0.063 11.131 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[61] ------------------------------------------------------------------- required time 11.131 arrival time -7.906 ------------------------------------------------------------------- slack 3.225 Slack (MET) : 3.437ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[84]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.094ns (logic 1.188ns (23.322%) route 3.906ns (76.678%)) Logic Levels: 0 Clock Path Skew: 0.186ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.594ns = ( 10.911 - 8.317 ) Source Clock Delay (SCD): 2.600ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.175ns (routing 0.691ns, distribution 1.484ns) Clock Net Delay (Destination): 2.218ns (routing 0.628ns, distribution 1.590ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.175 2.600 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[4]) 1.188 3.788 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[4] net (fo=6, routed) 3.906 7.694 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[4] SLICE_X61Y597 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[84]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.218 10.911 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X61Y597 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[84]/C clock pessimism 0.192 11.103 clock uncertainty -0.035 11.068 SLICE_X61Y597 FDCE (Setup_HFF_SLICEM_C_D) 0.063 11.131 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[84] ------------------------------------------------------------------- required time 11.131 arrival time -7.694 ------------------------------------------------------------------- slack 3.437 Slack (MET) : 3.441ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.963ns (logic 1.565ns (31.533%) route 3.398ns (68.467%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.584ns = ( 10.901 - 8.317 ) Source Clock Delay (SCD): 2.600ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.175ns (routing 0.691ns, distribution 1.484ns) Clock Net Delay (Destination): 2.208ns (routing 0.628ns, distribution 1.580ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.175 2.600 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.686 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.658 6.344 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y598 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.569 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.307 6.876 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y598 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.165 7.041 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46/O net (fo=1, routed) 0.069 7.110 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46_n_0 SLICE_X51Y598 LUT6 (Prop_A6LUT_SLICEL_I5_O) 0.089 7.199 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46/O net (fo=2, routed) 0.364 7.563 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46_n_0 SLICE_X54Y598 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.208 10.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X54Y598 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.192 11.093 clock uncertainty -0.035 11.058 SLICE_X54Y598 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 11.004 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.004 arrival time -7.563 ------------------------------------------------------------------- slack 3.441 Slack (MET) : 3.441ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.963ns (logic 1.565ns (31.533%) route 3.398ns (68.467%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.584ns = ( 10.901 - 8.317 ) Source Clock Delay (SCD): 2.600ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.175ns (routing 0.691ns, distribution 1.484ns) Clock Net Delay (Destination): 2.208ns (routing 0.628ns, distribution 1.580ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.175 2.600 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.686 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.658 6.344 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y598 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.569 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.307 6.876 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y598 LUT4 (Prop_C6LUT_SLICEL_I2_O) 0.165 7.041 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46/O net (fo=1, routed) 0.069 7.110 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46_n_0 SLICE_X51Y598 LUT6 (Prop_A6LUT_SLICEL_I5_O) 0.089 7.199 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46/O net (fo=2, routed) 0.364 7.563 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46_n_0 SLICE_X54Y598 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.208 10.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X54Y598 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.192 11.093 clock uncertainty -0.035 11.058 SLICE_X54Y598 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 11.004 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.004 arrival time -7.563 ------------------------------------------------------------------- slack 3.441 Slack (MET) : 3.494ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.924ns (logic 1.457ns (29.590%) route 3.467ns (70.410%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.599ns = ( 10.916 - 8.317 ) Source Clock Delay (SCD): 2.600ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.175ns (routing 0.691ns, distribution 1.484ns) Clock Net Delay (Destination): 2.223ns (routing 0.628ns, distribution 1.595ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.175 2.600 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.686 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.658 6.344 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y598 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.569 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.184 6.753 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y598 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 6.899 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/O net (fo=7, routed) 0.625 7.524 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X53Y597 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.223 10.916 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X53Y597 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.192 11.108 clock uncertainty -0.035 11.073 SLICE_X53Y597 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.018 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.018 arrival time -7.524 ------------------------------------------------------------------- slack 3.494 Slack (MET) : 3.498ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.921ns (logic 1.457ns (29.608%) route 3.464ns (70.392%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.599ns = ( 10.916 - 8.317 ) Source Clock Delay (SCD): 2.600ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.175ns (routing 0.691ns, distribution 1.484ns) Clock Net Delay (Destination): 2.223ns (routing 0.628ns, distribution 1.595ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.175 2.600 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.686 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.658 6.344 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y598 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.569 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.184 6.753 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y598 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 6.899 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/O net (fo=7, routed) 0.622 7.521 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X53Y597 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.223 10.916 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X53Y597 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.192 11.108 clock uncertainty -0.035 11.073 SLICE_X53Y597 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.019 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.019 arrival time -7.521 ------------------------------------------------------------------- slack 3.498 Slack (MET) : 3.530ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[101]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 5.007ns (logic 1.086ns (21.690%) route 3.921ns (78.310%)) Logic Levels: 0 Clock Path Skew: 0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.596ns = ( 10.913 - 8.317 ) Source Clock Delay (SCD): 2.600ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.175ns (routing 0.691ns, distribution 1.484ns) Clock Net Delay (Destination): 2.220ns (routing 0.628ns, distribution 1.592ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.175 2.600 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.686 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 3.921 7.607 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[1] SLICE_X61Y596 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[101]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.220 10.913 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X61Y596 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[101]/C clock pessimism 0.192 11.105 clock uncertainty -0.035 11.070 SLICE_X61Y596 FDCE (Setup_DFF2_SLICEM_C_D) 0.067 11.137 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[101] ------------------------------------------------------------------- required time 11.137 arrival time -7.607 ------------------------------------------------------------------- slack 3.530 Slack (MET) : 3.577ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[33]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.955ns (logic 1.308ns (26.398%) route 3.647ns (73.602%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.595ns = ( 10.912 - 8.317 ) Source Clock Delay (SCD): 2.600ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.175ns (routing 0.691ns, distribution 1.484ns) Clock Net Delay (Destination): 2.219ns (routing 0.628ns, distribution 1.591ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.175 2.600 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[11]) 1.084 3.684 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[11] net (fo=6, routed) 3.609 7.293 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/D[13] SLICE_X64Y596 LUT5 (Prop_C6LUT_SLICEM_I3_O) 0.224 7.517 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[33]_i_1__38/O net (fo=1, routed) 0.038 7.555 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[33] SLICE_X64Y596 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[33]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.219 10.912 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X64Y596 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[33]/C clock pessimism 0.192 11.104 clock uncertainty -0.035 11.069 SLICE_X64Y596 FDCE (Setup_CFF_SLICEM_C_D) 0.063 11.132 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[33] ------------------------------------------------------------------- required time 11.132 arrival time -7.555 ------------------------------------------------------------------- slack 3.577 Slack (MET) : 3.594ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.803ns (logic 1.457ns (30.335%) route 3.346ns (69.665%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.578ns = ( 10.895 - 8.317 ) Source Clock Delay (SCD): 2.600ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.175ns (routing 0.691ns, distribution 1.484ns) Clock Net Delay (Destination): 2.202ns (routing 0.628ns, distribution 1.574ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.175 2.600 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.686 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.658 6.344 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y598 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.569 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.184 6.753 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y598 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 6.899 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/O net (fo=7, routed) 0.504 7.403 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X52Y597 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.202 10.895 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X52Y597 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.192 11.087 clock uncertainty -0.035 11.052 SLICE_X52Y597 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.997 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 10.997 arrival time -7.403 ------------------------------------------------------------------- slack 3.594 Slack (MET) : 3.606ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.786ns (logic 1.457ns (30.443%) route 3.329ns (69.557%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.168ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.576ns = ( 10.893 - 8.317 ) Source Clock Delay (SCD): 2.600ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.175ns (routing 0.691ns, distribution 1.484ns) Clock Net Delay (Destination): 2.200ns (routing 0.628ns, distribution 1.572ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.175 2.600 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.686 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.658 6.344 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y598 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.569 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/O net (fo=5, routed) 0.184 6.753 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X51Y598 LUT5 (Prop_F6LUT_SLICEL_I3_O) 0.146 6.899 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/O net (fo=7, routed) 0.487 7.386 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 SLICE_X51Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.200 10.893 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK SLICE_X51Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.192 11.085 clock uncertainty -0.035 11.050 SLICE_X51Y598 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.992 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.992 arrival time -7.386 ------------------------------------------------------------------- slack 3.606 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.032ns (arrival time - required time) Source: SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[23]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.048ns (32.653%) route 0.099ns (67.347%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.092ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.976ns (routing 0.317ns, distribution 0.659ns) Clock Net Delay (Destination): 1.175ns (routing 0.366ns, distribution 0.809ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.976 1.092 SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X60Y586 FDCE r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[23]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y586 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.140 r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[23]/Q net (fo=5, routed) 0.099 1.239 SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/Q[7] SLICE_X60Y584 FDRE r SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.175 1.327 SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X60Y584 FDRE r SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/C clock pessimism -0.176 1.151 SLICE_X60Y584 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.207 SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7] ------------------------------------------------------------------- required time -1.207 arrival time 1.239 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].rx_data_ngccm_reg[47][48]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.344ns Source Clock Delay (SCD): 1.113ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.997ns (routing 0.317ns, distribution 0.680ns) Clock Net Delay (Destination): 1.192ns (routing 0.366ns, distribution 0.826ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.113 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X66Y588 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y588 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.161 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/Q net (fo=1, routed) 0.094 1.255 rx_data[47][48] SLICE_X66Y589 FDCE r SFP_GEN[47].rx_data_ngccm_reg[47][48]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.344 g_gbt_bank[3].gbtbank_n_134 SLICE_X66Y589 FDCE r SFP_GEN[47].rx_data_ngccm_reg[47][48]/C clock pessimism -0.178 1.166 SLICE_X66Y589 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.222 SFP_GEN[47].rx_data_ngccm_reg[47][48] ------------------------------------------------------------------- required time -1.222 arrival time 1.255 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.063ns (37.059%) route 0.107ns (62.941%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.328ns Source Clock Delay (SCD): 1.105ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.176ns (routing 0.366ns, distribution 0.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.105 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y594 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.153 f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.091 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X64Y594 LUT5 (Prop_C6LUT_SLICEM_I1_O) 0.015 1.259 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[26]_i_1__38/O net (fo=1, routed) 0.016 1.275 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[26] SLICE_X64Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.176 1.328 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X64Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/C clock pessimism -0.145 1.183 SLICE_X64Y594 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.239 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26] ------------------------------------------------------------------- required time -1.239 arrival time 1.275 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.064ns (36.782%) route 0.110ns (63.218%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.328ns Source Clock Delay (SCD): 1.105ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.176ns (routing 0.366ns, distribution 0.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.105 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y594 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.153 f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.094 1.247 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X64Y594 LUT5 (Prop_D6LUT_SLICEM_I1_O) 0.016 1.263 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[25]_i_1__38/O net (fo=1, routed) 0.016 1.279 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[25] SLICE_X64Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.176 1.328 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X64Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25]/C clock pessimism -0.145 1.183 SLICE_X64Y594 FDCE (Hold_DFF_SLICEM_C_D) 0.056 1.239 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[25] ------------------------------------------------------------------- required time -1.239 arrival time 1.279 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.164ns (logic 0.064ns (39.024%) route 0.100ns (60.976%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.105ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.166ns (routing 0.366ns, distribution 0.800ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.105 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y594 FDCE (Prop_CFF2_SLICEL_C_Q) 0.048 1.153 f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Q net (fo=28, routed) 0.084 1.237 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] SLICE_X64Y593 LUT5 (Prop_H6LUT_SLICEM_I0_O) 0.016 1.253 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[24]_i_1__38/O net (fo=1, routed) 0.016 1.269 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[24] SLICE_X64Y593 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.318 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X64Y593 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24]/C clock pessimism -0.145 1.173 SLICE_X64Y593 FDCE (Hold_HFF_SLICEM_C_D) 0.056 1.229 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[24] ------------------------------------------------------------------- required time -1.229 arrival time 1.269 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].rx_data_ngccm_reg[47][79]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.048ns (33.103%) route 0.097ns (66.897%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 1.000ns (routing 0.317ns, distribution 0.683ns) Clock Net Delay (Destination): 1.190ns (routing 0.366ns, distribution 0.824ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.116 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X66Y592 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y592 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.164 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/Q net (fo=1, routed) 0.097 1.261 rx_data[47][79] SLICE_X66Y590 FDCE r SFP_GEN[47].rx_data_ngccm_reg[47][79]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.342 g_gbt_bank[3].gbtbank_n_134 SLICE_X66Y590 FDCE r SFP_GEN[47].rx_data_ngccm_reg[47][79]/C clock pessimism -0.178 1.164 SLICE_X66Y590 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.219 SFP_GEN[47].rx_data_ngccm_reg[47][79] ------------------------------------------------------------------- required time -1.219 arrival time 1.261 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].rx_data_ngccm_reg[47][55]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.049ns (27.072%) route 0.132ns (72.928%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.333ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.993ns (routing 0.317ns, distribution 0.676ns) Clock Net Delay (Destination): 1.181ns (routing 0.366ns, distribution 0.815ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.109 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X68Y592 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X68Y592 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.132 1.290 rx_data[47][55] SLICE_X69Y592 FDCE r SFP_GEN[47].rx_data_ngccm_reg[47][55]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.181 1.333 g_gbt_bank[3].gbtbank_n_134 SLICE_X69Y592 FDCE r SFP_GEN[47].rx_data_ngccm_reg[47][55]/C clock pessimism -0.145 1.188 SLICE_X69Y592 FDCE (Hold_GFF_SLICEL_C_D) 0.056 1.244 SFP_GEN[47].rx_data_ngccm_reg[47][55] ------------------------------------------------------------------- required time -1.244 arrival time 1.290 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[27]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.049ns (29.341%) route 0.118ns (70.659%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.310ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.984ns (routing 0.317ns, distribution 0.667ns) Clock Net Delay (Destination): 1.158ns (routing 0.366ns, distribution 0.792ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.984 1.100 SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y585 FDCE r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y585 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.149 r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[27]/Q net (fo=2, routed) 0.118 1.267 SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/Q[11] SLICE_X59Y585 FDRE r SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.158 1.310 SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y585 FDRE r SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C clock pessimism -0.145 1.165 SLICE_X59Y585 FDRE (Hold_GFF2_SLICEM_C_D) 0.056 1.221 SFP_GEN[47].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11] ------------------------------------------------------------------- required time -1.221 arrival time 1.267 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[37]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.078ns (43.094%) route 0.103ns (56.906%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.328ns Source Clock Delay (SCD): 1.105ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.176ns (routing 0.366ns, distribution 0.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.105 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X63Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y594 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.153 f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.091 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X64Y594 LUT5 (Prop_A6LUT_SLICEM_I1_O) 0.030 1.274 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[37]_i_1__38/O net (fo=1, routed) 0.012 1.286 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg00[37] SLICE_X64Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[37]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.176 1.328 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X64Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[37]/C clock pessimism -0.145 1.183 SLICE_X64Y594 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.239 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[37] ------------------------------------------------------------------- required time -1.239 arrival time 1.286 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_38 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.079ns (49.068%) route 0.082ns (50.932%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.106ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.990ns (routing 0.317ns, distribution 0.673ns) Clock Net Delay (Destination): 1.190ns (routing 0.366ns, distribution 0.824ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.106 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X66Y593 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y593 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.154 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.066 1.220 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_13_in SLICE_X66Y592 LUT3 (Prop_H6LUT_SLICEL_I2_O) 0.031 1.251 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__46/O net (fo=1, routed) 0.016 1.267 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] SLICE_X66Y592 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.342 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X66Y592 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.178 1.164 SLICE_X66Y592 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.220 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.220 arrival time 1.267 ------------------------------------------------------------------- slack 0.047 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_38 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y220 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X60Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X60Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X60Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X60Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X60Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X62Y541 g_clock_rate_din[47].ngccm_status_cnt_reg[47][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X60Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X48Y541 g_clock_rate_din[47].rx_wordclk_div2_reg[47]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][1]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X60Y540 g_clock_rate_din[47].ngccm_status_cnt_reg[47][2]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y584 SFP_GEN[47].ngCCM_gbt/RX_Clock_40MHz_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X65Y588 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[44]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X65Y588 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[46]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X65Y588 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[76]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X65Y588 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[78]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X61Y586 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[80]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y39 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_39 To Clock: gtwiz_userclk_rx_srcclk_out[0]_39 Setup : 0 Failing Endpoints, Worst Slack 4.185ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.037ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.185ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.865ns (logic 1.496ns (38.706%) route 2.369ns (61.294%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.177ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 3.070ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.645ns (routing 1.110ns, distribution 1.535ns) Clock Net Delay (Destination): 2.294ns (routing 1.013ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.645 3.070 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.156 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.623 5.779 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X22Y442 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.946 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/O net (fo=5, routed) 0.204 6.150 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X22Y443 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 6.393 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/O net (fo=7, routed) 0.542 6.935 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X23Y445 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.294 10.987 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X23Y445 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.223 11.210 clock uncertainty -0.035 11.175 SLICE_X23Y445 FDRE (Setup_BFF2_SLICEM_C_CE) -0.055 11.120 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.120 arrival time -6.935 ------------------------------------------------------------------- slack 4.185 Slack (MET) : 4.189ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.862ns (logic 1.496ns (38.736%) route 2.366ns (61.264%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.177ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.670ns = ( 10.987 - 8.317 ) Source Clock Delay (SCD): 3.070ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.645ns (routing 1.110ns, distribution 1.535ns) Clock Net Delay (Destination): 2.294ns (routing 1.013ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.645 3.070 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.156 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.623 5.779 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X22Y442 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.946 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/O net (fo=5, routed) 0.204 6.150 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X22Y443 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 6.393 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/O net (fo=7, routed) 0.539 6.932 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X23Y445 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.294 10.987 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X23Y445 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.223 11.210 clock uncertainty -0.035 11.175 SLICE_X23Y445 FDRE (Setup_BFF_SLICEM_C_CE) -0.054 11.121 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.121 arrival time -6.932 ------------------------------------------------------------------- slack 4.189 Slack (MET) : 4.266ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.782ns (logic 1.496ns (39.556%) route 2.286ns (60.444%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.671ns = ( 10.988 - 8.317 ) Source Clock Delay (SCD): 3.070ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.645ns (routing 1.110ns, distribution 1.535ns) Clock Net Delay (Destination): 2.295ns (routing 1.013ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.645 3.070 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.156 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.623 5.779 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X22Y442 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.946 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/O net (fo=5, routed) 0.204 6.150 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X22Y443 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 6.393 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/O net (fo=7, routed) 0.459 6.852 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X23Y443 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.295 10.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X23Y443 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.223 11.211 clock uncertainty -0.035 11.176 SLICE_X23Y443 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.118 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.118 arrival time -6.852 ------------------------------------------------------------------- slack 4.266 Slack (MET) : 4.272ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.779ns (logic 1.496ns (39.587%) route 2.283ns (60.413%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.671ns = ( 10.988 - 8.317 ) Source Clock Delay (SCD): 3.070ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.645ns (routing 1.110ns, distribution 1.535ns) Clock Net Delay (Destination): 2.295ns (routing 1.013ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.645 3.070 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.156 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.623 5.779 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X22Y442 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.946 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/O net (fo=5, routed) 0.204 6.150 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X22Y443 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 6.393 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/O net (fo=7, routed) 0.456 6.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X23Y443 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.295 10.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X23Y443 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.223 11.211 clock uncertainty -0.035 11.176 SLICE_X23Y443 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.121 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 11.121 arrival time -6.849 ------------------------------------------------------------------- slack 4.272 Slack (MET) : 4.272ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.779ns (logic 1.496ns (39.587%) route 2.283ns (60.413%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.671ns = ( 10.988 - 8.317 ) Source Clock Delay (SCD): 3.070ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.645ns (routing 1.110ns, distribution 1.535ns) Clock Net Delay (Destination): 2.295ns (routing 1.013ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.645 3.070 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.156 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.623 5.779 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X22Y442 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.946 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/O net (fo=5, routed) 0.204 6.150 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X22Y443 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 6.393 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/O net (fo=7, routed) 0.456 6.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X23Y443 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.295 10.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X23Y443 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.223 11.211 clock uncertainty -0.035 11.176 SLICE_X23Y443 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 11.121 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.121 arrival time -6.849 ------------------------------------------------------------------- slack 4.272 Slack (MET) : 4.272ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.779ns (logic 1.496ns (39.587%) route 2.283ns (60.413%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.671ns = ( 10.988 - 8.317 ) Source Clock Delay (SCD): 3.070ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.645ns (routing 1.110ns, distribution 1.535ns) Clock Net Delay (Destination): 2.295ns (routing 1.013ns, distribution 1.282ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.645 3.070 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.156 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.623 5.779 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X22Y442 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.946 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/O net (fo=5, routed) 0.204 6.150 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X22Y443 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 6.393 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/O net (fo=7, routed) 0.456 6.849 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X23Y443 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.295 10.988 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X23Y443 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.223 11.211 clock uncertainty -0.035 11.176 SLICE_X23Y443 FDRE (Setup_GFF_SLICEM_C_CE) -0.055 11.121 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.121 arrival time -6.849 ------------------------------------------------------------------- slack 4.272 Slack (MET) : 4.357ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.817ns (logic 1.496ns (39.193%) route 2.321ns (60.807%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.787ns = ( 11.104 - 8.317 ) Source Clock Delay (SCD): 3.070ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.645ns (routing 1.110ns, distribution 1.535ns) Clock Net Delay (Destination): 2.411ns (routing 1.013ns, distribution 1.398ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.645 3.070 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.156 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.623 5.779 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X22Y442 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.946 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/O net (fo=5, routed) 0.204 6.150 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X22Y443 LUT5 (Prop_A6LUT_SLICEM_I3_O) 0.243 6.393 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__37/O net (fo=7, routed) 0.494 6.887 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 SLICE_X22Y442 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.411 11.104 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X22Y442 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.233 11.337 clock uncertainty -0.035 11.302 SLICE_X22Y442 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 11.244 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 11.244 arrival time -6.887 ------------------------------------------------------------------- slack 4.357 Slack (MET) : 4.431ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.747ns (logic 1.496ns (39.925%) route 2.251ns (60.075%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.788ns = ( 11.105 - 8.317 ) Source Clock Delay (SCD): 3.070ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.645ns (routing 1.110ns, distribution 1.535ns) Clock Net Delay (Destination): 2.412ns (routing 1.013ns, distribution 1.399ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.645 3.070 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.156 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.623 5.779 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X22Y442 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.946 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/O net (fo=5, routed) 0.208 6.154 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X22Y443 LUT6 (Prop_B6LUT_SLICEM_I1_O) 0.243 6.397 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__36/O net (fo=2, routed) 0.420 6.817 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__36_n_0 SLICE_X22Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.412 11.105 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X22Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.233 11.338 clock uncertainty -0.035 11.303 SLICE_X22Y441 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.248 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.248 arrival time -6.817 ------------------------------------------------------------------- slack 4.431 Slack (MET) : 4.431ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.747ns (logic 1.496ns (39.925%) route 2.251ns (60.075%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.788ns = ( 11.105 - 8.317 ) Source Clock Delay (SCD): 3.070ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.645ns (routing 1.110ns, distribution 1.535ns) Clock Net Delay (Destination): 2.412ns (routing 1.013ns, distribution 1.399ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.645 3.070 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.156 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.623 5.779 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X22Y442 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.946 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/O net (fo=5, routed) 0.208 6.154 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X22Y443 LUT6 (Prop_B6LUT_SLICEM_I1_O) 0.243 6.397 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__36/O net (fo=2, routed) 0.420 6.817 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__36_n_0 SLICE_X22Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.412 11.105 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X22Y441 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.233 11.338 clock uncertainty -0.035 11.303 SLICE_X22Y441 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.248 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.248 arrival time -6.817 ------------------------------------------------------------------- slack 4.431 Slack (MET) : 4.434ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.746ns (logic 1.405ns (37.507%) route 2.341ns (62.493%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.047ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.790ns = ( 11.107 - 8.317 ) Source Clock Delay (SCD): 3.070ns Clock Pessimism Removal (CPR): 0.233ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.645ns (routing 1.110ns, distribution 1.535ns) Clock Net Delay (Destination): 2.414ns (routing 1.013ns, distribution 1.401ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.645 3.070 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 4.156 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 1.623 5.779 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X22Y442 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.946 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__36/O net (fo=5, routed) 0.202 6.148 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X22Y444 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.152 6.300 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__37/O net (fo=5, routed) 0.516 6.816 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 SLICE_X22Y441 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.414 11.107 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/CLK SLICE_X22Y441 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C clock pessimism 0.233 11.340 clock uncertainty -0.035 11.305 SLICE_X22Y441 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.250 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1] ------------------------------------------------------------------- required time 11.250 arrival time -6.816 ------------------------------------------------------------------- slack 4.434 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.037ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.079ns (47.305%) route 0.088ns (52.695%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.137ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.021ns (routing 0.483ns, distribution 0.538ns) Clock Net Delay (Destination): 1.207ns (routing 0.550ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.137 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X24Y436 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y436 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.186 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.076 1.262 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/O85[1] SLICE_X25Y436 LUT3 (Prop_A6LUT_SLICEM_I0_O) 0.030 1.292 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__36/O net (fo=1, routed) 0.012 1.304 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[1] SLICE_X25Y436 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.207 1.359 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X25Y436 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.148 1.211 SLICE_X25Y436 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.267 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.267 arrival time 1.304 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.064ns (42.953%) route 0.085ns (57.047%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.364ns Source Clock Delay (SCD): 1.132ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 1.016ns (routing 0.483ns, distribution 0.533ns) Clock Net Delay (Destination): 1.212ns (routing 0.550ns, distribution 0.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.132 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X24Y437 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y437 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.181 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.070 1.251 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/O84[0] SLICE_X24Y438 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.015 1.266 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__36/O net (fo=1, routed) 0.015 1.281 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] SLICE_X24Y438 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.212 1.364 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X24Y438 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.178 1.186 SLICE_X24Y438 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.242 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.242 arrival time 1.281 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][61]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.049ns (33.562%) route 0.097ns (66.438%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.363ns Source Clock Delay (SCD): 1.135ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 1.019ns (routing 0.483ns, distribution 0.536ns) Clock Net Delay (Destination): 1.211ns (routing 0.550ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.135 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X24Y438 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y438 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.184 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/Q net (fo=1, routed) 0.097 1.281 rx_data[37][61] SLICE_X24Y436 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][61]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.363 g_gbt_bank[3].gbtbank_n_34 SLICE_X24Y436 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][61]/C clock pessimism -0.178 1.185 SLICE_X24Y436 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.240 SFP_GEN[37].rx_data_ngccm_reg[37][61] ------------------------------------------------------------------- required time -1.240 arrival time 1.281 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][67]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.157ns (logic 0.048ns (30.573%) route 0.109ns (69.427%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.123ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 1.007ns (routing 0.483ns, distribution 0.524ns) Clock Net Delay (Destination): 1.207ns (routing 0.550ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.123 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X24Y435 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y435 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.171 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.109 1.280 rx_data[37][67] SLICE_X24Y434 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][67]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.207 1.359 g_gbt_bank[3].gbtbank_n_34 SLICE_X24Y434 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][67]/C clock pessimism -0.178 1.181 SLICE_X24Y434 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.237 SFP_GEN[37].rx_data_ngccm_reg[37][67] ------------------------------------------------------------------- required time -1.237 arrival time 1.280 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.164ns (logic 0.064ns (39.024%) route 0.100ns (60.976%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.129ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.013ns (routing 0.483ns, distribution 0.530ns) Clock Net Delay (Destination): 1.190ns (routing 0.550ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.013 1.129 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X28Y431 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y431 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.178 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/Q net (fo=10, routed) 0.084 1.262 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gbtBank_Clk_gen[1].cnt_reg[1][7]_0[0] SLICE_X27Y431 LUT6 (Prop_D6LUT_SLICEL_I4_O) 0.015 1.277 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i[1]_i_1__2/O net (fo=1, routed) 0.016 1.293 g_gbt_bank[3].gbtbank/i_gbt_bank_n_146 SLICE_X27Y431 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.342 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X27Y431 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C clock pessimism -0.148 1.194 SLICE_X27Y431 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.250 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1] ------------------------------------------------------------------- required time -1.250 arrival time 1.293 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.104ns (53.886%) route 0.089ns (46.114%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.363ns Source Clock Delay (SCD): 1.122ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.006ns (routing 0.483ns, distribution 0.523ns) Clock Net Delay (Destination): 1.211ns (routing 0.550ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.006 1.122 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X25Y439 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y439 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.171 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.078 1.249 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_31_in SLICE_X24Y439 LUT3 (Prop_C5LUT_SLICEL_I2_O) 0.055 1.304 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__36/O net (fo=1, routed) 0.011 1.315 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[14] SLICE_X24Y439 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.211 1.363 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X24Y439 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.148 1.215 SLICE_X24Y439 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.271 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -1.271 arrival time 1.315 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].rx_data_ngccm_reg[37][68]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.049ns (26.344%) route 0.137ns (73.656%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.010ns (routing 0.483ns, distribution 0.527ns) Clock Net Delay (Destination): 1.207ns (routing 0.550ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.126 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X25Y434 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y434 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.175 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.137 1.312 rx_data[37][68] SLICE_X24Y434 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][68]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.207 1.359 g_gbt_bank[3].gbtbank_n_34 SLICE_X24Y434 FDCE r SFP_GEN[37].rx_data_ngccm_reg[37][68]/C clock pessimism -0.148 1.211 SLICE_X24Y434 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 1.267 SFP_GEN[37].rx_data_ngccm_reg[37][68] ------------------------------------------------------------------- required time -1.267 arrival time 1.312 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.370ns Source Clock Delay (SCD): 1.140ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 1.024ns (routing 0.483ns, distribution 0.541ns) Clock Net Delay (Destination): 1.218ns (routing 0.550ns, distribution 0.668ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.024 1.140 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X29Y436 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y436 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.189 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.035 1.224 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X29Y436 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.269 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__36/O net (fo=1, routed) 0.016 1.285 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] SLICE_X29Y436 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.370 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X29Y436 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.189 1.181 SLICE_X29Y436 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.237 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.237 arrival time 1.285 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.179ns (logic 0.088ns (49.162%) route 0.091ns (50.838%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.137ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.021ns (routing 0.483ns, distribution 0.538ns) Clock Net Delay (Destination): 1.207ns (routing 0.550ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.137 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X24Y436 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y436 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.186 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.078 1.264 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[1] SLICE_X25Y436 LUT3 (Prop_B5LUT_SLICEM_I2_O) 0.039 1.303 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__36/O net (fo=1, routed) 0.013 1.316 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[18] SLICE_X25Y436 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.207 1.359 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X25Y436 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.148 1.211 SLICE_X25Y436 FDRE (Hold_BFF2_SLICEM_C_D) 0.056 1.267 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -1.267 arrival time 1.316 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_39 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.095ns (64.626%) route 0.052ns (35.374%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.364ns Source Clock Delay (SCD): 1.134ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 1.018ns (routing 0.483ns, distribution 0.535ns) Clock Net Delay (Destination): 1.212ns (routing 0.550ns, distribution 0.662ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.134 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X23Y439 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X23Y439 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.183 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.036 1.219 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_3_in SLICE_X23Y439 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.046 1.265 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__36/O net (fo=1, routed) 0.016 1.281 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[0] SLICE_X23Y439 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.212 1.364 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X23Y439 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.189 1.175 SLICE_X23Y439 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.231 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.231 arrival time 1.281 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_39 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y172 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y416 g_clock_rate_din[37].ngccm_status_cnt_reg[37][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y419 g_clock_rate_din[37].ngccm_status_cnt_reg[37][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X52Y418 g_clock_rate_din[37].ngccm_status_cnt_reg[37][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X52Y418 g_clock_rate_din[37].ngccm_status_cnt_reg[37][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X52Y418 g_clock_rate_din[37].ngccm_status_cnt_reg[37][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X52Y418 g_clock_rate_din[37].ngccm_status_cnt_reg[37][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y419 g_clock_rate_din[37].ngccm_status_cnt_reg[37][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X31Y433 SFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X31Y433 SFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X31Y433 SFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X31Y433 SFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[3]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X26Y443 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[50]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y416 g_clock_rate_din[37].ngccm_status_cnt_reg[37][0]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X21Y427 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[50]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X21Y427 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[52]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X21Y426 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[54]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X21Y426 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[56]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X21Y426 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[58]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X21Y426 SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[60]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y29 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_40 To Clock: gtwiz_userclk_rx_srcclk_out[0]_40 Setup : 0 Failing Endpoints, Worst Slack 3.870ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.870ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 4.193ns (logic 1.520ns (36.251%) route 2.673ns (63.749%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.164ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.281ns = ( 10.598 - 8.317 ) Source Clock Delay (SCD): 2.634ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.209ns (routing 0.699ns, distribution 1.510ns) Clock Net Delay (Destination): 1.905ns (routing 0.636ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.209 2.634 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.718 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.502 5.220 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X30Y459 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.166 5.386 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.297 5.683 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X30Y458 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.219 5.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37/O net (fo=1, routed) 0.426 6.328 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37_n_0 SLICE_X30Y458 LUT6 (Prop_A6LUT_SLICEL_I5_O) 0.051 6.379 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37/O net (fo=2, routed) 0.448 6.827 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37_n_0 SLICE_X31Y461 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.905 10.598 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X31Y461 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.189 10.787 clock uncertainty -0.035 10.752 SLICE_X31Y461 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.697 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.697 arrival time -6.827 ------------------------------------------------------------------- slack 3.870 Slack (MET) : 3.876ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 4.190ns (logic 1.520ns (36.277%) route 2.670ns (63.723%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.283ns = ( 10.600 - 8.317 ) Source Clock Delay (SCD): 2.634ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.209ns (routing 0.699ns, distribution 1.510ns) Clock Net Delay (Destination): 1.907ns (routing 0.636ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.209 2.634 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.718 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.502 5.220 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X30Y459 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.166 5.386 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.297 5.683 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X30Y458 LUT4 (Prop_B6LUT_SLICEL_I2_O) 0.219 5.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37/O net (fo=1, routed) 0.426 6.328 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37_n_0 SLICE_X30Y458 LUT6 (Prop_A6LUT_SLICEL_I5_O) 0.051 6.379 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37/O net (fo=2, routed) 0.445 6.824 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37_n_0 SLICE_X31Y461 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.907 10.600 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X31Y461 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.189 10.789 clock uncertainty -0.035 10.754 SLICE_X31Y461 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 10.700 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.700 arrival time -6.824 ------------------------------------------------------------------- slack 3.876 Slack (MET) : 4.018ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 4.025ns (logic 1.339ns (33.267%) route 2.686ns (66.733%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.184ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.261ns = ( 10.578 - 8.317 ) Source Clock Delay (SCD): 2.634ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.209ns (routing 0.699ns, distribution 1.510ns) Clock Net Delay (Destination): 1.885ns (routing 0.636ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.209 2.634 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2]) 1.084 3.718 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2] net (fo=10, routed) 1.502 5.220 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] SLICE_X30Y459 LUT4 (Prop_D6LUT_SLICEL_I3_O) 0.166 5.386 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/O net (fo=5, routed) 0.404 5.790 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X30Y458 LUT5 (Prop_G6LUT_SLICEL_I3_O) 0.089 5.879 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/O net (fo=7, routed) 0.780 6.659 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 SLICE_X30Y458 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.885 10.578 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK SLICE_X30Y458 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.189 10.767 clock uncertainty -0.035 10.732 SLICE_X30Y458 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 10.677 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.677 arrival time -6.659 ------------------------------------------------------------------- slack 4.018 Slack (MET) : 4.065ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].rx_data_ngccm_reg[38][66]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.882ns (logic 0.312ns (8.037%) route 3.570ns (91.963%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.295ns = ( 10.612 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.919ns (routing 0.636ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.869 4.771 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X34Y458 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 4.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/O net (fo=76, routed) 1.701 6.645 rx_data_ngccm[38] SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][66]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.919 10.612 g_gbt_bank[3].gbtbank_n_44 SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][66]/C clock pessimism 0.188 10.800 clock uncertainty -0.035 10.765 SLICE_X29Y477 FDCE (Setup_AFF2_SLICEM_C_CE) -0.055 10.710 SFP_GEN[38].rx_data_ngccm_reg[38][66] ------------------------------------------------------------------- required time 10.710 arrival time -6.645 ------------------------------------------------------------------- slack 4.065 Slack (MET) : 4.065ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].rx_data_ngccm_reg[38][69]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.882ns (logic 0.312ns (8.037%) route 3.570ns (91.963%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.295ns = ( 10.612 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.919ns (routing 0.636ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.869 4.771 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X34Y458 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 4.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/O net (fo=76, routed) 1.701 6.645 rx_data_ngccm[38] SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][69]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.919 10.612 g_gbt_bank[3].gbtbank_n_44 SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][69]/C clock pessimism 0.188 10.800 clock uncertainty -0.035 10.765 SLICE_X29Y477 FDCE (Setup_BFF2_SLICEM_C_CE) -0.055 10.710 SFP_GEN[38].rx_data_ngccm_reg[38][69] ------------------------------------------------------------------- required time 10.710 arrival time -6.645 ------------------------------------------------------------------- slack 4.065 Slack (MET) : 4.065ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].rx_data_ngccm_reg[38][71]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.882ns (logic 0.312ns (8.037%) route 3.570ns (91.963%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.295ns = ( 10.612 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.919ns (routing 0.636ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.869 4.771 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X34Y458 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 4.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/O net (fo=76, routed) 1.701 6.645 rx_data_ngccm[38] SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][71]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.919 10.612 g_gbt_bank[3].gbtbank_n_44 SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][71]/C clock pessimism 0.188 10.800 clock uncertainty -0.035 10.765 SLICE_X29Y477 FDCE (Setup_CFF2_SLICEM_C_CE) -0.055 10.710 SFP_GEN[38].rx_data_ngccm_reg[38][71] ------------------------------------------------------------------- required time 10.710 arrival time -6.645 ------------------------------------------------------------------- slack 4.065 Slack (MET) : 4.069ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].rx_data_ngccm_reg[38][65]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.879ns (logic 0.312ns (8.043%) route 3.567ns (91.957%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.295ns = ( 10.612 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.919ns (routing 0.636ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.869 4.771 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X34Y458 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 4.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/O net (fo=76, routed) 1.698 6.642 rx_data_ngccm[38] SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][65]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.919 10.612 g_gbt_bank[3].gbtbank_n_44 SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][65]/C clock pessimism 0.188 10.800 clock uncertainty -0.035 10.765 SLICE_X29Y477 FDCE (Setup_AFF_SLICEM_C_CE) -0.054 10.711 SFP_GEN[38].rx_data_ngccm_reg[38][65] ------------------------------------------------------------------- required time 10.711 arrival time -6.642 ------------------------------------------------------------------- slack 4.069 Slack (MET) : 4.069ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].rx_data_ngccm_reg[38][68]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.879ns (logic 0.312ns (8.043%) route 3.567ns (91.957%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.295ns = ( 10.612 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.919ns (routing 0.636ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.869 4.771 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X34Y458 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 4.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/O net (fo=76, routed) 1.698 6.642 rx_data_ngccm[38] SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][68]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.919 10.612 g_gbt_bank[3].gbtbank_n_44 SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][68]/C clock pessimism 0.188 10.800 clock uncertainty -0.035 10.765 SLICE_X29Y477 FDCE (Setup_BFF_SLICEM_C_CE) -0.054 10.711 SFP_GEN[38].rx_data_ngccm_reg[38][68] ------------------------------------------------------------------- required time 10.711 arrival time -6.642 ------------------------------------------------------------------- slack 4.069 Slack (MET) : 4.069ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].rx_data_ngccm_reg[38][70]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.879ns (logic 0.312ns (8.043%) route 3.567ns (91.957%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.295ns = ( 10.612 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.919ns (routing 0.636ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.869 4.771 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X34Y458 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 4.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/O net (fo=76, routed) 1.698 6.642 rx_data_ngccm[38] SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][70]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.919 10.612 g_gbt_bank[3].gbtbank_n_44 SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][70]/C clock pessimism 0.188 10.800 clock uncertainty -0.035 10.765 SLICE_X29Y477 FDCE (Setup_CFF_SLICEM_C_CE) -0.054 10.711 SFP_GEN[38].rx_data_ngccm_reg[38][70] ------------------------------------------------------------------- required time 10.711 arrival time -6.642 ------------------------------------------------------------------- slack 4.069 Slack (MET) : 4.069ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].rx_data_ngccm_reg[38][72]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.879ns (logic 0.312ns (8.043%) route 3.567ns (91.957%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.295ns = ( 10.612 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.919ns (routing 0.636ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.869 4.771 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X34Y458 LUT6 (Prop_H6LUT_SLICEM_I0_O) 0.173 4.944 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/SFP_GEN[38].rx_data_ngccm[38][83]_i_1/O net (fo=76, routed) 1.698 6.642 rx_data_ngccm[38] SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][72]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.919 10.612 g_gbt_bank[3].gbtbank_n_44 SLICE_X29Y477 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][72]/C clock pessimism 0.188 10.800 clock uncertainty -0.035 10.765 SLICE_X29Y477 FDCE (Setup_DFF_SLICEM_C_CE) -0.054 10.711 SFP_GEN[38].rx_data_ngccm_reg[38][72] ------------------------------------------------------------------- required time 10.711 arrival time -6.642 ------------------------------------------------------------------- slack 4.069 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].rx_data_ngccm_reg[38][76]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.048ns (26.966%) route 0.130ns (73.034%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.161ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.828ns (routing 0.319ns, distribution 0.509ns) Clock Net Delay (Destination): 1.009ns (routing 0.369ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.944 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X30Y475 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y475 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 0.992 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.130 1.122 rx_data[38][76] SLICE_X32Y475 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][76]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.161 g_gbt_bank[3].gbtbank_n_44 SLICE_X32Y475 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][76]/C clock pessimism -0.130 1.031 SLICE_X32Y475 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.087 SFP_GEN[38].rx_data_ngccm_reg[38][76] ------------------------------------------------------------------- required time -1.087 arrival time 1.122 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].rx_data_ngccm_reg[38][78]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.048ns (26.966%) route 0.130ns (73.034%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.161ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.828ns (routing 0.319ns, distribution 0.509ns) Clock Net Delay (Destination): 1.009ns (routing 0.369ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.944 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X30Y475 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y475 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 0.992 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/Q net (fo=1, routed) 0.130 1.122 rx_data[38][78] SLICE_X32Y475 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][78]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.161 g_gbt_bank[3].gbtbank_n_44 SLICE_X32Y475 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][78]/C clock pessimism -0.130 1.031 SLICE_X32Y475 FDCE (Hold_BFF2_SLICEL_C_D) 0.056 1.087 SFP_GEN[38].rx_data_ngccm_reg[38][78] ------------------------------------------------------------------- required time -1.087 arrival time 1.122 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.040ns (arrival time - required time) Source: SFP_GEN[38].rx_data_ngccm_reg[38][34]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.088ns (50.867%) route 0.085ns (49.133%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.157ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.834ns (routing 0.319ns, distribution 0.515ns) Clock Net Delay (Destination): 1.005ns (routing 0.369ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.834 0.950 g_gbt_bank[3].gbtbank_n_44 SLICE_X33Y462 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][34]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y462 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 0.998 r SFP_GEN[38].rx_data_ngccm_reg[38][34]/Q net (fo=1, routed) 0.073 1.071 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[83]_0[26] SLICE_X34Y462 LUT3 (Prop_H5LUT_SLICEM_I1_O) 0.040 1.111 r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[34]_i_1/O net (fo=1, routed) 0.012 1.123 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[34]_i_1_n_0 SLICE_X34Y462 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.157 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y462 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.130 1.027 SLICE_X34Y462 FDCE (Hold_HFF2_SLICEM_C_D) 0.056 1.083 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.083 arrival time 1.123 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[24]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.049ns (31.613%) route 0.106ns (68.387%)) Logic Levels: 0 Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.837ns (routing 0.319ns, distribution 0.518ns) Clock Net Delay (Destination): 1.017ns (routing 0.369ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.953 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X31Y470 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y470 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.002 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/Q net (fo=1, routed) 0.106 1.108 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[24] SLICE_X31Y471 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X31Y471 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[24]/C clock pessimism -0.159 1.010 SLICE_X31Y471 FDCE (Hold_DFF2_SLICEM_C_D) 0.056 1.066 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[24] ------------------------------------------------------------------- required time -1.066 arrival time 1.108 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].rx_data_ngccm_reg[38][7]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.157ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 0.837ns (routing 0.319ns, distribution 0.518ns) Clock Net Delay (Destination): 1.005ns (routing 0.369ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.953 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X33Y467 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y467 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 1.001 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.094 1.095 rx_data[38][7] SLICE_X33Y468 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][7]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.157 g_gbt_bank[3].gbtbank_n_44 SLICE_X33Y468 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][7]/C clock pessimism -0.161 0.996 SLICE_X33Y468 FDCE (Hold_GFF_SLICEL_C_D) 0.056 1.052 SFP_GEN[38].rx_data_ngccm_reg[38][7] ------------------------------------------------------------------- required time -1.052 arrival time 1.095 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.080ns (47.337%) route 0.089ns (52.663%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.156ns Source Clock Delay (SCD): 0.957ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.841ns (routing 0.319ns, distribution 0.522ns) Clock Net Delay (Destination): 1.004ns (routing 0.369ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.841 0.957 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X34Y466 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y466 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.006 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.073 1.079 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in SLICE_X33Y466 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.031 1.110 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__37/O net (fo=1, routed) 0.016 1.126 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] SLICE_X33Y466 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.004 1.156 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X33Y466 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.130 1.026 SLICE_X33Y466 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.082 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.082 arrival time 1.126 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.167ns Source Clock Delay (SCD): 0.952ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.836ns (routing 0.319ns, distribution 0.517ns) Clock Net Delay (Destination): 1.015ns (routing 0.369ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.836 0.952 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y477 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y477 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.001 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.034 1.035 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_35_in SLICE_X30Y477 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.080 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__37/O net (fo=1, routed) 0.016 1.096 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[16] SLICE_X30Y477 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.167 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y477 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.173 0.994 SLICE_X30Y477 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.050 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.050 arrival time 1.096 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].rx_data_ngccm_reg[38][58]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.048ns (26.229%) route 0.135ns (73.770%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.954ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.838ns (routing 0.319ns, distribution 0.519ns) Clock Net Delay (Destination): 1.014ns (routing 0.369ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.838 0.954 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y477 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y477 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.002 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/Q net (fo=1, routed) 0.135 1.137 rx_data[38][58] SLICE_X32Y476 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][58]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[3].gbtbank_n_44 SLICE_X32Y476 FDCE r SFP_GEN[38].rx_data_ngccm_reg[38][58]/C clock pessimism -0.130 1.036 SLICE_X32Y476 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.091 SFP_GEN[38].rx_data_ngccm_reg[38][58] ------------------------------------------------------------------- required time -1.091 arrival time 1.137 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.167ns (logic 0.080ns (47.904%) route 0.087ns (52.096%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.147ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.837ns (routing 0.319ns, distribution 0.518ns) Clock Net Delay (Destination): 0.995ns (routing 0.369ns, distribution 0.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.953 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X31Y475 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y475 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.002 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.071 1.073 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_27_in SLICE_X30Y475 LUT3 (Prop_H6LUT_SLICEL_I2_O) 0.031 1.104 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__37/O net (fo=1, routed) 0.016 1.120 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[12] SLICE_X30Y475 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.995 1.147 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X30Y475 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.130 1.017 SLICE_X30Y475 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.073 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -1.073 arrival time 1.120 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_40 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.109ns (logic 0.064ns (58.716%) route 0.045ns (41.284%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.948ns Clock Pessimism Removal (CPR): 0.207ns Clock Net Delay (Source): 0.832ns (routing 0.319ns, distribution 0.513ns) Clock Net Delay (Destination): 1.008ns (routing 0.369ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.832 0.948 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/CLK SLICE_X29Y460 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y460 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 0.997 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Q net (fo=2, routed) 0.033 1.030 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/timer[5] SLICE_X29Y460 LUT6 (Prop_A6LUT_SLICEM_I0_O) 0.015 1.045 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__38/O net (fo=1, routed) 0.012 1.057 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__38_n_0 SLICE_X29Y460 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.160 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/CLK SLICE_X29Y460 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C clock pessimism -0.207 0.953 SLICE_X29Y460 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.009 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/clkSlipProcess.timer_reg[5] ------------------------------------------------------------------- required time -1.009 arrival time 1.057 ------------------------------------------------------------------- slack 0.048 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_40 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y173 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y422 g_clock_rate_din[38].ngccm_status_cnt_reg[38][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y422 g_clock_rate_din[38].ngccm_status_cnt_reg[38][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y422 g_clock_rate_din[38].ngccm_status_cnt_reg[38][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y422 g_clock_rate_din[38].ngccm_status_cnt_reg[38][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y422 g_clock_rate_din[38].ngccm_status_cnt_reg[38][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y422 g_clock_rate_din[38].ngccm_status_cnt_reg[38][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y435 g_clock_rate_din[38].ngccm_status_cnt_reg[38][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X33Y458 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X33Y458 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X33Y458 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X33Y457 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X33Y458 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X33Y458 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y426 g_clock_rate_din[38].ngccm_status_cnt_reg[38][7]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X36Y461 g_clock_rate_din[38].rx_frameclk_div2_reg[38]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X33Y455 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X33Y458 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X33Y458 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X33Y458 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y30 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_41 To Clock: gtwiz_userclk_rx_srcclk_out[0]_41 Setup : 0 Failing Endpoints, Worst Slack 3.171ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.171ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][48]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.810ns (logic 0.228ns (4.740%) route 4.582ns (95.260%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.938ns (routing 0.603ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.044 5.926 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.089 6.015 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/O net (fo=76, routed) 1.538 7.553 rx_data_ngccm[39] SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][48]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.631 g_gbt_bank[3].gbtbank_n_54 SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][48]/C clock pessimism 0.186 10.817 clock uncertainty -0.035 10.782 SLICE_X37Y449 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 10.724 SFP_GEN[39].rx_data_ngccm_reg[39][48] ------------------------------------------------------------------- required time 10.724 arrival time -7.553 ------------------------------------------------------------------- slack 3.171 Slack (MET) : 3.171ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][51]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.810ns (logic 0.228ns (4.740%) route 4.582ns (95.260%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.938ns (routing 0.603ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.044 5.926 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.089 6.015 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/O net (fo=76, routed) 1.538 7.553 rx_data_ngccm[39] SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][51]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.631 g_gbt_bank[3].gbtbank_n_54 SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][51]/C clock pessimism 0.186 10.817 clock uncertainty -0.035 10.782 SLICE_X37Y449 FDCE (Setup_FFF2_SLICEM_C_CE) -0.058 10.724 SFP_GEN[39].rx_data_ngccm_reg[39][51] ------------------------------------------------------------------- required time 10.724 arrival time -7.553 ------------------------------------------------------------------- slack 3.171 Slack (MET) : 3.171ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][53]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.810ns (logic 0.228ns (4.740%) route 4.582ns (95.260%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.938ns (routing 0.603ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.044 5.926 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.089 6.015 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/O net (fo=76, routed) 1.538 7.553 rx_data_ngccm[39] SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][53]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.631 g_gbt_bank[3].gbtbank_n_54 SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][53]/C clock pessimism 0.186 10.817 clock uncertainty -0.035 10.782 SLICE_X37Y449 FDCE (Setup_GFF2_SLICEM_C_CE) -0.058 10.724 SFP_GEN[39].rx_data_ngccm_reg[39][53] ------------------------------------------------------------------- required time 10.724 arrival time -7.553 ------------------------------------------------------------------- slack 3.171 Slack (MET) : 3.171ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][69]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.810ns (logic 0.228ns (4.740%) route 4.582ns (95.260%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.938ns (routing 0.603ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.044 5.926 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.089 6.015 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/O net (fo=76, routed) 1.538 7.553 rx_data_ngccm[39] SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][69]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.631 g_gbt_bank[3].gbtbank_n_54 SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][69]/C clock pessimism 0.186 10.817 clock uncertainty -0.035 10.782 SLICE_X37Y449 FDCE (Setup_HFF2_SLICEM_C_CE) -0.058 10.724 SFP_GEN[39].rx_data_ngccm_reg[39][69] ------------------------------------------------------------------- required time 10.724 arrival time -7.553 ------------------------------------------------------------------- slack 3.171 Slack (MET) : 3.177ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][47]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.807ns (logic 0.228ns (4.743%) route 4.579ns (95.257%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.938ns (routing 0.603ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.044 5.926 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.089 6.015 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/O net (fo=76, routed) 1.535 7.550 rx_data_ngccm[39] SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][47]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.631 g_gbt_bank[3].gbtbank_n_54 SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][47]/C clock pessimism 0.186 10.817 clock uncertainty -0.035 10.782 SLICE_X37Y449 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 10.727 SFP_GEN[39].rx_data_ngccm_reg[39][47] ------------------------------------------------------------------- required time 10.727 arrival time -7.550 ------------------------------------------------------------------- slack 3.177 Slack (MET) : 3.177ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][50]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.807ns (logic 0.228ns (4.743%) route 4.579ns (95.257%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.938ns (routing 0.603ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.044 5.926 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.089 6.015 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/O net (fo=76, routed) 1.535 7.550 rx_data_ngccm[39] SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][50]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.631 g_gbt_bank[3].gbtbank_n_54 SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][50]/C clock pessimism 0.186 10.817 clock uncertainty -0.035 10.782 SLICE_X37Y449 FDCE (Setup_FFF_SLICEM_C_CE) -0.055 10.727 SFP_GEN[39].rx_data_ngccm_reg[39][50] ------------------------------------------------------------------- required time 10.727 arrival time -7.550 ------------------------------------------------------------------- slack 3.177 Slack (MET) : 3.177ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][52]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.807ns (logic 0.228ns (4.743%) route 4.579ns (95.257%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.938ns (routing 0.603ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.044 5.926 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.089 6.015 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/O net (fo=76, routed) 1.535 7.550 rx_data_ngccm[39] SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][52]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.631 g_gbt_bank[3].gbtbank_n_54 SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][52]/C clock pessimism 0.186 10.817 clock uncertainty -0.035 10.782 SLICE_X37Y449 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 10.727 SFP_GEN[39].rx_data_ngccm_reg[39][52] ------------------------------------------------------------------- required time 10.727 arrival time -7.550 ------------------------------------------------------------------- slack 3.177 Slack (MET) : 3.177ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][63]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.807ns (logic 0.228ns (4.743%) route 4.579ns (95.257%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.243ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.938ns (routing 0.603ns, distribution 1.335ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.044 5.926 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.089 6.015 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/O net (fo=76, routed) 1.535 7.550 rx_data_ngccm[39] SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][63]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.631 g_gbt_bank[3].gbtbank_n_54 SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][63]/C clock pessimism 0.186 10.817 clock uncertainty -0.035 10.782 SLICE_X37Y449 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 10.727 SFP_GEN[39].rx_data_ngccm_reg[39][63] ------------------------------------------------------------------- required time 10.727 arrival time -7.550 ------------------------------------------------------------------- slack 3.177 Slack (MET) : 3.277ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][54]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.691ns (logic 0.228ns (4.860%) route 4.463ns (95.140%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.256ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.301ns = ( 10.618 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.925ns (routing 0.603ns, distribution 1.322ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.044 5.926 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.089 6.015 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/O net (fo=76, routed) 1.419 7.434 rx_data_ngccm[39] SLICE_X37Y450 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][54]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.925 10.618 g_gbt_bank[3].gbtbank_n_54 SLICE_X37Y450 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][54]/C clock pessimism 0.186 10.805 clock uncertainty -0.035 10.769 SLICE_X37Y450 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 10.711 SFP_GEN[39].rx_data_ngccm_reg[39][54] ------------------------------------------------------------------- required time 10.711 arrival time -7.434 ------------------------------------------------------------------- slack 3.277 Slack (MET) : 3.277ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][65]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.691ns (logic 0.228ns (4.860%) route 4.463ns (95.140%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.256ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.301ns = ( 10.618 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.925ns (routing 0.603ns, distribution 1.322ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.044 5.926 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X45Y439 LUT6 (Prop_G6LUT_SLICEL_I0_O) 0.089 6.015 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/SFP_GEN[39].rx_data_ngccm[39][83]_i_1/O net (fo=76, routed) 1.419 7.434 rx_data_ngccm[39] SLICE_X37Y450 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][65]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.925 10.618 g_gbt_bank[3].gbtbank_n_54 SLICE_X37Y450 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][65]/C clock pessimism 0.186 10.805 clock uncertainty -0.035 10.769 SLICE_X37Y450 FDCE (Setup_FFF2_SLICEM_C_CE) -0.058 10.711 SFP_GEN[39].rx_data_ngccm_reg[39][65] ------------------------------------------------------------------- required time 10.711 arrival time -7.434 ------------------------------------------------------------------- slack 3.277 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.034ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[29]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.151ns (logic 0.049ns (32.450%) route 0.102ns (67.550%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.182ns Source Clock Delay (SCD): 0.960ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.844ns (routing 0.301ns, distribution 0.543ns) Clock Net Delay (Destination): 1.030ns (routing 0.348ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.844 0.960 SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y442 FDCE r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[29]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y442 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.009 r SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[29]/Q net (fo=2, routed) 0.102 1.111 SFP_GEN[39].ngCCM_gbt/gbt_rx_checker/Q[13] SLICE_X43Y440 FDRE r SFP_GEN[39].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.030 1.182 SFP_GEN[39].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y440 FDRE r SFP_GEN[39].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/C clock pessimism -0.160 1.022 SLICE_X43Y440 FDRE (Hold_FFF2_SLICEL_C_D) 0.055 1.077 SFP_GEN[39].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13] ------------------------------------------------------------------- required time -1.077 arrival time 1.111 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][52]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.049ns (26.486%) route 0.136ns (73.514%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.172ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.837ns (routing 0.301ns, distribution 0.536ns) Clock Net Delay (Destination): 1.020ns (routing 0.348ns, distribution 0.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.837 0.953 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X36Y449 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y449 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.002 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.136 1.138 rx_data[39][52] SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][52]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.172 g_gbt_bank[3].gbtbank_n_54 SLICE_X37Y449 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][52]/C clock pessimism -0.125 1.047 SLICE_X37Y449 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.103 SFP_GEN[39].rx_data_ngccm_reg[39][52] ------------------------------------------------------------------- required time -1.103 arrival time 1.138 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.164ns (logic 0.048ns (29.268%) route 0.116ns (70.732%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.170ns Source Clock Delay (SCD): 0.973ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.857ns (routing 0.301ns, distribution 0.556ns) Clock Net Delay (Destination): 1.018ns (routing 0.348ns, distribution 0.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.857 0.973 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X38Y442 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y442 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.021 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.116 1.137 rx_data[39][39] SLICE_X39Y442 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.170 g_gbt_bank[3].gbtbank_n_54 SLICE_X39Y442 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][39]/C clock pessimism -0.125 1.045 SLICE_X39Y442 FDCE (Hold_HFF2_SLICEM_C_D) 0.056 1.101 SFP_GEN[39].rx_data_ngccm_reg[39][39] ------------------------------------------------------------------- required time -1.101 arrival time 1.137 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.187ns (logic 0.103ns (55.080%) route 0.084ns (44.920%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.175ns Source Clock Delay (SCD): 0.959ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.843ns (routing 0.301ns, distribution 0.542ns) Clock Net Delay (Destination): 1.023ns (routing 0.348ns, distribution 0.675ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.843 0.959 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X39Y449 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y449 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.007 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.073 1.080 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_7_in SLICE_X38Y449 LUT3 (Prop_C5LUT_SLICEL_I2_O) 0.055 1.135 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__38/O net (fo=1, routed) 0.011 1.146 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] SLICE_X38Y449 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.175 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X38Y449 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.125 1.050 SLICE_X38Y449 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.106 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -1.106 arrival time 1.146 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.093ns (65.035%) route 0.050ns (34.965%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.178ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.848ns (routing 0.301ns, distribution 0.547ns) Clock Net Delay (Destination): 1.026ns (routing 0.348ns, distribution 0.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X38Y447 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y447 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.034 1.046 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in SLICE_X38Y447 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.091 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__38/O net (fo=1, routed) 0.016 1.107 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] SLICE_X38Y447 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.178 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X38Y447 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.170 1.008 SLICE_X38Y447 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.064 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.064 arrival time 1.107 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.101ns (66.447%) route 0.051ns (33.553%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.183ns Source Clock Delay (SCD): 0.971ns Clock Pessimism Removal (CPR): 0.162ns Clock Net Delay (Source): 0.855ns (routing 0.301ns, distribution 0.554ns) Clock Net Delay (Destination): 1.031ns (routing 0.348ns, distribution 0.683ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.855 0.971 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X37Y444 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y444 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.020 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Q net (fo=2, routed) 0.035 1.055 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_9_in SLICE_X37Y443 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.052 1.107 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__38/O net (fo=1, routed) 0.016 1.123 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[5] SLICE_X37Y443 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.031 1.183 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X37Y443 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.162 1.021 SLICE_X37Y443 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.077 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.077 arrival time 1.123 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.145ns (logic 0.094ns (64.828%) route 0.051ns (35.172%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.184ns Source Clock Delay (SCD): 0.974ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 0.858ns (routing 0.301ns, distribution 0.557ns) Clock Net Delay (Destination): 1.032ns (routing 0.348ns, distribution 0.684ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.858 0.974 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X42Y440 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y440 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.023 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.035 1.058 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in SLICE_X42Y440 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.045 1.103 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__38/O net (fo=1, routed) 0.016 1.119 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] SLICE_X42Y440 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.032 1.184 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X42Y440 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.169 1.015 SLICE_X42Y440 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.071 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -1.071 arrival time 1.119 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.103ns (69.595%) route 0.045ns (30.405%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.178ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.848ns (routing 0.301ns, distribution 0.547ns) Clock Net Delay (Destination): 1.026ns (routing 0.348ns, distribution 0.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X38Y447 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y447 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.012 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.034 1.046 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in SLICE_X38Y447 LUT3 (Prop_C5LUT_SLICEL_I0_O) 0.055 1.101 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__38/O net (fo=1, routed) 0.011 1.112 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[3] SLICE_X38Y447 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.026 1.178 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X38Y447 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C clock pessimism -0.170 1.008 SLICE_X38Y447 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.064 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3] ------------------------------------------------------------------- required time -1.064 arrival time 1.112 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[39].rx_data_ngccm_reg[39][70]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.048ns (25.263%) route 0.142ns (74.737%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.171ns Source Clock Delay (SCD): 0.960ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.844ns (routing 0.301ns, distribution 0.543ns) Clock Net Delay (Destination): 1.019ns (routing 0.348ns, distribution 0.671ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.844 0.960 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X39Y449 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y449 FDRE (Prop_CFF2_SLICEM_C_Q) 0.048 1.008 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/Q net (fo=1, routed) 0.142 1.150 rx_data[39][70] SLICE_X39Y451 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][70]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.171 g_gbt_bank[3].gbtbank_n_54 SLICE_X39Y451 FDCE r SFP_GEN[39].rx_data_ngccm_reg[39][70]/C clock pessimism -0.125 1.046 SLICE_X39Y451 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.102 SFP_GEN[39].rx_data_ngccm_reg[39][70] ------------------------------------------------------------------- required time -1.102 arrival time 1.150 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_41 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.147ns (logic 0.094ns (63.946%) route 0.053ns (36.054%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.172ns Source Clock Delay (SCD): 0.960ns Clock Pessimism Removal (CPR): 0.170ns Clock Net Delay (Source): 0.844ns (routing 0.301ns, distribution 0.543ns) Clock Net Delay (Destination): 1.020ns (routing 0.348ns, distribution 0.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.844 0.960 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X40Y447 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y447 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.009 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.037 1.046 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/O85[1] SLICE_X40Y447 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.091 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__38/O net (fo=1, routed) 0.016 1.107 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[1] SLICE_X40Y447 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.172 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X40Y447 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.170 1.002 SLICE_X40Y447 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.058 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.058 arrival time 1.107 ------------------------------------------------------------------- slack 0.049 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_41 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y171 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y422 g_clock_rate_din[39].ngccm_status_cnt_reg[39][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y422 g_clock_rate_din[39].ngccm_status_cnt_reg[39][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y422 g_clock_rate_din[39].ngccm_status_cnt_reg[39][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y422 g_clock_rate_din[39].ngccm_status_cnt_reg[39][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y422 g_clock_rate_din[39].ngccm_status_cnt_reg[39][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y422 g_clock_rate_din[39].ngccm_status_cnt_reg[39][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X51Y423 g_clock_rate_din[39].ngccm_status_cnt_reg[39][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y422 g_clock_rate_din[39].ngccm_status_cnt_reg[39][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y422 g_clock_rate_din[39].ngccm_status_cnt_reg[39][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y422 g_clock_rate_din[39].ngccm_status_cnt_reg[39][2]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y422 g_clock_rate_din[39].ngccm_status_cnt_reg[39][3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y422 g_clock_rate_din[39].ngccm_status_cnt_reg[39][4]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y422 g_clock_rate_din[39].ngccm_status_cnt_reg[39][5]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y423 g_clock_rate_din[39].ngccm_status_cnt_reg[39][6]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y423 g_clock_rate_din[39].rx_test_comm_cnt_reg[39]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X44Y440 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X44Y440 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X44Y441 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X44Y441 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y31 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_42 To Clock: gtwiz_userclk_rx_srcclk_out[0]_42 Setup : 0 Failing Endpoints, Worst Slack 3.630ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.038ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.630ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.759ns (logic 1.630ns (34.251%) route 3.129ns (65.749%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.600ns = ( 10.917 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.692ns, distribution 1.514ns) Clock Net Delay (Destination): 2.224ns (routing 0.629ns, distribution 1.595ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.447 6.164 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y490 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.389 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.186 6.575 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y488 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.146 6.721 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39/O net (fo=1, routed) 0.084 6.805 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39_n_0 SLICE_X52Y488 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 6.978 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39/O net (fo=2, routed) 0.412 7.390 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39_n_0 SLICE_X52Y490 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.224 10.917 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X52Y490 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.193 11.110 clock uncertainty -0.035 11.075 SLICE_X52Y490 FDCE (Setup_GFF_SLICEM_C_CE) -0.055 11.020 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.020 arrival time -7.390 ------------------------------------------------------------------- slack 3.630 Slack (MET) : 3.630ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.759ns (logic 1.630ns (34.251%) route 3.129ns (65.749%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.600ns = ( 10.917 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.692ns, distribution 1.514ns) Clock Net Delay (Destination): 2.224ns (routing 0.629ns, distribution 1.595ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.447 6.164 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y490 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.389 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.186 6.575 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y488 LUT4 (Prop_C6LUT_SLICEM_I2_O) 0.146 6.721 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39/O net (fo=1, routed) 0.084 6.805 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39_n_0 SLICE_X52Y488 LUT6 (Prop_H6LUT_SLICEM_I5_O) 0.173 6.978 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39/O net (fo=2, routed) 0.412 7.390 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39_n_0 SLICE_X52Y490 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.224 10.917 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X52Y490 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.193 11.110 clock uncertainty -0.035 11.075 SLICE_X52Y490 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.020 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.020 arrival time -7.390 ------------------------------------------------------------------- slack 3.630 Slack (MET) : 3.666ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.711ns (logic 1.461ns (31.013%) route 3.250ns (68.987%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.588ns = ( 10.905 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.692ns, distribution 1.514ns) Clock Net Delay (Destination): 2.212ns (routing 0.629ns, distribution 1.583ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.447 6.164 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y490 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.389 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.209 6.598 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y488 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/O net (fo=7, routed) 0.594 7.342 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X50Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.905 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X50Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.193 11.098 clock uncertainty -0.035 11.063 SLICE_X50Y489 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 11.008 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.008 arrival time -7.342 ------------------------------------------------------------------- slack 3.666 Slack (MET) : 3.666ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.711ns (logic 1.461ns (31.013%) route 3.250ns (68.987%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.588ns = ( 10.905 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.692ns, distribution 1.514ns) Clock Net Delay (Destination): 2.212ns (routing 0.629ns, distribution 1.583ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.447 6.164 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y490 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.389 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.209 6.598 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y488 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/O net (fo=7, routed) 0.594 7.342 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X50Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.905 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X50Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.193 11.098 clock uncertainty -0.035 11.063 SLICE_X50Y489 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 11.008 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.008 arrival time -7.342 ------------------------------------------------------------------- slack 3.666 Slack (MET) : 3.671ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.707ns (logic 1.461ns (31.039%) route 3.246ns (68.961%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.588ns = ( 10.905 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.692ns, distribution 1.514ns) Clock Net Delay (Destination): 2.212ns (routing 0.629ns, distribution 1.583ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.447 6.164 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y490 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.389 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.209 6.598 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y488 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/O net (fo=7, routed) 0.590 7.338 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X50Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.905 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X50Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.193 11.098 clock uncertainty -0.035 11.063 SLICE_X50Y489 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 11.009 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.009 arrival time -7.338 ------------------------------------------------------------------- slack 3.671 Slack (MET) : 3.671ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.707ns (logic 1.461ns (31.039%) route 3.246ns (68.961%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.588ns = ( 10.905 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.692ns, distribution 1.514ns) Clock Net Delay (Destination): 2.212ns (routing 0.629ns, distribution 1.583ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.447 6.164 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y490 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.389 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.209 6.598 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y488 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/O net (fo=7, routed) 0.590 7.338 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X50Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.905 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X50Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.193 11.098 clock uncertainty -0.035 11.063 SLICE_X50Y489 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 11.009 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.009 arrival time -7.338 ------------------------------------------------------------------- slack 3.671 Slack (MET) : 3.671ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.707ns (logic 1.461ns (31.039%) route 3.246ns (68.961%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.588ns = ( 10.905 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.692ns, distribution 1.514ns) Clock Net Delay (Destination): 2.212ns (routing 0.629ns, distribution 1.583ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.447 6.164 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y490 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.389 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.209 6.598 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y488 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.150 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/O net (fo=7, routed) 0.590 7.338 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 SLICE_X50Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.905 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X50Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.193 11.098 clock uncertainty -0.035 11.063 SLICE_X50Y489 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 11.009 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.009 arrival time -7.338 ------------------------------------------------------------------- slack 3.671 Slack (MET) : 3.723ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[19]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.791ns (logic 0.879ns (18.347%) route 3.912ns (81.653%)) Logic Levels: 0 Clock Path Skew: 0.169ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.607ns = ( 10.924 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.692ns, distribution 1.514ns) Clock Net Delay (Destination): 2.231ns (routing 0.629ns, distribution 1.602ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXCTRL1[1]) 0.879 3.510 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXCTRL1[1] net (fo=6, routed) 3.912 7.422 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[19] SLICE_X57Y489 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.924 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X57Y489 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[19]/C clock pessimism 0.193 11.117 clock uncertainty -0.035 11.082 SLICE_X57Y489 FDCE (Setup_HFF_SLICEL_C_D) 0.063 11.145 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[19] ------------------------------------------------------------------- required time 11.145 arrival time -7.422 ------------------------------------------------------------------- slack 3.723 Slack (MET) : 3.804ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[117]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.742ns (logic 1.123ns (23.682%) route 3.619ns (76.318%)) Logic Levels: 0 Clock Path Skew: 0.197ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.952 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.692ns, distribution 1.514ns) Clock Net Delay (Destination): 2.259ns (routing 0.629ns, distribution 1.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[15]) 1.123 3.754 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[15] net (fo=6, routed) 3.619 7.373 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/D[17] SLICE_X55Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[117]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.259 10.952 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X55Y486 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[117]/C clock pessimism 0.193 11.145 clock uncertainty -0.035 11.110 SLICE_X55Y486 FDCE (Setup_DFF2_SLICEM_C_D) 0.067 11.177 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[117] ------------------------------------------------------------------- required time 11.177 arrival time -7.373 ------------------------------------------------------------------- slack 3.804 Slack (MET) : 3.824ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 4.565ns (logic 1.555ns (34.064%) route 3.010ns (65.936%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.600ns = ( 10.917 - 8.317 ) Source Clock Delay (SCD): 2.631ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.206ns (routing 0.692ns, distribution 1.514ns) Clock Net Delay (Destination): 2.224ns (routing 0.629ns, distribution 1.595ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.206 2.631 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.717 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.447 6.164 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X52Y490 LUT4 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.389 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/O net (fo=5, routed) 0.186 6.575 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X52Y489 LUT6 (Prop_E6LUT_SLICEM_I0_O) 0.244 6.819 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__40/O net (fo=5, routed) 0.377 7.196 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 SLICE_X51Y488 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.224 10.917 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X51Y488 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C clock pessimism 0.193 11.110 clock uncertainty -0.035 11.075 SLICE_X51Y488 FDRE (Setup_AFF2_SLICEL_C_CE) -0.055 11.020 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3] ------------------------------------------------------------------- required time 11.020 arrival time -7.196 ------------------------------------------------------------------- slack 3.824 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.094ns (51.087%) route 0.090ns (48.913%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.341ns Source Clock Delay (SCD): 1.105ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.189ns (routing 0.366ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.105 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X56Y487 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y487 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.154 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Q net (fo=2, routed) 0.074 1.228 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_19_in SLICE_X54Y487 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.273 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__39/O net (fo=1, routed) 0.016 1.289 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[10] SLICE_X54Y487 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.341 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X54Y487 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.146 1.195 SLICE_X54Y487 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.251 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.251 arrival time 1.289 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.150ns (logic 0.063ns (42.000%) route 0.087ns (58.000%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.341ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 0.991ns (routing 0.317ns, distribution 0.674ns) Clock Net Delay (Destination): 1.189ns (routing 0.366ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.107 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X54Y488 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y488 FDCE (Prop_FFF2_SLICEL_C_Q) 0.048 1.155 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.072 1.227 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/O84[0] SLICE_X54Y487 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.015 1.242 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__39/O net (fo=1, routed) 0.015 1.257 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] SLICE_X54Y487 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.341 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X54Y487 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.179 1.162 SLICE_X54Y487 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.218 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.218 arrival time 1.257 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].rx_data_ngccm_reg[40][60]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.048ns (31.373%) route 0.105ns (68.627%)) Logic Levels: 0 Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.341ns Source Clock Delay (SCD): 1.105ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.189ns (routing 0.366ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.105 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X54Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y489 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.153 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.105 1.258 rx_data[40][60] SLICE_X54Y488 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][60]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.341 g_gbt_bank[3].gbtbank_n_64 SLICE_X54Y488 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][60]/C clock pessimism -0.179 1.162 SLICE_X54Y488 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.218 SFP_GEN[40].rx_data_ngccm_reg[40][60] ------------------------------------------------------------------- required time -1.218 arrival time 1.258 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: SFP_GEN[40].rx_data_ngccm_reg[40][28]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[28]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.158ns (logic 0.048ns (30.380%) route 0.110ns (69.620%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 1.113ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 0.997ns (routing 0.317ns, distribution 0.680ns) Clock Net Delay (Destination): 1.202ns (routing 0.366ns, distribution 0.836ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.113 g_gbt_bank[3].gbtbank_n_64 SLICE_X62Y484 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][28]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y484 FDCE (Prop_GFF_SLICEM_C_Q) 0.048 1.161 r SFP_GEN[40].rx_data_ngccm_reg[40][28]/Q net (fo=1, routed) 0.110 1.271 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[83]_0[20] SLICE_X62Y483 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[28]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.202 1.354 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y483 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.179 1.175 SLICE_X62Y483 FDCE (Hold_AFF2_SLICEM_C_D) 0.056 1.231 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.231 arrival time 1.271 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].rx_data_ngccm_reg[40][56]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.049ns (31.613%) route 0.106ns (68.387%)) Logic Levels: 0 Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.341ns Source Clock Delay (SCD): 1.105ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.189ns (routing 0.366ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.105 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X54Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y489 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.154 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/Q net (fo=1, routed) 0.106 1.260 rx_data[40][56] SLICE_X54Y488 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][56]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.341 g_gbt_bank[3].gbtbank_n_64 SLICE_X54Y488 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][56]/C clock pessimism -0.179 1.162 SLICE_X54Y488 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.218 SFP_GEN[40].rx_data_ngccm_reg[40][56] ------------------------------------------------------------------- required time -1.218 arrival time 1.260 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.104ns (55.026%) route 0.085ns (44.974%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.341ns Source Clock Delay (SCD): 1.105ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.189ns (routing 0.366ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.105 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X56Y487 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y487 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.154 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Q net (fo=2, routed) 0.074 1.228 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_19_in SLICE_X54Y487 LUT3 (Prop_C5LUT_SLICEL_I2_O) 0.055 1.283 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[8]_i_1__39/O net (fo=1, routed) 0.011 1.294 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[8] SLICE_X54Y487 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.341 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X54Y487 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C clock pessimism -0.146 1.195 SLICE_X54Y487 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.251 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8] ------------------------------------------------------------------- required time -1.251 arrival time 1.294 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].rx_data_ngccm_reg[40][47]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.157ns (logic 0.048ns (30.573%) route 0.109ns (69.427%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.338ns Source Clock Delay (SCD): 1.103ns Clock Pessimism Removal (CPR): 0.179ns Clock Net Delay (Source): 0.987ns (routing 0.317ns, distribution 0.670ns) Clock Net Delay (Destination): 1.186ns (routing 0.366ns, distribution 0.820ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.987 1.103 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X54Y489 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y489 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.151 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.109 1.260 rx_data[40][47] SLICE_X54Y487 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][47]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.186 1.338 g_gbt_bank[3].gbtbank_n_64 SLICE_X54Y487 FDCE r SFP_GEN[40].rx_data_ngccm_reg[40][47]/C clock pessimism -0.179 1.159 SLICE_X54Y487 FDCE (Hold_EFF_SLICEL_C_D) 0.056 1.215 SFP_GEN[40].rx_data_ngccm_reg[40][47] ------------------------------------------------------------------- required time -1.215 arrival time 1.260 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.338ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 0.991ns (routing 0.317ns, distribution 0.674ns) Clock Net Delay (Destination): 1.186ns (routing 0.366ns, distribution 0.820ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.107 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y484 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y484 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.156 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.034 1.190 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_21_in SLICE_X60Y484 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.235 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__39/O net (fo=1, routed) 0.016 1.251 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] SLICE_X60Y484 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.186 1.338 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y484 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.189 1.149 SLICE_X60Y484 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.205 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.205 arrival time 1.251 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr_reg_inv/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.153ns (logic 0.064ns (41.830%) route 0.089ns (58.170%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.340ns Source Clock Delay (SCD): 1.111ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.995ns (routing 0.317ns, distribution 0.678ns) Clock Net Delay (Destination): 1.188ns (routing 0.366ns, distribution 0.822ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.995 1.111 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X53Y487 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y487 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.160 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/Q net (fo=6, routed) 0.073 1.233 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/bitSlipCnt[0] SLICE_X53Y488 LUT6 (Prop_C6LUT_SLICEM_I3_O) 0.015 1.248 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr_inv_i_1__40/O net (fo=1, routed) 0.016 1.264 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr3_out SLICE_X53Y488 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr_reg_inv/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.340 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK SLICE_X53Y488 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr_reg_inv/C clock pessimism -0.178 1.162 SLICE_X53Y488 FDPE (Hold_CFF_SLICEM_C_D) 0.056 1.218 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/shiftPsAddr_reg_inv ------------------------------------------------------------------- required time -1.217 arrival time 1.264 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/pwr_good_pre_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_42 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.064ns (43.836%) route 0.082ns (56.164%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.341ns Source Clock Delay (SCD): 1.109ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 0.993ns (routing 0.317ns, distribution 0.676ns) Clock Net Delay (Destination): 1.189ns (routing 0.366ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.109 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y482 FDCE r SFP_GEN[40].ngCCM_gbt/pwr_good_pre_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y482 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.158 r SFP_GEN[40].ngCCM_gbt/pwr_good_pre_reg/Q net (fo=1, routed) 0.066 1.224 SFP_GEN[40].ngCCM_gbt/pwr_good_pre SLICE_X53Y482 LUT4 (Prop_C6LUT_SLICEM_I1_O) 0.015 1.239 r SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_i_1__15/O net (fo=1, routed) 0.016 1.255 SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_i_1__15_n_0 SLICE_X53Y482 FDRE r SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.341 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y482 FDRE r SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg/C clock pessimism -0.189 1.152 SLICE_X53Y482 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.208 SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg ------------------------------------------------------------------- required time -1.208 arrival time 1.255 ------------------------------------------------------------------- slack 0.047 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_42 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y196 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y482 SFP_GEN[40].ngCCM_gbt/RX_Clock_20MHz_dl_reg[0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y482 SFP_GEN[40].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X53Y482 SFP_GEN[40].ngCCM_gbt/RX_Clock_40MHz_reg/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X55Y484 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[0]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X62Y485 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[16]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X62Y484 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[17]/C Min Period n/a FDCE/C n/a 0.550 8.317 7.767 SLICE_X62Y484 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[18]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X53Y492 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X53Y492 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X53Y492 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X54Y491 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y491 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y491 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X53Y482 SFP_GEN[40].ngCCM_gbt/RX_Clock_40MHz_reg/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X57Y482 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[32]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X57Y482 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[34]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X57Y482 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[36]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X57Y482 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[38]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X53Y486 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[44]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y32 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_43 To Clock: gtwiz_userclk_rx_srcclk_out[0]_43 Setup : 0 Failing Endpoints, Worst Slack 2.559ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.031ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.559ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.872ns (logic 1.795ns (30.569%) route 4.077ns (69.431%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.203ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.593ns = ( 10.910 - 8.317 ) Source Clock Delay (SCD): 2.585ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.667ns, distribution 1.493ns) Clock Net Delay (Destination): 2.217ns (routing 0.603ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.585 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.746 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.307 7.053 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X53Y497 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.226 7.523 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y495 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.767 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__40/O net (fo=1, routed) 0.075 7.842 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__40_n_0 SLICE_X53Y495 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__40/O net (fo=2, routed) 0.469 8.457 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__40_n_0 SLICE_X54Y497 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.217 10.910 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y497 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.195 11.105 clock uncertainty -0.035 11.070 SLICE_X54Y497 FDCE (Setup_BFF_SLICEL_C_CE) -0.054 11.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.016 arrival time -8.457 ------------------------------------------------------------------- slack 2.559 Slack (MET) : 2.559ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.872ns (logic 1.795ns (30.569%) route 4.077ns (69.431%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.203ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.593ns = ( 10.910 - 8.317 ) Source Clock Delay (SCD): 2.585ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.667ns, distribution 1.493ns) Clock Net Delay (Destination): 2.217ns (routing 0.603ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.585 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.746 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.307 7.053 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X53Y497 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.226 7.523 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y495 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.767 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__40/O net (fo=1, routed) 0.075 7.842 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__40_n_0 SLICE_X53Y495 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.146 7.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__40/O net (fo=2, routed) 0.469 8.457 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__40_n_0 SLICE_X54Y497 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.217 10.910 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y497 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.195 11.105 clock uncertainty -0.035 11.070 SLICE_X54Y497 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 11.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.016 arrival time -8.457 ------------------------------------------------------------------- slack 2.559 Slack (MET) : 2.866ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.569ns (logic 1.650ns (29.628%) route 3.919ns (70.372%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.208ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.598ns = ( 10.915 - 8.317 ) Source Clock Delay (SCD): 2.585ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.667ns, distribution 1.493ns) Clock Net Delay (Destination): 2.222ns (routing 0.603ns, distribution 1.619ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.585 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.746 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.307 7.053 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X53Y497 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.212 7.509 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y495 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.245 7.754 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__41/O net (fo=3, routed) 0.400 8.154 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X53Y494 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.222 10.915 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y494 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C clock pessimism 0.195 11.110 clock uncertainty -0.035 11.075 SLICE_X53Y494 FDRE (Setup_EFF_SLICEM_C_CE) -0.055 11.020 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2] ------------------------------------------------------------------- required time 11.020 arrival time -8.154 ------------------------------------------------------------------- slack 2.866 Slack (MET) : 2.897ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.544ns (logic 1.456ns (26.263%) route 4.088ns (73.737%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.604ns = ( 10.921 - 8.317 ) Source Clock Delay (SCD): 2.585ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.667ns, distribution 1.493ns) Clock Net Delay (Destination): 2.228ns (routing 0.603ns, distribution 1.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.585 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.746 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.307 7.053 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X53Y497 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.194 7.491 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y495 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.051 7.542 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/O net (fo=7, routed) 0.587 8.129 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X53Y499 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.228 10.921 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y499 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.195 11.116 clock uncertainty -0.035 11.081 SLICE_X53Y499 FDRE (Setup_CFF2_SLICEM_C_CE) -0.055 11.026 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 11.026 arrival time -8.129 ------------------------------------------------------------------- slack 2.897 Slack (MET) : 2.901ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.541ns (logic 1.456ns (26.277%) route 4.085ns (73.723%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.604ns = ( 10.921 - 8.317 ) Source Clock Delay (SCD): 2.585ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.667ns, distribution 1.493ns) Clock Net Delay (Destination): 2.228ns (routing 0.603ns, distribution 1.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.585 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.746 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.307 7.053 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X53Y497 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.194 7.491 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y495 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.051 7.542 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/O net (fo=7, routed) 0.584 8.126 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X53Y499 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.228 10.921 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y499 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.195 11.116 clock uncertainty -0.035 11.081 SLICE_X53Y499 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.027 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 11.027 arrival time -8.126 ------------------------------------------------------------------- slack 2.901 Slack (MET) : 2.920ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.516ns (logic 1.650ns (29.913%) route 3.866ns (70.087%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.209ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.599ns = ( 10.916 - 8.317 ) Source Clock Delay (SCD): 2.585ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.667ns, distribution 1.493ns) Clock Net Delay (Destination): 2.223ns (routing 0.603ns, distribution 1.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.585 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.746 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.307 7.053 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X53Y497 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.212 7.509 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y495 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.245 7.754 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__41/O net (fo=3, routed) 0.347 8.101 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X53Y494 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.223 10.916 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y494 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C clock pessimism 0.195 11.111 clock uncertainty -0.035 11.076 SLICE_X53Y494 FDRE (Setup_AFF2_SLICEM_C_CE) -0.055 11.021 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1] ------------------------------------------------------------------- required time 11.021 arrival time -8.101 ------------------------------------------------------------------- slack 2.920 Slack (MET) : 2.924ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.513ns (logic 1.650ns (29.929%) route 3.863ns (70.071%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: 0.209ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.599ns = ( 10.916 - 8.317 ) Source Clock Delay (SCD): 2.585ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.667ns, distribution 1.493ns) Clock Net Delay (Destination): 2.223ns (routing 0.603ns, distribution 1.620ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.585 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.746 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.307 7.053 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X53Y497 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.212 7.509 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y495 LUT6 (Prop_F6LUT_SLICEM_I5_O) 0.245 7.754 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__41/O net (fo=3, routed) 0.344 8.098 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 SLICE_X53Y494 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.223 10.916 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y494 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C clock pessimism 0.195 11.111 clock uncertainty -0.035 11.076 SLICE_X53Y494 FDRE (Setup_AFF_SLICEM_C_CE) -0.054 11.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0] ------------------------------------------------------------------- required time 11.022 arrival time -8.098 ------------------------------------------------------------------- slack 2.924 Slack (MET) : 3.029ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.404ns (logic 1.456ns (26.943%) route 3.948ns (73.057%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.206ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.596ns = ( 10.913 - 8.317 ) Source Clock Delay (SCD): 2.585ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.667ns, distribution 1.493ns) Clock Net Delay (Destination): 2.220ns (routing 0.603ns, distribution 1.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.585 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.746 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.307 7.053 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X53Y497 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.194 7.491 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y495 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.051 7.542 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/O net (fo=7, routed) 0.447 7.989 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X53Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.220 10.913 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.195 11.108 clock uncertainty -0.035 11.073 SLICE_X53Y498 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 11.018 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 11.018 arrival time -7.989 ------------------------------------------------------------------- slack 3.029 Slack (MET) : 3.033ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.401ns (logic 1.456ns (26.958%) route 3.945ns (73.042%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.206ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.596ns = ( 10.913 - 8.317 ) Source Clock Delay (SCD): 2.585ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.667ns, distribution 1.493ns) Clock Net Delay (Destination): 2.220ns (routing 0.603ns, distribution 1.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.585 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.746 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.307 7.053 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X53Y497 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.194 7.491 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y495 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.051 7.542 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/O net (fo=7, routed) 0.444 7.986 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X53Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.220 10.913 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.195 11.108 clock uncertainty -0.035 11.073 SLICE_X53Y498 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 11.019 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 11.019 arrival time -7.986 ------------------------------------------------------------------- slack 3.033 Slack (MET) : 3.033ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 5.401ns (logic 1.456ns (26.958%) route 3.945ns (73.042%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.206ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.596ns = ( 10.913 - 8.317 ) Source Clock Delay (SCD): 2.585ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.160ns (routing 0.667ns, distribution 1.493ns) Clock Net Delay (Destination): 2.220ns (routing 0.603ns, distribution 1.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.160 2.585 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3]) 1.161 3.746 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3] net (fo=10, routed) 3.307 7.053 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] SLICE_X53Y497 LUT4 (Prop_D6LUT_SLICEM_I2_O) 0.244 7.297 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/O net (fo=5, routed) 0.194 7.491 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X53Y495 LUT5 (Prop_E6LUT_SLICEM_I3_O) 0.051 7.542 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/O net (fo=7, routed) 0.444 7.986 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 SLICE_X53Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.220 10.913 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y498 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.195 11.108 clock uncertainty -0.035 11.073 SLICE_X53Y498 FDRE (Setup_CFF_SLICEM_C_CE) -0.054 11.019 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.019 arrival time -7.986 ------------------------------------------------------------------- slack 3.033 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].rx_data_ngccm_reg[41][80]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.048ns (31.579%) route 0.104ns (68.421%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.300ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.974ns (routing 0.301ns, distribution 0.673ns) Clock Net Delay (Destination): 1.148ns (routing 0.348ns, distribution 0.800ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y503 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y503 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.138 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/Q net (fo=1, routed) 0.104 1.242 rx_data[41][80] SLICE_X55Y503 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][80]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.148 1.300 g_gbt_bank[3].gbtbank_n_74 SLICE_X55Y503 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][80]/C clock pessimism -0.144 1.156 SLICE_X55Y503 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.211 SFP_GEN[41].rx_data_ngccm_reg[41][80] ------------------------------------------------------------------- required time -1.211 arrival time 1.242 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.033ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.078ns (45.882%) route 0.092ns (54.118%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.308ns Source Clock Delay (SCD): 1.083ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.967ns (routing 0.301ns, distribution 0.666ns) Clock Net Delay (Destination): 1.156ns (routing 0.348ns, distribution 0.808ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.083 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X55Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y510 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.131 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.076 1.207 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in SLICE_X54Y510 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.030 1.237 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__40/O net (fo=1, routed) 0.016 1.253 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] SLICE_X54Y510 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.308 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X54Y510 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.144 1.164 SLICE_X54Y510 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.220 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -1.220 arrival time 1.253 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].rx_data_ngccm_reg[41][33]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.048ns (27.746%) route 0.125ns (72.254%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.301ns Source Clock Delay (SCD): 1.082ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.966ns (routing 0.301ns, distribution 0.665ns) Clock Net Delay (Destination): 1.149ns (routing 0.348ns, distribution 0.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.966 1.082 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X56Y510 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y510 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.130 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/Q net (fo=1, routed) 0.125 1.255 rx_data[41][33] SLICE_X56Y509 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][33]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.149 1.301 g_gbt_bank[3].gbtbank_n_74 SLICE_X56Y509 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][33]/C clock pessimism -0.144 1.157 SLICE_X56Y509 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.213 SFP_GEN[41].rx_data_ngccm_reg[41][33] ------------------------------------------------------------------- required time -1.213 arrival time 1.255 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.972ns (routing 0.301ns, distribution 0.671ns) Clock Net Delay (Destination): 1.166ns (routing 0.348ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y503 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.137 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.034 1.171 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in SLICE_X54Y503 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.216 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__40/O net (fo=1, routed) 0.016 1.232 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X54Y503 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.318 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y503 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.186 1.132 SLICE_X54Y503 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.188 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.188 arrival time 1.232 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].rx_data_ngccm_reg[41][26]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.140ns (logic 0.048ns (34.286%) route 0.092ns (65.714%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.290ns Source Clock Delay (SCD): 1.074ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.958ns (routing 0.301ns, distribution 0.657ns) Clock Net Delay (Destination): 1.138ns (routing 0.348ns, distribution 0.790ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.958 1.074 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y508 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y508 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.122 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.092 1.214 rx_data[41][26] SLICE_X57Y507 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][26]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.138 1.290 g_gbt_bank[3].gbtbank_n_74 SLICE_X57Y507 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][26]/C clock pessimism -0.176 1.114 SLICE_X57Y507 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.170 SFP_GEN[41].rx_data_ngccm_reg[41][26] ------------------------------------------------------------------- required time -1.170 arrival time 1.214 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].rx_data_ngccm_reg[41][55]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.299ns Source Clock Delay (SCD): 1.080ns Clock Pessimism Removal (CPR): 0.177ns Clock Net Delay (Source): 0.964ns (routing 0.301ns, distribution 0.663ns) Clock Net Delay (Destination): 1.147ns (routing 0.348ns, distribution 0.799ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.964 1.080 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X50Y500 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y500 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.128 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.095 1.223 rx_data[41][55] SLICE_X50Y501 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][55]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.299 g_gbt_bank[3].gbtbank_n_74 SLICE_X50Y501 FDCE r SFP_GEN[41].rx_data_ngccm_reg[41][55]/C clock pessimism -0.177 1.122 SLICE_X50Y501 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.178 SFP_GEN[41].rx_data_ngccm_reg[41][55] ------------------------------------------------------------------- required time -1.178 arrival time 1.223 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.089ns (46.597%) route 0.102ns (53.403%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.317ns Source Clock Delay (SCD): 1.083ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.967ns (routing 0.301ns, distribution 0.666ns) Clock Net Delay (Destination): 1.165ns (routing 0.348ns, distribution 0.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.083 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X52Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y503 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.132 f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[0]/Q net (fo=5, routed) 0.090 1.222 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/Q[0] SLICE_X53Y503 LUT5 (Prop_D5LUT_SLICEM_I3_O) 0.040 1.262 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/decoder/RX_ISDATA_FLAG_O0/O net (fo=1, routed) 0.012 1.274 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_I SLICE_X53Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.165 1.317 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/CLK SLICE_X53Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.144 1.173 SLICE_X53Y503 FDCE (Hold_DFF2_SLICEM_C_D) 0.056 1.229 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.229 arrival time 1.274 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.087ns (47.283%) route 0.097ns (52.717%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.294ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.953ns (routing 0.301ns, distribution 0.652ns) Clock Net Delay (Destination): 1.142ns (routing 0.348ns, distribution 0.794ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.069 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y509 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.118 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.086 1.204 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_7_in SLICE_X57Y510 LUT3 (Prop_C5LUT_SLICEL_I2_O) 0.038 1.242 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__40/O net (fo=1, routed) 0.011 1.253 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[2] SLICE_X57Y510 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.142 1.294 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y510 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.144 1.150 SLICE_X57Y510 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.206 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -1.206 arrival time 1.253 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.149ns (logic 0.104ns (69.799%) route 0.045ns (30.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.972ns (routing 0.301ns, distribution 0.671ns) Clock Net Delay (Destination): 1.166ns (routing 0.348ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y503 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y503 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.137 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.034 1.171 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in SLICE_X54Y503 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.055 1.226 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__40/O net (fo=1, routed) 0.011 1.237 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[18] SLICE_X54Y503 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.318 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X54Y503 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.186 1.132 SLICE_X54Y503 FDRE (Hold_DFF2_SLICEL_C_D) 0.056 1.188 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -1.188 arrival time 1.237 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_43 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.063ns (40.645%) route 0.092ns (59.355%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.082ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.966ns (routing 0.301ns, distribution 0.665ns) Clock Net Delay (Destination): 1.157ns (routing 0.348ns, distribution 0.809ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.966 1.082 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X56Y511 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y511 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.130 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.080 1.210 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/O83[1] SLICE_X56Y510 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.225 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__40/O net (fo=1, routed) 0.012 1.237 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/I7[1] SLICE_X56Y510 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X56Y510 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.178 1.131 SLICE_X56Y510 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.187 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.187 arrival time 1.237 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_43 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y195 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X50Y498 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X50Y498 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y498 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X58Y499 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y498 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y504 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y498 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y498 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X51Y498 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X55Y503 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[72]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X55Y503 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[74]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X55Y503 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[80]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X55Y503 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[82]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y498 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y500 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[62]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X52Y500 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X54Y498 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X58Y504 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/shiftA_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X58Y504 SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/shiftA_reg[1]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y33 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_44 To Clock: gtwiz_userclk_rx_srcclk_out[0]_44 Setup : 0 Failing Endpoints, Worst Slack 2.735ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.735ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.292ns (logic 0.392ns (7.407%) route 4.900ns (92.593%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.197ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.264ns = ( 10.581 - 8.317 ) Source Clock Delay (SCD): 2.650ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.225ns (routing 0.699ns, distribution 1.526ns) Clock Net Delay (Destination): 1.888ns (routing 0.636ns, distribution 1.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.225 2.650 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y486 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.789 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.272 6.061 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X33Y508 LUT2 (Prop_B5LUT_SLICEL_I1_O) 0.253 6.314 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/O net (fo=76, routed) 1.628 7.942 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X28Y517 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.888 10.581 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X28Y517 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism 0.189 10.771 clock uncertainty -0.035 10.735 SLICE_X28Y517 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.677 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time 10.677 arrival time -7.942 ------------------------------------------------------------------- slack 2.735 Slack (MET) : 2.741ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.289ns (logic 0.392ns (7.412%) route 4.897ns (92.588%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.197ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.264ns = ( 10.581 - 8.317 ) Source Clock Delay (SCD): 2.650ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.225ns (routing 0.699ns, distribution 1.526ns) Clock Net Delay (Destination): 1.888ns (routing 0.636ns, distribution 1.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.225 2.650 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y486 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.789 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.272 6.061 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X33Y508 LUT2 (Prop_B5LUT_SLICEL_I1_O) 0.253 6.314 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/O net (fo=76, routed) 1.625 7.939 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X28Y517 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.888 10.581 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X28Y517 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism 0.189 10.771 clock uncertainty -0.035 10.735 SLICE_X28Y517 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.680 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time 10.680 arrival time -7.939 ------------------------------------------------------------------- slack 2.741 Slack (MET) : 2.920ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.104ns (logic 0.392ns (7.680%) route 4.712ns (92.320%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.203ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.258ns = ( 10.575 - 8.317 ) Source Clock Delay (SCD): 2.650ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.225ns (routing 0.699ns, distribution 1.526ns) Clock Net Delay (Destination): 1.882ns (routing 0.636ns, distribution 1.246ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.225 2.650 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y486 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.789 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.272 6.061 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X33Y508 LUT2 (Prop_B5LUT_SLICEL_I1_O) 0.253 6.314 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/O net (fo=76, routed) 1.440 7.754 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X30Y519 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.882 10.575 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y519 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism 0.189 10.765 clock uncertainty -0.035 10.729 SLICE_X30Y519 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.674 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time 10.674 arrival time -7.754 ------------------------------------------------------------------- slack 2.920 Slack (MET) : 2.920ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.104ns (logic 0.392ns (7.680%) route 4.712ns (92.320%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.203ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.258ns = ( 10.575 - 8.317 ) Source Clock Delay (SCD): 2.650ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.225ns (routing 0.699ns, distribution 1.526ns) Clock Net Delay (Destination): 1.882ns (routing 0.636ns, distribution 1.246ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.225 2.650 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y486 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.789 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.272 6.061 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X33Y508 LUT2 (Prop_B5LUT_SLICEL_I1_O) 0.253 6.314 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/O net (fo=76, routed) 1.440 7.754 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X30Y519 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.882 10.575 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y519 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism 0.189 10.765 clock uncertainty -0.035 10.729 SLICE_X30Y519 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 10.674 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time 10.674 arrival time -7.754 ------------------------------------------------------------------- slack 2.920 Slack (MET) : 2.925ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.100ns (logic 0.392ns (7.686%) route 4.708ns (92.314%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.203ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.258ns = ( 10.575 - 8.317 ) Source Clock Delay (SCD): 2.650ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.225ns (routing 0.699ns, distribution 1.526ns) Clock Net Delay (Destination): 1.882ns (routing 0.636ns, distribution 1.246ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.225 2.650 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y486 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.789 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.272 6.061 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X33Y508 LUT2 (Prop_B5LUT_SLICEL_I1_O) 0.253 6.314 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/O net (fo=76, routed) 1.436 7.750 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X30Y519 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.882 10.575 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y519 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism 0.189 10.765 clock uncertainty -0.035 10.729 SLICE_X30Y519 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 10.675 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time 10.675 arrival time -7.750 ------------------------------------------------------------------- slack 2.925 Slack (MET) : 2.925ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.100ns (logic 0.392ns (7.686%) route 4.708ns (92.314%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.203ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.258ns = ( 10.575 - 8.317 ) Source Clock Delay (SCD): 2.650ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.225ns (routing 0.699ns, distribution 1.526ns) Clock Net Delay (Destination): 1.882ns (routing 0.636ns, distribution 1.246ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.225 2.650 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y486 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.789 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.272 6.061 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X33Y508 LUT2 (Prop_B5LUT_SLICEL_I1_O) 0.253 6.314 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/O net (fo=76, routed) 1.436 7.750 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X30Y519 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.882 10.575 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y519 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism 0.189 10.765 clock uncertainty -0.035 10.729 SLICE_X30Y519 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 10.675 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time 10.675 arrival time -7.750 ------------------------------------------------------------------- slack 2.925 Slack (MET) : 2.925ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 5.100ns (logic 0.392ns (7.686%) route 4.708ns (92.314%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.203ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.258ns = ( 10.575 - 8.317 ) Source Clock Delay (SCD): 2.650ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.225ns (routing 0.699ns, distribution 1.526ns) Clock Net Delay (Destination): 1.882ns (routing 0.636ns, distribution 1.246ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.225 2.650 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y486 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.789 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.272 6.061 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X33Y508 LUT2 (Prop_B5LUT_SLICEL_I1_O) 0.253 6.314 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/O net (fo=76, routed) 1.436 7.750 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X30Y519 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.882 10.575 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y519 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism 0.189 10.765 clock uncertainty -0.035 10.729 SLICE_X30Y519 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 10.675 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time 10.675 arrival time -7.750 ------------------------------------------------------------------- slack 2.925 Slack (MET) : 3.068ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 4.981ns (logic 0.392ns (7.870%) route 4.589ns (92.130%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.178ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.283ns = ( 10.600 - 8.317 ) Source Clock Delay (SCD): 2.650ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.225ns (routing 0.699ns, distribution 1.526ns) Clock Net Delay (Destination): 1.907ns (routing 0.636ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.225 2.650 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y486 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.789 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.272 6.061 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X33Y508 LUT2 (Prop_B5LUT_SLICEL_I1_O) 0.253 6.314 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/O net (fo=76, routed) 1.317 7.631 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X31Y518 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.907 10.600 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X31Y518 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C clock pessimism 0.189 10.789 clock uncertainty -0.035 10.754 SLICE_X31Y518 FDRE (Setup_DFF2_SLICEM_C_CE) -0.055 10.699 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7] ------------------------------------------------------------------- required time 10.699 arrival time -7.631 ------------------------------------------------------------------- slack 3.068 Slack (MET) : 3.072ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 4.978ns (logic 0.392ns (7.875%) route 4.586ns (92.125%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.177ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.284ns = ( 10.601 - 8.317 ) Source Clock Delay (SCD): 2.650ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.225ns (routing 0.699ns, distribution 1.526ns) Clock Net Delay (Destination): 1.908ns (routing 0.636ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.225 2.650 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y486 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.789 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.272 6.061 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X33Y508 LUT2 (Prop_B5LUT_SLICEL_I1_O) 0.253 6.314 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/O net (fo=76, routed) 1.314 7.628 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X32Y518 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.908 10.601 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X32Y518 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C clock pessimism 0.189 10.790 clock uncertainty -0.035 10.755 SLICE_X32Y518 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.700 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3] ------------------------------------------------------------------- required time 10.700 arrival time -7.628 ------------------------------------------------------------------- slack 3.072 Slack (MET) : 3.072ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 4.978ns (logic 0.392ns (7.875%) route 4.586ns (92.125%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.177ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.284ns = ( 10.601 - 8.317 ) Source Clock Delay (SCD): 2.650ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.225ns (routing 0.699ns, distribution 1.526ns) Clock Net Delay (Destination): 1.908ns (routing 0.636ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.225 2.650 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y486 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.789 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/Q net (fo=137, routed) 3.272 6.061 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X33Y508 LUT2 (Prop_B5LUT_SLICEL_I1_O) 0.253 6.314 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__41/O net (fo=76, routed) 1.314 7.628 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X32Y518 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.908 10.601 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X32Y518 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism 0.189 10.790 clock uncertainty -0.035 10.755 SLICE_X32Y518 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 10.700 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time 10.700 arrival time -7.628 ------------------------------------------------------------------- slack 3.072 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].rx_data_ngccm_reg[42][4]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.176ns (logic 0.048ns (27.273%) route 0.128ns (72.727%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.149ns Source Clock Delay (SCD): 0.935ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.819ns (routing 0.319ns, distribution 0.500ns) Clock Net Delay (Destination): 0.997ns (routing 0.369ns, distribution 0.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.819 0.935 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X28Y517 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y517 FDRE (Prop_HFF_SLICEM_C_Q) 0.048 0.983 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.128 1.111 rx_data[42][4] SLICE_X29Y517 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.149 g_gbt_bank[3].gbtbank_n_84 SLICE_X29Y517 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][4]/C clock pessimism -0.130 1.019 SLICE_X29Y517 FDCE (Hold_EFF_SLICEM_C_D) 0.056 1.075 SFP_GEN[42].rx_data_ngccm_reg[42][4] ------------------------------------------------------------------- required time -1.075 arrival time 1.111 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.036ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.080ns (46.243%) route 0.093ns (53.757%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.145ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.818ns (routing 0.319ns, distribution 0.499ns) Clock Net Delay (Destination): 0.993ns (routing 0.369ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.818 0.934 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X29Y511 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y511 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 0.983 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.077 1.060 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_5_in SLICE_X31Y511 LUT3 (Prop_D6LUT_SLICEM_I2_O) 0.031 1.091 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__41/O net (fo=1, routed) 0.016 1.107 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] SLICE_X31Y511 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.145 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X31Y511 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.130 1.015 SLICE_X31Y511 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.071 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -1.071 arrival time 1.107 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].rx_data_ngccm_reg[42][57]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.149ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.824ns (routing 0.319ns, distribution 0.505ns) Clock Net Delay (Destination): 0.997ns (routing 0.369ns, distribution 0.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.940 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y517 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y517 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 0.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/Q net (fo=1, routed) 0.095 1.083 rx_data[42][57] SLICE_X30Y518 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][57]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.149 g_gbt_bank[3].gbtbank_n_84 SLICE_X30Y518 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][57]/C clock pessimism -0.159 0.990 SLICE_X30Y518 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.045 SFP_GEN[42].rx_data_ngccm_reg[42][57] ------------------------------------------------------------------- required time -1.045 arrival time 1.083 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].rx_data_ngccm_reg[42][51]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.145ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.824ns (routing 0.319ns, distribution 0.505ns) Clock Net Delay (Destination): 0.993ns (routing 0.369ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.940 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y516 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y516 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 0.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/Q net (fo=1, routed) 0.094 1.082 rx_data[42][51] SLICE_X30Y515 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][51]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.145 g_gbt_bank[3].gbtbank_n_84 SLICE_X30Y515 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][51]/C clock pessimism -0.159 0.986 SLICE_X30Y515 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.042 SFP_GEN[42].rx_data_ngccm_reg[42][51] ------------------------------------------------------------------- required time -1.042 arrival time 1.082 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].rx_data_ngccm_reg[42][53]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.048ns (33.803%) route 0.094ns (66.197%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.145ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 0.824ns (routing 0.319ns, distribution 0.505ns) Clock Net Delay (Destination): 0.993ns (routing 0.369ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.940 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y516 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y516 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 0.988 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/Q net (fo=1, routed) 0.094 1.082 rx_data[42][53] SLICE_X30Y515 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][53]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.145 g_gbt_bank[3].gbtbank_n_84 SLICE_X30Y515 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][53]/C clock pessimism -0.159 0.986 SLICE_X30Y515 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.042 SFP_GEN[42].rx_data_ngccm_reg[42][53] ------------------------------------------------------------------- required time -1.042 arrival time 1.082 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.178ns (logic 0.089ns (50.000%) route 0.089ns (50.000%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.145ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.818ns (routing 0.319ns, distribution 0.499ns) Clock Net Delay (Destination): 0.993ns (routing 0.369ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.818 0.934 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X29Y511 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y511 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 0.983 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.077 1.060 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_5_in SLICE_X31Y511 LUT3 (Prop_D5LUT_SLICEM_I0_O) 0.040 1.100 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__41/O net (fo=1, routed) 0.012 1.112 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[3] SLICE_X31Y511 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.993 1.145 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X31Y511 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C clock pessimism -0.130 1.015 SLICE_X31Y511 FDRE (Hold_DFF2_SLICEM_C_D) 0.056 1.071 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3] ------------------------------------------------------------------- required time -1.071 arrival time 1.112 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.044ns (arrival time - required time) Source: SFP_GEN[42].rx_data_ngccm_reg[42][7]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[6]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.087ns (49.714%) route 0.088ns (50.286%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.946ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.830ns (routing 0.319ns, distribution 0.511ns) Clock Net Delay (Destination): 0.999ns (routing 0.369ns, distribution 0.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.830 0.946 g_gbt_bank[3].gbtbank_n_84 SLICE_X31Y517 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][7]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y517 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 0.995 r SFP_GEN[42].rx_data_ngccm_reg[42][7]/Q net (fo=1, routed) 0.077 1.072 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[83]_0[7] SLICE_X29Y517 LUT3 (Prop_C5LUT_SLICEM_I0_O) 0.038 1.110 r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40[6]_i_1/O net (fo=1, routed) 0.011 1.121 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40[6]_i_1_n_0 SLICE_X29Y517 FDCE r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.151 SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X29Y517 FDCE r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[6]/C clock pessimism -0.130 1.021 SLICE_X29Y517 FDCE (Hold_CFF2_SLICEM_C_D) 0.056 1.077 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[6] ------------------------------------------------------------------- required time -1.077 arrival time 1.121 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].rx_data_ngccm_reg[42][47]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.049ns (28.824%) route 0.121ns (71.176%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.137ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.824ns (routing 0.319ns, distribution 0.505ns) Clock Net Delay (Destination): 0.985ns (routing 0.369ns, distribution 0.616ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.940 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y516 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y516 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 0.989 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/Q net (fo=1, routed) 0.121 1.110 rx_data[42][47] SLICE_X31Y516 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][47]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.985 1.137 g_gbt_bank[3].gbtbank_n_84 SLICE_X31Y516 FDCE r SFP_GEN[42].rx_data_ngccm_reg[42][47]/C clock pessimism -0.130 1.007 SLICE_X31Y516 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.063 SFP_GEN[42].rx_data_ngccm_reg[42][47] ------------------------------------------------------------------- required time -1.063 arrival time 1.110 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.149ns Source Clock Delay (SCD): 0.938ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 0.822ns (routing 0.319ns, distribution 0.503ns) Clock Net Delay (Destination): 0.997ns (routing 0.369ns, distribution 0.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.938 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y516 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y516 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 0.987 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Q net (fo=2, routed) 0.036 1.023 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in SLICE_X30Y516 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.045 1.068 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__41/O net (fo=1, routed) 0.016 1.084 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] SLICE_X30Y516 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.149 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X30Y516 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.169 0.980 SLICE_X30Y516 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.036 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -1.036 arrival time 1.084 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_44 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.170ns (logic 0.079ns (46.471%) route 0.091ns (53.529%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.164ns Source Clock Delay (SCD): 0.968ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.852ns (routing 0.319ns, distribution 0.533ns) Clock Net Delay (Destination): 1.012ns (routing 0.369ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.852 0.968 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X41Y484 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y484 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.017 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/Q net (fo=9, routed) 0.079 1.096 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt_reg[6][7]_0[4] SLICE_X40Y484 LUT6 (Prop_A6LUT_SLICEL_I4_O) 0.030 1.126 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt[6][5]_i_1__2/O net (fo=1, routed) 0.012 1.138 g_gbt_bank[3].gbtbank/i_gbt_bank_n_308 SLICE_X40Y484 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.164 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y484 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/C clock pessimism -0.130 1.034 SLICE_X40Y484 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.090 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5] ------------------------------------------------------------------- required time -1.090 arrival time 1.138 ------------------------------------------------------------------- slack 0.048 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_44 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y197 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X58Y482 g_clock_rate_din[42].ngccm_status_cnt_reg[42][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X58Y482 g_clock_rate_din[42].ngccm_status_cnt_reg[42][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X58Y482 g_clock_rate_din[42].ngccm_status_cnt_reg[42][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X59Y481 g_clock_rate_din[42].ngccm_status_cnt_reg[42][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][1]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][3]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y480 g_clock_rate_din[42].ngccm_status_cnt_reg[42][6]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y480 g_clock_rate_din[42].rx_test_comm_cnt_reg[42]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X29Y518 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[52]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X29Y518 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[54]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X58Y482 g_clock_rate_din[42].ngccm_status_cnt_reg[42][0]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X58Y482 g_clock_rate_din[42].ngccm_status_cnt_reg[42][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X58Y482 g_clock_rate_din[42].ngccm_status_cnt_reg[42][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X35Y510 SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X34Y511 SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X28Y527 SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[60]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y34 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_45 To Clock: gtwiz_userclk_rx_srcclk_out[0]_45 Setup : 0 Failing Endpoints, Worst Slack 3.659ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.031ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.659ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][56]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 4.243ns (logic 0.360ns (8.485%) route 3.883ns (91.515%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.322ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.375ns = ( 10.692 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 1.999ns (routing 0.721ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.199 5.239 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.460 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.684 7.144 rx_data_ngccm[43] SLICE_X45Y525 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][56]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.999 10.692 g_gbt_bank[3].gbtbank_n_94 SLICE_X45Y525 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][56]/C clock pessimism 0.204 10.897 clock uncertainty -0.035 10.861 SLICE_X45Y525 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 10.803 SFP_GEN[43].rx_data_ngccm_reg[43][56] ------------------------------------------------------------------- required time 10.803 arrival time -7.144 ------------------------------------------------------------------- slack 3.659 Slack (MET) : 3.659ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][62]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 4.243ns (logic 0.360ns (8.485%) route 3.883ns (91.515%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.322ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.375ns = ( 10.692 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 1.999ns (routing 0.721ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.199 5.239 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.460 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.684 7.144 rx_data_ngccm[43] SLICE_X45Y525 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][62]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.999 10.692 g_gbt_bank[3].gbtbank_n_94 SLICE_X45Y525 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][62]/C clock pessimism 0.204 10.897 clock uncertainty -0.035 10.861 SLICE_X45Y525 FDCE (Setup_FFF2_SLICEL_C_CE) -0.058 10.803 SFP_GEN[43].rx_data_ngccm_reg[43][62] ------------------------------------------------------------------- required time 10.803 arrival time -7.144 ------------------------------------------------------------------- slack 3.659 Slack (MET) : 3.665ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][54]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 4.240ns (logic 0.360ns (8.491%) route 3.880ns (91.509%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.322ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.375ns = ( 10.692 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 1.999ns (routing 0.721ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.199 5.239 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.460 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.681 7.141 rx_data_ngccm[43] SLICE_X45Y525 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][54]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.999 10.692 g_gbt_bank[3].gbtbank_n_94 SLICE_X45Y525 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][54]/C clock pessimism 0.204 10.897 clock uncertainty -0.035 10.861 SLICE_X45Y525 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 10.806 SFP_GEN[43].rx_data_ngccm_reg[43][54] ------------------------------------------------------------------- required time 10.806 arrival time -7.141 ------------------------------------------------------------------- slack 3.665 Slack (MET) : 3.665ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][61]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 4.240ns (logic 0.360ns (8.491%) route 3.880ns (91.509%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.322ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.375ns = ( 10.692 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 1.999ns (routing 0.721ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.199 5.239 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.460 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.681 7.141 rx_data_ngccm[43] SLICE_X45Y525 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][61]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.999 10.692 g_gbt_bank[3].gbtbank_n_94 SLICE_X45Y525 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][61]/C clock pessimism 0.204 10.897 clock uncertainty -0.035 10.861 SLICE_X45Y525 FDCE (Setup_FFF_SLICEL_C_CE) -0.055 10.806 SFP_GEN[43].rx_data_ngccm_reg[43][61] ------------------------------------------------------------------- required time 10.806 arrival time -7.141 ------------------------------------------------------------------- slack 3.665 Slack (MET) : 3.674ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][57]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 4.241ns (logic 0.360ns (8.489%) route 3.881ns (91.511%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.385ns = ( 10.702 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.009ns (routing 0.721ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.199 5.239 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.460 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.682 7.142 rx_data_ngccm[43] SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][57]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.009 10.702 g_gbt_bank[3].gbtbank_n_94 SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][57]/C clock pessimism 0.204 10.907 clock uncertainty -0.035 10.871 SLICE_X45Y524 FDCE (Setup_AFF2_SLICEL_C_CE) -0.055 10.816 SFP_GEN[43].rx_data_ngccm_reg[43][57] ------------------------------------------------------------------- required time 10.816 arrival time -7.142 ------------------------------------------------------------------- slack 3.674 Slack (MET) : 3.674ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][59]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 4.241ns (logic 0.360ns (8.489%) route 3.881ns (91.511%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.385ns = ( 10.702 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.009ns (routing 0.721ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.199 5.239 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.460 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.682 7.142 rx_data_ngccm[43] SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][59]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.009 10.702 g_gbt_bank[3].gbtbank_n_94 SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][59]/C clock pessimism 0.204 10.907 clock uncertainty -0.035 10.871 SLICE_X45Y524 FDCE (Setup_BFF2_SLICEL_C_CE) -0.055 10.816 SFP_GEN[43].rx_data_ngccm_reg[43][59] ------------------------------------------------------------------- required time 10.816 arrival time -7.142 ------------------------------------------------------------------- slack 3.674 Slack (MET) : 3.674ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][74]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 4.241ns (logic 0.360ns (8.489%) route 3.881ns (91.511%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.385ns = ( 10.702 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.009ns (routing 0.721ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.199 5.239 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.460 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.682 7.142 rx_data_ngccm[43] SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][74]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.009 10.702 g_gbt_bank[3].gbtbank_n_94 SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][74]/C clock pessimism 0.204 10.907 clock uncertainty -0.035 10.871 SLICE_X45Y524 FDCE (Setup_CFF2_SLICEL_C_CE) -0.055 10.816 SFP_GEN[43].rx_data_ngccm_reg[43][74] ------------------------------------------------------------------- required time 10.816 arrival time -7.142 ------------------------------------------------------------------- slack 3.674 Slack (MET) : 3.679ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][55]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 4.237ns (logic 0.360ns (8.497%) route 3.877ns (91.503%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.385ns = ( 10.702 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.009ns (routing 0.721ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.199 5.239 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.460 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.678 7.138 rx_data_ngccm[43] SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][55]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.009 10.702 g_gbt_bank[3].gbtbank_n_94 SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][55]/C clock pessimism 0.204 10.907 clock uncertainty -0.035 10.871 SLICE_X45Y524 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 10.817 SFP_GEN[43].rx_data_ngccm_reg[43][55] ------------------------------------------------------------------- required time 10.817 arrival time -7.138 ------------------------------------------------------------------- slack 3.679 Slack (MET) : 3.679ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][58]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 4.237ns (logic 0.360ns (8.497%) route 3.877ns (91.503%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.385ns = ( 10.702 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.009ns (routing 0.721ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.199 5.239 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.460 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.678 7.138 rx_data_ngccm[43] SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][58]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.009 10.702 g_gbt_bank[3].gbtbank_n_94 SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][58]/C clock pessimism 0.204 10.907 clock uncertainty -0.035 10.871 SLICE_X45Y524 FDCE (Setup_BFF_SLICEL_C_CE) -0.054 10.817 SFP_GEN[43].rx_data_ngccm_reg[43][58] ------------------------------------------------------------------- required time 10.817 arrival time -7.138 ------------------------------------------------------------------- slack 3.679 Slack (MET) : 3.679ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][60]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 4.237ns (logic 0.360ns (8.497%) route 3.877ns (91.503%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.385ns = ( 10.702 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.009ns (routing 0.721ns, distribution 1.288ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.199 5.239 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT6 (Prop_F6LUT_SLICEL_I0_O) 0.221 5.460 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/O net (fo=76, routed) 1.678 7.138 rx_data_ngccm[43] SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][60]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.009 10.702 g_gbt_bank[3].gbtbank_n_94 SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][60]/C clock pessimism 0.204 10.907 clock uncertainty -0.035 10.871 SLICE_X45Y524 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 10.817 SFP_GEN[43].rx_data_ngccm_reg[43][60] ------------------------------------------------------------------- required time 10.817 arrival time -7.138 ------------------------------------------------------------------- slack 3.679 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.168ns (logic 0.079ns (47.024%) route 0.089ns (52.976%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.254ns Source Clock Delay (SCD): 1.030ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.914ns (routing 0.382ns, distribution 0.532ns) Clock Net Delay (Destination): 1.102ns (routing 0.446ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.914 1.030 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X38Y519 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y519 FDCE (Prop_CFF_SLICEL_C_Q) 0.048 1.078 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.074 1.152 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_7_in SLICE_X39Y519 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.031 1.183 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__42/O net (fo=1, routed) 0.015 1.198 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] SLICE_X39Y519 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.102 1.254 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X39Y519 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.143 1.111 SLICE_X39Y519 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.167 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.167 arrival time 1.198 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.079ns (45.402%) route 0.095ns (54.598%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.253ns Source Clock Delay (SCD): 1.034ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.918ns (routing 0.382ns, distribution 0.536ns) Clock Net Delay (Destination): 1.101ns (routing 0.446ns, distribution 0.655ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.918 1.034 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/CLK SLICE_X31Y523 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y523 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 1.083 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.079 1.162 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/ready_from_bitSlipCtrller_7 SLICE_X29Y523 LUT6 (Prop_C6LUT_SLICEM_I0_O) 0.030 1.192 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_i_1__42/O net (fo=1, routed) 0.016 1.208 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd SLICE_X29Y523 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.101 1.253 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK SLICE_X29Y523 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/C clock pessimism -0.143 1.110 SLICE_X29Y523 FDCE (Hold_CFF_SLICEM_C_D) 0.056 1.166 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg ------------------------------------------------------------------- required time -1.166 arrival time 1.208 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.079ns (43.889%) route 0.101ns (56.111%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.259ns Source Clock Delay (SCD): 1.035ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.919ns (routing 0.382ns, distribution 0.537ns) Clock Net Delay (Destination): 1.107ns (routing 0.446ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.919 1.035 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X38Y525 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y525 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.084 f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Q net (fo=27, routed) 0.089 1.173 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] SLICE_X39Y525 LUT5 (Prop_A6LUT_SLICEM_I1_O) 0.030 1.203 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[35]_i_1__42/O net (fo=1, routed) 0.012 1.215 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg00[35] SLICE_X39Y525 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.107 1.259 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X39Y525 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]/C clock pessimism -0.143 1.116 SLICE_X39Y525 FDCE (Hold_AFF_SLICEM_C_D) 0.056 1.172 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35] ------------------------------------------------------------------- required time -1.172 arrival time 1.215 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.094ns (50.538%) route 0.092ns (49.462%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.249ns Source Clock Delay (SCD): 1.019ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.903ns (routing 0.382ns, distribution 0.521ns) Clock Net Delay (Destination): 1.097ns (routing 0.446ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.903 1.019 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X45Y524 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y524 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.068 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.076 1.144 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in SLICE_X43Y524 LUT3 (Prop_D6LUT_SLICEL_I2_O) 0.045 1.189 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__42/O net (fo=1, routed) 0.016 1.205 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[10] SLICE_X43Y524 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.097 1.249 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X43Y524 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C clock pessimism -0.143 1.106 SLICE_X43Y524 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.162 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10] ------------------------------------------------------------------- required time -1.162 arrival time 1.205 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][65]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.048ns (32.877%) route 0.098ns (67.123%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.223ns Source Clock Delay (SCD): 1.003ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.887ns (routing 0.382ns, distribution 0.505ns) Clock Net Delay (Destination): 1.071ns (routing 0.446ns, distribution 0.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.887 1.003 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X46Y522 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X46Y522 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.051 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/Q net (fo=1, routed) 0.098 1.149 rx_data[43][65] SLICE_X46Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][65]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.071 1.223 g_gbt_bank[3].gbtbank_n_94 SLICE_X46Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][65]/C clock pessimism -0.173 1.050 SLICE_X46Y524 FDCE (Hold_AFF2_SLICEL_C_D) 0.056 1.106 SFP_GEN[43].rx_data_ngccm_reg[43][65] ------------------------------------------------------------------- required time -1.106 arrival time 1.149 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].rx_data_ngccm_reg[43][60]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.049ns (31.613%) route 0.106ns (68.387%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.247ns Source Clock Delay (SCD): 1.020ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.904ns (routing 0.382ns, distribution 0.522ns) Clock Net Delay (Destination): 1.095ns (routing 0.446ns, distribution 0.649ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.904 1.020 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X45Y523 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y523 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.069 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.106 1.175 rx_data[43][60] SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][60]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.095 1.247 g_gbt_bank[3].gbtbank_n_94 SLICE_X45Y524 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][60]/C clock pessimism -0.174 1.073 SLICE_X45Y524 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.129 SFP_GEN[43].rx_data_ngccm_reg[43][60] ------------------------------------------------------------------- required time -1.129 arrival time 1.175 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.152ns (logic 0.064ns (42.105%) route 0.088ns (57.895%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.274ns Source Clock Delay (SCD): 1.047ns Clock Pessimism Removal (CPR): 0.177ns Clock Net Delay (Source): 0.931ns (routing 0.382ns, distribution 0.549ns) Clock Net Delay (Destination): 1.122ns (routing 0.446ns, distribution 0.676ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.931 1.047 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK SLICE_X30Y522 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y522 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.096 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]/Q net (fo=5, routed) 0.073 1.169 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnt[3] SLICE_X30Y521 LUT6 (Prop_B6LUT_SLICEL_I5_O) 0.015 1.184 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_inv_i_1__43/O net (fo=1, routed) 0.015 1.199 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr3_out SLICE_X30Y521 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.122 1.274 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK SLICE_X30Y521 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv/C clock pessimism -0.177 1.097 SLICE_X30Y521 FDPE (Hold_BFF_SLICEL_C_D) 0.056 1.153 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv ------------------------------------------------------------------- required time -1.153 arrival time 1.199 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: SFP_GEN[43].rx_data_ngccm_reg[43][49]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[48]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.144ns (logic 0.094ns (65.278%) route 0.050ns (34.722%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.246ns Source Clock Delay (SCD): 1.019ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 0.903ns (routing 0.382ns, distribution 0.521ns) Clock Net Delay (Destination): 1.094ns (routing 0.446ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.903 1.019 g_gbt_bank[3].gbtbank_n_94 SLICE_X43Y520 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][49]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y520 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.068 r SFP_GEN[43].rx_data_ngccm_reg[43][49]/Q net (fo=1, routed) 0.034 1.102 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[83]_0[41] SLICE_X43Y520 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.147 r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40[48]_i_1/O net (fo=1, routed) 0.016 1.163 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40[48]_i_1_n_0 SLICE_X43Y520 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[48]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.094 1.246 SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X43Y520 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[48]/C clock pessimism -0.185 1.061 SLICE_X43Y520 FDCE (Hold_DFF_SLICEL_C_D) 0.056 1.117 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[48] ------------------------------------------------------------------- required time -1.117 arrival time 1.163 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.047ns (arrival time - required time) Source: SFP_GEN[43].rx_data_ngccm_reg[43][40]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[40]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.187ns (logic 0.096ns (51.337%) route 0.091ns (48.663%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.243ns Source Clock Delay (SCD): 1.016ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.900ns (routing 0.382ns, distribution 0.518ns) Clock Net Delay (Destination): 1.091ns (routing 0.446ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.900 1.016 g_gbt_bank[3].gbtbank_n_94 SLICE_X43Y521 FDCE r SFP_GEN[43].rx_data_ngccm_reg[43][40]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y521 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.065 r SFP_GEN[43].rx_data_ngccm_reg[43][40]/Q net (fo=1, routed) 0.075 1.140 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[83]_0[32] SLICE_X44Y521 LUT3 (Prop_H6LUT_SLICEM_I1_O) 0.047 1.187 r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40[40]_i_1/O net (fo=1, routed) 0.016 1.203 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 SLICE_X44Y521 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[40]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.091 1.243 SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y521 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[40]/C clock pessimism -0.143 1.100 SLICE_X44Y521 FDCE (Hold_HFF_SLICEM_C_D) 0.056 1.156 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[40] ------------------------------------------------------------------- required time -1.156 arrival time 1.203 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_45 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.259ns Source Clock Delay (SCD): 1.030ns Clock Pessimism Removal (CPR): 0.187ns Clock Net Delay (Source): 0.914ns (routing 0.382ns, distribution 0.532ns) Clock Net Delay (Destination): 1.107ns (routing 0.446ns, distribution 0.661ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.914 1.030 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X38Y521 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y521 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.079 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.036 1.115 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in SLICE_X38Y521 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.045 1.160 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__42/O net (fo=1, routed) 0.016 1.176 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] SLICE_X38Y521 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.107 1.259 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X38Y521 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.187 1.072 SLICE_X38Y521 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.128 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.128 arrival time 1.176 ------------------------------------------------------------------- slack 0.048 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_45 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y215 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y480 g_clock_rate_din[43].ngccm_status_cnt_reg[43][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y480 g_clock_rate_din[43].ngccm_status_cnt_reg[43][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y480 g_clock_rate_din[43].ngccm_status_cnt_reg[43][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X54Y480 g_clock_rate_din[43].ngccm_status_cnt_reg[43][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y481 g_clock_rate_din[43].ngccm_status_cnt_reg[43][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X56Y481 g_clock_rate_din[43].ngccm_status_cnt_reg[43][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X55Y482 g_clock_rate_din[43].ngccm_status_cnt_reg[43][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y520 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y520 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[38]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X43Y516 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[81]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X42Y515 SFP_GEN[43].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X42Y515 SFP_GEN[43].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X42Y515 SFP_GEN[43].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[12]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X49Y480 g_clock_rate_din[43].rx_wordclk_div2_reg[43]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X45Y521 SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X45Y521 SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X43Y517 SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X45Y521 SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X45Y521 SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y35 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_46 To Clock: gtwiz_userclk_rx_srcclk_out[0]_46 Setup : 0 Failing Endpoints, Worst Slack 3.118ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.118ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.303ns (logic 1.618ns (30.511%) route 3.685ns (69.489%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.193ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.579ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.154ns (routing 0.666ns, distribution 1.488ns) Clock Net Delay (Destination): 2.203ns (routing 0.602ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.154 2.579 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.665 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.844 6.509 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X57Y545 LUT4 (Prop_G6LUT_SLICEL_I0_O) 0.239 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.262 7.010 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y542 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.146 7.156 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43/O net (fo=1, routed) 0.159 7.315 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43_n_0 SLICE_X57Y541 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 7.462 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43/O net (fo=2, routed) 0.420 7.882 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43_n_0 SLICE_X57Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X57Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.193 11.089 clock uncertainty -0.035 11.054 SLICE_X57Y545 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 11.000 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.000 arrival time -7.882 ------------------------------------------------------------------- slack 3.118 Slack (MET) : 3.118ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.303ns (logic 1.618ns (30.511%) route 3.685ns (69.489%)) Logic Levels: 3 (LUT4=2 LUT6=1) Clock Path Skew: 0.193ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.579ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.154ns (routing 0.666ns, distribution 1.488ns) Clock Net Delay (Destination): 2.203ns (routing 0.602ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.154 2.579 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.665 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.844 6.509 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X57Y545 LUT4 (Prop_G6LUT_SLICEL_I0_O) 0.239 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.262 7.010 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y542 LUT4 (Prop_D6LUT_SLICEL_I2_O) 0.146 7.156 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43/O net (fo=1, routed) 0.159 7.315 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43_n_0 SLICE_X57Y541 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 7.462 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43/O net (fo=2, routed) 0.420 7.882 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43_n_0 SLICE_X57Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X57Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.193 11.089 clock uncertainty -0.035 11.054 SLICE_X57Y545 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 11.000 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.000 arrival time -7.882 ------------------------------------------------------------------- slack 3.118 Slack (MET) : 3.333ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[98]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 5.239ns (logic 0.956ns (18.248%) route 4.283ns (81.752%)) Logic Levels: 0 Clock Path Skew: 0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.613ns = ( 10.930 - 8.317 ) Source Clock Delay (SCD): 2.579ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.154ns (routing 0.666ns, distribution 1.488ns) Clock Net Delay (Destination): 2.237ns (routing 0.602ns, distribution 1.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.154 2.579 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXCTRL0[1]) 0.956 3.535 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXCTRL0[1] net (fo=6, routed) 4.283 7.818 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/D[18] SLICE_X65Y552 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[98]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.237 10.930 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X65Y552 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[98]/C clock pessimism 0.193 11.123 clock uncertainty -0.035 11.088 SLICE_X65Y552 FDCE (Setup_HFF_SLICEM_C_D) 0.063 11.151 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[98] ------------------------------------------------------------------- required time 11.151 arrival time -7.818 ------------------------------------------------------------------- slack 3.333 Slack (MET) : 3.434ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.981ns (logic 1.412ns (28.348%) route 3.569ns (71.652%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.577ns = ( 10.894 - 8.317 ) Source Clock Delay (SCD): 2.579ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.154ns (routing 0.666ns, distribution 1.488ns) Clock Net Delay (Destination): 2.201ns (routing 0.602ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.154 2.579 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.665 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.844 6.509 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X57Y545 LUT4 (Prop_G6LUT_SLICEL_I0_O) 0.239 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.275 7.023 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y541 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.087 7.110 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.450 7.560 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X58Y543 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 10.894 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X58Y543 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C clock pessimism 0.193 11.087 clock uncertainty -0.035 11.052 SLICE_X58Y543 FDRE (Setup_HFF2_SLICEM_C_CE) -0.058 10.994 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 10.994 arrival time -7.560 ------------------------------------------------------------------- slack 3.434 Slack (MET) : 3.440ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.978ns (logic 1.412ns (28.365%) route 3.566ns (71.635%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.577ns = ( 10.894 - 8.317 ) Source Clock Delay (SCD): 2.579ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.154ns (routing 0.666ns, distribution 1.488ns) Clock Net Delay (Destination): 2.201ns (routing 0.602ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.154 2.579 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.665 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.844 6.509 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X57Y545 LUT4 (Prop_G6LUT_SLICEL_I0_O) 0.239 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.275 7.023 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y541 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.087 7.110 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.447 7.557 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X58Y543 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 10.894 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X58Y543 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C clock pessimism 0.193 11.087 clock uncertainty -0.035 11.052 SLICE_X58Y543 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 10.997 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 10.997 arrival time -7.557 ------------------------------------------------------------------- slack 3.440 Slack (MET) : 3.451ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.964ns (logic 1.412ns (28.445%) route 3.552ns (71.555%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.577ns = ( 10.894 - 8.317 ) Source Clock Delay (SCD): 2.579ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.154ns (routing 0.666ns, distribution 1.488ns) Clock Net Delay (Destination): 2.201ns (routing 0.602ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.154 2.579 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.665 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.844 6.509 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X57Y545 LUT4 (Prop_G6LUT_SLICEL_I0_O) 0.239 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.275 7.023 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y541 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.087 7.110 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.433 7.543 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X57Y542 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 10.894 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X57Y542 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C clock pessimism 0.193 11.087 clock uncertainty -0.035 11.052 SLICE_X57Y542 FDRE (Setup_EFF2_SLICEL_C_CE) -0.058 10.994 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 10.994 arrival time -7.543 ------------------------------------------------------------------- slack 3.451 Slack (MET) : 3.451ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.964ns (logic 1.412ns (28.445%) route 3.552ns (71.555%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.577ns = ( 10.894 - 8.317 ) Source Clock Delay (SCD): 2.579ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.154ns (routing 0.666ns, distribution 1.488ns) Clock Net Delay (Destination): 2.201ns (routing 0.602ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.154 2.579 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.665 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.844 6.509 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X57Y545 LUT4 (Prop_G6LUT_SLICEL_I0_O) 0.239 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.275 7.023 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y541 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.087 7.110 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.433 7.543 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X57Y542 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 10.894 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X57Y542 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C clock pessimism 0.193 11.087 clock uncertainty -0.035 11.052 SLICE_X57Y542 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.994 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 10.994 arrival time -7.543 ------------------------------------------------------------------- slack 3.451 Slack (MET) : 3.457ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.961ns (logic 1.412ns (28.462%) route 3.549ns (71.538%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.577ns = ( 10.894 - 8.317 ) Source Clock Delay (SCD): 2.579ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.154ns (routing 0.666ns, distribution 1.488ns) Clock Net Delay (Destination): 2.201ns (routing 0.602ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.154 2.579 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.665 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.844 6.509 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X57Y545 LUT4 (Prop_G6LUT_SLICEL_I0_O) 0.239 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.275 7.023 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y541 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.087 7.110 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.430 7.540 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X57Y542 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 10.894 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X57Y542 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C clock pessimism 0.193 11.087 clock uncertainty -0.035 11.052 SLICE_X57Y542 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 10.997 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 10.997 arrival time -7.540 ------------------------------------------------------------------- slack 3.457 Slack (MET) : 3.457ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.961ns (logic 1.412ns (28.462%) route 3.549ns (71.538%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.577ns = ( 10.894 - 8.317 ) Source Clock Delay (SCD): 2.579ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.154ns (routing 0.666ns, distribution 1.488ns) Clock Net Delay (Destination): 2.201ns (routing 0.602ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.154 2.579 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.665 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.844 6.509 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X57Y545 LUT4 (Prop_G6LUT_SLICEL_I0_O) 0.239 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.275 7.023 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y541 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.087 7.110 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.430 7.540 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X57Y542 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 10.894 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X57Y542 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C clock pessimism 0.193 11.087 clock uncertainty -0.035 11.052 SLICE_X57Y542 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.997 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 10.997 arrival time -7.540 ------------------------------------------------------------------- slack 3.457 Slack (MET) : 3.480ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.941ns (logic 1.412ns (28.577%) route 3.529ns (71.423%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: 0.193ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.579ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.154ns (routing 0.666ns, distribution 1.488ns) Clock Net Delay (Destination): 2.203ns (routing 0.602ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.154 2.579 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1]) 1.086 3.665 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1] net (fo=10, routed) 2.844 6.509 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] SLICE_X57Y545 LUT4 (Prop_G6LUT_SLICEL_I0_O) 0.239 6.748 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/O net (fo=5, routed) 0.275 7.023 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 SLICE_X57Y541 LUT5 (Prop_E6LUT_SLICEL_I3_O) 0.087 7.110 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/O net (fo=7, routed) 0.410 7.520 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 SLICE_X57Y542 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK SLICE_X57Y542 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C clock pessimism 0.193 11.089 clock uncertainty -0.035 11.054 SLICE_X57Y542 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 11.000 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 11.000 arrival time -7.520 ------------------------------------------------------------------- slack 3.480 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.157ns (logic 0.064ns (40.764%) route 0.093ns (59.236%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.297ns Source Clock Delay (SCD): 1.083ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.967ns (routing 0.301ns, distribution 0.666ns) Clock Net Delay (Destination): 1.145ns (routing 0.348ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.967 1.083 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X58Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y541 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.132 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/Q net (fo=10, routed) 0.077 1.209 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gbtBank_Clk_gen[8].cnt_reg[8][7]_0[0] SLICE_X57Y541 LUT6 (Prop_C6LUT_SLICEL_I4_O) 0.015 1.224 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i[8]_i_1__2/O net (fo=1, routed) 0.016 1.240 g_gbt_bank[3].gbtbank/i_gbt_bank_n_153 SLICE_X57Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.145 1.297 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X57Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/C clock pessimism -0.143 1.154 SLICE_X57Y541 FDCE (Hold_CFF_SLICEL_C_D) 0.056 1.210 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8] ------------------------------------------------------------------- required time -1.210 arrival time 1.240 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[44].rx_data_ngccm_reg[44][39]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.197ns (logic 0.048ns (24.365%) route 0.149ns (75.634%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.982ns (routing 0.301ns, distribution 0.681ns) Clock Net Delay (Destination): 1.190ns (routing 0.348ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.098 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X64Y546 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y546 FDRE (Prop_GFF2_SLICEM_C_Q) 0.048 1.146 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/Q net (fo=1, routed) 0.149 1.295 rx_data[44][39] SLICE_X62Y546 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][39]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.342 g_gbt_bank[3].gbtbank_n_104 SLICE_X62Y546 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][39]/C clock pessimism -0.143 1.199 SLICE_X62Y546 FDCE (Hold_HFF_SLICEM_C_D) 0.056 1.255 SFP_GEN[44].rx_data_ngccm_reg[44][39] ------------------------------------------------------------------- required time -1.255 arrival time 1.295 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[44].rx_data_ngccm_reg[44][1]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.199ns (logic 0.048ns (24.121%) route 0.151ns (75.879%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.982ns (routing 0.301ns, distribution 0.681ns) Clock Net Delay (Destination): 1.190ns (routing 0.348ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.098 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X64Y546 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y546 FDRE (Prop_HFF_SLICEM_C_Q) 0.048 1.146 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.151 1.297 rx_data[44][1] SLICE_X62Y546 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][1]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.342 g_gbt_bank[3].gbtbank_n_104 SLICE_X62Y546 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][1]/C clock pessimism -0.143 1.199 SLICE_X62Y546 FDCE (Hold_EFF_SLICEM_C_D) 0.056 1.255 SFP_GEN[44].rx_data_ngccm_reg[44][1] ------------------------------------------------------------------- required time -1.255 arrival time 1.297 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.045ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.102ns (66.234%) route 0.052ns (33.766%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.113ns Clock Pessimism Removal (CPR): 0.177ns Clock Net Delay (Source): 0.997ns (routing 0.301ns, distribution 0.696ns) Clock Net Delay (Destination): 1.191ns (routing 0.348ns, distribution 0.843ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.113 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X63Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y547 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.162 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.036 1.198 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X63Y546 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.053 1.251 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__43/O net (fo=1, routed) 0.016 1.267 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] SLICE_X63Y546 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.191 1.343 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X63Y546 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.177 1.166 SLICE_X63Y546 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.222 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.222 arrival time 1.267 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.111ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 0.995ns (routing 0.301ns, distribution 0.694ns) Clock Net Delay (Destination): 1.191ns (routing 0.348ns, distribution 0.843ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.995 1.111 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X63Y545 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y545 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 1.160 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Q net (fo=2, routed) 0.036 1.196 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_7_in SLICE_X63Y545 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.241 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__43/O net (fo=1, routed) 0.016 1.257 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] SLICE_X63Y545 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.191 1.343 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X63Y545 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.190 1.153 SLICE_X63Y545 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.209 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.209 arrival time 1.257 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.048ns (arrival time - required time) Source: SFP_GEN[44].ngCCM_gbt/pwr_good_pre_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.148ns (logic 0.064ns (43.243%) route 0.084ns (56.757%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.325ns Source Clock Delay (SCD): 1.103ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.987ns (routing 0.301ns, distribution 0.686ns) Clock Net Delay (Destination): 1.173ns (routing 0.348ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.987 1.103 SFP_GEN[44].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y545 FDCE r SFP_GEN[44].ngCCM_gbt/pwr_good_pre_reg/C ------------------------------------------------------------------- ------------------- SLICE_X61Y545 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.152 r SFP_GEN[44].ngCCM_gbt/pwr_good_pre_reg/Q net (fo=1, routed) 0.068 1.220 SFP_GEN[44].ngCCM_gbt/pwr_good_pre SLICE_X61Y544 LUT4 (Prop_C6LUT_SLICEM_I1_O) 0.015 1.235 r SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_i_1__37/O net (fo=1, routed) 0.016 1.251 SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_i_1__37_n_0 SLICE_X61Y544 FDRE r SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.173 1.325 SFP_GEN[44].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y544 FDRE r SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg/C clock pessimism -0.178 1.147 SLICE_X61Y544 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.203 SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg ------------------------------------------------------------------- required time -1.203 arrival time 1.251 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[44].rx_data_ngccm_reg[44][59]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.049ns (31.613%) route 0.106ns (68.387%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.340ns Source Clock Delay (SCD): 1.112ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.996ns (routing 0.301ns, distribution 0.695ns) Clock Net Delay (Destination): 1.188ns (routing 0.348ns, distribution 0.840ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.996 1.112 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X62Y552 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y552 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.161 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/Q net (fo=1, routed) 0.106 1.267 rx_data[44][59] SLICE_X62Y554 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][59]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.340 g_gbt_bank[3].gbtbank_n_104 SLICE_X62Y554 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][59]/C clock pessimism -0.178 1.162 SLICE_X62Y554 FDCE (Hold_DFF2_SLICEM_C_D) 0.056 1.218 SFP_GEN[44].rx_data_ngccm_reg[44][59] ------------------------------------------------------------------- required time -1.218 arrival time 1.267 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[44].rx_data_ngccm_reg[44][52]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.159ns (logic 0.048ns (30.189%) route 0.111ns (69.811%)) Logic Levels: 0 Clock Path Skew: 0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.340ns Source Clock Delay (SCD): 1.111ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.995ns (routing 0.301ns, distribution 0.694ns) Clock Net Delay (Destination): 1.188ns (routing 0.348ns, distribution 0.840ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.995 1.111 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X62Y553 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y553 FDRE (Prop_HFF_SLICEM_C_Q) 0.048 1.159 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/Q net (fo=1, routed) 0.111 1.270 rx_data[44][52] SLICE_X62Y554 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][52]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.188 1.340 g_gbt_bank[3].gbtbank_n_104 SLICE_X62Y554 FDCE r SFP_GEN[44].rx_data_ngccm_reg[44][52]/C clock pessimism -0.178 1.162 SLICE_X62Y554 FDCE (Hold_BFF2_SLICEM_C_D) 0.056 1.218 SFP_GEN[44].rx_data_ngccm_reg[44][52] ------------------------------------------------------------------- required time -1.218 arrival time 1.270 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.112ns (logic 0.064ns (57.143%) route 0.048ns (42.857%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.004ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.302ns Source Clock Delay (SCD): 1.084ns Clock Pessimism Removal (CPR): 0.214ns Clock Net Delay (Source): 0.968ns (routing 0.301ns, distribution 0.667ns) Clock Net Delay (Destination): 1.150ns (routing 0.348ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.968 1.084 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK SLICE_X57Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X57Y544 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.133 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/Q net (fo=2, routed) 0.036 1.169 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/ready_from_bitSlipCtrller_8 SLICE_X57Y544 LUT3 (Prop_E6LUT_SLICEL_I2_O) 0.015 1.184 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_i_1__43/O net (fo=1, routed) 0.012 1.196 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_i_1__43_n_0 SLICE_X57Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.150 1.302 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK SLICE_X57Y544 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg/C clock pessimism -0.214 1.088 SLICE_X57Y544 FDCE (Hold_EFF_SLICEL_C_D) 0.056 1.144 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time -1.144 arrival time 1.196 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_46 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.146ns (logic 0.094ns (64.384%) route 0.052ns (35.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.092ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 0.976ns (routing 0.301ns, distribution 0.675ns) Clock Net Delay (Destination): 1.164ns (routing 0.348ns, distribution 0.816ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.976 1.092 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X60Y553 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y553 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.141 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.037 1.178 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/O84[1] SLICE_X60Y553 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.045 1.223 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__43/O net (fo=1, routed) 0.015 1.238 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] SLICE_X60Y553 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.164 1.316 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X60Y553 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.186 1.130 SLICE_X60Y553 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.186 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.186 arrival time 1.238 ------------------------------------------------------------------- slack 0.052 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_46 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y219 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X61Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X59Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X59Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X59Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X59Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X61Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X61Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][6]/C Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][0]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][0]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][5]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][5]/C Low Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][7]/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X61Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][7]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][1]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][2]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][3]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y541 g_clock_rate_din[44].ngccm_status_cnt_reg[44][4]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X59Y541 g_clock_rate_din[44].rx_frameclk_div2_reg[44]/C High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X57Y557 SFP_GEN[44].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y36 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: gtwiz_userclk_rx_srcclk_out[0]_47 To Clock: gtwiz_userclk_rx_srcclk_out[0]_47 Setup : 0 Failing Endpoints, Worst Slack 3.239ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.510ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.239ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 4.832ns (logic 0.285ns (5.898%) route 4.547ns (94.102%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.372ns = ( 10.689 - 8.317 ) Source Clock Delay (SCD): 2.729ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.304ns (routing 0.802ns, distribution 1.502ns) Clock Net Delay (Destination): 1.996ns (routing 0.719ns, distribution 1.277ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.304 2.729 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X38Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y541 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.868 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Q net (fo=137, routed) 2.514 5.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X36Y569 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.146 5.528 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/O net (fo=76, routed) 2.033 7.561 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.996 10.689 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism 0.204 10.893 clock uncertainty -0.035 10.858 SLICE_X40Y561 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 10.800 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time 10.800 arrival time -7.561 ------------------------------------------------------------------- slack 3.239 Slack (MET) : 3.239ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 4.832ns (logic 0.285ns (5.898%) route 4.547ns (94.102%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.372ns = ( 10.689 - 8.317 ) Source Clock Delay (SCD): 2.729ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.304ns (routing 0.802ns, distribution 1.502ns) Clock Net Delay (Destination): 1.996ns (routing 0.719ns, distribution 1.277ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.304 2.729 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X38Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y541 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.868 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Q net (fo=137, routed) 2.514 5.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X36Y569 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.146 5.528 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/O net (fo=76, routed) 2.033 7.561 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.996 10.689 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C clock pessimism 0.204 10.893 clock uncertainty -0.035 10.858 SLICE_X40Y561 FDRE (Setup_GFF2_SLICEL_C_CE) -0.058 10.800 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7] ------------------------------------------------------------------- required time 10.800 arrival time -7.561 ------------------------------------------------------------------- slack 3.239 Slack (MET) : 3.245ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 4.829ns (logic 0.285ns (5.902%) route 4.544ns (94.098%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.372ns = ( 10.689 - 8.317 ) Source Clock Delay (SCD): 2.729ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.304ns (routing 0.802ns, distribution 1.502ns) Clock Net Delay (Destination): 1.996ns (routing 0.719ns, distribution 1.277ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.304 2.729 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X38Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y541 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.868 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Q net (fo=137, routed) 2.514 5.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X36Y569 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.146 5.528 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/O net (fo=76, routed) 2.030 7.558 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.996 10.689 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism 0.204 10.893 clock uncertainty -0.035 10.858 SLICE_X40Y561 FDRE (Setup_HFF_SLICEL_C_CE) -0.055 10.803 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time 10.803 arrival time -7.558 ------------------------------------------------------------------- slack 3.245 Slack (MET) : 3.245ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 4.829ns (logic 0.285ns (5.902%) route 4.544ns (94.098%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.372ns = ( 10.689 - 8.317 ) Source Clock Delay (SCD): 2.729ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.304ns (routing 0.802ns, distribution 1.502ns) Clock Net Delay (Destination): 1.996ns (routing 0.719ns, distribution 1.277ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.304 2.729 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X38Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y541 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.868 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Q net (fo=137, routed) 2.514 5.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X36Y569 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.146 5.528 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/O net (fo=76, routed) 2.030 7.558 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.996 10.689 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism 0.204 10.893 clock uncertainty -0.035 10.858 SLICE_X40Y561 FDRE (Setup_FFF_SLICEL_C_CE) -0.055 10.803 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time 10.803 arrival time -7.558 ------------------------------------------------------------------- slack 3.245 Slack (MET) : 3.245ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 4.829ns (logic 0.285ns (5.902%) route 4.544ns (94.098%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.372ns = ( 10.689 - 8.317 ) Source Clock Delay (SCD): 2.729ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.304ns (routing 0.802ns, distribution 1.502ns) Clock Net Delay (Destination): 1.996ns (routing 0.719ns, distribution 1.277ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.304 2.729 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X38Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y541 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.868 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Q net (fo=137, routed) 2.514 5.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X36Y569 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.146 5.528 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/O net (fo=76, routed) 2.030 7.558 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.996 10.689 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism 0.204 10.893 clock uncertainty -0.035 10.858 SLICE_X40Y561 FDRE (Setup_GFF_SLICEL_C_CE) -0.055 10.803 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time 10.803 arrival time -7.558 ------------------------------------------------------------------- slack 3.245 Slack (MET) : 3.247ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 4.829ns (logic 0.285ns (5.902%) route 4.544ns (94.098%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.374ns = ( 10.691 - 8.317 ) Source Clock Delay (SCD): 2.729ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.304ns (routing 0.802ns, distribution 1.502ns) Clock Net Delay (Destination): 1.998ns (routing 0.719ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.304 2.729 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X38Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y541 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.868 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Q net (fo=137, routed) 2.514 5.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X36Y569 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.146 5.528 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/O net (fo=76, routed) 2.030 7.558 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.998 10.691 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism 0.204 10.895 clock uncertainty -0.035 10.860 SLICE_X40Y561 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 10.805 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time 10.805 arrival time -7.558 ------------------------------------------------------------------- slack 3.247 Slack (MET) : 3.247ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 4.829ns (logic 0.285ns (5.902%) route 4.544ns (94.098%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.374ns = ( 10.691 - 8.317 ) Source Clock Delay (SCD): 2.729ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.304ns (routing 0.802ns, distribution 1.502ns) Clock Net Delay (Destination): 1.998ns (routing 0.719ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.304 2.729 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X38Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y541 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.868 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Q net (fo=137, routed) 2.514 5.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X36Y569 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.146 5.528 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/O net (fo=76, routed) 2.030 7.558 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.998 10.691 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism 0.204 10.895 clock uncertainty -0.035 10.860 SLICE_X40Y561 FDRE (Setup_CFF2_SLICEL_C_CE) -0.055 10.805 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time 10.805 arrival time -7.558 ------------------------------------------------------------------- slack 3.247 Slack (MET) : 3.252ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 4.825ns (logic 0.285ns (5.907%) route 4.540ns (94.093%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.374ns = ( 10.691 - 8.317 ) Source Clock Delay (SCD): 2.729ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.304ns (routing 0.802ns, distribution 1.502ns) Clock Net Delay (Destination): 1.998ns (routing 0.719ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.304 2.729 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X38Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y541 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.868 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Q net (fo=137, routed) 2.514 5.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X36Y569 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.146 5.528 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/O net (fo=76, routed) 2.026 7.554 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.998 10.691 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism 0.204 10.895 clock uncertainty -0.035 10.860 SLICE_X40Y561 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 10.806 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time 10.806 arrival time -7.554 ------------------------------------------------------------------- slack 3.252 Slack (MET) : 3.252ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 4.825ns (logic 0.285ns (5.907%) route 4.540ns (94.093%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.374ns = ( 10.691 - 8.317 ) Source Clock Delay (SCD): 2.729ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.304ns (routing 0.802ns, distribution 1.502ns) Clock Net Delay (Destination): 1.998ns (routing 0.719ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.304 2.729 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X38Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y541 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.868 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Q net (fo=137, routed) 2.514 5.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X36Y569 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.146 5.528 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/O net (fo=76, routed) 2.026 7.554 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.998 10.691 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism 0.204 10.895 clock uncertainty -0.035 10.860 SLICE_X40Y561 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 10.806 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time 10.806 arrival time -7.554 ------------------------------------------------------------------- slack 3.252 Slack (MET) : 3.252ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/CE (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 4.825ns (logic 0.285ns (5.907%) route 4.540ns (94.093%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.374ns = ( 10.691 - 8.317 ) Source Clock Delay (SCD): 2.729ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.304ns (routing 0.802ns, distribution 1.502ns) Clock Net Delay (Destination): 1.998ns (routing 0.719ns, distribution 1.279ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.304 2.729 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X38Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y541 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.868 r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/Q net (fo=137, routed) 2.514 5.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] SLICE_X36Y569 LUT2 (Prop_E6LUT_SLICEL_I1_O) 0.146 5.528 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__44/O net (fo=76, routed) 2.026 7.554 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/CE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.998 10.691 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism 0.204 10.895 clock uncertainty -0.035 10.860 SLICE_X40Y561 FDRE (Setup_BFF_SLICEL_C_CE) -0.054 10.806 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time 10.806 arrival time -7.554 ------------------------------------------------------------------- slack 3.252 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.169ns (logic 0.079ns (46.746%) route 0.090ns (53.254%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.225ns Source Clock Delay (SCD): 1.005ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.889ns (routing 0.382ns, distribution 0.507ns) Clock Net Delay (Destination): 1.073ns (routing 0.446ns, distribution 0.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.889 1.005 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X37Y572 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y572 FDCE (Prop_GFF_SLICEM_C_Q) 0.048 1.053 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.074 1.127 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_11_in SLICE_X36Y572 LUT3 (Prop_H6LUT_SLICEL_I2_O) 0.031 1.158 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__44/O net (fo=1, routed) 0.016 1.174 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] SLICE_X36Y572 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.073 1.225 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X36Y572 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C clock pessimism -0.142 1.083 SLICE_X36Y572 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.139 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4] ------------------------------------------------------------------- required time -1.139 arrival time 1.174 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.038ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[26]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[26]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.049ns (34.507%) route 0.093ns (65.493%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.230ns Source Clock Delay (SCD): 1.007ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 0.891ns (routing 0.382ns, distribution 0.509ns) Clock Net Delay (Destination): 1.078ns (routing 0.446ns, distribution 0.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.891 1.007 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X40Y568 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y568 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.056 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[26]/Q net (fo=1, routed) 0.093 1.149 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[26] SLICE_X40Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.078 1.230 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X40Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[26]/C clock pessimism -0.175 1.055 SLICE_X40Y569 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.111 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[26] ------------------------------------------------------------------- required time -1.111 arrival time 1.149 ------------------------------------------------------------------- slack 0.038 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.174ns (logic 0.080ns (45.977%) route 0.094ns (54.023%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.240ns Source Clock Delay (SCD): 1.019ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.903ns (routing 0.382ns, distribution 0.521ns) Clock Net Delay (Destination): 1.088ns (routing 0.446ns, distribution 0.642ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.903 1.019 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X34Y574 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y574 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.068 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.078 1.146 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X35Y574 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.031 1.177 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__44/O net (fo=1, routed) 0.016 1.193 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[0] SLICE_X35Y574 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.088 1.240 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X35Y574 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.142 1.098 SLICE_X35Y574 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.154 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -1.154 arrival time 1.193 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.039ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.087ns (50.289%) route 0.086ns (49.711%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.225ns Source Clock Delay (SCD): 1.005ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.889ns (routing 0.382ns, distribution 0.507ns) Clock Net Delay (Destination): 1.073ns (routing 0.446ns, distribution 0.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.889 1.005 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X37Y572 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y572 FDCE (Prop_GFF_SLICEM_C_Q) 0.048 1.053 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Q net (fo=2, routed) 0.074 1.127 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_11_in SLICE_X36Y572 LUT3 (Prop_H5LUT_SLICEL_I0_O) 0.039 1.166 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__44/O net (fo=1, routed) 0.012 1.178 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[6] SLICE_X36Y572 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.073 1.225 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X36Y572 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism -0.142 1.083 SLICE_X36Y572 FDRE (Hold_HFF2_SLICEL_C_D) 0.056 1.139 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time -1.139 arrival time 1.178 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.151ns (logic 0.064ns (42.384%) route 0.087ns (57.616%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.243ns Source Clock Delay (SCD): 1.013ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 0.897ns (routing 0.382ns, distribution 0.515ns) Clock Net Delay (Destination): 1.091ns (routing 0.446ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.897 1.013 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X35Y570 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y570 FDCE (Prop_BFF2_SLICEM_C_Q) 0.048 1.061 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Q net (fo=2, routed) 0.072 1.133 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/O84[1] SLICE_X35Y571 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.016 1.149 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__44/O net (fo=1, routed) 0.015 1.164 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] SLICE_X35Y571 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.091 1.243 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X35Y571 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C clock pessimism -0.175 1.068 SLICE_X35Y571 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.124 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20] ------------------------------------------------------------------- required time -1.124 arrival time 1.164 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].rx_data_ngccm_reg[45][42]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.156ns (logic 0.049ns (31.410%) route 0.107ns (68.590%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.245ns Source Clock Delay (SCD): 1.012ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.896ns (routing 0.382ns, distribution 0.514ns) Clock Net Delay (Destination): 1.093ns (routing 0.446ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.896 1.012 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X36Y572 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y572 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.061 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/Q net (fo=1, routed) 0.107 1.168 rx_data[45][42] SLICE_X36Y573 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][42]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.093 1.245 g_gbt_bank[3].gbtbank_n_114 SLICE_X36Y573 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][42]/C clock pessimism -0.174 1.071 SLICE_X36Y573 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.127 SFP_GEN[45].rx_data_ngccm_reg[45][42] ------------------------------------------------------------------- required time -1.127 arrival time 1.168 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.094ns (50.000%) route 0.094ns (50.000%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.239ns Source Clock Delay (SCD): 1.008ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.892ns (routing 0.382ns, distribution 0.510ns) Clock Net Delay (Destination): 1.087ns (routing 0.446ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.008 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X37Y574 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y574 FDCE (Prop_FFF_SLICEM_C_Q) 0.049 1.057 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.078 1.135 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/O85[0] SLICE_X36Y574 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.045 1.180 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__44/O net (fo=1, routed) 0.016 1.196 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] SLICE_X36Y574 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.087 1.239 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X36Y574 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C clock pessimism -0.142 1.097 SLICE_X36Y574 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.153 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19] ------------------------------------------------------------------- required time -1.153 arrival time 1.196 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.101ns (65.161%) route 0.054ns (34.839%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.245ns Source Clock Delay (SCD): 1.015ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.899ns (routing 0.382ns, distribution 0.517ns) Clock Net Delay (Destination): 1.093ns (routing 0.446ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.899 1.015 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y562 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.064 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.038 1.102 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in SLICE_X40Y561 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.052 1.154 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__44/O net (fo=1, routed) 0.016 1.170 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.093 1.245 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y561 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.174 1.071 SLICE_X40Y561 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.127 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -1.127 arrival time 1.170 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.047ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv/D (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.179ns (logic 0.093ns (51.955%) route 0.086ns (48.045%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.241ns Source Clock Delay (SCD): 1.023ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.907ns (routing 0.382ns, distribution 0.525ns) Clock Net Delay (Destination): 1.089ns (routing 0.446ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.907 1.023 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X33Y559 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X33Y559 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.071 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/Q net (fo=6, routed) 0.074 1.145 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitSlipCnt[1] SLICE_X34Y559 LUT6 (Prop_A6LUT_SLICEM_I2_O) 0.045 1.190 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_inv_i_1__45/O net (fo=1, routed) 0.012 1.202 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr3_out SLICE_X34Y559 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.089 1.241 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK SLICE_X34Y559 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv/C clock pessimism -0.142 1.099 SLICE_X34Y559 FDPE (Hold_AFF_SLICEM_C_D) 0.056 1.155 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/shiftPsAddr_reg_inv ------------------------------------------------------------------- required time -1.155 arrival time 1.202 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.048ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C (rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].rx_data_ngccm_reg[45][71]/D (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: gtwiz_userclk_rx_srcclk_out[0]_47 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.175ns (logic 0.048ns (27.429%) route 0.127ns (72.571%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.233ns Source Clock Delay (SCD): 1.020ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.904ns (routing 0.382ns, distribution 0.522ns) Clock Net Delay (Destination): 1.081ns (routing 0.446ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.904 1.020 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X35Y574 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y574 FDRE (Prop_CFF2_SLICEM_C_Q) 0.048 1.068 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/Q net (fo=1, routed) 0.127 1.195 rx_data[45][71] SLICE_X34Y574 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][71]/D ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.081 1.233 g_gbt_bank[3].gbtbank_n_114 SLICE_X34Y574 FDCE r SFP_GEN[45].rx_data_ngccm_reg[45][71]/C clock pessimism -0.142 1.091 SLICE_X34Y574 FDCE (Hold_HFF2_SLICEM_C_D) 0.056 1.147 SFP_GEN[45].rx_data_ngccm_reg[45][71] ------------------------------------------------------------------- required time -1.147 arrival time 1.195 ------------------------------------------------------------------- slack 0.048 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: gtwiz_userclk_rx_srcclk_out[0]_47 Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 3.200 8.317 5.117 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFG_GT/I n/a 1.587 8.317 6.730 BUFG_GT_X0Y239 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y541 g_clock_rate_din[45].ngccm_status_cnt_reg[45][0]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y541 g_clock_rate_din[45].ngccm_status_cnt_reg[45][1]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y541 g_clock_rate_din[45].ngccm_status_cnt_reg[45][2]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X58Y540 g_clock_rate_din[45].ngccm_status_cnt_reg[45][3]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X57Y541 g_clock_rate_din[45].ngccm_status_cnt_reg[45][4]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X58Y540 g_clock_rate_din[45].ngccm_status_cnt_reg[45][5]/C Min Period n/a FDRE/C n/a 0.550 8.317 7.767 SLICE_X58Y540 g_clock_rate_din[45].ngccm_status_cnt_reg[45][6]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y540 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y540 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C Low Pulse Width Fast FDRE/C n/a 0.275 4.159 3.884 SLICE_X40Y557 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X39Y557 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X39Y557 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C Low Pulse Width Fast FDCE/C n/a 0.275 4.159 3.884 SLICE_X39Y557 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.440 4.159 2.719 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FDRE/C n/a 0.275 4.159 3.884 SLICE_X34Y561 SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[72]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y555 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[21]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y555 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[22]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y555 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[23]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y555 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[28]/C High Pulse Width Slow FDCE/C n/a 0.275 4.159 3.884 SLICE_X40Y555 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[31]/C Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.009 0.510 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.017 0.513 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.009 0.873 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.017 1.311 GTHE3_CHANNEL_X0Y37 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: rxoutclk_out[0]_1 To Clock: rxoutclk_out[0]_1 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 1.532ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxoutclk_out[0]_1 Waveform(ns): { 0.000 1.559 } Period(ns): 3.119 Sources: { i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG_GT/I n/a 1.587 3.119 1.532 BUFG_GT_X1Y4 i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I --------------------------------------------------------------------------------------------------- From Clock: TTC_rxusrclk To Clock: TTC_rxusrclk Setup : 0 Failing Endpoints, Worst Slack 0.154ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.031ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.407ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.154ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[13]/R (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.914ns (logic 0.140ns (4.804%) route 2.774ns (95.196%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.661ns = ( 6.780 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.661ns (routing 1.487ns, distribution 2.174ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.774 6.783 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/reset_i SLICE_X130Y88 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[13]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.661 6.780 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out SLICE_X130Y88 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[13]/C clock pessimism 0.288 7.068 clock uncertainty -0.035 7.033 SLICE_X130Y88 FDRE (Setup_DFF_SLICEL_C_R) -0.096 6.937 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[13] ------------------------------------------------------------------- required time 6.937 arrival time -6.783 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.154ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[14]/R (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.914ns (logic 0.140ns (4.804%) route 2.774ns (95.196%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.661ns = ( 6.780 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.661ns (routing 1.487ns, distribution 2.174ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.774 6.783 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/reset_i SLICE_X130Y88 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[14]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.661 6.780 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out SLICE_X130Y88 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[14]/C clock pessimism 0.288 7.068 clock uncertainty -0.035 7.033 SLICE_X130Y88 FDRE (Setup_CFF_SLICEL_C_R) -0.096 6.937 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[14] ------------------------------------------------------------------- required time 6.937 arrival time -6.783 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.154ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[33]/R (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.914ns (logic 0.140ns (4.804%) route 2.774ns (95.196%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.661ns = ( 6.780 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.661ns (routing 1.487ns, distribution 2.174ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.774 6.783 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/reset_i SLICE_X130Y88 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[33]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.661 6.780 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out SLICE_X130Y88 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[33]/C clock pessimism 0.288 7.068 clock uncertainty -0.035 7.033 SLICE_X130Y88 FDRE (Setup_BFF_SLICEL_C_R) -0.096 6.937 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[33] ------------------------------------------------------------------- required time 6.937 arrival time -6.783 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.154ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[52]/R (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.914ns (logic 0.140ns (4.804%) route 2.774ns (95.196%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.661ns = ( 6.780 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.661ns (routing 1.487ns, distribution 2.174ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.774 6.783 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/reset_i SLICE_X130Y88 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[52]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.661 6.780 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out SLICE_X130Y88 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[52]/C clock pessimism 0.288 7.068 clock uncertainty -0.035 7.033 SLICE_X130Y88 FDRE (Setup_AFF_SLICEL_C_R) -0.096 6.937 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[52] ------------------------------------------------------------------- required time 6.937 arrival time -6.783 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.154ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[1]/R (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.912ns (logic 0.140ns (4.808%) route 2.772ns (95.192%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.659ns = ( 6.778 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.659ns (routing 1.487ns, distribution 2.172ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.772 6.781 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/reset_i SLICE_X130Y89 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[1]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.659 6.778 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/rxusrclk_out SLICE_X130Y89 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[1]/C clock pessimism 0.288 7.066 clock uncertainty -0.035 7.031 SLICE_X130Y89 FDRE (Setup_DFF_SLICEL_C_R) -0.096 6.935 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[1] ------------------------------------------------------------------- required time 6.935 arrival time -6.781 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.154ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[20]/R (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.912ns (logic 0.140ns (4.808%) route 2.772ns (95.192%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.659ns = ( 6.778 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.659ns (routing 1.487ns, distribution 2.172ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.772 6.781 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/reset_i SLICE_X130Y89 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[20]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.659 6.778 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/rxusrclk_out SLICE_X130Y89 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[20]/C clock pessimism 0.288 7.066 clock uncertainty -0.035 7.031 SLICE_X130Y89 FDRE (Setup_CFF_SLICEL_C_R) -0.096 6.935 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[20] ------------------------------------------------------------------- required time 6.935 arrival time -6.781 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.154ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[39]/R (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.912ns (logic 0.140ns (4.808%) route 2.772ns (95.192%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.659ns = ( 6.778 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.659ns (routing 1.487ns, distribution 2.172ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.772 6.781 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/reset_i SLICE_X130Y89 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[39]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.659 6.778 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/rxusrclk_out SLICE_X130Y89 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[39]/C clock pessimism 0.288 7.066 clock uncertainty -0.035 7.031 SLICE_X130Y89 FDRE (Setup_BFF_SLICEL_C_R) -0.096 6.935 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[39] ------------------------------------------------------------------- required time 6.935 arrival time -6.781 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.162ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[22]/R (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.899ns (logic 0.140ns (4.829%) route 2.759ns (95.171%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.653ns = ( 6.772 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.653ns (routing 1.487ns, distribution 2.166ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.759 6.768 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/reset_i SLICE_X129Y78 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[22]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.653 6.772 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out SLICE_X129Y78 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[22]/C clock pessimism 0.289 7.061 clock uncertainty -0.035 7.025 SLICE_X129Y78 FDRE (Setup_EFF_SLICEL_C_R) -0.095 6.930 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[22] ------------------------------------------------------------------- required time 6.930 arrival time -6.768 ------------------------------------------------------------------- slack 0.162 Slack (MET) : 0.162ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[41]/R (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.899ns (logic 0.140ns (4.829%) route 2.759ns (95.171%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.653ns = ( 6.772 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.653ns (routing 1.487ns, distribution 2.166ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.759 6.768 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/reset_i SLICE_X129Y78 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[41]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.653 6.772 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out SLICE_X129Y78 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[41]/C clock pessimism 0.289 7.061 clock uncertainty -0.035 7.025 SLICE_X129Y78 FDRE (Setup_EFF2_SLICEL_C_R) -0.095 6.930 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[41] ------------------------------------------------------------------- required time 6.930 arrival time -6.768 ------------------------------------------------------------------- slack 0.162 Slack (MET) : 0.162ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[51]/R (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Setup (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.899ns (logic 0.140ns (4.829%) route 2.759ns (95.171%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.653ns = ( 6.772 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.289ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.653ns (routing 1.487ns, distribution 2.166ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 f i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.759 6.768 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/reset_i SLICE_X129Y78 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[51]/R (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.653 6.772 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out SLICE_X129Y78 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[51]/C clock pessimism 0.289 7.061 clock uncertainty -0.035 7.025 SLICE_X129Y78 FDRE (Setup_FFF_SLICEL_C_R) -0.095 6.930 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[51] ------------------------------------------------------------------- required time 6.930 arrival time -6.768 ------------------------------------------------------------------- slack 0.162 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.031ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[19]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[19]/D (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.145ns (logic 0.049ns (33.793%) route 0.096ns (66.207%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.833ns Source Clock Delay (SCD): 1.602ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 1.602ns (routing 0.696ns, distribution 0.906ns) Clock Net Delay (Destination): 1.833ns (routing 0.779ns, distribution 1.054ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.602 1.602 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X139Y89 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y89 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.651 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[19]/Q net (fo=1, routed) 0.096 1.747 i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[19] SLICE_X140Y89 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[19]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.833 1.833 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X140Y89 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[19]/C clock pessimism -0.172 1.661 SLICE_X140Y89 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.716 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[19] ------------------------------------------------------------------- required time -1.716 arrival time 1.747 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.034ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[205]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[205]/D (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.174ns (logic 0.049ns (28.161%) route 0.125ns (71.839%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.858ns Source Clock Delay (SCD): 1.602ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.602ns (routing 0.696ns, distribution 0.906ns) Clock Net Delay (Destination): 1.858ns (routing 0.779ns, distribution 1.079ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.602 1.602 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X138Y91 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[205]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y91 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.651 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[205]/Q net (fo=1, routed) 0.125 1.776 i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[205] SLICE_X137Y91 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[205]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.858 1.858 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X137Y91 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[205]/C clock pessimism -0.171 1.687 SLICE_X137Y91 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.742 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[205] ------------------------------------------------------------------- required time -1.742 arrival time 1.776 ------------------------------------------------------------------- slack 0.034 Slack (MET) : 0.041ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[220]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[220]/D (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.865ns Source Clock Delay (SCD): 1.613ns Clock Pessimism Removal (CPR): 0.205ns Clock Net Delay (Source): 1.613ns (routing 0.696ns, distribution 0.917ns) Clock Net Delay (Destination): 1.865ns (routing 0.779ns, distribution 1.086ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.613 1.613 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X131Y68 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[220]/C ------------------------------------------------------------------- ------------------- SLICE_X131Y68 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.661 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[220]/Q net (fo=1, routed) 0.095 1.756 i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[220] SLICE_X131Y70 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[220]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.865 1.865 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X131Y70 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[220]/C clock pessimism -0.205 1.660 SLICE_X131Y70 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.715 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[220] ------------------------------------------------------------------- required time -1.715 arrival time 1.756 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[240]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[240]/D (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.144ns (logic 0.049ns (34.028%) route 0.095ns (65.972%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.863ns Source Clock Delay (SCD): 1.610ns Clock Pessimism Removal (CPR): 0.205ns Clock Net Delay (Source): 1.610ns (routing 0.696ns, distribution 0.914ns) Clock Net Delay (Destination): 1.863ns (routing 0.779ns, distribution 1.084ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.610 1.610 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X132Y77 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[240]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y77 FDCE (Prop_AFF2_SLICEL_C_Q) 0.049 1.659 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[240]/Q net (fo=1, routed) 0.095 1.754 i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[240] SLICE_X132Y78 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[240]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.863 1.863 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X132Y78 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[240]/C clock pessimism -0.205 1.658 SLICE_X132Y78 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.713 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[240] ------------------------------------------------------------------- required time -1.713 arrival time 1.754 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.043ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[215]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[212]/D (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@6.238ns - TTC_rxusrclk rise@6.238ns) Data Path Delay: 0.188ns (logic 0.063ns (33.511%) route 0.125ns (66.489%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.866ns Source Clock Delay (SCD): 1.606ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.606ns (routing 0.696ns, distribution 0.910ns) Clock Net Delay (Destination): 1.866ns (routing 0.779ns, distribution 1.087ns) Timing Exception: MultiCycle Path Setup -end 3 Hold -start 2 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 6.238 6.238 r BUFG_GT_X1Y4 BUFG_GT 0.000 6.238 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.606 7.844 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X138Y96 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[215]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y96 FDCE (Prop_CFF2_SLICEL_C_Q) 0.048 7.892 r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[215]/Q net (fo=11, routed) 0.113 8.005 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/Q[215] SLICE_X137Y94 LUT6 (Prop_A6LUT_SLICEL_I5_O) 0.015 8.020 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o[212]_i_1/O net (fo=1, routed) 0.012 8.032 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o[212]_i_1_n_0 SLICE_X137Y94 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[212]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 6.238 6.238 r BUFG_GT_X1Y4 BUFG_GT 0.000 6.238 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.866 8.104 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/rxusrclk_out SLICE_X137Y94 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[212]/C clock pessimism -0.171 7.933 SLICE_X137Y94 FDRE (Hold_AFF_SLICEL_C_D) 0.056 7.989 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[212] ------------------------------------------------------------------- required time -7.989 arrival time 8.032 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.043ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[54]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[19]/D (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@6.238ns - TTC_rxusrclk rise@6.238ns) Data Path Delay: 0.194ns (logic 0.064ns (32.990%) route 0.130ns (67.010%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.095ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.866ns Source Clock Delay (SCD): 1.600ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.600ns (routing 0.696ns, distribution 0.904ns) Clock Net Delay (Destination): 1.866ns (routing 0.779ns, distribution 1.087ns) Timing Exception: MultiCycle Path Setup -end 3 Hold -start 2 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 6.238 6.238 r BUFG_GT_X1Y4 BUFG_GT 0.000 6.238 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.600 7.838 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X130Y70 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[54]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y70 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 7.887 r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[54]/Q net (fo=11, routed) 0.114 8.001 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/Q[54] SLICE_X131Y72 LUT6 (Prop_C6LUT_SLICEL_I5_O) 0.015 8.016 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o[19]_i_1/O net (fo=1, routed) 0.016 8.032 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o[19]_i_1_n_0 SLICE_X131Y72 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[19]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 6.238 6.238 r BUFG_GT_X1Y4 BUFG_GT 0.000 6.238 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.866 8.104 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/rxusrclk_out SLICE_X131Y72 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[19]/C clock pessimism -0.171 7.933 SLICE_X131Y72 FDRE (Hold_CFF_SLICEL_C_D) 0.056 7.989 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[19] ------------------------------------------------------------------- required time -7.989 arrival time 8.032 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.044ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/memory_register_reg[41]/C (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[22]/D (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.193ns (logic 0.101ns (52.332%) route 0.092ns (47.668%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.858ns Source Clock Delay (SCD): 1.593ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 1.593ns (routing 0.696ns, distribution 0.897ns) Clock Net Delay (Destination): 1.858ns (routing 0.779ns, distribution 1.079ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.593 1.593 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out SLICE_X133Y88 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/memory_register_reg[41]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y88 FDRE (Prop_EFF2_SLICEL_C_Q) 0.048 1.641 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/memory_register_reg[41]/Q net (fo=2, routed) 0.076 1.717 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/memory_register[41] SLICE_X134Y88 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.053 1.770 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData[22]_i_1/O net (fo=1, routed) 0.016 1.786 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/p_0_out[22] SLICE_X134Y88 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[22]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.858 1.858 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out SLICE_X134Y88 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[22]/C clock pessimism -0.172 1.686 SLICE_X134Y88 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.742 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[22] ------------------------------------------------------------------- required time -1.742 arrival time 1.786 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/FSM_sequential_gen_gtwiz_buffbypass_rx_main.gen_auto_mode.sm_buffbypass_rx_reg[1]/C (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.gtwiz_buffbypass_rx_done_out_reg/D (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.158ns (logic 0.048ns (30.380%) route 0.110ns (69.620%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.882ns Source Clock Delay (SCD): 1.621ns Clock Pessimism Removal (CPR): 0.203ns Clock Net Delay (Source): 1.621ns (routing 0.696ns, distribution 0.925ns) Clock Net Delay (Destination): 1.882ns (routing 0.779ns, distribution 1.103ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.621 1.621 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/rxusrclk2_in[0] SLICE_X132Y54 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/FSM_sequential_gen_gtwiz_buffbypass_rx_main.gen_auto_mode.sm_buffbypass_rx_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y54 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.669 r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/FSM_sequential_gen_gtwiz_buffbypass_rx_main.gen_auto_mode.sm_buffbypass_rx_reg[1]/Q net (fo=6, routed) 0.110 1.779 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/FSM_sequential_gen_gtwiz_buffbypass_rx_main.gen_auto_mode.sm_buffbypass_rx_reg_n_0_[1] SLICE_X132Y55 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.gtwiz_buffbypass_rx_done_out_reg/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.882 1.882 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/rxusrclk2_in[0] SLICE_X132Y55 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.gtwiz_buffbypass_rx_done_out_reg/C clock pessimism -0.203 1.679 SLICE_X132Y55 FDRE (Hold_HFF_SLICEL_C_D) 0.056 1.735 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.gtwiz_buffbypass_rx_done_out_reg ------------------------------------------------------------------- required time -1.735 arrival time 1.779 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.044ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[64]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[24]/D (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@6.238ns - TTC_rxusrclk rise@6.238ns) Data Path Delay: 0.195ns (logic 0.064ns (32.821%) route 0.131ns (67.179%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.095ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.867ns Source Clock Delay (SCD): 1.601ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.601ns (routing 0.696ns, distribution 0.905ns) Clock Net Delay (Destination): 1.867ns (routing 0.779ns, distribution 1.088ns) Timing Exception: MultiCycle Path Setup -end 3 Hold -start 2 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 6.238 6.238 r BUFG_GT_X1Y4 BUFG_GT 0.000 6.238 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.601 7.839 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X130Y71 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[64]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y71 FDCE (Prop_FFF_SLICEL_C_Q) 0.049 7.888 r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[64]/Q net (fo=11, routed) 0.115 8.003 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/Q[64] SLICE_X132Y73 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.015 8.018 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o[24]_i_1/O net (fo=1, routed) 0.016 8.034 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o[24]_i_1_n_0 SLICE_X132Y73 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[24]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 6.238 6.238 r BUFG_GT_X1Y4 BUFG_GT 0.000 6.238 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.867 8.105 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/rxusrclk_out SLICE_X132Y73 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[24]/C clock pessimism -0.171 7.934 SLICE_X132Y73 FDRE (Hold_HFF_SLICEL_C_D) 0.056 7.990 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[24] ------------------------------------------------------------------- required time -7.990 arrival time 8.034 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.045ns (arrival time - required time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[92]/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[92]/D (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: TTC_rxusrclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.191ns (logic 0.049ns (25.654%) route 0.142ns (74.346%)) Logic Levels: 0 Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.863ns Source Clock Delay (SCD): 1.602ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.602ns (routing 0.696ns, distribution 0.906ns) Clock Net Delay (Destination): 1.863ns (routing 0.779ns, distribution 1.084ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.602 1.602 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X130Y73 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[92]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y73 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.651 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[92]/Q net (fo=1, routed) 0.142 1.793 i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[92] SLICE_X131Y73 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[92]/D ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.863 1.863 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X131Y73 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[92]/C clock pessimism -0.171 1.692 SLICE_X131Y73 FDCE (Hold_EFF_SLICEL_C_D) 0.056 1.748 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[92] ------------------------------------------------------------------- required time -1.748 arrival time 1.793 ------------------------------------------------------------------- slack 0.045 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: TTC_rxusrclk Waveform(ns): { 0.000 1.559 } Period(ns): 3.119 Sources: { i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 2.560 3.119 0.559 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 2.560 3.119 0.559 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a BUFGCE_DIV/I n/a 1.250 3.119 1.869 BUFGCE_DIV_X1Y16 i_tcds2_if/bufgce_clk_40_rx/I Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X99Y111 i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X130Y70 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[0]/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X135Y76 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[100]/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X133Y78 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[101]/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X134Y78 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[102]/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X135Y78 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[103]/C Min Period n/a FDCE/C n/a 0.550 3.119 2.569 SLICE_X131Y71 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[104]/C Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X130Y70 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[0]/C Low Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X134Y78 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[102]/C Low Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y85 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[106]/C Low Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y85 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[106]/C Low Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X134Y71 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[10]/C Low Pulse Width Slow FDCE/C n/a 0.275 1.559 1.284 SLICE_X132Y75 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[110]/C High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.152 1.559 0.407 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.152 1.560 0.408 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X130Y70 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[0]/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X135Y76 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[100]/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X132Y75 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[110]/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X139Y93 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[117]/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X132Y86 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[118]/C High Pulse Width Fast FDCE/C n/a 0.275 1.559 1.284 SLICE_X136Y71 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[120]/C Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.045 0.485 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.021 0.498 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.021 0.861 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.045 1.283 GTHE3_CHANNEL_X1Y3 i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: fabric_clk_in To Clock: fabric_clk_in Setup : 0 Failing Endpoints, Worst Slack 20.969ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.046ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 6.238ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 20.969ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/CE (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 3.701ns (logic 1.432ns (38.692%) route 2.269ns (61.308%)) Logic Levels: 11 (CARRY8=9 LUT5=1 LUT6=1) Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.438ns = ( 31.390 - 24.952 ) Source Clock Delay (SCD): 7.259ns Clock Pessimism Removal (CPR): 0.633ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.784ns (routing 1.326ns, distribution 2.458ns) Clock Net Delay (Destination): 3.342ns (routing 1.221ns, distribution 2.121ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.130 3.130 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.475 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.784 7.259 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X128Y84 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X128Y84 FDRE (Prop_HFF2_SLICEL_C_Q) 0.137 7.396 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/Q net (fo=1, routed) 1.111 8.507 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg_n_0_[26] SLICE_X126Y81 LUT6 (Prop_A6LUT_SLICEM_I3_O) 0.243 8.750 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85/O net (fo=1, routed) 0.000 8.750 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85_n_0 SLICE_X126Y81 CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7]) 0.502 9.252 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68/CO[7] net (fo=1, routed) 0.030 9.282 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68_n_0 SLICE_X126Y82 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.310 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CO[7] net (fo=1, routed) 0.030 9.340 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_n_0 SLICE_X126Y83 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.368 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CO[7] net (fo=1, routed) 0.030 9.398 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50_n_0 SLICE_X126Y84 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.426 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CO[7] net (fo=1, routed) 0.030 9.456 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41_n_0 SLICE_X126Y85 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.484 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CO[7] net (fo=1, routed) 0.030 9.514 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32_n_0 SLICE_X126Y86 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.542 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CO[7] net (fo=1, routed) 0.030 9.572 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23_n_0 SLICE_X126Y87 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.600 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CO[7] net (fo=1, routed) 0.030 9.630 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14_n_0 SLICE_X126Y88 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.658 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CO[7] net (fo=1, routed) 0.030 9.688 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7_n_0 SLICE_X126Y89 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[5]) 0.136 9.824 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CO[5] net (fo=3, routed) 0.579 10.403 i_tcds2_if/prbs_checker/cmp_prbs_gen/CO[0] SLICE_X122Y77 LUT5 (Prop_G6LUT_SLICEL_I1_O) 0.218 10.621 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_2/O net (fo=2, routed) 0.339 10.960 i_tcds2_if/prbs_checker/prbs_lock_state SLICE_X123Y77 FDRE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y4 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.836 27.788 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.048 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.342 31.390 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X123Y77 FDRE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/C clock pessimism 0.633 32.023 clock uncertainty -0.035 31.987 SLICE_X123Y77 FDRE (Setup_HFF2_SLICEL_C_CE) -0.058 31.929 i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0] ------------------------------------------------------------------- required time 31.929 arrival time -10.960 ------------------------------------------------------------------- slack 20.969 Slack (MET) : 20.969ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/CE (rising edge-triggered cell FDSE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 3.701ns (logic 1.432ns (38.692%) route 2.269ns (61.308%)) Logic Levels: 11 (CARRY8=9 LUT5=1 LUT6=1) Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.438ns = ( 31.390 - 24.952 ) Source Clock Delay (SCD): 7.259ns Clock Pessimism Removal (CPR): 0.633ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.784ns (routing 1.326ns, distribution 2.458ns) Clock Net Delay (Destination): 3.342ns (routing 1.221ns, distribution 2.121ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.130 3.130 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.475 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.784 7.259 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X128Y84 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X128Y84 FDRE (Prop_HFF2_SLICEL_C_Q) 0.137 7.396 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/Q net (fo=1, routed) 1.111 8.507 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg_n_0_[26] SLICE_X126Y81 LUT6 (Prop_A6LUT_SLICEM_I3_O) 0.243 8.750 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85/O net (fo=1, routed) 0.000 8.750 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85_n_0 SLICE_X126Y81 CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7]) 0.502 9.252 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68/CO[7] net (fo=1, routed) 0.030 9.282 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68_n_0 SLICE_X126Y82 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.310 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CO[7] net (fo=1, routed) 0.030 9.340 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_n_0 SLICE_X126Y83 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.368 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CO[7] net (fo=1, routed) 0.030 9.398 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50_n_0 SLICE_X126Y84 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.426 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CO[7] net (fo=1, routed) 0.030 9.456 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41_n_0 SLICE_X126Y85 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.484 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CO[7] net (fo=1, routed) 0.030 9.514 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32_n_0 SLICE_X126Y86 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.542 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CO[7] net (fo=1, routed) 0.030 9.572 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23_n_0 SLICE_X126Y87 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.600 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CO[7] net (fo=1, routed) 0.030 9.630 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14_n_0 SLICE_X126Y88 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.658 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CO[7] net (fo=1, routed) 0.030 9.688 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7_n_0 SLICE_X126Y89 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[5]) 0.136 9.824 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CO[5] net (fo=3, routed) 0.579 10.403 i_tcds2_if/prbs_checker/cmp_prbs_gen/CO[0] SLICE_X122Y77 LUT5 (Prop_G6LUT_SLICEL_I1_O) 0.218 10.621 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_2/O net (fo=2, routed) 0.339 10.960 i_tcds2_if/prbs_checker/prbs_lock_state SLICE_X123Y77 FDSE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y4 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.836 27.788 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.048 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.342 31.390 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X123Y77 FDSE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/C clock pessimism 0.633 32.023 clock uncertainty -0.035 31.987 SLICE_X123Y77 FDSE (Setup_GFF2_SLICEL_C_CE) -0.058 31.929 i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1] ------------------------------------------------------------------- required time 31.929 arrival time -10.960 ------------------------------------------------------------------- slack 20.969 Slack (MET) : 21.086ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/D (rising edge-triggered cell FDSE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 3.707ns (logic 1.477ns (39.844%) route 2.230ns (60.156%)) Logic Levels: 11 (CARRY8=9 LUT4=1 LUT6=1) Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.438ns = ( 31.390 - 24.952 ) Source Clock Delay (SCD): 7.259ns Clock Pessimism Removal (CPR): 0.633ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.784ns (routing 1.326ns, distribution 2.458ns) Clock Net Delay (Destination): 3.342ns (routing 1.221ns, distribution 2.121ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.130 3.130 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.475 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.784 7.259 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X128Y84 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X128Y84 FDRE (Prop_HFF2_SLICEL_C_Q) 0.137 7.396 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/Q net (fo=1, routed) 1.111 8.507 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg_n_0_[26] SLICE_X126Y81 LUT6 (Prop_A6LUT_SLICEM_I3_O) 0.243 8.750 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85/O net (fo=1, routed) 0.000 8.750 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85_n_0 SLICE_X126Y81 CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7]) 0.502 9.252 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68/CO[7] net (fo=1, routed) 0.030 9.282 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68_n_0 SLICE_X126Y82 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.310 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CO[7] net (fo=1, routed) 0.030 9.340 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_n_0 SLICE_X126Y83 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.368 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CO[7] net (fo=1, routed) 0.030 9.398 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50_n_0 SLICE_X126Y84 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.426 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CO[7] net (fo=1, routed) 0.030 9.456 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41_n_0 SLICE_X126Y85 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.484 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CO[7] net (fo=1, routed) 0.030 9.514 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32_n_0 SLICE_X126Y86 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.542 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CO[7] net (fo=1, routed) 0.030 9.572 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23_n_0 SLICE_X126Y87 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.600 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CO[7] net (fo=1, routed) 0.030 9.630 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14_n_0 SLICE_X126Y88 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.658 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CO[7] net (fo=1, routed) 0.030 9.688 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7_n_0 SLICE_X126Y89 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[5]) 0.136 9.824 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CO[5] net (fo=3, routed) 0.831 10.655 i_tcds2_if/prbs_checker/error SLICE_X123Y77 LUT4 (Prop_G5LUT_SLICEL_I2_O) 0.263 10.918 r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state[1]_i_3/O net (fo=1, routed) 0.048 10.966 i_tcds2_if/prbs_checker/prbs_lock_state__1[1] SLICE_X123Y77 FDSE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y4 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.836 27.788 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.048 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.342 31.390 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X123Y77 FDSE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/C clock pessimism 0.633 32.023 clock uncertainty -0.035 31.987 SLICE_X123Y77 FDSE (Setup_GFF2_SLICEL_C_D) 0.065 32.052 i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1] ------------------------------------------------------------------- required time 32.052 arrival time -10.966 ------------------------------------------------------------------- slack 21.086 Slack (MET) : 21.087ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 3.705ns (logic 1.475ns (39.811%) route 2.230ns (60.189%)) Logic Levels: 11 (CARRY8=9 LUT4=1 LUT6=1) Clock Path Skew: -0.188ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.438ns = ( 31.390 - 24.952 ) Source Clock Delay (SCD): 7.259ns Clock Pessimism Removal (CPR): 0.633ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.784ns (routing 1.326ns, distribution 2.458ns) Clock Net Delay (Destination): 3.342ns (routing 1.221ns, distribution 2.121ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.130 3.130 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.475 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.784 7.259 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X128Y84 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X128Y84 FDRE (Prop_HFF2_SLICEL_C_Q) 0.137 7.396 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[26]/Q net (fo=1, routed) 1.111 8.507 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg_n_0_[26] SLICE_X126Y81 LUT6 (Prop_A6LUT_SLICEM_I3_O) 0.243 8.750 r i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85/O net (fo=1, routed) 0.000 8.750 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_85_n_0 SLICE_X126Y81 CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7]) 0.502 9.252 f i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68/CO[7] net (fo=1, routed) 0.030 9.282 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_68_n_0 SLICE_X126Y82 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.310 f i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CO[7] net (fo=1, routed) 0.030 9.340 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_n_0 SLICE_X126Y83 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.368 f i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CO[7] net (fo=1, routed) 0.030 9.398 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50_n_0 SLICE_X126Y84 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.426 f i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CO[7] net (fo=1, routed) 0.030 9.456 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41_n_0 SLICE_X126Y85 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.484 f i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CO[7] net (fo=1, routed) 0.030 9.514 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32_n_0 SLICE_X126Y86 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.542 f i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CO[7] net (fo=1, routed) 0.030 9.572 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23_n_0 SLICE_X126Y87 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.600 f i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CO[7] net (fo=1, routed) 0.030 9.630 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14_n_0 SLICE_X126Y88 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7]) 0.028 9.658 f i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CO[7] net (fo=1, routed) 0.030 9.688 i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7_n_0 SLICE_X126Y89 CARRY8 (Prop_CARRY8_SLICEM_CI_CO[5]) 0.136 9.824 f i_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CO[5] net (fo=3, routed) 0.833 10.657 i_tcds2_if/prbs_checker/error SLICE_X123Y77 LUT4 (Prop_H5LUT_SLICEL_I1_O) 0.261 10.918 r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state[0]_i_1/O net (fo=1, routed) 0.046 10.964 i_tcds2_if/prbs_checker/prbs_lock_state__1[0] SLICE_X123Y77 FDRE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y4 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.836 27.788 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.048 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.342 31.390 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X123Y77 FDRE r i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/C clock pessimism 0.633 32.023 clock uncertainty -0.035 31.987 SLICE_X123Y77 FDRE (Setup_HFF2_SLICEL_C_D) 0.064 32.051 i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0] ------------------------------------------------------------------- required time 32.051 arrival time -10.964 ------------------------------------------------------------------- slack 21.087 Slack (MET) : 21.371ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[6]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[129]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 3.400ns (logic 0.849ns (24.971%) route 2.551ns (75.029%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.207ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.423ns = ( 31.375 - 24.952 ) Source Clock Delay (SCD): 7.263ns Clock Pessimism Removal (CPR): 0.633ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.788ns (routing 1.326ns, distribution 2.462ns) Clock Net Delay (Destination): 3.327ns (routing 1.221ns, distribution 2.106ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.130 3.130 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.475 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.788 7.263 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X128Y83 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X128Y83 FDRE (Prop_CFF_SLICEL_C_Q) 0.138 7.401 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[6]/Q net (fo=53, routed) 1.357 8.758 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[5] SLICE_X124Y87 LUT4 (Prop_F5LUT_SLICEL_I0_O) 0.274 9.032 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_3/O net (fo=18, routed) 0.816 9.848 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_3_n_0 SLICE_X122Y84 LUT5 (Prop_A6LUT_SLICEL_I0_O) 0.218 10.066 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[129]_i_2__0/O net (fo=1, routed) 0.345 10.411 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[129]_i_2__0_n_0 SLICE_X122Y84 LUT6 (Prop_B6LUT_SLICEL_I5_O) 0.219 10.630 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[129]_i_1__0/O net (fo=1, routed) 0.033 10.663 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[115]_4[14] SLICE_X122Y84 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[129]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y4 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.836 27.788 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.048 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.327 31.375 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X122Y84 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[129]/C clock pessimism 0.633 32.008 clock uncertainty -0.035 31.972 SLICE_X122Y84 FDRE (Setup_BFF_SLICEL_C_D) 0.062 32.034 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[129] ------------------------------------------------------------------- required time 32.034 arrival time -10.663 ------------------------------------------------------------------- slack 21.371 Slack (MET) : 21.455ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[7]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[0]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 3.365ns (logic 0.838ns (24.903%) route 2.527ns (75.097%)) Logic Levels: 3 (LUT3=1 LUT6=2) Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.477ns = ( 31.429 - 24.952 ) Source Clock Delay (SCD): 7.269ns Clock Pessimism Removal (CPR): 0.632ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.794ns (routing 1.326ns, distribution 2.468ns) Clock Net Delay (Destination): 3.381ns (routing 1.221ns, distribution 2.160ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.130 3.130 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.475 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.794 7.269 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X127Y78 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y78 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 7.409 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[7]/Q net (fo=50, routed) 1.300 8.709 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[6] SLICE_X124Y84 LUT3 (Prop_G6LUT_SLICEL_I1_O) 0.239 8.948 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[221]_i_4/O net (fo=9, routed) 0.846 9.794 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[221]_i_4_n_0 SLICE_X129Y84 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.221 10.015 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff[0]_i_2__0/O net (fo=1, routed) 0.346 10.361 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[229]__0[5] SLICE_X128Y81 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.238 10.599 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff[0]_i_1__0/O net (fo=1, routed) 0.035 10.634 i_tcds2_if/prbs_checker/cmp_prbs_gen/p_1_in[0] SLICE_X128Y81 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[0]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y4 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.836 27.788 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.048 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.381 31.429 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X128Y81 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[0]/C clock pessimism 0.632 32.061 clock uncertainty -0.035 32.026 SLICE_X128Y81 FDRE (Setup_HFF_SLICEL_C_D) 0.063 32.089 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[0] ------------------------------------------------------------------- required time 32.089 arrival time -10.634 ------------------------------------------------------------------- slack 21.455 Slack (MET) : 21.463ns (required time - arrival time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[18]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[190]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 3.323ns (logic 0.575ns (17.304%) route 2.748ns (82.696%)) Logic Levels: 2 (LUT5=2) Clock Path Skew: -0.194ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.442ns = ( 31.394 - 24.952 ) Source Clock Delay (SCD): 7.269ns Clock Pessimism Removal (CPR): 0.633ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.794ns (routing 1.326ns, distribution 2.468ns) Clock Net Delay (Destination): 3.346ns (routing 1.221ns, distribution 2.125ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.130 3.130 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.475 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.794 7.269 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X127Y78 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y78 FDRE (Prop_CFF_SLICEL_C_Q) 0.138 7.407 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[18]/Q net (fo=59, routed) 1.768 9.175 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[17] SLICE_X122Y87 LUT5 (Prop_A6LUT_SLICEL_I0_O) 0.218 9.393 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[190]_i_2__0/O net (fo=4, routed) 0.516 9.909 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[190]_i_2__0_n_0 SLICE_X123Y87 LUT5 (Prop_B6LUT_SLICEL_I3_O) 0.219 10.128 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[190]_i_1__0/O net (fo=1, routed) 0.464 10.592 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[172]_8[18] SLICE_X123Y87 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[190]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y4 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.836 27.788 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.048 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.346 31.394 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X123Y87 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[190]/C clock pessimism 0.633 32.027 clock uncertainty -0.035 31.991 SLICE_X123Y87 FDRE (Setup_EFF_SLICEL_C_D) 0.064 32.055 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[190] ------------------------------------------------------------------- required time 32.055 arrival time -10.592 ------------------------------------------------------------------- slack 21.463 Slack (MET) : 21.484ns (required time - arrival time) Source: i_tcds2_if/prbs_rst_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_chk_unlock_cnt/count_reg[28]/R (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 3.120ns (logic 0.193ns (6.186%) route 2.927ns (93.814%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.429ns = ( 31.381 - 24.952 ) Source Clock Delay (SCD): 7.278ns Clock Pessimism Removal (CPR): 0.633ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.803ns (routing 1.326ns, distribution 2.477ns) Clock Net Delay (Destination): 3.333ns (routing 1.221ns, distribution 2.112ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.130 3.130 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.475 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.803 7.278 i_tcds2_if/fabric_clk_in SLICE_X130Y70 FDPE r i_tcds2_if/prbs_rst_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y70 FDPE (Prop_FFF2_SLICEL_C_Q) 0.138 7.416 r i_tcds2_if/prbs_rst_reg[3]/Q net (fo=1, routed) 0.668 8.084 ctrl_regs_inst/count_reg[0][0] SLICE_X126Y74 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.055 8.139 r ctrl_regs_inst/FSM_sequential_prbs_lock_state[1]_i_1/O net (fo=293, routed) 2.259 10.398 i_tcds2_if/prbs_chk_unlock_cnt/prbschk_reset SLICE_X122Y94 FDRE r i_tcds2_if/prbs_chk_unlock_cnt/count_reg[28]/R ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y4 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.836 27.788 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.048 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.333 31.381 i_tcds2_if/prbs_chk_unlock_cnt/CLK SLICE_X122Y94 FDRE r i_tcds2_if/prbs_chk_unlock_cnt/count_reg[28]/C clock pessimism 0.633 32.014 clock uncertainty -0.035 31.978 SLICE_X122Y94 FDRE (Setup_DFF_SLICEL_C_R) -0.096 31.882 i_tcds2_if/prbs_chk_unlock_cnt/count_reg[28] ------------------------------------------------------------------- required time 31.882 arrival time -10.398 ------------------------------------------------------------------- slack 21.484 Slack (MET) : 21.484ns (required time - arrival time) Source: i_tcds2_if/prbs_rst_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_chk_unlock_cnt/count_reg[29]/R (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 3.120ns (logic 0.193ns (6.186%) route 2.927ns (93.814%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.429ns = ( 31.381 - 24.952 ) Source Clock Delay (SCD): 7.278ns Clock Pessimism Removal (CPR): 0.633ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.803ns (routing 1.326ns, distribution 2.477ns) Clock Net Delay (Destination): 3.333ns (routing 1.221ns, distribution 2.112ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.130 3.130 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.475 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.803 7.278 i_tcds2_if/fabric_clk_in SLICE_X130Y70 FDPE r i_tcds2_if/prbs_rst_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y70 FDPE (Prop_FFF2_SLICEL_C_Q) 0.138 7.416 r i_tcds2_if/prbs_rst_reg[3]/Q net (fo=1, routed) 0.668 8.084 ctrl_regs_inst/count_reg[0][0] SLICE_X126Y74 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.055 8.139 r ctrl_regs_inst/FSM_sequential_prbs_lock_state[1]_i_1/O net (fo=293, routed) 2.259 10.398 i_tcds2_if/prbs_chk_unlock_cnt/prbschk_reset SLICE_X122Y94 FDRE r i_tcds2_if/prbs_chk_unlock_cnt/count_reg[29]/R ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y4 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.836 27.788 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.048 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.333 31.381 i_tcds2_if/prbs_chk_unlock_cnt/CLK SLICE_X122Y94 FDRE r i_tcds2_if/prbs_chk_unlock_cnt/count_reg[29]/C clock pessimism 0.633 32.014 clock uncertainty -0.035 31.978 SLICE_X122Y94 FDRE (Setup_CFF_SLICEL_C_R) -0.096 31.882 i_tcds2_if/prbs_chk_unlock_cnt/count_reg[29] ------------------------------------------------------------------- required time 31.882 arrival time -10.398 ------------------------------------------------------------------- slack 21.484 Slack (MET) : 21.484ns (required time - arrival time) Source: i_tcds2_if/prbs_rst_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_chk_unlock_cnt/count_reg[30]/R (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000ns) Data Path Delay: 3.120ns (logic 0.193ns (6.186%) route 2.927ns (93.814%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.429ns = ( 31.381 - 24.952 ) Source Clock Delay (SCD): 7.278ns Clock Pessimism Removal (CPR): 0.633ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.803ns (routing 1.326ns, distribution 2.477ns) Clock Net Delay (Destination): 3.333ns (routing 1.221ns, distribution 2.112ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 3.130 3.130 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.345 3.475 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.803 7.278 i_tcds2_if/fabric_clk_in SLICE_X130Y70 FDPE r i_tcds2_if/prbs_rst_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y70 FDPE (Prop_FFF2_SLICEL_C_Q) 0.138 7.416 r i_tcds2_if/prbs_rst_reg[3]/Q net (fo=1, routed) 0.668 8.084 ctrl_regs_inst/count_reg[0][0] SLICE_X126Y74 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.055 8.139 r ctrl_regs_inst/FSM_sequential_prbs_lock_state[1]_i_1/O net (fo=293, routed) 2.259 10.398 i_tcds2_if/prbs_chk_unlock_cnt/prbschk_reset SLICE_X122Y94 FDRE r i_tcds2_if/prbs_chk_unlock_cnt/count_reg[30]/R ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 24.952 24.952 r BUFG_GT_X1Y4 BUFG_GT 0.000 24.952 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 2.836 27.788 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.260 28.048 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 3.333 31.381 i_tcds2_if/prbs_chk_unlock_cnt/CLK SLICE_X122Y94 FDRE r i_tcds2_if/prbs_chk_unlock_cnt/count_reg[30]/C clock pessimism 0.633 32.014 clock uncertainty -0.035 31.978 SLICE_X122Y94 FDRE (Setup_BFF_SLICEL_C_R) -0.096 31.882 i_tcds2_if/prbs_chk_unlock_cnt/count_reg[30] ------------------------------------------------------------------- required time 31.882 arrival time -10.398 ------------------------------------------------------------------- slack 21.484 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.046ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[10]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[106]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.193ns (logic 0.063ns (32.642%) route 0.130ns (67.357%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.130ns Source Clock Delay (SCD): 2.640ns Clock Pessimism Removal (CPR): 0.399ns Clock Net Delay (Source): 1.356ns (routing 0.503ns, distribution 0.853ns) Clock Net Delay (Destination): 1.593ns (routing 0.559ns, distribution 1.034ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.264 1.264 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.284 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.356 2.640 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X122Y85 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y85 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 2.688 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[10]/Q net (fo=52, routed) 0.114 2.802 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[9] SLICE_X124Y84 LUT6 (Prop_H6LUT_SLICEL_I2_O) 0.015 2.817 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[106]_i_1__0/O net (fo=1, routed) 0.016 2.833 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[96]_2[10] SLICE_X124Y84 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[106]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.416 1.416 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.537 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.593 3.130 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X124Y84 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[106]/C clock pessimism -0.399 2.731 SLICE_X124Y84 FDRE (Hold_HFF_SLICEL_C_D) 0.056 2.787 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[106] ------------------------------------------------------------------- required time -2.787 arrival time 2.833 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.046ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[22]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.146ns (logic 0.048ns (32.877%) route 0.098ns (67.123%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.129ns Source Clock Delay (SCD): 2.660ns Clock Pessimism Removal (CPR): 0.425ns Clock Net Delay (Source): 1.376ns (routing 0.503ns, distribution 0.873ns) Clock Net Delay (Destination): 1.592ns (routing 0.559ns, distribution 1.033ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.264 1.264 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.284 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.376 2.660 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X124Y79 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X124Y79 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 2.708 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]/Q net (fo=56, routed) 0.098 2.806 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[20]_11[2] SLICE_X124Y80 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[22]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.416 1.416 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.537 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.592 3.129 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X124Y80 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[22]/C clock pessimism -0.425 2.704 SLICE_X124Y80 FDRE (Hold_BFF2_SLICEL_C_D) 0.056 2.760 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[22] ------------------------------------------------------------------- required time -2.760 arrival time 2.806 ------------------------------------------------------------------- slack 0.046 Slack (MET) : 0.051ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[70]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.198ns (logic 0.094ns (47.475%) route 0.104ns (52.525%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.135ns Source Clock Delay (SCD): 2.645ns Clock Pessimism Removal (CPR): 0.399ns Clock Net Delay (Source): 1.361ns (routing 0.503ns, distribution 0.858ns) Clock Net Delay (Destination): 1.598ns (routing 0.559ns, distribution 1.039ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.264 1.264 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.284 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.361 2.645 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X122Y82 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y82 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 2.694 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/Q net (fo=66, routed) 0.089 2.783 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[0] SLICE_X124Y82 LUT6 (Prop_B6LUT_SLICEL_I1_O) 0.045 2.828 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[70]_i_1__0/O net (fo=1, routed) 0.015 2.843 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[58]_0[12] SLICE_X124Y82 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[70]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.416 1.416 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.537 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.598 3.135 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X124Y82 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[70]/C clock pessimism -0.399 2.736 SLICE_X124Y82 FDRE (Hold_BFF_SLICEL_C_D) 0.056 2.792 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[70] ------------------------------------------------------------------- required time -2.792 arrival time 2.843 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[64]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.195ns (logic 0.094ns (48.205%) route 0.101ns (51.795%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.132ns Source Clock Delay (SCD): 2.645ns Clock Pessimism Removal (CPR): 0.399ns Clock Net Delay (Source): 1.361ns (routing 0.503ns, distribution 0.858ns) Clock Net Delay (Destination): 1.595ns (routing 0.559ns, distribution 1.036ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.264 1.264 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.284 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.361 2.645 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X122Y82 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y82 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 2.694 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/Q net (fo=66, routed) 0.087 2.781 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[0] SLICE_X124Y82 LUT6 (Prop_G6LUT_SLICEL_I4_O) 0.045 2.826 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[64]_i_1__0/O net (fo=1, routed) 0.014 2.840 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[58]_0[6] SLICE_X124Y82 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[64]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.416 1.416 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.537 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.595 3.132 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X124Y82 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[64]/C clock pessimism -0.399 2.733 SLICE_X124Y82 FDRE (Hold_GFF_SLICEL_C_D) 0.056 2.789 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[64] ------------------------------------------------------------------- required time -2.789 arrival time 2.840 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.054ns (arrival time - required time) Source: i_tcds2_if/ttc_rx_err_cnt_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/ttc_rx_err_cnt_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.115ns (logic 0.064ns (55.652%) route 0.051ns (44.348%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.156ns Source Clock Delay (SCD): 2.687ns Clock Pessimism Removal (CPR): 0.464ns Clock Net Delay (Source): 1.403ns (routing 0.503ns, distribution 0.900ns) Clock Net Delay (Destination): 1.619ns (routing 0.559ns, distribution 1.060ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.264 1.264 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.284 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.403 2.687 i_tcds2_if/fabric_clk_in SLICE_X132Y94 FDRE r i_tcds2_if/ttc_rx_err_cnt_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y94 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 2.736 r i_tcds2_if/ttc_rx_err_cnt_reg/Q net (fo=2, routed) 0.035 2.771 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/ttc_rx_err_cnt_reg_0[0] SLICE_X132Y94 LUT6 (Prop_D6LUT_SLICEL_I5_O) 0.015 2.786 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/ttc_rx_err_cnt_i_1/O net (fo=1, routed) 0.016 2.802 i_tcds2_if/cmp_lpgbtfpga_uplink_n_41 SLICE_X132Y94 FDRE r i_tcds2_if/ttc_rx_err_cnt_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.416 1.416 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.537 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.619 3.156 i_tcds2_if/fabric_clk_in SLICE_X132Y94 FDRE r i_tcds2_if/ttc_rx_err_cnt_reg/C clock pessimism -0.464 2.692 SLICE_X132Y94 FDRE (Hold_DFF_SLICEL_C_D) 0.056 2.748 i_tcds2_if/ttc_rx_err_cnt_reg ------------------------------------------------------------------- required time -2.748 arrival time 2.802 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.054ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/data_notzero_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/data_notzero_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.115ns (logic 0.064ns (55.652%) route 0.051ns (44.348%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.121ns Source Clock Delay (SCD): 2.655ns Clock Pessimism Removal (CPR): 0.461ns Clock Net Delay (Source): 1.371ns (routing 0.503ns, distribution 0.868ns) Clock Net Delay (Destination): 1.584ns (routing 0.559ns, distribution 1.025ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.264 1.264 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.284 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.371 2.655 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X123Y77 FDRE r i_tcds2_if/prbs_checker/data_notzero_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y77 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 2.704 r i_tcds2_if/prbs_checker/data_notzero_reg/Q net (fo=3, routed) 0.035 2.739 i_tcds2_if/prbs_checker/data_notzero_reg_n_0 SLICE_X123Y77 LUT5 (Prop_D6LUT_SLICEL_I0_O) 0.015 2.754 r i_tcds2_if/prbs_checker/data_notzero_i_1/O net (fo=1, routed) 0.016 2.770 i_tcds2_if/prbs_checker/data_notzero_i_1_n_0 SLICE_X123Y77 FDRE r i_tcds2_if/prbs_checker/data_notzero_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.416 1.416 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.537 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.584 3.121 i_tcds2_if/prbs_checker/node_ff_reg[22] SLICE_X123Y77 FDRE r i_tcds2_if/prbs_checker/data_notzero_reg/C clock pessimism -0.461 2.660 SLICE_X123Y77 FDRE (Hold_DFF_SLICEL_C_D) 0.056 2.716 i_tcds2_if/prbs_checker/data_notzero_reg ------------------------------------------------------------------- required time -2.716 arrival time 2.770 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.056ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[119]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.201ns (logic 0.064ns (31.841%) route 0.137ns (68.159%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.133ns Source Clock Delay (SCD): 2.645ns Clock Pessimism Removal (CPR): 0.399ns Clock Net Delay (Source): 1.361ns (routing 0.503ns, distribution 0.858ns) Clock Net Delay (Destination): 1.596ns (routing 0.559ns, distribution 1.037ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.264 1.264 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.284 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.361 2.645 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X122Y82 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y82 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 2.694 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[1]/Q net (fo=66, routed) 0.121 2.815 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[0] SLICE_X124Y84 LUT6 (Prop_D6LUT_SLICEL_I1_O) 0.015 2.830 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[119]_i_1__0/O net (fo=1, routed) 0.016 2.846 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[115]_4[4] SLICE_X124Y84 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[119]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.416 1.416 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.537 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.596 3.133 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X124Y84 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[119]/C clock pessimism -0.399 2.734 SLICE_X124Y84 FDRE (Hold_DFF_SLICEL_C_D) 0.056 2.790 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[119] ------------------------------------------------------------------- required time -2.790 arrival time 2.846 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.056ns (arrival time - required time) Source: i_tcds2_if/BC0_onTime_cnt_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/BC0_onTime_cnt_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.117ns (logic 0.065ns (55.556%) route 0.052ns (44.444%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.999ns Source Clock Delay (SCD): 2.542ns Clock Pessimism Removal (CPR): 0.452ns Clock Net Delay (Source): 1.258ns (routing 0.503ns, distribution 0.755ns) Clock Net Delay (Destination): 1.462ns (routing 0.559ns, distribution 0.903ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.264 1.264 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.284 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.258 2.542 i_tcds2_if/fabric_clk_in SLR Crossing[0->1] SLICE_X62Y318 FDRE r i_tcds2_if/BC0_onTime_cnt_reg/C ------------------------------------------------------------------- ------------------- SLICE_X62Y318 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 2.591 r i_tcds2_if/BC0_onTime_cnt_reg/Q net (fo=2, routed) 0.037 2.628 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/BC0_early_cnt_reg[3] SLICE_X62Y318 LUT5 (Prop_B6LUT_SLICEM_I4_O) 0.016 2.644 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/BC0_onTime_cnt_i_1/O net (fo=1, routed) 0.015 2.659 i_tcds2_if/cmp_lpgbtfpga_uplink_n_45 SLICE_X62Y318 FDRE r i_tcds2_if/BC0_onTime_cnt_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.416 1.416 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.537 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.462 2.999 i_tcds2_if/fabric_clk_in SLR Crossing[0->1] SLICE_X62Y318 FDRE r i_tcds2_if/BC0_onTime_cnt_reg/C clock pessimism -0.452 2.547 SLICE_X62Y318 FDRE (Hold_BFF_SLICEM_C_D) 0.056 2.603 i_tcds2_if/BC0_onTime_cnt_reg ------------------------------------------------------------------- required time -2.603 arrival time 2.659 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.056ns (arrival time - required time) Source: i_tcds2_if/bcnt_reg[5]/C (rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/bcnt_reg[5]/D (rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.117ns (logic 0.065ns (55.556%) route 0.052ns (44.444%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.001ns Source Clock Delay (SCD): 2.545ns Clock Pessimism Removal (CPR): 0.451ns Clock Net Delay (Source): 1.261ns (routing 0.503ns, distribution 0.758ns) Clock Net Delay (Destination): 1.464ns (routing 0.559ns, distribution 0.905ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.264 1.264 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.284 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.261 2.545 i_tcds2_if/fabric_clk_in SLR Crossing[0->1] SLICE_X61Y317 FDCE r i_tcds2_if/bcnt_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y317 FDCE (Prop_BFF_SLICEM_C_Q) 0.049 2.594 r i_tcds2_if/bcnt_reg[5]/Q net (fo=8, routed) 0.037 2.631 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt_reg[11][5] SLICE_X61Y317 LUT6 (Prop_B6LUT_SLICEM_I5_O) 0.016 2.647 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt[5]_i_1/O net (fo=1, routed) 0.015 2.662 i_tcds2_if/p_0_in[5] SLICE_X61Y317 FDCE r i_tcds2_if/bcnt_reg[5]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.416 1.416 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.537 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.464 3.001 i_tcds2_if/fabric_clk_in SLR Crossing[0->1] SLICE_X61Y317 FDCE r i_tcds2_if/bcnt_reg[5]/C clock pessimism -0.451 2.550 SLICE_X61Y317 FDCE (Hold_BFF_SLICEM_C_D) 0.056 2.606 i_tcds2_if/bcnt_reg[5] ------------------------------------------------------------------- required time -2.606 arrival time 2.662 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.057ns (arrival time - required time) Source: i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[10]/C (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]/D (rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk_in Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000ns) Data Path Delay: 0.202ns (logic 0.101ns (50.000%) route 0.101ns (50.000%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.128ns Source Clock Delay (SCD): 2.640ns Clock Pessimism Removal (CPR): 0.399ns Clock Net Delay (Source): 1.356ns (routing 0.503ns, distribution 0.853ns) Clock Net Delay (Destination): 1.591ns (routing 0.559ns, distribution 1.032ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.264 1.264 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.020 1.284 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.356 2.640 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X122Y85 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y85 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 2.688 r i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[10]/Q net (fo=52, routed) 0.086 2.774 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[9] SLICE_X123Y85 LUT6 (Prop_B6LUT_SLICEL_I4_O) 0.053 2.827 r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[130]_i_1__0/O net (fo=1, routed) 0.015 2.842 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[115]_4[15] SLICE_X123Y85 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_in rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O net (fo=1861, routed) 1.416 1.416 i_tcds2_if/rxusrclk_out BUFGCE_DIV_X1Y16 BUFGCE_DIV (Prop_BUFGCE_DIV_I_O) 0.121 1.537 r i_tcds2_if/bufgce_clk_40_rx/O X3Y3 (CLOCK_ROOT) net (fo=792, routed) 1.591 3.128 i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 SLICE_X123Y85 FDRE r i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]/C clock pessimism -0.399 2.729 SLICE_X123Y85 FDRE (Hold_BFF_SLICEL_C_D) 0.056 2.785 i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130] ------------------------------------------------------------------- required time -2.785 arrival time 2.842 ------------------------------------------------------------------- slack 0.057 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: fabric_clk_in Waveform(ns): { 0.000 12.476 } Period(ns): 24.952 Sources: { i_tcds2_if/bufgce_clk_40_rx/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME3_ADV/CLKIN1 n/a 1.250 24.952 23.702 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKIN1 Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X62Y318 i_tcds2_if/BC0_early_cnt_reg/C Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X62Y318 i_tcds2_if/BC0_late_cnt_reg/C Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X62Y318 i_tcds2_if/BC0_onTime_cnt_reg/C Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X122Y80 i_tcds2_if/EvCntRes_cnt_reg/C Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X62Y318 i_tcds2_if/QIEreset_cnt_reg/C Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X117Y122 i_tcds2_if/WTE_cnt_reg/C Min Period n/a FDRE/C n/a 0.550 24.952 24.402 SLICE_X125Y80 i_tcds2_if/WTE_i_reg/C Min Period n/a FDCE/C n/a 0.550 24.952 24.402 SLICE_X60Y318 i_tcds2_if/bcnt_reg[0]/C Min Period n/a FDCE/C n/a 0.550 24.952 24.402 SLICE_X60Y318 i_tcds2_if/bcnt_reg[10]/C Low Pulse Width Slow MMCME3_ADV/CLKIN1 n/a 6.238 12.476 6.238 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKIN1 Low Pulse Width Fast MMCME3_ADV/CLKIN1 n/a 6.238 12.476 6.238 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKIN1 Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X129Y83 i_tcds2_if/prbs_checker/data_r2_reg[114]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X129Y83 i_tcds2_if/prbs_checker/data_r2_reg[115]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X129Y83 i_tcds2_if/prbs_checker/data_r2_reg[74]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X129Y83 i_tcds2_if/prbs_checker/data_r2_reg[75]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X129Y83 i_tcds2_if/prbs_checker/data_r2_reg[82]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X129Y83 i_tcds2_if/prbs_checker/data_r2_reg[83]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X129Y83 i_tcds2_if/prbs_checker/data_r2_reg[96]/C Low Pulse Width Slow FDRE/C n/a 0.275 12.476 12.201 SLICE_X129Y83 i_tcds2_if/prbs_checker/data_r2_reg[97]/C High Pulse Width Fast MMCME3_ADV/CLKIN1 n/a 6.238 12.476 6.238 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKIN1 High Pulse Width Slow MMCME3_ADV/CLKIN1 n/a 6.238 12.476 6.238 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKIN1 High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X62Y318 i_tcds2_if/BC0_early_cnt_reg/C High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X62Y318 i_tcds2_if/BC0_late_cnt_reg/C High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X62Y318 i_tcds2_if/BC0_onTime_cnt_reg/C High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X122Y80 i_tcds2_if/EvCntRes_cnt_reg/C High Pulse Width Fast FDRE/C n/a 0.275 12.476 12.201 SLICE_X62Y318 i_tcds2_if/QIEreset_cnt_reg/C High Pulse Width Fast FDCE/C n/a 0.275 12.476 12.201 SLICE_X61Y317 i_tcds2_if/bcnt_reg[2]/C High Pulse Width Fast FDCE/C n/a 0.275 12.476 12.201 SLICE_X61Y317 i_tcds2_if/bcnt_reg[3]/C High Pulse Width Fast FDCE/C n/a 0.275 12.476 12.201 SLICE_X61Y317 i_tcds2_if/bcnt_reg[5]/C --------------------------------------------------------------------------------------------------- From Clock: CLKFBOUT To Clock: CLKFBOUT Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 23.365ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: CLKFBOUT Waveform(ns): { 6.238 18.714 } Period(ns): 24.952 Sources: { fabric_clk_MMCM/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 24.952 23.365 BUFGCE_X2Y119 CLKFBOUT_bufg/I Min Period n/a MMCME3_ADV/CLKFBOUT n/a 1.250 24.952 23.702 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKFBOUT Min Period n/a MMCME3_ADV/CLKFBIN n/a 1.250 24.952 23.702 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: fabric_clk_dcm To Clock: fabric_clk_dcm Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 23.365ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: fabric_clk_dcm Waveform(ns): { 0.000 12.476 } Period(ns): 24.952 Sources: { fabric_clk_MMCM/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 24.952 23.365 BUFGCE_X2Y110 fabric_clk_bufg/I Min Period n/a MMCME3_ADV/CLKOUT0 n/a 1.250 24.952 23.702 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKOUT0 --------------------------------------------------------------------------------------------------- From Clock: tx_wordclk_dcm To Clock: tx_wordclk_dcm Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 6.730ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: tx_wordclk_dcm Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { fabric_clk_MMCM/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 8.317 6.730 BUFGCE_X2Y98 tx_wordclk_bufg/I Min Period n/a MMCME3_ADV/CLKOUT1 n/a 1.250 8.317 7.067 MMCME3_ADV_X2Y4 fabric_clk_MMCM/CLKOUT1 --------------------------------------------------------------------------------------------------- From Clock: clk125 To Clock: clk125 Setup : 0 Failing Endpoints, Worst Slack 2.365ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.048ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.365ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2_reg[1]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.rst_rstoneven_s_reg/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 5.208ns (logic 0.476ns (9.140%) route 4.732ns (90.860%)) Logic Levels: 2 (BUFGCE=1 LUT6=1) Clock Path Skew: -0.436ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.813ns = ( 10.813 - 8.000 ) Source Clock Delay (SCD): 3.522ns Clock Pessimism Removal (CPR): 0.273ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.522ns (routing 0.705ns, distribution 2.817ns) Clock Net Delay (Destination): 2.813ns (routing 0.650ns, distribution 2.163ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.522 3.522 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/m_aclk SLICE_X96Y207 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y207 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.660 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2_reg[1]/Q net (fo=1273, routed) 2.382 6.042 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2[1] BUFGCE_X2Y73 BUFGCE (Prop_BUFCE_BUFGCE_I_O) 0.101 6.143 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_chip2chip_sync_cell_inst/sync_flop_2[1]_BUFG_inst/O net (fo=166521, routed) 2.317 8.460 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/sta_headerLocked_o_bit_synchronizer/axi_c2c_link_status_out SLICE_X91Y208 LUT6 (Prop_B6LUT_SLICEL_I1_O) 0.237 8.697 r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/sta_headerLocked_o_bit_synchronizer/resetOnEven_gen.rst_rstoneven_s_i_1/O net (fo=1, routed) 0.033 8.730 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/sta_headerLocked_o_bit_synchronizer_n_0 SLICE_X91Y208 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.rst_rstoneven_s_reg/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 2.813 10.813 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/CLKFBIN SLICE_X91Y208 FDRE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.rst_rstoneven_s_reg/C clock pessimism 0.273 11.086 clock uncertainty -0.053 11.033 SLICE_X91Y208 FDRE (Setup_BFF_SLICEL_C_D) 0.062 11.095 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.rst_rstoneven_s_reg ------------------------------------------------------------------- required time 11.095 arrival time -8.730 ------------------------------------------------------------------- slack 2.365 Slack (MET) : 3.368ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C (rising edge-triggered cell FDPE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_tx_out_reg/S (rising edge-triggered cell FDSE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.703ns (logic 0.139ns (2.956%) route 4.564ns (97.044%)) Logic Levels: 0 Clock Path Skew: 0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.374ns = ( 11.374 - 8.000 ) Source Clock Delay (SCD): 3.226ns Clock Pessimism Removal (CPR): 0.071ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.226ns (routing 0.705ns, distribution 2.521ns) Clock Net Delay (Destination): 3.374ns (routing 0.650ns, distribution 2.724ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.226 3.226 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X90Y210 FDPE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X90Y210 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 3.365 r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/Q net (fo=7, routed) 4.564 7.929 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_sync SLICE_X134Y62 FDSE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_tx_out_reg/S ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.374 11.374 i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN SLICE_X134Y62 FDSE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_tx_out_reg/C clock pessimism 0.071 11.445 clock uncertainty -0.053 11.392 SLICE_X134Y62 FDSE (Setup_HFF2_SLICEL_C_S) -0.095 11.297 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_tx_out_reg ------------------------------------------------------------------- required time 11.297 arrival time -7.929 ------------------------------------------------------------------- slack 3.368 Slack (MET) : 3.489ns (required time - arrival time) Source: i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C (rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[1] (rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 3.632ns (logic 0.678ns (18.667%) route 2.954ns (81.333%)) Logic Levels: 3 (LUT3=1 LUT4=2) Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.169ns = ( 11.169 - 8.000 ) Source Clock Delay (SCD): 3.534ns Clock Pessimism Removal (CPR): 0.232ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.534ns (routing 0.705ns, distribution 2.829ns) Clock Net Delay (Destination): 3.169ns (routing 0.650ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.534 3.534 i_AXI4_to_ipbus/CLKFBIN SLICE_X101Y56 FDCE r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y56 FDCE (Prop_BFF_SLICEM_C_Q) 0.139 3.673 r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Q net (fo=69, routed) 0.702 4.375 i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] SLICE_X102Y56 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.088 4.463 r i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/O net (fo=1, routed) 1.021 5.484 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid SLICE_X117Y36 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.260 5.744 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/O net (fo=4, routed) 0.335 6.079 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X118Y37 LUT4 (Prop_C5LUT_SLICEM_I0_O) 0.191 6.270 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=40, routed) 0.896 7.166 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[1] ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.169 11.169 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.232 11.401 clock uncertainty -0.053 11.348 RAMB36_X14Y8 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[1]) -0.693 10.655 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 10.655 arrival time -7.166 ------------------------------------------------------------------- slack 3.489 Slack (MET) : 3.490ns (required time - arrival time) Source: i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C (rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[0] (rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 3.631ns (logic 0.678ns (18.673%) route 2.953ns (81.327%)) Logic Levels: 3 (LUT3=1 LUT4=2) Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.169ns = ( 11.169 - 8.000 ) Source Clock Delay (SCD): 3.534ns Clock Pessimism Removal (CPR): 0.232ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.534ns (routing 0.705ns, distribution 2.829ns) Clock Net Delay (Destination): 3.169ns (routing 0.650ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.534 3.534 i_AXI4_to_ipbus/CLKFBIN SLICE_X101Y56 FDCE r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y56 FDCE (Prop_BFF_SLICEM_C_Q) 0.139 3.673 r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Q net (fo=69, routed) 0.702 4.375 i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] SLICE_X102Y56 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.088 4.463 r i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/O net (fo=1, routed) 1.021 5.484 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid SLICE_X117Y36 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.260 5.744 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/O net (fo=4, routed) 0.335 6.079 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X118Y37 LUT4 (Prop_C5LUT_SLICEM_I0_O) 0.191 6.270 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=40, routed) 0.895 7.165 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[0] ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.169 11.169 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.232 11.401 clock uncertainty -0.053 11.348 RAMB36_X14Y8 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[0]) -0.693 10.655 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 10.655 arrival time -7.165 ------------------------------------------------------------------- slack 3.490 Slack (MET) : 3.494ns (required time - arrival time) Source: i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C (rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[3] (rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 3.627ns (logic 0.678ns (18.693%) route 2.949ns (81.307%)) Logic Levels: 3 (LUT3=1 LUT4=2) Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.169ns = ( 11.169 - 8.000 ) Source Clock Delay (SCD): 3.534ns Clock Pessimism Removal (CPR): 0.232ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.534ns (routing 0.705ns, distribution 2.829ns) Clock Net Delay (Destination): 3.169ns (routing 0.650ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.534 3.534 i_AXI4_to_ipbus/CLKFBIN SLICE_X101Y56 FDCE r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y56 FDCE (Prop_BFF_SLICEM_C_Q) 0.139 3.673 r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Q net (fo=69, routed) 0.702 4.375 i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] SLICE_X102Y56 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.088 4.463 r i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/O net (fo=1, routed) 1.021 5.484 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid SLICE_X117Y36 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.260 5.744 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/O net (fo=4, routed) 0.335 6.079 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X118Y37 LUT4 (Prop_C5LUT_SLICEM_I0_O) 0.191 6.270 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=40, routed) 0.891 7.161 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[3] ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.169 11.169 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.232 11.401 clock uncertainty -0.053 11.348 RAMB36_X14Y8 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[3]) -0.693 10.655 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 10.655 arrival time -7.161 ------------------------------------------------------------------- slack 3.494 Slack (MET) : 3.500ns (required time - arrival time) Source: i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C (rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[2] (rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 3.621ns (logic 0.678ns (18.724%) route 2.943ns (81.276%)) Logic Levels: 3 (LUT3=1 LUT4=2) Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.169ns = ( 11.169 - 8.000 ) Source Clock Delay (SCD): 3.534ns Clock Pessimism Removal (CPR): 0.232ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.534ns (routing 0.705ns, distribution 2.829ns) Clock Net Delay (Destination): 3.169ns (routing 0.650ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.534 3.534 i_AXI4_to_ipbus/CLKFBIN SLICE_X101Y56 FDCE r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y56 FDCE (Prop_BFF_SLICEM_C_Q) 0.139 3.673 r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Q net (fo=69, routed) 0.702 4.375 i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] SLICE_X102Y56 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.088 4.463 r i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/O net (fo=1, routed) 1.021 5.484 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid SLICE_X117Y36 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.260 5.744 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/O net (fo=4, routed) 0.335 6.079 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X118Y37 LUT4 (Prop_C5LUT_SLICEM_I0_O) 0.191 6.270 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=40, routed) 0.885 7.155 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[2] ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.169 11.169 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.232 11.401 clock uncertainty -0.053 11.348 RAMB36_X14Y8 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[2]) -0.693 10.655 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 10.655 arrival time -7.155 ------------------------------------------------------------------- slack 3.500 Slack (MET) : 3.573ns (required time - arrival time) Source: i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C (rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 3.548ns (logic 0.678ns (19.109%) route 2.870ns (80.891%)) Logic Levels: 3 (LUT3=1 LUT4=2) Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.169ns = ( 11.169 - 8.000 ) Source Clock Delay (SCD): 3.534ns Clock Pessimism Removal (CPR): 0.232ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.534ns (routing 0.705ns, distribution 2.829ns) Clock Net Delay (Destination): 3.169ns (routing 0.650ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.534 3.534 i_AXI4_to_ipbus/CLKFBIN SLICE_X101Y56 FDCE r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y56 FDCE (Prop_BFF_SLICEM_C_Q) 0.139 3.673 r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Q net (fo=69, routed) 0.702 4.375 i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] SLICE_X102Y56 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.088 4.463 r i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/O net (fo=1, routed) 1.021 5.484 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid SLICE_X117Y36 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.260 5.744 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/O net (fo=4, routed) 0.335 6.079 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X118Y37 LUT4 (Prop_C5LUT_SLICEM_I0_O) 0.191 6.270 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=40, routed) 0.812 7.082 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.169 11.169 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.232 11.401 clock uncertainty -0.053 11.348 RAMB36_X14Y8 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[5]) -0.693 10.655 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 10.655 arrival time -7.082 ------------------------------------------------------------------- slack 3.573 Slack (MET) : 3.577ns (required time - arrival time) Source: i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C (rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 3.544ns (logic 0.678ns (19.131%) route 2.866ns (80.869%)) Logic Levels: 3 (LUT3=1 LUT4=2) Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.169ns = ( 11.169 - 8.000 ) Source Clock Delay (SCD): 3.534ns Clock Pessimism Removal (CPR): 0.232ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.534ns (routing 0.705ns, distribution 2.829ns) Clock Net Delay (Destination): 3.169ns (routing 0.650ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.534 3.534 i_AXI4_to_ipbus/CLKFBIN SLICE_X101Y56 FDCE r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y56 FDCE (Prop_BFF_SLICEM_C_Q) 0.139 3.673 r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Q net (fo=69, routed) 0.702 4.375 i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] SLICE_X102Y56 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.088 4.463 r i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/O net (fo=1, routed) 1.021 5.484 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid SLICE_X117Y36 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.260 5.744 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/O net (fo=4, routed) 0.335 6.079 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X118Y37 LUT4 (Prop_C5LUT_SLICEM_I0_O) 0.191 6.270 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=40, routed) 0.808 7.078 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.169 11.169 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.232 11.401 clock uncertainty -0.053 11.348 RAMB36_X14Y8 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[6]) -0.693 10.655 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 10.655 arrival time -7.078 ------------------------------------------------------------------- slack 3.577 Slack (MET) : 3.578ns (required time - arrival time) Source: i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C (rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[7] (rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 3.543ns (logic 0.678ns (19.136%) route 2.865ns (80.864%)) Logic Levels: 3 (LUT3=1 LUT4=2) Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.169ns = ( 11.169 - 8.000 ) Source Clock Delay (SCD): 3.534ns Clock Pessimism Removal (CPR): 0.232ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.534ns (routing 0.705ns, distribution 2.829ns) Clock Net Delay (Destination): 3.169ns (routing 0.650ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.534 3.534 i_AXI4_to_ipbus/CLKFBIN SLICE_X101Y56 FDCE r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y56 FDCE (Prop_BFF_SLICEM_C_Q) 0.139 3.673 r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Q net (fo=69, routed) 0.702 4.375 i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] SLICE_X102Y56 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.088 4.463 r i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/O net (fo=1, routed) 1.021 5.484 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid SLICE_X117Y36 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.260 5.744 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/O net (fo=4, routed) 0.335 6.079 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X118Y37 LUT4 (Prop_C5LUT_SLICEM_I0_O) 0.191 6.270 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=40, routed) 0.807 7.077 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[7] ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.169 11.169 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.232 11.401 clock uncertainty -0.053 11.348 RAMB36_X14Y8 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[7]) -0.693 10.655 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 10.655 arrival time -7.077 ------------------------------------------------------------------- slack 3.578 Slack (MET) : 3.592ns (required time - arrival time) Source: i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C (rising edge-triggered cell FDCE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[4] (rising edge-triggered cell RAMB36E2 clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 3.529ns (logic 0.678ns (19.212%) route 2.851ns (80.788%)) Logic Levels: 3 (LUT3=1 LUT4=2) Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.169ns = ( 11.169 - 8.000 ) Source Clock Delay (SCD): 3.534ns Clock Pessimism Removal (CPR): 0.232ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.534ns (routing 0.705ns, distribution 2.829ns) Clock Net Delay (Destination): 3.169ns (routing 0.650ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.534 3.534 i_AXI4_to_ipbus/CLKFBIN SLICE_X101Y56 FDCE r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X101Y56 FDCE (Prop_BFF_SLICEM_C_Q) 0.139 3.673 r i_AXI4_to_ipbus/FSM_sequential_axi_state_reg[2]/Q net (fo=69, routed) 0.702 4.375 i_AXI4_to_ipbus/i_r_FIFO/dout_reg[0]_0[2] SLICE_X102Y56 LUT4 (Prop_C6LUT_SLICEL_I3_O) 0.088 4.463 r i_AXI4_to_ipbus/i_r_FIFO/i_axi_chip2chip_i_3/O net (fo=1, routed) 1.021 5.484 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/m_axi_rvalid SLICE_X117Y36 LUT3 (Prop_D5LUT_SLICEL_I0_O) 0.260 5.744 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__2/O net (fo=4, routed) 0.335 6.079 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X118Y37 LUT4 (Prop_C5LUT_SLICEM_I0_O) 0.191 6.270 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=40, routed) 0.793 7.063 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[4] ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.169 11.169 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.232 11.401 clock uncertainty -0.053 11.348 RAMB36_X14Y8 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[4]) -0.693 10.655 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 10.655 arrival time -7.063 ------------------------------------------------------------------- slack 3.592 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: i_AXI4_to_ipbus/length_cntr_reg[0]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_AXI4_to_ipbus/length_cntr_reg[4]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.080ns (43.011%) route 0.106ns (56.989%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.497ns Source Clock Delay (SCD): 1.268ns Clock Pessimism Removal (CPR): 0.135ns Clock Net Delay (Source): 1.268ns (routing 0.241ns, distribution 1.027ns) Clock Net Delay (Destination): 1.497ns (routing 0.268ns, distribution 1.229ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.268 1.268 i_AXI4_to_ipbus/CLKFBIN SLICE_X96Y55 FDRE r i_AXI4_to_ipbus/length_cntr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y55 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.317 r i_AXI4_to_ipbus/length_cntr_reg[0]/Q net (fo=9, routed) 0.090 1.407 i_AXI4_to_ipbus/length_cntr_reg_n_0_[0] SLICE_X97Y55 LUT6 (Prop_D6LUT_SLICEM_I1_O) 0.031 1.438 r i_AXI4_to_ipbus/length_cntr[4]_i_1/O net (fo=1, routed) 0.016 1.454 i_AXI4_to_ipbus/length_cntr[4] SLICE_X97Y55 FDRE r i_AXI4_to_ipbus/length_cntr_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.497 1.497 i_AXI4_to_ipbus/CLKFBIN SLICE_X97Y55 FDRE r i_AXI4_to_ipbus/length_cntr_reg[4]/C clock pessimism -0.135 1.362 SLICE_X97Y55 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.418 i_AXI4_to_ipbus/length_cntr_reg[4] ------------------------------------------------------------------- required time -1.418 arrival time 1.454 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.039ns (arrival time - required time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/count_value_i_reg[6]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[5]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.250ns (logic 0.079ns (31.600%) route 0.171ns (68.400%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.155ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.476ns Source Clock Delay (SCD): 1.266ns Clock Pessimism Removal (CPR): 0.055ns Clock Net Delay (Source): 1.266ns (routing 0.241ns, distribution 1.025ns) Clock Net Delay (Destination): 1.476ns (routing 0.268ns, distribution 1.208ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.266 1.266 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/rd_clk SLICE_X103Y60 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/count_value_i_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y60 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 1.315 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/count_value_i_reg[6]/Q net (fo=6, routed) 0.157 1.472 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_in_bin[6] SLICE_X104Y58 LUT2 (Prop_G6LUT_SLICEL_I0_O) 0.030 1.502 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff[5]_i_1/O net (fo=1, routed) 0.014 1.516 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/gray_enc[5] SLICE_X104Y58 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.476 1.476 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk SLICE_X104Y58 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[5]/C clock pessimism -0.055 1.421 SLICE_X104Y58 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.477 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[5] ------------------------------------------------------------------- required time -1.477 arrival time 1.516 ------------------------------------------------------------------- slack 0.039 Slack (MET) : 0.040ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/C (rising edge-triggered cell FDPE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/sm_reset_rx_pll_timer_clr_reg/S (rising edge-triggered cell FDSE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.049ns (22.072%) route 0.173ns (77.928%)) Logic Levels: 0 Clock Path Skew: 0.177ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.374ns Clock Pessimism Removal (CPR): 0.055ns Clock Net Delay (Source): 1.374ns (routing 0.241ns, distribution 1.133ns) Clock Net Delay (Destination): 1.606ns (routing 0.268ns, distribution 1.338ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.374 1.374 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in SLICE_X137Y61 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y61 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.423 r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/Q net (fo=11, routed) 0.173 1.596 i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_any_sync SLICE_X137Y59 FDSE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/sm_reset_rx_pll_timer_clr_reg/S ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.606 1.606 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X137Y59 FDSE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/sm_reset_rx_pll_timer_clr_reg/C clock pessimism -0.055 1.551 SLICE_X137Y59 FDSE (Hold_DFF2_SLICEL_C_S) 0.005 1.556 i_tcds2_if/i_mgt_wrapper/i_reset_sm/sm_reset_rx_pll_timer_clr_reg ------------------------------------------------------------------- required time -1.556 arrival time 1.596 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[2][7]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/reg_out_i_reg[7]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.197ns (logic 0.048ns (24.365%) route 0.149ns (75.634%)) Logic Levels: 0 Clock Path Skew: 0.100ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.507ns Source Clock Delay (SCD): 1.272ns Clock Pessimism Removal (CPR): 0.135ns Clock Net Delay (Source): 1.272ns (routing 0.241ns, distribution 1.031ns) Clock Net Delay (Destination): 1.507ns (routing 0.268ns, distribution 1.239ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.272 1.272 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk SLICE_X99Y59 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[2][7]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y59 FDRE (Prop_BFF2_SLICEL_C_Q) 0.048 1.320 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[2][7]/Q net (fo=6, routed) 0.149 1.469 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/D[7] SLICE_X102Y59 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/reg_out_i_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.507 1.507 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/rd_clk SLICE_X102Y59 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/reg_out_i_reg[7]/C clock pessimism -0.135 1.372 SLICE_X102Y59 FDRE (Hold_EFF2_SLICEL_C_D) 0.055 1.427 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/reg_out_i_reg[7] ------------------------------------------------------------------- required time -1.427 arrival time 1.469 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.045ns (arrival time - required time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/count_value_i_reg[6]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[6]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.087ns (33.984%) route 0.169ns (66.016%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.155ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.476ns Source Clock Delay (SCD): 1.266ns Clock Pessimism Removal (CPR): 0.055ns Clock Net Delay (Source): 1.266ns (routing 0.241ns, distribution 1.025ns) Clock Net Delay (Destination): 1.476ns (routing 0.268ns, distribution 1.208ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.266 1.266 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/rd_clk SLICE_X103Y60 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/count_value_i_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X103Y60 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 1.315 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdp_inst/count_value_i_reg[6]/Q net (fo=6, routed) 0.157 1.472 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_in_bin[6] SLICE_X104Y58 LUT2 (Prop_G5LUT_SLICEL_I1_O) 0.038 1.510 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff[6]_i_1/O net (fo=1, routed) 0.012 1.522 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/gray_enc[6] SLICE_X104Y58 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.476 1.476 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk SLICE_X104Y58 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[6]/C clock pessimism -0.055 1.421 SLICE_X104Y58 FDRE (Hold_GFF2_SLICEL_C_D) 0.056 1.477 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[6] ------------------------------------------------------------------- required time -1.477 arrival time 1.522 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.047ns (arrival time - required time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[2][1]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rpw_gray_reg/reg_out_i_reg[1]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.452ns (logic 0.208ns (46.018%) route 0.244ns (53.982%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.672ns Source Clock Delay (SCD): 3.165ns Clock Pessimism Removal (CPR): 0.231ns Clock Net Delay (Source): 3.165ns (routing 0.650ns, distribution 2.515ns) Clock Net Delay (Destination): 3.672ns (routing 0.705ns, distribution 2.967ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.165 3.165 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk SLICE_X117Y37 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[2][1]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y37 FDRE (Prop_BFF2_SLICEL_C_Q) 0.124 3.289 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[2][1]/Q net (fo=2, routed) 0.217 3.506 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff[2][1] SLICE_X119Y37 LUT3 (Prop_C5LUT_SLICEM_I0_O) 0.084 3.590 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_out_bin[1]_INST_0/O net (fo=1, routed) 0.027 3.617 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rpw_gray_reg/D[1] SLICE_X119Y37 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rpw_gray_reg/reg_out_i_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.672 3.672 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rpw_gray_reg/wr_clk SLICE_X119Y37 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rpw_gray_reg/reg_out_i_reg[1]/C clock pessimism -0.231 3.441 SLICE_X119Y37 FDRE (Hold_CFF2_SLICEM_C_D) 0.129 3.570 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rpw_gray_reg/reg_out_i_reg[1] ------------------------------------------------------------------- required time -3.570 arrival time 3.617 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.047ns (arrival time - required time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_pf_ic_rc.ram_empty_i_reg/D (rising edge-triggered cell FDSE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.259ns (logic 0.119ns (45.946%) route 0.140ns (54.054%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.156ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.493ns Source Clock Delay (SCD): 1.282ns Clock Pessimism Removal (CPR): 0.055ns Clock Net Delay (Source): 1.282ns (routing 0.241ns, distribution 1.041ns) Clock Net Delay (Destination): 1.493ns (routing 0.268ns, distribution 1.225ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.282 1.282 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rd_clk SLICE_X102Y57 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y57 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.331 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/Q net (fo=12, routed) 0.124 1.455 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/Q[0] SLICE_X102Y60 LUT6 (Prop_C6LUT_SLICEL_I1_O) 0.070 1.525 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/gen_pf_ic_rc.ram_empty_i_i_1/O net (fo=1, routed) 0.016 1.541 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/ram_empty_i0 SLICE_X102Y60 FDSE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_pf_ic_rc.ram_empty_i_reg/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.493 1.493 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rd_clk SLICE_X102Y60 FDSE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_pf_ic_rc.ram_empty_i_reg/C clock pessimism -0.055 1.438 SLICE_X102Y60 FDSE (Hold_CFF_SLICEL_C_D) 0.056 1.494 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_pf_ic_rc.ram_empty_i_reg ------------------------------------------------------------------- required time -1.494 arrival time 1.541 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.049ns (arrival time - required time) Source: i_AXI4_to_ipbus/i_r_FIFO/a_reg[3]/C (rising edge-triggered cell FDSE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_AXI4_to_ipbus/i_r_FIFO/dout_reg[32]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.284ns (logic 0.078ns (27.465%) route 0.206ns (72.535%)) Logic Levels: 1 (SRL16E=1) Clock Path Skew: 0.179ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.493ns Source Clock Delay (SCD): 1.259ns Clock Pessimism Removal (CPR): 0.055ns Clock Net Delay (Source): 1.259ns (routing 0.241ns, distribution 1.018ns) Clock Net Delay (Destination): 1.493ns (routing 0.268ns, distribution 1.225ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.259 1.259 i_AXI4_to_ipbus/i_r_FIFO/CLKFBIN SLICE_X100Y61 FDSE r i_AXI4_to_ipbus/i_r_FIFO/a_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X100Y61 FDSE (Prop_CFF_SLICEM_C_Q) 0.048 1.307 r i_AXI4_to_ipbus/i_r_FIFO/a_reg[3]/Q net (fo=38, routed) 0.194 1.501 i_AXI4_to_ipbus/i_r_FIFO/A3 SLICE_X100Y57 SRL16E (Prop_A6LUT_SLICEM_A3_Q) 0.030 1.531 r i_AXI4_to_ipbus/i_r_FIFO/g_FIFO[32].SRL16E_inst/Q net (fo=1, routed) 0.012 1.543 i_AXI4_to_ipbus/i_r_FIFO/dout_i[32] SLICE_X100Y57 FDRE r i_AXI4_to_ipbus/i_r_FIFO/dout_reg[32]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.493 1.493 i_AXI4_to_ipbus/i_r_FIFO/CLKFBIN SLICE_X100Y57 FDRE r i_AXI4_to_ipbus/i_r_FIFO/dout_reg[32]/C clock pessimism -0.055 1.438 SLICE_X100Y57 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.494 i_AXI4_to_ipbus/i_r_FIFO/dout_reg[32] ------------------------------------------------------------------- required time -1.494 arrival time 1.543 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.049ns (arrival time - required time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[3]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[5]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.110ns (logic 0.064ns (58.182%) route 0.046ns (41.818%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.502ns Source Clock Delay (SCD): 1.283ns Clock Pessimism Removal (CPR): 0.214ns Clock Net Delay (Source): 1.283ns (routing 0.241ns, distribution 1.042ns) Clock Net Delay (Destination): 1.502ns (routing 0.268ns, distribution 1.234ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.283 1.283 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/rd_clk SLICE_X102Y58 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y58 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.332 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[3]/Q net (fo=6, routed) 0.034 1.366 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/Q[3] SLICE_X102Y58 LUT5 (Prop_A6LUT_SLICEL_I0_O) 0.015 1.381 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i[5]_i_1__3/O net (fo=1, routed) 0.012 1.393 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i[5]_i_1__3_n_0 SLICE_X102Y58 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.502 1.502 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/rd_clk SLICE_X102Y58 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[5]/C clock pessimism -0.214 1.288 SLICE_X102Y58 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.344 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[5] ------------------------------------------------------------------- required time -1.344 arrival time 1.393 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[1]/D (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.143ns (logic 0.094ns (65.734%) route 0.049ns (34.266%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.499ns Source Clock Delay (SCD): 1.282ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 1.282ns (routing 0.241ns, distribution 1.041ns) Clock Net Delay (Destination): 1.499ns (routing 0.268ns, distribution 1.231ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.282 1.282 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rd_clk SLICE_X102Y57 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y57 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.331 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/Q net (fo=12, routed) 0.037 1.368 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[1]_0[0] SLICE_X102Y57 LUT5 (Prop_F6LUT_SLICEL_I1_O) 0.045 1.413 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i[1]_i_1__2/O net (fo=1, routed) 0.012 1.425 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i[1]_i_1__2_n_0 SLICE_X102Y57 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.499 1.499 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/rd_clk SLICE_X102Y57 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[1]/C clock pessimism -0.180 1.319 SLICE_X102Y57 FDRE (Hold_FFF_SLICEL_C_D) 0.056 1.375 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rdpp1_inst/count_value_i_reg[1] ------------------------------------------------------------------- required time -1.375 arrival time 1.425 ------------------------------------------------------------------- slack 0.050 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk125 Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { i_clk125_bufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 8.000 6.095 RAMB36_X12Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 8.000 6.095 RAMB36_X12Y11 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.905 8.000 6.095 RAMB36_X14Y8 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 8.000 6.095 RAMB36_X13Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Min Period n/a RAMD64E/CLK n/a 1.582 8.000 6.418 SLICE_X113Y38 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6/RAMA/CLK Min Period n/a RAMD64E/CLK n/a 1.582 8.000 6.418 SLICE_X113Y38 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6/RAMB/CLK Min Period n/a RAMD64E/CLK n/a 1.582 8.000 6.418 SLICE_X113Y38 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6/RAMC/CLK Min Period n/a RAMD64E/CLK n/a 1.582 8.000 6.418 SLICE_X113Y38 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6/RAMD/CLK Min Period n/a RAMD64E/CLK n/a 1.582 8.000 6.418 SLICE_X113Y38 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6/RAME/CLK Min Period n/a RAMD64E/CLK n/a 1.582 8.000 6.418 SLICE_X113Y38 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6/RAMF/CLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X12Y11 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 4.000 3.048 RAMB36_X14Y8 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X13Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X13Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X12Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X12Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X12Y11 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 4.000 3.048 RAMB36_X14Y8 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Low Pulse Width Slow RAMD64E/CLK n/a 0.791 4.000 3.209 SLICE_X113Y36 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7/DP/CLK Low Pulse Width Slow RAMD64E/CLK n/a 0.791 4.000 3.209 SLICE_X113Y36 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7/SP/CLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X12Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X12Y11 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 4.000 3.048 RAMB36_X14Y8 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X12Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X12Y11 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X13Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 4.000 3.048 RAMB36_X14Y8 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 4.000 3.048 RAMB36_X13Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK High Pulse Width Fast RAMD64E/CLK n/a 0.791 4.000 3.209 SLICE_X112Y38 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7/DP/CLK High Pulse Width Fast RAMD64E/CLK n/a 0.791 4.000 3.209 SLICE_X112Y38 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7/SP/CLK --------------------------------------------------------------------------------------------------- From Clock: clk250 To Clock: clk250 Setup : 0 Failing Endpoints, Worst Slack 0.163ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 1.048ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.163ns (required time - arrival time) Source: g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[6]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.915ns (logic 0.138ns (3.525%) route 3.777ns (96.475%)) Logic Levels: 0 Clock Path Skew: 0.195ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.956ns = ( 6.956 - 4.000 ) Source Clock Delay (SCD): 2.983ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.983ns (routing 1.166ns, distribution 1.817ns) Clock Net Delay (Destination): 2.956ns (routing 1.071ns, distribution 1.885ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.983 2.983 g_clock_rate_din[10].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X71Y376 FDRE r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y376 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.121 r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.777 6.898 g_clock_rate_din[10].i_rate_ngccm_status2/E[0] SLICE_X100Y403 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.956 6.956 g_clock_rate_din[10].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X100Y403 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[6]/C clock pessimism 0.222 7.178 clock uncertainty -0.063 7.115 SLICE_X100Y403 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 7.061 g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[6] ------------------------------------------------------------------- required time 7.061 arrival time -6.898 ------------------------------------------------------------------- slack 0.163 Slack (MET) : 0.179ns (required time - arrival time) Source: stat_regs_inst/load_count_cntr_reg_replica_2/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CEA2 (rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 2.948ns (logic 0.137ns (4.647%) route 2.811ns (95.353%)) Logic Levels: 0 Clock Path Skew: -0.240ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.909ns = ( 6.909 - 4.000 ) Source Clock Delay (SCD): 3.244ns Clock Pessimism Removal (CPR): 0.095ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.244ns (routing 1.166ns, distribution 2.078ns) Clock Net Delay (Destination): 2.909ns (routing 1.071ns, distribution 1.838ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 3.244 3.244 stat_regs_inst/clk250 SLR Crossing[0->1] SLICE_X46Y419 FDRE r stat_regs_inst/load_count_cntr_reg_replica_2/C ------------------------------------------------------------------- ------------------- SLICE_X46Y419 FDRE (Prop_HFF2_SLICEL_C_Q) 0.137 3.381 r stat_regs_inst/load_count_cntr_reg_replica_2/Q net (fo=102, routed) 2.811 6.192 stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/CEA2 DSP48E2_X6Y197 DSP_A_B_DATA r stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CEA2 ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.909 6.909 stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/CLK SLR Crossing[0->1] DSP48E2_X6Y197 DSP_A_B_DATA r stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CLK clock pessimism 0.095 7.004 clock uncertainty -0.063 6.941 DSP48E2_X6Y197 DSP_A_B_DATA (Setup_DSP_A_B_DATA_DSP48E2_CLK_CEA2) -0.570 6.371 stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST ------------------------------------------------------------------- required time 6.371 arrival time -6.192 ------------------------------------------------------------------- slack 0.179 Slack (MET) : 0.228ns (required time - arrival time) Source: g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[13]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.853ns (logic 0.138ns (3.582%) route 3.715ns (96.418%)) Logic Levels: 0 Clock Path Skew: 0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.963ns = ( 6.963 - 4.000 ) Source Clock Delay (SCD): 2.983ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.983ns (routing 1.166ns, distribution 1.817ns) Clock Net Delay (Destination): 2.963ns (routing 1.071ns, distribution 1.892ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.983 2.983 g_clock_rate_din[10].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X71Y376 FDRE r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y376 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.121 r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.715 6.836 g_clock_rate_din[10].i_rate_ngccm_status2/E[0] SLICE_X99Y408 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[13]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.963 6.963 g_clock_rate_din[10].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X99Y408 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[13]/C clock pessimism 0.222 7.185 clock uncertainty -0.063 7.122 SLICE_X99Y408 FDRE (Setup_EFF2_SLICEL_C_CE) -0.058 7.064 g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[13] ------------------------------------------------------------------- required time 7.064 arrival time -6.836 ------------------------------------------------------------------- slack 0.228 Slack (MET) : 0.228ns (required time - arrival time) Source: g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[2]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.853ns (logic 0.138ns (3.582%) route 3.715ns (96.418%)) Logic Levels: 0 Clock Path Skew: 0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.963ns = ( 6.963 - 4.000 ) Source Clock Delay (SCD): 2.983ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.983ns (routing 1.166ns, distribution 1.817ns) Clock Net Delay (Destination): 2.963ns (routing 1.071ns, distribution 1.892ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.983 2.983 g_clock_rate_din[10].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X71Y376 FDRE r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y376 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.121 r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.715 6.836 g_clock_rate_din[10].i_rate_ngccm_status2/E[0] SLICE_X99Y408 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.963 6.963 g_clock_rate_din[10].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X99Y408 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[2]/C clock pessimism 0.222 7.185 clock uncertainty -0.063 7.122 SLICE_X99Y408 FDRE (Setup_FFF2_SLICEL_C_CE) -0.058 7.064 g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[2] ------------------------------------------------------------------- required time 7.064 arrival time -6.836 ------------------------------------------------------------------- slack 0.228 Slack (MET) : 0.228ns (required time - arrival time) Source: g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[8]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.853ns (logic 0.138ns (3.582%) route 3.715ns (96.418%)) Logic Levels: 0 Clock Path Skew: 0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.963ns = ( 6.963 - 4.000 ) Source Clock Delay (SCD): 2.983ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.983ns (routing 1.166ns, distribution 1.817ns) Clock Net Delay (Destination): 2.963ns (routing 1.071ns, distribution 1.892ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.983 2.983 g_clock_rate_din[10].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X71Y376 FDRE r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y376 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.121 r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.715 6.836 g_clock_rate_din[10].i_rate_ngccm_status2/E[0] SLICE_X99Y408 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[8]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.963 6.963 g_clock_rate_din[10].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X99Y408 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[8]/C clock pessimism 0.222 7.185 clock uncertainty -0.063 7.122 SLICE_X99Y408 FDRE (Setup_GFF2_SLICEL_C_CE) -0.058 7.064 g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[8] ------------------------------------------------------------------- required time 7.064 arrival time -6.836 ------------------------------------------------------------------- slack 0.228 Slack (MET) : 0.230ns (required time - arrival time) Source: stat_regs_inst/load_count_cntr_reg_replica_2/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CEA2 (rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 2.899ns (logic 0.137ns (4.726%) route 2.762ns (95.274%)) Logic Levels: 0 Clock Path Skew: -0.238ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.911ns = ( 6.911 - 4.000 ) Source Clock Delay (SCD): 3.244ns Clock Pessimism Removal (CPR): 0.095ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.244ns (routing 1.166ns, distribution 2.078ns) Clock Net Delay (Destination): 2.911ns (routing 1.071ns, distribution 1.840ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 3.244 3.244 stat_regs_inst/clk250 SLR Crossing[0->1] SLICE_X46Y419 FDRE r stat_regs_inst/load_count_cntr_reg_replica_2/C ------------------------------------------------------------------- ------------------- SLICE_X46Y419 FDRE (Prop_HFF2_SLICEL_C_Q) 0.137 3.381 r stat_regs_inst/load_count_cntr_reg_replica_2/Q net (fo=102, routed) 2.762 6.143 stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst/CEA2 DSP48E2_X6Y195 DSP_A_B_DATA r stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CEA2 ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.911 6.911 stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst/CLK SLR Crossing[0->1] DSP48E2_X6Y195 DSP_A_B_DATA r stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CLK clock pessimism 0.095 7.006 clock uncertainty -0.063 6.943 DSP48E2_X6Y195 DSP_A_B_DATA (Setup_DSP_A_B_DATA_DSP48E2_CLK_CEA2) -0.570 6.373 stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST ------------------------------------------------------------------- required time 6.373 arrival time -6.143 ------------------------------------------------------------------- slack 0.230 Slack (MET) : 0.231ns (required time - arrival time) Source: g_clock_rate_din[30].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/DSP_OUTPUT_INST/RSTP (rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.347ns (logic 0.139ns (4.153%) route 3.208ns (95.847%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.854ns = ( 6.854 - 4.000 ) Source Clock Delay (SCD): 2.905ns Clock Pessimism Removal (CPR): 0.095ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.905ns (routing 1.166ns, distribution 1.739ns) Clock Net Delay (Destination): 2.854ns (routing 1.071ns, distribution 1.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.905 2.905 g_clock_rate_din[30].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X52Y379 FDRE r g_clock_rate_din[30].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X52Y379 FDRE (Prop_DFF_SLICEM_C_Q) 0.139 3.044 r g_clock_rate_din[30].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.208 6.252 g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/RSTP DSP48E2_X8Y125 DSP_OUTPUT r g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/DSP_OUTPUT_INST/RSTP ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.854 6.854 g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/CLK SLR Crossing[0->1] DSP48E2_X8Y125 DSP_OUTPUT r g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/DSP_OUTPUT_INST/CLK clock pessimism 0.095 6.949 clock uncertainty -0.063 6.886 DSP48E2_X8Y125 DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_RSTP) -0.403 6.483 g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst/DSP_OUTPUT_INST ------------------------------------------------------------------- required time 6.483 arrival time -6.252 ------------------------------------------------------------------- slack 0.231 Slack (MET) : 0.235ns (required time - arrival time) Source: g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[12]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.849ns (logic 0.138ns (3.585%) route 3.711ns (96.415%)) Logic Levels: 0 Clock Path Skew: 0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.963ns = ( 6.963 - 4.000 ) Source Clock Delay (SCD): 2.983ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.983ns (routing 1.166ns, distribution 1.817ns) Clock Net Delay (Destination): 2.963ns (routing 1.071ns, distribution 1.892ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.983 2.983 g_clock_rate_din[10].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X71Y376 FDRE r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y376 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.121 r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.711 6.832 g_clock_rate_din[10].i_rate_ngccm_status2/E[0] SLICE_X99Y408 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[12]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.963 6.963 g_clock_rate_din[10].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X99Y408 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[12]/C clock pessimism 0.222 7.185 clock uncertainty -0.063 7.122 SLICE_X99Y408 FDRE (Setup_EFF_SLICEL_C_CE) -0.055 7.067 g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[12] ------------------------------------------------------------------- required time 7.067 arrival time -6.832 ------------------------------------------------------------------- slack 0.235 Slack (MET) : 0.235ns (required time - arrival time) Source: g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[15]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.849ns (logic 0.138ns (3.585%) route 3.711ns (96.415%)) Logic Levels: 0 Clock Path Skew: 0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.963ns = ( 6.963 - 4.000 ) Source Clock Delay (SCD): 2.983ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.983ns (routing 1.166ns, distribution 1.817ns) Clock Net Delay (Destination): 2.963ns (routing 1.071ns, distribution 1.892ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.983 2.983 g_clock_rate_din[10].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X71Y376 FDRE r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y376 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.121 r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.711 6.832 g_clock_rate_din[10].i_rate_ngccm_status2/E[0] SLICE_X99Y408 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[15]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.963 6.963 g_clock_rate_din[10].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X99Y408 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[15]/C clock pessimism 0.222 7.185 clock uncertainty -0.063 7.122 SLICE_X99Y408 FDRE (Setup_FFF_SLICEL_C_CE) -0.055 7.067 g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[15] ------------------------------------------------------------------- required time 7.067 arrival time -6.832 ------------------------------------------------------------------- slack 0.235 Slack (MET) : 0.235ns (required time - arrival time) Source: g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[7]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - clk250 rise@0.000ns) Data Path Delay: 3.849ns (logic 0.138ns (3.585%) route 3.711ns (96.415%)) Logic Levels: 0 Clock Path Skew: 0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.963ns = ( 6.963 - 4.000 ) Source Clock Delay (SCD): 2.983ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.104ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.983ns (routing 1.166ns, distribution 1.817ns) Clock Net Delay (Destination): 2.963ns (routing 1.071ns, distribution 1.892ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.983 2.983 g_clock_rate_din[10].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X71Y376 FDRE r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y376 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.121 r g_clock_rate_din[10].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 3.711 6.832 g_clock_rate_din[10].i_rate_ngccm_status2/E[0] SLICE_X99Y408 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.963 6.963 g_clock_rate_din[10].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X99Y408 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[7]/C clock pessimism 0.222 7.185 clock uncertainty -0.063 7.122 SLICE_X99Y408 FDRE (Setup_GFF_SLICEL_C_CE) -0.055 7.067 g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[7] ------------------------------------------------------------------- required time 7.067 arrival time -6.832 ------------------------------------------------------------------- slack 0.235 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: g_clock_rate_din[41].i_rate_ngccm_status0/q_reg/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[41].i_rate_ngccm_status2/rate_i_reg[46]/CE (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.228ns (logic 0.048ns (21.053%) route 0.180ns (78.947%)) Logic Levels: 0 Clock Path Skew: 0.192ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.254ns Source Clock Delay (SCD): 1.015ns Clock Pessimism Removal (CPR): 0.047ns Clock Net Delay (Source): 1.015ns (routing 0.441ns, distribution 0.574ns) Clock Net Delay (Destination): 1.254ns (routing 0.488ns, distribution 0.766ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.015 1.015 g_clock_rate_din[41].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X70Y419 FDRE r g_clock_rate_din[41].i_rate_ngccm_status0/q_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y419 FDRE (Prop_HFF2_SLICEM_C_Q) 0.048 1.063 r g_clock_rate_din[41].i_rate_ngccm_status0/q_reg/Q net (fo=98, routed) 0.180 1.243 g_clock_rate_din[41].i_rate_ngccm_status2/E[0] SLICE_X74Y423 FDRE r g_clock_rate_din[41].i_rate_ngccm_status2/rate_i_reg[46]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.254 1.254 g_clock_rate_din[41].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X74Y423 FDRE r g_clock_rate_din[41].i_rate_ngccm_status2/rate_i_reg[46]/C clock pessimism -0.047 1.207 SLICE_X74Y423 FDRE (Hold_EFF_SLICEL_C_CE) 0.000 1.207 g_clock_rate_din[41].i_rate_ngccm_status2/rate_i_reg[46] ------------------------------------------------------------------- required time -1.207 arrival time 1.243 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.043ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/reset_r_reg[3]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst_reg[3]/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.245ns (logic 0.112ns (45.714%) route 0.133ns (54.286%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.147ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.286ns Source Clock Delay (SCD): 1.092ns Clock Pessimism Removal (CPR): 0.047ns Clock Net Delay (Source): 1.092ns (routing 0.441ns, distribution 0.651ns) Clock Net Delay (Destination): 1.286ns (routing 0.488ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.092 1.092 stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/clk250 SLR Crossing[0->1] SLICE_X82Y360 FDRE r stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/reset_r_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y360 FDRE (Prop_GFF_SLICEM_C_Q) 0.048 1.140 r stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/reset_r_reg[3]/Q net (fo=2, routed) 0.119 1.259 stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/p_9_in SLICE_X82Y357 LUT3 (Prop_F5LUT_SLICEM_I1_O) 0.064 1.323 r stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst[3]_i_1/O net (fo=1, routed) 0.014 1.337 stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst[3]_i_1_n_0 SLICE_X82Y357 FDRE r stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst_reg[3]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.286 1.286 stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/clk250 SLR Crossing[0->1] SLICE_X82Y357 FDRE r stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst_reg[3]/C clock pessimism -0.047 1.239 SLICE_X82Y357 FDRE (Hold_FFF2_SLICEM_C_D) 0.055 1.294 stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/d_sync_rst_reg[3] ------------------------------------------------------------------- required time -1.294 arrival time 1.337 ------------------------------------------------------------------- slack 0.043 Slack (MET) : 0.048ns (arrival time - required time) Source: g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/CLK (rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[9]/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.108ns (37.370%) route 0.181ns (62.630%)) Logic Levels: 0 Clock Path Skew: 0.185ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.445ns Source Clock Delay (SCD): 1.213ns Clock Pessimism Removal (CPR): 0.047ns Clock Net Delay (Source): 1.213ns (routing 0.441ns, distribution 0.772ns) Clock Net Delay (Destination): 1.445ns (routing 0.488ns, distribution 0.957ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.213 1.213 g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/CLK SLR Crossing[0->1] DSP48E2_X5Y167 DSP_OUTPUT r g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/CLK ------------------------------------------------------------------- ------------------- DSP48E2_X5Y167 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[33]) 0.108 1.321 r g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/P[33] net (fo=1, routed) 0.181 1.502 g_clock_rate_din[28].i_rate_test_comm/P[33] SLICE_X28Y420 FDRE r g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.445 1.445 g_clock_rate_din[28].i_rate_test_comm/clk250 SLR Crossing[0->1] SLICE_X28Y420 FDRE r g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[9]/C clock pessimism -0.047 1.398 SLICE_X28Y420 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.454 g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[9] ------------------------------------------------------------------- required time -1.454 arrival time 1.502 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.049ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[1]/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.093ns (51.099%) route 0.089ns (48.901%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.411ns Source Clock Delay (SCD): 1.214ns Clock Pessimism Removal (CPR): 0.120ns Clock Net Delay (Source): 1.214ns (routing 0.441ns, distribution 0.773ns) Clock Net Delay (Destination): 1.411ns (routing 0.488ns, distribution 0.923ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.214 1.214 stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/dest_clk SLR Crossing[0->1] SLICE_X34Y371 FDRE r stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y371 FDRE (Prop_GFF2_SLICEM_C_Q) 0.048 1.262 r stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=2, routed) 0.074 1.336 stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_sync_1 SLICE_X33Y371 LUT2 (Prop_B6LUT_SLICEL_I1_O) 0.045 1.381 r stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d[1]_i_1/O net (fo=1, routed) 0.015 1.396 stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/p_3_out[1] SLICE_X33Y371 FDRE r stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.411 1.411 stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/clk250 SLR Crossing[0->1] SLICE_X33Y371 FDRE r stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[1]/C clock pessimism -0.120 1.291 SLICE_X33Y371 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.347 stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[1] ------------------------------------------------------------------- required time -1.347 arrival time 1.396 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.050ns (arrival time - required time) Source: stat_regs_inst/addr_cntr_reg[7]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/ram_addra_cntr_reg[7]/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.049ns (27.072%) route 0.132ns (72.928%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.197ns Source Clock Delay (SCD): 1.021ns Clock Pessimism Removal (CPR): 0.101ns Clock Net Delay (Source): 1.021ns (routing 0.441ns, distribution 0.580ns) Clock Net Delay (Destination): 1.197ns (routing 0.488ns, distribution 0.709ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.021 1.021 stat_regs_inst/clk250 SLR Crossing[0->1] SLICE_X58Y374 FDRE r stat_regs_inst/addr_cntr_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y374 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.070 r stat_regs_inst/addr_cntr_reg[7]/Q net (fo=20, routed) 0.132 1.202 stat_regs_inst/addr_cntr_reg[7] SLICE_X57Y375 FDRE r stat_regs_inst/ram_addra_cntr_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.197 1.197 stat_regs_inst/clk250 SLR Crossing[0->1] SLICE_X57Y375 FDRE r stat_regs_inst/ram_addra_cntr_reg[7]/C clock pessimism -0.101 1.096 SLICE_X57Y375 FDRE (Hold_HFF2_SLICEL_C_D) 0.056 1.152 stat_regs_inst/ram_addra_cntr_reg[7] ------------------------------------------------------------------- required time -1.152 arrival time 1.202 ------------------------------------------------------------------- slack 0.050 Slack (MET) : 0.052ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/reset_r_reg[0]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst_reg[0]/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.103ns (54.787%) route 0.085ns (45.213%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.407ns Source Clock Delay (SCD): 1.207ns Clock Pessimism Removal (CPR): 0.120ns Clock Net Delay (Source): 1.207ns (routing 0.441ns, distribution 0.766ns) Clock Net Delay (Destination): 1.407ns (routing 0.488ns, distribution 0.919ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.207 1.207 stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/clk250 SLR Crossing[0->1] SLICE_X34Y377 FDRE r stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/reset_r_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y377 FDRE (Prop_GFF2_SLICEM_C_Q) 0.048 1.255 r stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/reset_r_reg[0]/Q net (fo=2, routed) 0.074 1.329 stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/reset_r_reg_n_0_[0] SLICE_X33Y377 LUT3 (Prop_C5LUT_SLICEL_I1_O) 0.055 1.384 r stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst[0]_i_1/O net (fo=1, routed) 0.011 1.395 stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst[0]_i_1_n_0 SLICE_X33Y377 FDRE r stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.407 1.407 stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/clk250 SLR Crossing[0->1] SLICE_X33Y377 FDRE r stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst_reg[0]/C clock pessimism -0.120 1.287 SLICE_X33Y377 FDRE (Hold_CFF2_SLICEL_C_D) 0.056 1.343 stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_rst_reg[0] ------------------------------------------------------------------- required time -1.343 arrival time 1.395 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.054ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/reset_r_reg[0]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst_reg[0]/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.162ns (logic 0.113ns (69.753%) route 0.049ns (30.247%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.385ns Source Clock Delay (SCD): 1.182ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.182ns (routing 0.441ns, distribution 0.741ns) Clock Net Delay (Destination): 1.385ns (routing 0.488ns, distribution 0.897ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.182 1.182 stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/clk250 SLR Crossing[0->1] SLICE_X47Y364 FDRE r stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/reset_r_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y364 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 1.231 r stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/reset_r_reg[0]/Q net (fo=2, routed) 0.037 1.268 stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/reset_r_reg_n_0_[0] SLICE_X47Y363 LUT3 (Prop_D5LUT_SLICEM_I1_O) 0.064 1.332 r stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst[0]_i_1/O net (fo=1, routed) 0.012 1.344 stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst[0]_i_1_n_0 SLICE_X47Y363 FDRE r stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.385 1.385 stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/clk250 SLR Crossing[0->1] SLICE_X47Y363 FDRE r stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst_reg[0]/C clock pessimism -0.151 1.234 SLICE_X47Y363 FDRE (Hold_DFF2_SLICEM_C_D) 0.056 1.290 stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/d_sync_rst_reg[0] ------------------------------------------------------------------- required time -1.290 arrival time 1.344 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.054ns (arrival time - required time) Source: g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/CLK (rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[8]/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.295ns (logic 0.111ns (37.627%) route 0.184ns (62.373%)) Logic Levels: 0 Clock Path Skew: 0.185ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.445ns Source Clock Delay (SCD): 1.213ns Clock Pessimism Removal (CPR): 0.047ns Clock Net Delay (Source): 1.213ns (routing 0.441ns, distribution 0.772ns) Clock Net Delay (Destination): 1.445ns (routing 0.488ns, distribution 0.957ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.213 1.213 g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/CLK SLR Crossing[0->1] DSP48E2_X5Y167 DSP_OUTPUT r g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/CLK ------------------------------------------------------------------- ------------------- DSP48E2_X5Y167 DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[32]) 0.111 1.324 r g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/P[32] net (fo=1, routed) 0.184 1.508 g_clock_rate_din[28].i_rate_test_comm/P[32] SLICE_X28Y420 FDRE r g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.445 1.445 g_clock_rate_din[28].i_rate_test_comm/clk250 SLR Crossing[0->1] SLICE_X28Y420 FDRE r g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[8]/C clock pessimism -0.047 1.398 SLICE_X28Y420 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.454 g_clock_rate_din[28].i_rate_test_comm/rate_i_reg[8] ------------------------------------------------------------------- required time -1.454 arrival time 1.508 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.054ns (arrival time - required time) Source: stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]/C (rising edge-triggered cell FDSE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]/D (rising edge-triggered cell FDSE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.115ns (logic 0.064ns (55.652%) route 0.051ns (44.348%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.005ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.207ns Source Clock Delay (SCD): 1.031ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 1.031ns (routing 0.441ns, distribution 0.590ns) Clock Net Delay (Destination): 1.207ns (routing 0.488ns, distribution 0.719ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.031 1.031 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X56Y366 FDSE r stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y366 FDSE (Prop_DFF_SLICEL_C_Q) 0.049 1.080 r stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]/Q net (fo=13, routed) 0.035 1.115 stat_regs_inst/i_cntr_rst_ctrl/B[0] SLICE_X56Y366 LUT6 (Prop_D6LUT_SLICEL_I0_O) 0.015 1.130 r stat_regs_inst/i_cntr_rst_ctrl/SR[0]_i_1/O net (fo=1, routed) 0.016 1.146 stat_regs_inst/i_cntr_rst_ctrl/SR[0]_i_1_n_0 SLICE_X56Y366 FDSE r stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.207 1.207 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X56Y366 FDSE r stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0]/C clock pessimism -0.171 1.036 SLICE_X56Y366 FDSE (Hold_DFF_SLICEL_C_D) 0.056 1.092 stat_regs_inst/i_cntr_rst_ctrl/SR_reg[0] ------------------------------------------------------------------- required time -1.092 arrival time 1.146 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.055ns (arrival time - required time) Source: stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d_reg[1]/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.101ns (52.332%) route 0.092ns (47.668%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.449ns Source Clock Delay (SCD): 1.238ns Clock Pessimism Removal (CPR): 0.129ns Clock Net Delay (Source): 1.238ns (routing 0.441ns, distribution 0.797ns) Clock Net Delay (Destination): 1.449ns (routing 0.488ns, distribution 0.961ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.238 1.238 stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/dest_clk SLR Crossing[0->1] SLICE_X20Y364 FDRE r stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y364 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.286 r stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/g_sync[1].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=2, routed) 0.077 1.363 stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d_sync_1 SLICE_X18Y364 LUT2 (Prop_B6LUT_SLICEL_I1_O) 0.053 1.416 r stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d[1]_i_1/O net (fo=1, routed) 0.015 1.431 stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/p_3_out[1] SLICE_X18Y364 FDRE r stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.449 1.449 stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/clk250 SLR Crossing[0->1] SLICE_X18Y364 FDRE r stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d_reg[1]/C clock pessimism -0.129 1.320 SLICE_X18Y364 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.376 stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/d_reg[1] ------------------------------------------------------------------- required time -1.376 arrival time 1.431 ------------------------------------------------------------------- slack 0.055 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk250 Waveform(ns): { 0.000 2.000 } Period(ns): 4.000 Sources: { i_clk250_bufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 4.000 2.095 RAMB36_X7Y75 stat_regs_inst/i_ram_cntr/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 4.000 2.095 RAMB36_X5Y82 stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Min Period n/a SRL16E/CLK n/a 1.356 4.000 2.644 SLICE_X59Y369 stat_regs_inst/clk_phase_reg[2]_srl3/CLK Min Period n/a SRL16E/CLK n/a 1.356 4.000 2.644 SLICE_X53Y376 stat_regs_inst/clk_phase_reg[5]_srl2/CLK Min Period n/a DSP_OUTPUT/CLK n/a 1.350 4.000 2.650 DSP48E2_X9Y180 stat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK Min Period n/a DSP_OUTPUT/CLK n/a 1.350 4.000 2.650 DSP48E2_X5Y169 g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst/DSP_OUTPUT_INST/CLK Min Period n/a DSP_OUTPUT/CLK n/a 1.350 4.000 2.650 DSP48E2_X15Y136 g_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst/DSP_OUTPUT_INST/CLK Min Period n/a DSP_OUTPUT/CLK n/a 1.350 4.000 2.650 DSP48E2_X18Y122 stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK Min Period n/a DSP_OUTPUT/CLK n/a 1.350 4.000 2.650 DSP48E2_X12Y142 stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK Min Period n/a DSP_OUTPUT/CLK n/a 1.350 4.000 2.650 DSP48E2_X9Y178 stat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X5Y82 stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X7Y75 stat_regs_inst/i_ram_cntr/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X5Y82 stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X7Y75 stat_regs_inst/i_ram_cntr/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Low Pulse Width Slow SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X53Y376 stat_regs_inst/clk_phase_reg[5]_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X53Y376 stat_regs_inst/clk_phase_reg[5]_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X59Y369 stat_regs_inst/clk_phase_reg[2]_srl3/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X59Y369 stat_regs_inst/clk_phase_reg[2]_srl3/CLK Low Pulse Width Slow FDRE/C n/a 0.275 2.000 1.725 SLICE_X61Y326 stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/d_reg[0]/C Low Pulse Width Slow FDRE/C n/a 0.275 2.000 1.725 SLICE_X61Y326 stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/d_sync_rst_reg[0]/C High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X7Y75 stat_regs_inst/i_ram_cntr/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X7Y75 stat_regs_inst/i_ram_cntr/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X5Y82 stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 2.000 1.048 RAMB36_X5Y82 stat_regs_inst/i_ram_rate/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_bram_0/CLKARDCLK High Pulse Width Slow SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X59Y369 stat_regs_inst/clk_phase_reg[2]_srl3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X59Y369 stat_regs_inst/clk_phase_reg[2]_srl3/CLK High Pulse Width Slow SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X53Y376 stat_regs_inst/clk_phase_reg[5]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.678 2.000 1.322 SLICE_X53Y376 stat_regs_inst/clk_phase_reg[5]_srl2/CLK High Pulse Width Fast FDRE/C n/a 0.275 2.000 1.725 SLICE_X61Y326 stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/d_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.275 2.000 1.725 SLICE_X65Y325 stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/d_reg[1]/C --------------------------------------------------------------------------------------------------- From Clock: fabric_clk To Clock: fabric_clk Setup : 0 Failing Endpoints, Worst Slack 7.164ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 11.390ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 7.164ns (required time - arrival time) Source: i2c_clk_en_reg_rep__8/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 17.126ns (logic 0.441ns (2.575%) route 16.685ns (97.425%)) Logic Levels: 3 (LUT3=1 LUT6=2) Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.443ns = ( 28.395 - 24.952 ) Source Clock Delay (SCD): 3.739ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.377ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.443ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.739ns (routing 1.005ns, distribution 2.734ns) Clock Net Delay (Destination): 3.443ns (routing 0.929ns, distribution 2.514ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.739 3.739 fabric_clk SLR Crossing[0->1] SLICE_X46Y379 FDRE r i2c_clk_en_reg_rep__8/C ------------------------------------------------------------------- ------------------- SLICE_X46Y379 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.877 r i2c_clk_en_reg_rep__8/Q net (fo=132, routed) 16.097 19.974 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X6Y115 LUT6 (Prop_F6LUT_SLICEL_I5_O) 0.051 20.025 r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/sda_chk_i_3__51/O net (fo=2, routed) 0.241 20.266 SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/isda_oen_reg_2 SLICE_X6Y117 LUT3 (Prop_B5LUT_SLICEL_I2_O) 0.201 20.467 r SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/isda_oen_i_4__51/O net (fo=1, routed) 0.310 20.777 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg_0 SLICE_X6Y114 LUT6 (Prop_C6LUT_SLICEL_I2_O) 0.051 20.828 r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__51/O net (fo=1, routed) 0.037 20.865 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__51_n_0 SLICE_X6Y114 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.443 28.395 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X6Y114 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/C clock pessimism 0.076 28.471 inter-SLR compensation -0.377 28.094 clock uncertainty -0.128 27.966 SLICE_X6Y114 FDRE (Setup_CFF_SLICEL_C_D) 0.063 28.029 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg ------------------------------------------------------------------- required time 28.029 arrival time -20.865 ------------------------------------------------------------------- slack 7.164 Slack (MET) : 7.268ns (required time - arrival time) Source: i2c_clk_en_reg_rep__8/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 17.030ns (logic 0.529ns (3.106%) route 16.501ns (96.894%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: -0.210ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.453ns = ( 28.405 - 24.952 ) Source Clock Delay (SCD): 3.739ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.379ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.453ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.739ns (routing 1.005ns, distribution 2.734ns) Clock Net Delay (Destination): 3.453ns (routing 0.929ns, distribution 2.524ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.739 3.739 fabric_clk SLR Crossing[0->1] SLICE_X46Y379 FDRE r i2c_clk_en_reg_rep__8/C ------------------------------------------------------------------- ------------------- SLICE_X46Y379 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.877 r i2c_clk_en_reg_rep__8/Q net (fo=132, routed) 16.095 19.972 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X6Y115 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 20.119 r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/O net (fo=6, routed) 0.371 20.490 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51_n_0 SLICE_X7Y114 LUT3 (Prop_H6LUT_SLICEM_I1_O) 0.244 20.734 r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_i_1__51/O net (fo=1, routed) 0.035 20.769 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_i_1__51_n_0 SLICE_X7Y114 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.453 28.405 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X7Y114 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg/C clock pessimism 0.076 28.481 inter-SLR compensation -0.379 28.102 clock uncertainty -0.128 27.974 SLICE_X7Y114 FDRE (Setup_HFF_SLICEM_C_D) 0.063 28.037 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg ------------------------------------------------------------------- required time 28.037 arrival time -20.769 ------------------------------------------------------------------- slack 7.268 Slack (MET) : 7.322ns (required time - arrival time) Source: i2c_clk_en_reg_rep__8/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 16.951ns (logic 0.434ns (2.560%) route 16.517ns (97.440%)) Logic Levels: 3 (LUT3=1 LUT6=2) Clock Path Skew: -0.240ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.423ns = ( 28.375 - 24.952 ) Source Clock Delay (SCD): 3.739ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.374ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.423ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.739ns (routing 1.005ns, distribution 2.734ns) Clock Net Delay (Destination): 3.423ns (routing 0.929ns, distribution 2.494ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.739 3.739 fabric_clk SLR Crossing[0->1] SLICE_X46Y379 FDRE r i2c_clk_en_reg_rep__8/C ------------------------------------------------------------------- ------------------- SLICE_X46Y379 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.877 r i2c_clk_en_reg_rep__8/Q net (fo=132, routed) 15.991 19.868 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X13Y117 LUT6 (Prop_G6LUT_SLICEM_I5_O) 0.051 19.919 r SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/sda_chk_i_3__52/O net (fo=2, routed) 0.266 20.185 SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/isda_oen_reg_3 SLICE_X14Y118 LUT3 (Prop_A5LUT_SLICEM_I2_O) 0.194 20.379 r SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/isda_oen_i_4__52/O net (fo=1, routed) 0.222 20.601 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg_0 SLICE_X14Y117 LUT6 (Prop_C6LUT_SLICEM_I2_O) 0.051 20.652 r SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__52/O net (fo=1, routed) 0.038 20.690 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__52_n_0 SLICE_X14Y117 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.423 28.375 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X14Y117 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/C clock pessimism 0.076 28.451 inter-SLR compensation -0.374 28.077 clock uncertainty -0.128 27.949 SLICE_X14Y117 FDRE (Setup_CFF_SLICEM_C_D) 0.063 28.012 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg ------------------------------------------------------------------- required time 28.012 arrival time -20.690 ------------------------------------------------------------------- slack 7.322 Slack (MET) : 7.357ns (required time - arrival time) Source: i2c_clk_en_reg_rep__8/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/CE (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 16.813ns (logic 0.285ns (1.695%) route 16.528ns (98.305%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.441ns = ( 28.393 - 24.952 ) Source Clock Delay (SCD): 3.739ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.377ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.441ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.739ns (routing 1.005ns, distribution 2.734ns) Clock Net Delay (Destination): 3.441ns (routing 0.929ns, distribution 2.512ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.739 3.739 fabric_clk SLR Crossing[0->1] SLICE_X46Y379 FDRE r i2c_clk_en_reg_rep__8/C ------------------------------------------------------------------- ------------------- SLICE_X46Y379 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.877 r i2c_clk_en_reg_rep__8/Q net (fo=132, routed) 16.095 19.972 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X6Y115 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 20.119 r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/O net (fo=6, routed) 0.433 20.552 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51_n_0 SLICE_X6Y114 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.441 28.393 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X6Y114 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/C clock pessimism 0.076 28.469 inter-SLR compensation -0.377 28.092 clock uncertainty -0.128 27.964 SLICE_X6Y114 FDRE (Setup_GFF_SLICEL_C_CE) -0.055 27.909 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0] ------------------------------------------------------------------- required time 27.909 arrival time -20.552 ------------------------------------------------------------------- slack 7.357 Slack (MET) : 7.424ns (required time - arrival time) Source: i2c_clk_en_reg_rep__8/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/CE (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 16.737ns (logic 0.285ns (1.703%) route 16.452ns (98.297%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.233ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.430ns = ( 28.382 - 24.952 ) Source Clock Delay (SCD): 3.739ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.375ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.430ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.739ns (routing 1.005ns, distribution 2.734ns) Clock Net Delay (Destination): 3.430ns (routing 0.929ns, distribution 2.501ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.739 3.739 fabric_clk SLR Crossing[0->1] SLICE_X46Y379 FDRE r i2c_clk_en_reg_rep__8/C ------------------------------------------------------------------- ------------------- SLICE_X46Y379 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.877 r i2c_clk_en_reg_rep__8/Q net (fo=132, routed) 16.095 19.972 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X6Y115 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 20.119 r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/O net (fo=6, routed) 0.357 20.476 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51_n_0 SLICE_X7Y115 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.430 28.382 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X7Y115 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/C clock pessimism 0.076 28.458 inter-SLR compensation -0.375 28.083 clock uncertainty -0.128 27.955 SLICE_X7Y115 FDRE (Setup_HFF_SLICEM_C_CE) -0.055 27.900 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2] ------------------------------------------------------------------- required time 27.900 arrival time -20.476 ------------------------------------------------------------------- slack 7.424 Slack (MET) : 7.454ns (required time - arrival time) Source: i2c_clk_en_reg_rep__8/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]/CE (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 16.722ns (logic 0.285ns (1.704%) route 16.437ns (98.296%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.216ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.447ns = ( 28.399 - 24.952 ) Source Clock Delay (SCD): 3.739ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.378ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.447ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.739ns (routing 1.005ns, distribution 2.734ns) Clock Net Delay (Destination): 3.447ns (routing 0.929ns, distribution 2.518ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.739 3.739 fabric_clk SLR Crossing[0->1] SLICE_X46Y379 FDRE r i2c_clk_en_reg_rep__8/C ------------------------------------------------------------------- ------------------- SLICE_X46Y379 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.877 r i2c_clk_en_reg_rep__8/Q net (fo=132, routed) 16.095 19.972 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X6Y115 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 20.119 r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/O net (fo=6, routed) 0.342 20.461 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51_n_0 SLICE_X5Y114 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.447 28.399 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X5Y114 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]/C clock pessimism 0.076 28.475 inter-SLR compensation -0.378 28.097 clock uncertainty -0.128 27.969 SLICE_X5Y114 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 27.915 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3] ------------------------------------------------------------------- required time 27.915 arrival time -20.461 ------------------------------------------------------------------- slack 7.454 Slack (MET) : 7.478ns (required time - arrival time) Source: i2c_clk_en_reg_rep__8/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]/CE (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 16.672ns (logic 0.326ns (1.955%) route 16.346ns (98.045%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.246ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.417ns = ( 28.369 - 24.952 ) Source Clock Delay (SCD): 3.739ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.373ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.417ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.739ns (routing 1.005ns, distribution 2.734ns) Clock Net Delay (Destination): 3.417ns (routing 0.929ns, distribution 2.488ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.739 3.739 fabric_clk SLR Crossing[0->1] SLICE_X46Y379 FDRE r i2c_clk_en_reg_rep__8/C ------------------------------------------------------------------- ------------------- SLICE_X46Y379 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.877 r i2c_clk_en_reg_rep__8/Q net (fo=132, routed) 15.664 19.541 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X9Y110 LUT3 (Prop_C5LUT_SLICEL_I1_O) 0.188 19.729 r SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__52/O net (fo=8, routed) 0.682 20.411 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__52_n_0 SLICE_X9Y110 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.417 28.369 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X9Y110 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]/C clock pessimism 0.076 28.445 inter-SLR compensation -0.373 28.072 clock uncertainty -0.128 27.944 SLICE_X9Y110 FDRE (Setup_DFF2_SLICEL_C_CE) -0.055 27.889 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1] ------------------------------------------------------------------- required time 27.889 arrival time -20.411 ------------------------------------------------------------------- slack 7.478 Slack (MET) : 7.483ns (required time - arrival time) Source: i2c_clk_en_reg_rep__8/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[0]/CE (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 16.668ns (logic 0.326ns (1.956%) route 16.342ns (98.044%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.246ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.417ns = ( 28.369 - 24.952 ) Source Clock Delay (SCD): 3.739ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.373ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.417ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.739ns (routing 1.005ns, distribution 2.734ns) Clock Net Delay (Destination): 3.417ns (routing 0.929ns, distribution 2.488ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.739 3.739 fabric_clk SLR Crossing[0->1] SLICE_X46Y379 FDRE r i2c_clk_en_reg_rep__8/C ------------------------------------------------------------------- ------------------- SLICE_X46Y379 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.877 r i2c_clk_en_reg_rep__8/Q net (fo=132, routed) 15.664 19.541 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X9Y110 LUT3 (Prop_C5LUT_SLICEL_I1_O) 0.188 19.729 r SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__52/O net (fo=8, routed) 0.678 20.407 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__52_n_0 SLICE_X9Y110 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.417 28.369 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X9Y110 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[0]/C clock pessimism 0.076 28.445 inter-SLR compensation -0.373 28.072 clock uncertainty -0.128 27.944 SLICE_X9Y110 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 27.890 SFP_GEN[27].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[0] ------------------------------------------------------------------- required time 27.890 arrival time -20.407 ------------------------------------------------------------------- slack 7.483 Slack (MET) : 7.518ns (required time - arrival time) Source: i2c_clk_en_reg_rep__8/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]/CE (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 16.659ns (logic 0.285ns (1.711%) route 16.374ns (98.289%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.215ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.448ns = ( 28.400 - 24.952 ) Source Clock Delay (SCD): 3.739ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.378ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.448ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.739ns (routing 1.005ns, distribution 2.734ns) Clock Net Delay (Destination): 3.448ns (routing 0.929ns, distribution 2.519ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.739 3.739 fabric_clk SLR Crossing[0->1] SLICE_X46Y379 FDRE r i2c_clk_en_reg_rep__8/C ------------------------------------------------------------------- ------------------- SLICE_X46Y379 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.877 r i2c_clk_en_reg_rep__8/Q net (fo=132, routed) 16.095 19.972 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X6Y115 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 20.119 r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/O net (fo=6, routed) 0.279 20.398 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51_n_0 SLICE_X5Y115 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.448 28.400 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X5Y115 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]/C clock pessimism 0.076 28.476 inter-SLR compensation -0.378 28.098 clock uncertainty -0.128 27.970 SLICE_X5Y115 FDRE (Setup_DFF_SLICEM_C_CE) -0.054 27.916 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4] ------------------------------------------------------------------- required time 27.916 arrival time -20.398 ------------------------------------------------------------------- slack 7.518 Slack (MET) : 7.519ns (required time - arrival time) Source: i2c_clk_en_reg_rep__8/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]/CE (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 16.655ns (logic 0.285ns (1.711%) route 16.370ns (98.289%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.444ns = ( 28.396 - 24.952 ) Source Clock Delay (SCD): 3.739ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.377ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.444ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.739ns (routing 1.005ns, distribution 2.734ns) Clock Net Delay (Destination): 3.444ns (routing 0.929ns, distribution 2.515ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.739 3.739 fabric_clk SLR Crossing[0->1] SLICE_X46Y379 FDRE r i2c_clk_en_reg_rep__8/C ------------------------------------------------------------------- ------------------- SLICE_X46Y379 FDRE (Prop_FFF2_SLICEL_C_Q) 0.138 3.877 r i2c_clk_en_reg_rep__8/Q net (fo=132, routed) 16.095 19.972 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 SLR Crossing[1->0] SLICE_X6Y115 LUT6 (Prop_G6LUT_SLICEL_I5_O) 0.147 20.119 r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51/O net (fo=6, routed) 0.275 20.394 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__51_n_0 SLICE_X6Y115 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.444 28.396 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X6Y115 FDRE r SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]/C clock pessimism 0.076 28.472 inter-SLR compensation -0.377 28.095 clock uncertainty -0.128 27.967 SLICE_X6Y115 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 27.913 SFP_GEN[27].ngCCM_gbt/i2c_gen[4].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1] ------------------------------------------------------------------- required time 27.913 arrival time -20.394 ------------------------------------------------------------------- slack 7.519 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.ial_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_txd_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.162ns (logic 0.063ns (38.889%) route 0.099ns (61.111%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.729ns Source Clock Delay (SCD): 1.500ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.500ns (routing 0.393ns, distribution 1.107ns) Clock Net Delay (Destination): 1.729ns (routing 0.434ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.500 1.500 SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLR Crossing[0->1] SLICE_X0Y553 FDRE r SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.ial_reg/C ------------------------------------------------------------------- ------------------- SLICE_X0Y553 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.548 f SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.ial_reg/Q net (fo=12, routed) 0.083 1.631 SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.ial_reg_0 SLICE_X2Y553 LUT4 (Prop_C6LUT_SLICEL_I0_O) 0.015 1.646 r SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/statemachine.core_txd_i_1__571/O net (fo=1, routed) 0.016 1.662 SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl_n_4 SLICE_X2Y553 FDRE r SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_txd_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.729 1.729 SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk SLR Crossing[0->1] SLICE_X2Y553 FDRE r SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_txd_reg/C clock pessimism -0.153 1.576 SLICE_X2Y553 FDRE (Hold_CFF_SLICEL_C_D) 0.056 1.632 SFP_GEN[42].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_txd_reg ------------------------------------------------------------------- required time -1.632 arrival time 1.662 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/fall_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.sta_condition_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.223ns (logic 0.093ns (41.704%) route 0.130ns (58.296%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.137ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.493ns Source Clock Delay (SCD): 1.222ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 1.222ns (routing 0.393ns, distribution 0.829ns) Clock Net Delay (Destination): 1.493ns (routing 0.434ns, distribution 1.059ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.222 1.222 SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/fabric_clk SLR Crossing[0->1] SLICE_X69Y378 FDRE r SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/fall_reg/C ------------------------------------------------------------------- ------------------- SLICE_X69Y378 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 1.270 r SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/fall_reg/Q net (fo=1, routed) 0.114 1.384 SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/fall SLICE_X71Y378 LUT4 (Prop_C6LUT_SLICEM_I0_O) 0.045 1.429 r SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_sda/bus_status_ctrl.sta_condition_i_1__170/O net (fo=1, routed) 0.016 1.445 SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/sta_condition SLICE_X71Y378 FDRE r SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.sta_condition_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.493 1.493 SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLR Crossing[0->1] SLICE_X71Y378 FDRE r SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.sta_condition_reg/C clock pessimism -0.134 1.359 SLICE_X71Y378 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.415 SFP_GEN[23].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.sta_condition_reg ------------------------------------------------------------------- required time -1.415 arrival time 1.445 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[1]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[1]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.155ns (logic 0.064ns (41.290%) route 0.091ns (58.710%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.688ns Source Clock Delay (SCD): 1.458ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 1.458ns (routing 0.393ns, distribution 1.065ns) Clock Net Delay (Destination): 1.688ns (routing 0.434ns, distribution 1.254ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.458 1.458 SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk SLR Crossing[0->1] SLICE_X3Y352 FDRE r SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y352 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.507 r SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[1]/Q net (fo=2, routed) 0.075 1.582 SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/dout[1] SLICE_X4Y352 LUT4 (Prop_C6LUT_SLICEM_I1_O) 0.015 1.597 r SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/wb_dat_o[1]_i_1__323/O net (fo=1, routed) 0.016 1.613 SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/wb_dat_o[1] SLICE_X4Y352 FDRE r SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[1]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.688 1.688 SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/fabric_clk SLR Crossing[0->1] SLICE_X4Y352 FDRE r SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[1]/C clock pessimism -0.161 1.527 SLICE_X4Y352 FDRE (Hold_CFF_SLICEM_C_D) 0.056 1.583 SFP_GEN[36].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[1] ------------------------------------------------------------------- required time -1.583 arrival time 1.613 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.167ns (logic 0.078ns (46.707%) route 0.089ns (53.293%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.679ns Source Clock Delay (SCD): 1.449ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 1.449ns (routing 0.393ns, distribution 1.056ns) Clock Net Delay (Destination): 1.679ns (routing 0.434ns, distribution 1.245ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.449 1.449 SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk SLR Crossing[0->1] SLICE_X24Y560 FDRE r SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y560 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 1.497 r SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7]/Q net (fo=2, routed) 0.077 1.574 SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/dout[7] SLICE_X25Y560 LUT4 (Prop_A6LUT_SLICEM_I1_O) 0.030 1.604 r SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/byte_ctrl/wb_dat_o[7]_i_1__557/O net (fo=1, routed) 0.012 1.616 SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/wb_dat_o[7] SLICE_X25Y560 FDRE r SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.679 1.679 SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/fabric_clk SLR Crossing[0->1] SLICE_X25Y560 FDRE r SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]/C clock pessimism -0.149 1.530 SLICE_X25Y560 FDRE (Hold_AFF_SLICEM_C_D) 0.056 1.586 SFP_GEN[42].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7] ------------------------------------------------------------------- required time -1.586 arrival time 1.616 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.host_ack_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.177ns (logic 0.079ns (44.633%) route 0.098ns (55.367%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.491ns Source Clock Delay (SCD): 1.272ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 1.272ns (routing 0.393ns, distribution 0.879ns) Clock Net Delay (Destination): 1.491ns (routing 0.434ns, distribution 1.057ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.272 1.272 SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk SLR Crossing[0->1] SLICE_X48Y548 FDRE r SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y548 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 1.320 f SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]/Q net (fo=15, routed) 0.083 1.403 SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/c_state__0[1] SLICE_X49Y548 LUT6 (Prop_B6LUT_SLICEM_I2_O) 0.031 1.434 r SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/statemachine.host_ack_i_1__253/O net (fo=1, routed) 0.015 1.449 SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/host_ack1_out SLICE_X49Y548 FDRE r SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.host_ack_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.491 1.491 SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk SLR Crossing[0->1] SLICE_X49Y548 FDRE r SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.host_ack_reg/C clock pessimism -0.128 1.363 SLICE_X49Y548 FDRE (Hold_BFF_SLICEM_C_D) 0.056 1.419 SFP_GEN[43].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.host_ack_reg ------------------------------------------------------------------- required time -1.419 arrival time 1.449 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[0]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.268ns (logic 0.079ns (29.478%) route 0.189ns (70.522%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.182ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.413ns Source Clock Delay (SCD): 1.182ns Clock Pessimism Removal (CPR): 0.049ns Clock Net Delay (Source): 1.182ns (routing 0.393ns, distribution 0.789ns) Clock Net Delay (Destination): 1.413ns (routing 0.434ns, distribution 0.979ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.182 1.182 SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk SLICE_X61Y181 FDRE r SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y181 FDRE (Prop_HFF_SLICEM_C_Q) 0.048 1.230 r SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[0]/Q net (fo=14, routed) 0.173 1.403 SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/c_state__0[0] SLICE_X62Y179 LUT6 (Prop_D6LUT_SLICEM_I2_O) 0.031 1.434 r SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_statemachine.c_state[1]_i_1__353/O net (fo=1, routed) 0.016 1.450 SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl_n_12 SLICE_X62Y179 FDRE r SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.413 1.413 SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk SLICE_X62Y179 FDRE r SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1]/C clock pessimism -0.049 1.364 SLICE_X62Y179 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.420 SFP_GEN[28].ngCCM_gbt/i2c_gen[9].LocalI2CBridge_fe/i2c_master/byte_ctrl/FSM_sequential_statemachine.c_state_reg[1] ------------------------------------------------------------------- required time -1.420 arrival time 1.450 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[8].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/DataIn_local_reg[4]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[8].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[4]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.272ns (logic 0.048ns (17.647%) route 0.224ns (82.353%)) Logic Levels: 0 Clock Path Skew: 0.186ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.765ns Source Clock Delay (SCD): 1.520ns Clock Pessimism Removal (CPR): 0.059ns Clock Net Delay (Source): 1.520ns (routing 0.393ns, distribution 1.127ns) Clock Net Delay (Destination): 1.765ns (routing 0.434ns, distribution 1.331ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.520 1.520 SFP_GEN[8].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/clk_local SLICE_X138Y120 FDRE r SFP_GEN[8].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/DataIn_local_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y120 FDRE (Prop_BFF2_SLICEL_C_Q) 0.048 1.568 r SFP_GEN[8].ngCCM_gbt/IPbus_gen[2].IPbus_local_inst/DataIn_local_reg[4]/Q net (fo=1, routed) 0.224 1.792 SFP_GEN[8].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/DataIn_local[4] SLICE_X139Y118 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[4]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.765 1.765 SFP_GEN[8].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/fabric_clk SLICE_X139Y118 FDRE r SFP_GEN[8].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[4]/C clock pessimism -0.059 1.706 SLICE_X139Y118 FDRE (Hold_FFF_SLICEL_C_D) 0.056 1.762 SFP_GEN[8].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[4] ------------------------------------------------------------------- required time -1.762 arrival time 1.792 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[4].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/addr_local_reg[1]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[9]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.153ns (logic 0.063ns (41.176%) route 0.090ns (58.824%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.522ns Source Clock Delay (SCD): 1.322ns Clock Pessimism Removal (CPR): 0.133ns Clock Net Delay (Source): 1.322ns (routing 0.393ns, distribution 0.929ns) Clock Net Delay (Destination): 1.522ns (routing 0.434ns, distribution 1.088ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.322 1.322 SFP_GEN[4].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/clk_local SLICE_X95Y3 FDRE r SFP_GEN[4].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/addr_local_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X95Y3 FDRE (Prop_EFF2_SLICEM_C_Q) 0.048 1.370 f SFP_GEN[4].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/addr_local_reg[1]/Q net (fo=15, routed) 0.078 1.448 SFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/addr_local[1] SLICE_X94Y4 LUT4 (Prop_A6LUT_SLICEL_I3_O) 0.015 1.463 r SFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/wb_dat_o[9]_i_1__290/O net (fo=1, routed) 0.012 1.475 SFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/wb_dat_o[9] SLICE_X94Y4 FDRE r SFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[9]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.522 1.522 SFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/fabric_clk SLICE_X94Y4 FDRE r SFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[9]/C clock pessimism -0.133 1.389 SLICE_X94Y4 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.445 SFP_GEN[4].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[9] ------------------------------------------------------------------- required time -1.445 arrival time 1.475 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[13].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/DataIn_local_reg[7]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[13].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/txr_reg[7]/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.141ns (logic 0.049ns (34.752%) route 0.092ns (65.248%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.791ns Source Clock Delay (SCD): 1.535ns Clock Pessimism Removal (CPR): 0.201ns Clock Net Delay (Source): 1.535ns (routing 0.393ns, distribution 1.142ns) Clock Net Delay (Destination): 1.791ns (routing 0.434ns, distribution 1.357ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.535 1.535 SFP_GEN[13].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/clk_local SLR Crossing[0->1] SLICE_X138Y316 FDRE r SFP_GEN[13].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/DataIn_local_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y316 FDRE (Prop_BFF_SLICEL_C_Q) 0.049 1.584 r SFP_GEN[13].ngCCM_gbt/IPbus_gen[3].IPbus_local_inst/DataIn_local_reg[7]/Q net (fo=1, routed) 0.092 1.676 SFP_GEN[13].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/DataIn_local[7] SLICE_X138Y317 FDRE r SFP_GEN[13].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/txr_reg[7]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.791 1.791 SFP_GEN[13].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/fabric_clk SLR Crossing[0->1] SLICE_X138Y317 FDRE r SFP_GEN[13].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/txr_reg[7]/C clock pessimism -0.201 1.590 SLICE_X138Y317 FDRE (Hold_HFF2_SLICEL_C_D) 0.056 1.646 SFP_GEN[13].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/txr_reg[7] ------------------------------------------------------------------- required time -1.646 arrival time 1.676 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_cmd_reg[1]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: fabric_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.156ns (logic 0.063ns (40.385%) route 0.093ns (59.615%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.391ns Source Clock Delay (SCD): 1.190ns Clock Pessimism Removal (CPR): 0.131ns Clock Net Delay (Source): 1.190ns (routing 0.393ns, distribution 0.797ns) Clock Net Delay (Destination): 1.391ns (routing 0.434ns, distribution 0.957ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.190 1.190 SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk SLICE_X54Y295 FDRE r SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_cmd_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y295 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.238 r SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/statemachine.core_cmd_reg[1]/Q net (fo=8, routed) 0.079 1.317 SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_reg_0[1] SLICE_X56Y295 LUT6 (Prop_G6LUT_SLICEL_I2_O) 0.015 1.332 r SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_i_1__553/O net (fo=1, routed) 0.014 1.346 SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_i_1__553_n_0 SLICE_X56Y295 FDRE r SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.391 1.391 SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk SLICE_X56Y295 FDRE r SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_reg/C clock pessimism -0.131 1.260 SLICE_X56Y295 FDRE (Hold_GFF_SLICEL_C_D) 0.056 1.316 SFP_GEN[31].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.cmd_stop_reg ------------------------------------------------------------------- required time -1.316 arrival time 1.346 ------------------------------------------------------------------- slack 0.030 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: fabric_clk Waveform(ns): { 0.000 12.476 } Period(ns): 24.952 Sources: { fabric_clk_bufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X5Y10 SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X8Y45 SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X13Y22 SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X17Y107 SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X5Y101 SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X16Y34 SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X8Y48 SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X13Y36 SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X14Y111 SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 2.174 24.952 22.778 RAMB36_X4Y106 SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X6Y110 SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X10Y113 SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X5Y10 SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X8Y45 SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X13Y22 SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X17Y107 SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X17Y107 SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X16Y34 SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X14Y111 SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X14Y45 SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X5Y10 SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X12Y66 SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X4Y54 SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X8Y78 SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X13Y68 SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X12Y72 SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X3Y73 SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X13Y44 SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X1Y78 SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 1.086 12.476 11.390 RAMB36_X16Y87 SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK --------------------------------------------------------------------------------------------------- From Clock: ipb_clk To Clock: ipb_clk Setup : 0 Failing Endpoints, Worst Slack 2.507ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 15.048ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.507ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[2][14]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: i_I2C_if/prescale_cnt_reg[14]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 28.965ns (logic 0.229ns (0.791%) route 28.736ns (99.209%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.170ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.768ns = ( 34.768 - 32.000 ) Source Clock Delay (SCD): 2.982ns Clock Pessimism Removal (CPR): 0.044ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.337ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 2.768ns Common Clock Delay (CCD): 0.519ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 2.982ns (routing 0.563ns, distribution 2.419ns) Clock Net Delay (Destination): 2.768ns (routing 0.519ns, distribution 2.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.982 2.982 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X57Y339 FDCE r ctrl_regs_inst/regs_reg[2][14]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y339 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 3.122 r ctrl_regs_inst/regs_reg[2][14]/Q net (fo=579, routed) 28.702 31.824 i_I2C_if/prescale_cnt_reg[15]_0[14] SLR Crossing[1->0] SLICE_X85Y22 LUT6 (Prop_G6LUT_SLICEM_I0_O) 0.089 31.913 r i_I2C_if/prescale_cnt[14]_i_1/O net (fo=1, routed) 0.034 31.947 i_I2C_if/prescale_cnt[14] SLICE_X85Y22 FDRE r i_I2C_if/prescale_cnt_reg[14]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.768 34.768 i_I2C_if/ipb_clk SLICE_X85Y22 FDRE r i_I2C_if/prescale_cnt_reg[14]/C clock pessimism 0.044 34.812 inter-SLR compensation -0.337 34.475 clock uncertainty -0.085 34.390 SLICE_X85Y22 FDRE (Setup_GFF_SLICEM_C_D) 0.064 34.454 i_I2C_if/prescale_cnt_reg[14] ------------------------------------------------------------------- required time 34.454 arrival time -31.947 ------------------------------------------------------------------- slack 2.507 Slack (MET) : 3.272ns (required time - arrival time) Source: i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/WEA[0] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 27.281ns (logic 0.618ns (2.265%) route 26.663ns (97.735%)) Logic Levels: 2 (LUT2=1 LUT5=1) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.099ns = ( 35.099 - 32.000 ) Source Clock Delay (SCD): 3.425ns Clock Pessimism Removal (CPR): 0.044ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.387ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.099ns Common Clock Delay (CCD): 0.519ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.425ns (routing 0.563ns, distribution 2.862ns) Clock Net Delay (Destination): 3.099ns (routing 0.519ns, distribution 2.580ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.425 3.425 i_AXI4_to_ipbus/ipb_clk SLICE_X99Y53 FDRE r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y53 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.564 r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/Q net (fo=10950, routed) 25.237 28.801 i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] SLR Crossing[0->1] SLICE_X12Y541 LUT5 (Prop_E6LUT_SLICEL_I4_O) 0.235 29.036 r i_AXI4_to_ipbus/BRAM_l_i_1__591/O net (fo=1, routed) 0.270 29.306 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/wea[0] SLICE_X13Y541 LUT2 (Prop_H6LUT_SLICEM_I0_O) 0.244 29.550 r SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/O net (fo=8, routed) 1.156 30.706 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 RAMB36_X0Y106 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/WEA[0] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.099 35.099 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X0Y106 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK clock pessimism 0.044 35.143 inter-SLR compensation -0.387 34.756 clock uncertainty -0.085 34.671 RAMB36_X0Y106 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[0]) -0.693 33.978 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 ------------------------------------------------------------------- required time 33.978 arrival time -30.706 ------------------------------------------------------------------- slack 3.272 Slack (MET) : 3.273ns (required time - arrival time) Source: i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/WEA[1] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 27.280ns (logic 0.618ns (2.265%) route 26.662ns (97.735%)) Logic Levels: 2 (LUT2=1 LUT5=1) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.099ns = ( 35.099 - 32.000 ) Source Clock Delay (SCD): 3.425ns Clock Pessimism Removal (CPR): 0.044ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.387ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.099ns Common Clock Delay (CCD): 0.519ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.425ns (routing 0.563ns, distribution 2.862ns) Clock Net Delay (Destination): 3.099ns (routing 0.519ns, distribution 2.580ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.425 3.425 i_AXI4_to_ipbus/ipb_clk SLICE_X99Y53 FDRE r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y53 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.564 r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/Q net (fo=10950, routed) 25.237 28.801 i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] SLR Crossing[0->1] SLICE_X12Y541 LUT5 (Prop_E6LUT_SLICEL_I4_O) 0.235 29.036 r i_AXI4_to_ipbus/BRAM_l_i_1__591/O net (fo=1, routed) 0.270 29.306 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/wea[0] SLICE_X13Y541 LUT2 (Prop_H6LUT_SLICEM_I0_O) 0.244 29.550 r SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/O net (fo=8, routed) 1.155 30.705 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 RAMB36_X0Y106 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/WEA[1] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.099 35.099 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X0Y106 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK clock pessimism 0.044 35.143 inter-SLR compensation -0.387 34.756 clock uncertainty -0.085 34.671 RAMB36_X0Y106 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[1]) -0.693 33.978 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 ------------------------------------------------------------------- required time 33.978 arrival time -30.705 ------------------------------------------------------------------- slack 3.273 Slack (MET) : 3.312ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[2][15]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: i_I2C_if/prescale_cnt_reg[15]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 28.168ns (logic 0.304ns (1.079%) route 27.864ns (98.921%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.771ns = ( 34.771 - 32.000 ) Source Clock Delay (SCD): 2.975ns Clock Pessimism Removal (CPR): 0.044ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.338ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 2.771ns Common Clock Delay (CCD): 0.519ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 2.975ns (routing 0.563ns, distribution 2.412ns) Clock Net Delay (Destination): 2.771ns (routing 0.519ns, distribution 2.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.975 2.975 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X52Y318 FDCE r ctrl_regs_inst/regs_reg[2][15]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y318 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.114 r ctrl_regs_inst/regs_reg[2][15]/Q net (fo=579, routed) 27.827 30.941 i_I2C_if/prescale_cnt_reg[15]_0[15] SLR Crossing[1->0] SLICE_X86Y22 LUT6 (Prop_C6LUT_SLICEL_I5_O) 0.165 31.106 r i_I2C_if/prescale_cnt[15]_i_1/O net (fo=1, routed) 0.037 31.143 i_I2C_if/prescale_cnt[15] SLICE_X86Y22 FDRE r i_I2C_if/prescale_cnt_reg[15]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.771 34.771 i_I2C_if/ipb_clk SLICE_X86Y22 FDRE r i_I2C_if/prescale_cnt_reg[15]/C clock pessimism 0.044 34.815 inter-SLR compensation -0.338 34.477 clock uncertainty -0.085 34.392 SLICE_X86Y22 FDRE (Setup_CFF_SLICEL_C_D) 0.063 34.455 i_I2C_if/prescale_cnt_reg[15] ------------------------------------------------------------------- required time 34.455 arrival time -31.143 ------------------------------------------------------------------- slack 3.312 Slack (MET) : 3.467ns (required time - arrival time) Source: i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[0] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 27.085ns (logic 0.591ns (2.182%) route 26.494ns (97.818%)) Logic Levels: 2 (LUT2=1 LUT5=1) Clock Path Skew: -0.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.098ns = ( 35.098 - 32.000 ) Source Clock Delay (SCD): 3.425ns Clock Pessimism Removal (CPR): 0.044ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.387ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.098ns Common Clock Delay (CCD): 0.519ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.425ns (routing 0.563ns, distribution 2.862ns) Clock Net Delay (Destination): 3.098ns (routing 0.519ns, distribution 2.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.425 3.425 i_AXI4_to_ipbus/ipb_clk SLICE_X99Y53 FDRE r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y53 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.564 r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/Q net (fo=10950, routed) 25.156 28.720 i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] SLR Crossing[0->1] SLICE_X11Y545 LUT5 (Prop_F6LUT_SLICEM_I4_O) 0.245 28.965 r i_AXI4_to_ipbus/BRAM_l_i_1__599/O net (fo=1, routed) 0.261 29.226 SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/wea[0] SLICE_X10Y545 LUT2 (Prop_B5LUT_SLICEM_I0_O) 0.207 29.433 r SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/O net (fo=8, routed) 1.077 30.510 SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 RAMB36_X0Y110 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[0] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.098 35.098 SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X0Y110 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK clock pessimism 0.044 35.142 inter-SLR compensation -0.387 34.755 clock uncertainty -0.085 34.670 RAMB36_X0Y110 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[0]) -0.693 33.977 SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time 33.977 arrival time -30.510 ------------------------------------------------------------------- slack 3.467 Slack (MET) : 3.629ns (required time - arrival time) Source: i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[1] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 26.893ns (logic 0.618ns (2.298%) route 26.275ns (97.702%)) Logic Levels: 2 (LUT2=1 LUT5=1) Clock Path Skew: -0.319ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.062ns = ( 35.062 - 32.000 ) Source Clock Delay (SCD): 3.425ns Clock Pessimism Removal (CPR): 0.044ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.381ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.062ns Common Clock Delay (CCD): 0.519ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.425ns (routing 0.563ns, distribution 2.862ns) Clock Net Delay (Destination): 3.062ns (routing 0.519ns, distribution 2.543ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.425 3.425 i_AXI4_to_ipbus/ipb_clk SLICE_X99Y53 FDRE r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y53 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.564 r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/Q net (fo=10950, routed) 25.237 28.801 i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] SLR Crossing[0->1] SLICE_X12Y541 LUT5 (Prop_E6LUT_SLICEL_I4_O) 0.235 29.036 r i_AXI4_to_ipbus/BRAM_l_i_1__591/O net (fo=1, routed) 0.270 29.306 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/wea[0] SLICE_X13Y541 LUT2 (Prop_H6LUT_SLICEM_I0_O) 0.244 29.550 r SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/O net (fo=8, routed) 0.768 30.318 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 RAMB36_X1Y106 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[1] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.062 35.062 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X1Y106 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK clock pessimism 0.044 35.106 inter-SLR compensation -0.381 34.725 clock uncertainty -0.085 34.640 RAMB36_X1Y106 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[1]) -0.693 33.947 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time 33.947 arrival time -30.318 ------------------------------------------------------------------- slack 3.629 Slack (MET) : 3.633ns (required time - arrival time) Source: i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[0] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 26.889ns (logic 0.618ns (2.298%) route 26.271ns (97.702%)) Logic Levels: 2 (LUT2=1 LUT5=1) Clock Path Skew: -0.319ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.062ns = ( 35.062 - 32.000 ) Source Clock Delay (SCD): 3.425ns Clock Pessimism Removal (CPR): 0.044ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.381ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.062ns Common Clock Delay (CCD): 0.519ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.425ns (routing 0.563ns, distribution 2.862ns) Clock Net Delay (Destination): 3.062ns (routing 0.519ns, distribution 2.543ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.425 3.425 i_AXI4_to_ipbus/ipb_clk SLICE_X99Y53 FDRE r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y53 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.564 r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/Q net (fo=10950, routed) 25.237 28.801 i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] SLR Crossing[0->1] SLICE_X12Y541 LUT5 (Prop_E6LUT_SLICEL_I4_O) 0.235 29.036 r i_AXI4_to_ipbus/BRAM_l_i_1__591/O net (fo=1, routed) 0.270 29.306 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/wea[0] SLICE_X13Y541 LUT2 (Prop_H6LUT_SLICEM_I0_O) 0.244 29.550 r SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/O net (fo=8, routed) 0.764 30.314 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 RAMB36_X1Y106 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[0] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.062 35.062 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X1Y106 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK clock pessimism 0.044 35.106 inter-SLR compensation -0.381 34.725 clock uncertainty -0.085 34.640 RAMB36_X1Y106 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[0]) -0.693 33.947 SFP_GEN[42].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time 33.947 arrival time -30.314 ------------------------------------------------------------------- slack 3.633 Slack (MET) : 3.662ns (required time - arrival time) Source: i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[1] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 26.890ns (logic 0.591ns (2.198%) route 26.299ns (97.802%)) Logic Levels: 2 (LUT2=1 LUT5=1) Clock Path Skew: -0.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.098ns = ( 35.098 - 32.000 ) Source Clock Delay (SCD): 3.425ns Clock Pessimism Removal (CPR): 0.044ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.387ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.098ns Common Clock Delay (CCD): 0.519ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.425ns (routing 0.563ns, distribution 2.862ns) Clock Net Delay (Destination): 3.098ns (routing 0.519ns, distribution 2.579ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.425 3.425 i_AXI4_to_ipbus/ipb_clk SLICE_X99Y53 FDRE r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y53 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.564 r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/Q net (fo=10950, routed) 25.156 28.720 i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] SLR Crossing[0->1] SLICE_X11Y545 LUT5 (Prop_F6LUT_SLICEM_I4_O) 0.245 28.965 r i_AXI4_to_ipbus/BRAM_l_i_1__599/O net (fo=1, routed) 0.261 29.226 SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/wea[0] SLICE_X10Y545 LUT2 (Prop_B5LUT_SLICEM_I0_O) 0.207 29.433 r SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/O net (fo=8, routed) 0.882 30.315 SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 RAMB36_X0Y110 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/WEA[1] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.098 35.098 SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X0Y110 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK clock pessimism 0.044 35.142 inter-SLR compensation -0.387 34.755 clock uncertainty -0.085 34.670 RAMB36_X0Y110 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[1]) -0.693 33.977 SFP_GEN[42].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time 33.977 arrival time -30.315 ------------------------------------------------------------------- slack 3.662 Slack (MET) : 3.706ns (required time - arrival time) Source: i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[42].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[11]/CE (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 27.318ns (logic 0.305ns (1.116%) route 27.013ns (98.884%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.906ns = ( 34.906 - 32.000 ) Source Clock Delay (SCD): 3.425ns Clock Pessimism Removal (CPR): 0.044ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.358ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 2.906ns Common Clock Delay (CCD): 0.519ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.425ns (routing 0.563ns, distribution 2.862ns) Clock Net Delay (Destination): 2.906ns (routing 0.519ns, distribution 2.387ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.425 3.425 i_AXI4_to_ipbus/ipb_clk SLICE_X99Y53 FDRE r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y53 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.564 r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/Q net (fo=10950, routed) 24.806 28.370 i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] SLR Crossing[0->1] SLICE_X20Y541 LUT6 (Prop_E6LUT_SLICEL_I3_O) 0.166 28.536 r i_AXI4_to_ipbus/input_size_i[12]_i_1__598/O net (fo=11, routed) 2.207 30.743 SFP_GEN[42].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[12]_0[0] SLICE_X42Y485 FDCE r SFP_GEN[42].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[11]/CE ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.906 34.906 SFP_GEN[42].ngFEC_module/bram_array[11].buffer_server/ipb_clk SLR Crossing[0->1] SLICE_X42Y485 FDCE r SFP_GEN[42].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[11]/C clock pessimism 0.044 34.950 inter-SLR compensation -0.358 34.592 clock uncertainty -0.085 34.507 SLICE_X42Y485 FDCE (Setup_HFF2_SLICEM_C_CE) -0.058 34.449 SFP_GEN[42].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[11] ------------------------------------------------------------------- required time 34.449 arrival time -30.743 ------------------------------------------------------------------- slack 3.706 Slack (MET) : 3.731ns (required time - arrival time) Source: i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/WEA[0] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (ipb_clk rise@32.000ns - ipb_clk rise@0.000ns) Data Path Delay: 26.803ns (logic 0.501ns (1.869%) route 26.302ns (98.131%)) Logic Levels: 2 (LUT2=1 LUT5=1) Clock Path Skew: -0.305ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.076ns = ( 35.076 - 32.000 ) Source Clock Delay (SCD): 3.425ns Clock Pessimism Removal (CPR): 0.044ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.384ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.076ns Common Clock Delay (CCD): 0.519ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.425ns (routing 0.563ns, distribution 2.862ns) Clock Net Delay (Destination): 3.076ns (routing 0.519ns, distribution 2.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.425 3.425 i_AXI4_to_ipbus/ipb_clk SLICE_X99Y53 FDRE r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/C ------------------------------------------------------------------- ------------------- SLICE_X99Y53 FDRE (Prop_EFF_SLICEL_C_Q) 0.139 3.564 r i_AXI4_to_ipbus/ipb_out_reg[ipb_write]/Q net (fo=10950, routed) 25.142 28.706 i_AXI4_to_ipbus/ipb_mosi[0][ipb_write] SLR Crossing[0->1] SLICE_X13Y541 LUT5 (Prop_F6LUT_SLICEM_I3_O) 0.245 28.951 r i_AXI4_to_ipbus/BRAM_l_i_1__597/O net (fo=1, routed) 0.076 29.027 SFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/wea[0] SLICE_X13Y541 LUT2 (Prop_H5LUT_SLICEM_I0_O) 0.117 29.144 r SFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2/O net (fo=8, routed) 1.084 30.228 SFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1_i_2_n_0 RAMB36_X1Y110 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/WEA[0] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.076 35.076 SFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X1Y110 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK clock pessimism 0.044 35.120 inter-SLR compensation -0.384 34.736 clock uncertainty -0.085 34.652 RAMB36_X1Y110 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[0]) -0.693 33.959 SFP_GEN[42].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 ------------------------------------------------------------------- required time 33.959 arrival time -30.228 ------------------------------------------------------------------- slack 3.731 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[31].ngCCM_gbt/IPbus_gen[9].IPbus_local_inst/IPbus_DataOut_reg[15]/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[31].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/data_pro_test.status_rep_reg[7]/D (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.158ns (logic 0.063ns (39.873%) route 0.095ns (60.127%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.957ns Clock Pessimism Removal (CPR): 0.111ns Clock Net Delay (Source): 0.957ns (routing 0.185ns, distribution 0.772ns) Clock Net Delay (Destination): 1.140ns (routing 0.206ns, distribution 0.934ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 0.957 0.957 SFP_GEN[31].ngCCM_gbt/IPbus_gen[9].IPbus_local_inst/IPbus_clk SLICE_X57Y269 FDRE r SFP_GEN[31].ngCCM_gbt/IPbus_gen[9].IPbus_local_inst/IPbus_DataOut_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y269 FDRE (Prop_EFF2_SLICEL_C_Q) 0.048 1.005 r SFP_GEN[31].ngCCM_gbt/IPbus_gen[9].IPbus_local_inst/IPbus_DataOut_reg[15]/Q net (fo=4, routed) 0.081 1.086 SFP_GEN[31].ngFEC_module/bram_array[9].RAM/data_pro_test.status_rep_reg[7][10] SLICE_X58Y269 LUT6 (Prop_G6LUT_SLICEM_I2_O) 0.015 1.101 r SFP_GEN[31].ngFEC_module/bram_array[9].RAM/data_pro_test.status_rep[7]_i_1__411/O net (fo=1, routed) 0.014 1.115 SFP_GEN[31].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/data_pro_test.status_rep_reg[7]_2[6] SLICE_X58Y269 FDCE r SFP_GEN[31].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/data_pro_test.status_rep_reg[7]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.140 1.140 SFP_GEN[31].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ipb_clk SLICE_X58Y269 FDCE r SFP_GEN[31].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/data_pro_test.status_rep_reg[7]/C clock pessimism -0.111 1.029 SLICE_X58Y269 FDCE (Hold_GFF_SLICEM_C_D) 0.056 1.085 SFP_GEN[31].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/data_pro_test.status_rep_reg[7] ------------------------------------------------------------------- required time -1.085 arrival time 1.115 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[13].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[30]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[12] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.185ns (logic 0.049ns (26.486%) route 0.136ns (73.514%)) Logic Levels: 0 Clock Path Skew: 0.126ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.508ns Source Clock Delay (SCD): 1.243ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 1.243ns (routing 0.185ns, distribution 1.058ns) Clock Net Delay (Destination): 1.508ns (routing 0.206ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.243 1.243 SFP_GEN[13].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ipb_clk SLR Crossing[0->1] SLICE_X116Y324 FDCE r SFP_GEN[13].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[30]/C ------------------------------------------------------------------- ------------------- SLICE_X116Y324 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.292 r SFP_GEN[13].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[30]/Q net (fo=2, routed) 0.136 1.428 SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/dinb[30] RAMB36_X14Y64 RAMB36E2 r SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[12] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.508 1.508 SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X14Y64 RAMB36E2 r SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK clock pessimism -0.139 1.369 RAMB36_X14Y64 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[12]) 0.029 1.398 SFP_GEN[13].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 ------------------------------------------------------------------- required time -1.398 arrival time 1.428 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[42].ngFEC_module/bkp_buffer_ngccm/ngccm_din_reg[11]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[11] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.148ns (logic 0.048ns (32.432%) route 0.100ns (67.568%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.461ns Source Clock Delay (SCD): 1.215ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.215ns (routing 0.185ns, distribution 1.030ns) Clock Net Delay (Destination): 1.461ns (routing 0.206ns, distribution 1.255ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.215 1.215 SFP_GEN[42].ngFEC_module/bkp_buffer_ngccm/ipb_clk SLR Crossing[0->1] SLICE_X27Y530 FDCE r SFP_GEN[42].ngFEC_module/bkp_buffer_ngccm/ngccm_din_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y530 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.263 r SFP_GEN[42].ngFEC_module/bkp_buffer_ngccm/ngccm_din_reg[11]/Q net (fo=2, routed) 0.100 1.363 SFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/dinb[11] RAMB36_X3Y105 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[11] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.461 1.461 SFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X3Y105 RAMB36E2 r SFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK clock pessimism -0.157 1.304 RAMB36_X3Y105 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[11]) 0.029 1.333 SFP_GEN[42].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time -1.333 arrival time 1.363 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[39].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/ngccm_din_reg[13]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[13] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.193ns (logic 0.048ns (24.870%) route 0.145ns (75.130%)) Logic Levels: 0 Clock Path Skew: 0.134ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.492ns Source Clock Delay (SCD): 1.226ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 1.226ns (routing 0.185ns, distribution 1.041ns) Clock Net Delay (Destination): 1.492ns (routing 0.206ns, distribution 1.286ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.226 1.226 SFP_GEN[39].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/ipb_clk SLR Crossing[0->1] SLICE_X10Y466 FDCE r SFP_GEN[39].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/ngccm_din_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y466 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.274 r SFP_GEN[39].ngFEC_module/i2c_comm_gen[0].buffer_ngccm/ngccm_din_reg[13]/Q net (fo=2, routed) 0.145 1.419 SFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/dinb[13] RAMB36_X1Y93 RAMB36E2 r SFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[13] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.492 1.492 SFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X1Y93 RAMB36E2 r SFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK clock pessimism -0.132 1.360 RAMB36_X1Y93 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[13]) 0.029 1.389 SFP_GEN[39].ngFEC_module/bram_array[0].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time -1.389 arrival time 1.419 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[5].ngFEC_module/buffer_ngccm_jtag/ngccm_din_reg[0]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[5].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[0] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.147ns (logic 0.048ns (32.653%) route 0.099ns (67.347%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 1.098ns (routing 0.185ns, distribution 0.913ns) Clock Net Delay (Destination): 1.327ns (routing 0.206ns, distribution 1.121ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.098 1.098 SFP_GEN[5].ngFEC_module/buffer_ngccm_jtag/ipb_clk SLICE_X81Y110 FDCE r SFP_GEN[5].ngFEC_module/buffer_ngccm_jtag/ngccm_din_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y110 FDCE (Prop_HFF_SLICEL_C_Q) 0.048 1.146 r SFP_GEN[5].ngFEC_module/buffer_ngccm_jtag/ngccm_din_reg[0]/Q net (fo=2, routed) 0.099 1.245 SFP_GEN[5].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/dinb[0] RAMB36_X10Y22 RAMB36E2 r SFP_GEN[5].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[0] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.327 1.327 SFP_GEN[5].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/clka RAMB36_X10Y22 RAMB36E2 r SFP_GEN[5].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK clock pessimism -0.141 1.186 RAMB36_X10Y22 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[0]) 0.029 1.215 SFP_GEN[5].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time -1.215 arrival time 1.245 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[41].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[15]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DINADIN[15] (rising edge-triggered cell RAMB18E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.181ns (logic 0.049ns (27.072%) route 0.132ns (72.928%)) Logic Levels: 0 Clock Path Skew: 0.122ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.284ns Source Clock Delay (SCD): 1.057ns Clock Pessimism Removal (CPR): 0.105ns Clock Net Delay (Source): 1.057ns (routing 0.185ns, distribution 0.872ns) Clock Net Delay (Destination): 1.284ns (routing 0.206ns, distribution 1.078ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.057 1.057 SFP_GEN[41].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ipb_clk SLR Crossing[0->1] SLICE_X68Y509 FDCE r SFP_GEN[41].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X68Y509 FDCE (Prop_BFF_SLICEL_C_Q) 0.049 1.106 r SFP_GEN[41].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[15]/Q net (fo=2, routed) 0.132 1.238 SFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/dina[15] RAMB18_X8Y202 RAMB18E2 r SFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DINADIN[15] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.284 1.284 SFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB18_X8Y202 RAMB18E2 r SFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism -0.105 1.179 RAMB18_X8Y202 RAMB18E2 (Hold_RAMB18E2_L_RAMB180_CLKBWRCLK_DINADIN[15]) 0.029 1.208 SFP_GEN[41].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time -1.208 arrival time 1.238 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[22].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[1]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[1] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: 0.129ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.353ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.117ns Clock Net Delay (Source): 1.107ns (routing 0.185ns, distribution 0.922ns) Clock Net Delay (Destination): 1.353ns (routing 0.206ns, distribution 1.147ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.107 1.107 SFP_GEN[22].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ipb_clk SLR Crossing[0->1] SLICE_X80Y448 FDCE r SFP_GEN[22].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y448 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 1.156 r SFP_GEN[22].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[1]/Q net (fo=2, routed) 0.139 1.295 SFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/dinb[1] RAMB36_X10Y89 RAMB36E2 r SFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[1] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.353 1.353 SFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X10Y89 RAMB36E2 r SFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK clock pessimism -0.117 1.236 RAMB36_X10Y89 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[1]) 0.029 1.265 SFP_GEN[22].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time -1.265 arrival time 1.295 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[19].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[30]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[12] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.186ns (logic 0.048ns (25.806%) route 0.138ns (74.194%)) Logic Levels: 0 Clock Path Skew: 0.127ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.590ns Source Clock Delay (SCD): 1.327ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.327ns (routing 0.185ns, distribution 1.142ns) Clock Net Delay (Destination): 1.590ns (routing 0.206ns, distribution 1.384ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.327 1.327 SFP_GEN[19].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ipb_clk SLR Crossing[0->1] SLICE_X127Y492 FDCE r SFP_GEN[19].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[30]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y492 FDCE (Prop_EFF2_SLICEL_C_Q) 0.048 1.375 r SFP_GEN[19].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[30]/Q net (fo=2, routed) 0.138 1.513 SFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/dinb[30] RAMB36_X15Y98 RAMB36E2 r SFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[12] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.590 1.590 SFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X15Y98 RAMB36E2 r SFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK clock pessimism -0.136 1.454 RAMB36_X15Y98 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[12]) 0.029 1.483 SFP_GEN[19].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 ------------------------------------------------------------------- required time -1.483 arrival time 1.513 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[16].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[24]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[6] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.152ns (logic 0.048ns (31.579%) route 0.104ns (68.421%)) Logic Levels: 0 Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.581ns Source Clock Delay (SCD): 1.312ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 1.312ns (routing 0.185ns, distribution 1.127ns) Clock Net Delay (Destination): 1.581ns (routing 0.206ns, distribution 1.375ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.312 1.312 SFP_GEN[16].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ipb_clk SLR Crossing[0->1] SLICE_X128Y400 FDCE r SFP_GEN[16].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X128Y400 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.360 r SFP_GEN[16].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[24]/Q net (fo=2, routed) 0.104 1.464 SFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/dinb[24] RAMB36_X16Y80 RAMB36E2 r SFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[6] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.581 1.581 SFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/clka SLR Crossing[0->1] RAMB36_X16Y80 RAMB36E2 r SFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK clock pessimism -0.176 1.405 RAMB36_X16Y80 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[6]) 0.029 1.434 SFP_GEN[16].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1 ------------------------------------------------------------------- required time -1.434 arrival time 1.464 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[24].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ngccm_din_reg[1]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: SFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[1] (rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.191ns (logic 0.048ns (25.131%) route 0.143ns (74.869%)) Logic Levels: 0 Clock Path Skew: 0.132ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.577ns Source Clock Delay (SCD): 1.304ns Clock Pessimism Removal (CPR): 0.141ns Clock Net Delay (Source): 1.304ns (routing 0.185ns, distribution 1.119ns) Clock Net Delay (Destination): 1.577ns (routing 0.206ns, distribution 1.371ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.304 1.304 SFP_GEN[24].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ipb_clk SLICE_X135Y250 FDCE r SFP_GEN[24].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ngccm_din_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X135Y250 FDCE (Prop_GFF2_SLICEL_C_Q) 0.048 1.352 r SFP_GEN[24].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ngccm_din_reg[1]/Q net (fo=2, routed) 0.143 1.495 SFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/dinb[1] RAMB36_X17Y50 RAMB36E2 r SFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[1] ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.577 1.577 SFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/clka RAMB36_X17Y50 RAMB36E2 r SFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK clock pessimism -0.141 1.436 RAMB36_X17Y50 RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[1]) 0.029 1.465 SFP_GEN[24].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0 ------------------------------------------------------------------- required time -1.465 arrival time 1.495 ------------------------------------------------------------------- slack 0.030 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ipb_clk Waveform(ns): { 0.000 16.000 } Period(ns): 32.000 Sources: { i_ipb_clk_bufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 32.000 30.095 RAMB36_X7Y15 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.905 32.000 30.095 RAMB36_X7Y15 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 32.000 30.095 RAMB36_X11Y14 SFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.905 32.000 30.095 RAMB36_X11Y14 SFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 32.000 30.095 RAMB36_X8Y15 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.905 32.000 30.095 RAMB36_X8Y15 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 32.000 30.095 RAMB36_X11Y13 SFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.905 32.000 30.095 RAMB36_X11Y13 SFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK Min Period n/a RAMB18E2/CLKARDCLK n/a 1.905 32.000 30.095 RAMB18_X15Y22 SFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Min Period n/a RAMB18E2/CLKBWRCLK n/a 1.905 32.000 30.095 RAMB18_X15Y22 SFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB36_X7Y15 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB36_X11Y14 SFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X8Y15 SFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB36_X11Y13 SFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK Low Pulse Width Slow RAMB18E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB18_X15Y22 SFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Low Pulse Width Fast RAMB18E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB18_X15Y22 SFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Low Pulse Width Fast RAMB18E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB18_X1Y18 SFP_GEN[1].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X2Y10 SFP_GEN[1].ngFEC_module/bram_array[1].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X15Y10 SFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X16Y11 SFP_GEN[7].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK High Pulse Width Fast RAMB18E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB18_X16Y24 SFP_GEN[7].ngFEC_module/bram_array[4].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK High Pulse Width Slow RAMB18E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB18_X1Y22 SFP_GEN[1].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X3Y10 SFP_GEN[1].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB36_X14Y13 SFP_GEN[7].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK High Pulse Width Slow RAMB18E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB18_X5Y168 SFP_GEN[40].ngFEC_module/bram_array[0].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Fast RAMB18E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB18_X4Y192 SFP_GEN[40].ngFEC_module/bram_array[10].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X7Y88 SFP_GEN[40].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB36_X6Y87 SFP_GEN[40].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 16.000 15.048 RAMB36_X6Y97 SFP_GEN[40].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK High Pulse Width Slow RAMB18E2/CLKARDCLK n/a 0.952 16.000 15.048 RAMB18_X1Y9 SFP_GEN[0].ngFEC_module/bram_array[1].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK --------------------------------------------------------------------------------------------------- From Clock: refclk125 To Clock: refclk125 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 1.600ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: refclk125 Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { refclk125_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG_GT/I n/a 1.587 8.000 6.413 BUFG_GT_X1Y7 i_refclk125_bufg/I Min Period n/a MMCME3_ADV/CLKIN1 n/a 1.250 8.000 6.750 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKIN1 Low Pulse Width Slow MMCME3_ADV/CLKIN1 n/a 2.400 4.000 1.600 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKIN1 Low Pulse Width Fast MMCME3_ADV/CLKIN1 n/a 2.400 4.000 1.600 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKIN1 High Pulse Width Slow MMCME3_ADV/CLKIN1 n/a 2.400 4.000 1.600 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKIN1 High Pulse Width Fast MMCME3_ADV/CLKIN1 n/a 2.400 4.000 1.600 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: DRPclk_dcm To Clock: DRPclk_dcm Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 18.413ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: DRPclk_dcm Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { i_clk125_MMCM/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 20.000 18.413 BUFGCE_X1Y109 i_DRPclk_bufg/I Min Period n/a MMCME3_ADV/CLKOUT0 n/a 1.250 20.000 18.750 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKOUT0 --------------------------------------------------------------------------------------------------- From Clock: clk125_dcm To Clock: clk125_dcm Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 6.413ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk125_dcm Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { i_clk125_MMCM/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 8.000 6.413 BUFGCE_X1Y111 i_clk125_bufg/I Min Period n/a MMCME3_ADV/CLKFBOUT n/a 1.250 8.000 6.750 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: clk250_dcm To Clock: clk250_dcm Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 2.413ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk250_dcm Waveform(ns): { 0.000 2.000 } Period(ns): 4.000 Sources: { i_clk125_MMCM/CLKOUT3 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 4.000 2.413 BUFGCE_X1Y118 i_clk250_bufg/I Min Period n/a MMCME3_ADV/CLKOUT3 n/a 1.250 4.000 2.750 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKOUT3 --------------------------------------------------------------------------------------------------- From Clock: ipb_clk_dcm To Clock: ipb_clk_dcm Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 30.413ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ipb_clk_dcm Waveform(ns): { 0.000 16.000 } Period(ns): 32.000 Sources: { i_clk125_MMCM/CLKOUT2 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFGCE/I n/a 1.587 32.000 30.413 BUFGCE_X1Y96 i_ipb_clk_bufg/I Min Period n/a MMCME3_ADV/CLKOUT2 n/a 1.250 32.000 30.750 MMCME3_ADV_X1Y4 i_clk125_MMCM/CLKOUT2 --------------------------------------------------------------------------------------------------- From Clock: rxoutclk_out[0] To Clock: rxoutclk_out[0] Setup : 0 Failing Endpoints, Worst Slack 3.825ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.495ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.825ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[28]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_reg/D (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 2.418ns (logic 0.715ns (29.570%) route 1.703ns (70.430%)) Logic Levels: 3 (LUT4=1 LUT5=2) Clock Path Skew: -0.185ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.328ns = ( 7.728 - 6.400 ) Source Clock Delay (SCD): 1.619ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.144ns (routing 0.114ns, distribution 1.030ns) Clock Net Delay (Destination): 0.930ns (routing 0.097ns, distribution 0.833ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.144 1.619 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X119Y45 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[28]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y45 FDRE (Prop_BFF2_SLICEM_C_Q) 0.138 1.757 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[28]/Q net (fo=2, routed) 0.606 2.363 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg_n_0_[28] SLICE_X119Y45 LUT4 (Prop_H6LUT_SLICEM_I2_O) 0.244 2.607 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_7/O net (fo=1, routed) 0.158 2.765 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_7_n_0 SLICE_X119Y44 LUT5 (Prop_G6LUT_SLICEM_I4_O) 0.089 2.854 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_5/O net (fo=1, routed) 0.444 3.298 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_5_n_0 SLICE_X119Y44 LUT5 (Prop_H6LUT_SLICEM_I4_O) 0.244 3.542 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_2/O net (fo=2, routed) 0.495 4.037 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect SLICE_X121Y44 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_reg/D ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.930 7.728 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X121Y44 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_reg/C clock pessimism 0.106 7.834 clock uncertainty -0.035 7.799 SLICE_X121Y44 FDRE (Setup_AFF_SLICEL_C_D) 0.063 7.862 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_reg ------------------------------------------------------------------- required time 7.862 arrival time -4.037 ------------------------------------------------------------------- slack 3.825 Slack (MET) : 3.973ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[28]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/cb_fifo_din_detect_q_reg/D (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 2.269ns (logic 0.715ns (31.512%) route 1.554ns (68.488%)) Logic Levels: 3 (LUT4=1 LUT5=2) Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.326ns = ( 7.726 - 6.400 ) Source Clock Delay (SCD): 1.619ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.144ns (routing 0.114ns, distribution 1.030ns) Clock Net Delay (Destination): 0.928ns (routing 0.097ns, distribution 0.831ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.144 1.619 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X119Y45 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[28]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y45 FDRE (Prop_BFF2_SLICEM_C_Q) 0.138 1.757 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[28]/Q net (fo=2, routed) 0.606 2.363 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg_n_0_[28] SLICE_X119Y45 LUT4 (Prop_H6LUT_SLICEM_I2_O) 0.244 2.607 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_7/O net (fo=1, routed) 0.158 2.765 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_7_n_0 SLICE_X119Y44 LUT5 (Prop_G6LUT_SLICEM_I4_O) 0.089 2.854 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_5/O net (fo=1, routed) 0.444 3.298 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_5_n_0 SLICE_X119Y44 LUT5 (Prop_H6LUT_SLICEM_I4_O) 0.244 3.542 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect_dlyd_i_2/O net (fo=2, routed) 0.346 3.888 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/any_vld_btf_fifo_din_detect SLICE_X121Y44 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/cb_fifo_din_detect_q_reg/D ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.928 7.726 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X121Y44 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/cb_fifo_din_detect_q_reg/C clock pessimism 0.106 7.832 clock uncertainty -0.035 7.797 SLICE_X121Y44 FDRE (Setup_GFF_SLICEL_C_D) 0.064 7.861 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/cb_fifo_din_detect_q_reg ------------------------------------------------------------------- required time 7.861 arrival time -3.888 ------------------------------------------------------------------- slack 3.973 Slack (MET) : 4.126ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/CC_detect_pulse_r_reg/D (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 2.163ns (logic 0.672ns (31.068%) route 1.491ns (68.932%)) Logic Levels: 3 (LUT3=1 LUT4=1 LUT5=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.346ns = ( 7.746 - 6.400 ) Source Clock Delay (SCD): 1.592ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.117ns (routing 0.114ns, distribution 1.003ns) Clock Net Delay (Destination): 0.948ns (routing 0.097ns, distribution 0.851ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.117 1.592 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X123Y38 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/C ------------------------------------------------------------------- ------------------- SLICE_X123Y38 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 1.732 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/Q net (fo=2, routed) 0.379 2.111 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/Q[28] SLICE_X120Y40 LUT4 (Prop_H6LUT_SLICEL_I0_O) 0.167 2.278 f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3/O net (fo=4, routed) 0.197 2.475 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3_n_0 SLICE_X121Y40 LUT5 (Prop_C6LUT_SLICEL_I4_O) 0.219 2.694 f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_2/O net (fo=1, routed) 0.332 3.026 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_2_n_0 SLICE_X121Y40 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 3.172 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_1/O net (fo=2, routed) 0.583 3.755 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/D[1] SLICE_X120Y43 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/CC_detect_pulse_r_reg/D ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.948 7.746 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X120Y43 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/CC_detect_pulse_r_reg/C clock pessimism 0.106 7.852 clock uncertainty -0.035 7.817 SLICE_X120Y43 FDRE (Setup_EFF_SLICEL_C_D) 0.064 7.881 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/CC_detect_pulse_r_reg ------------------------------------------------------------------- required time 7.881 arrival time -3.755 ------------------------------------------------------------------- slack 4.126 Slack (MET) : 4.133ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[36]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_reg/D (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 1.970ns (logic 0.522ns (26.497%) route 1.448ns (73.503%)) Logic Levels: 3 (LUT5=1 LUT6=2) Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.346ns = ( 7.746 - 6.400 ) Source Clock Delay (SCD): 1.767ns Clock Pessimism Removal (CPR): 0.096ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.292ns (routing 0.114ns, distribution 1.178ns) Clock Net Delay (Destination): 0.948ns (routing 0.097ns, distribution 0.851ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.292 1.767 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X117Y46 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[36]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y46 FDRE (Prop_CFF2_SLICEL_C_Q) 0.139 1.906 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[36]/Q net (fo=2, routed) 0.806 2.712 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/en32_fifo_din_i[76] SLICE_X117Y47 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.147 2.859 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_7/O net (fo=1, routed) 0.234 3.093 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_7_n_0 SLICE_X117Y45 LUT6 (Prop_H6LUT_SLICEL_I5_O) 0.089 3.182 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_2/O net (fo=1, routed) 0.373 3.555 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT1__15 SLICE_X120Y43 LUT5 (Prop_H6LUT_SLICEL_I2_O) 0.147 3.702 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_1/O net (fo=1, routed) 0.035 3.737 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_i_1_n_0 SLICE_X120Y43 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_reg/D ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.948 7.746 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X120Y43 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_reg/C clock pessimism 0.096 7.842 clock uncertainty -0.035 7.807 SLICE_X120Y43 FDRE (Setup_HFF_SLICEL_C_D) 0.063 7.870 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/FIRST_CB_BITERR_CB_RESET_OUT_reg ------------------------------------------------------------------- required time 7.870 arrival time -3.737 ------------------------------------------------------------------- slack 4.133 Slack (MET) : 4.201ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]/D (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 2.067ns (logic 0.737ns (35.656%) route 1.330ns (64.344%)) Logic Levels: 3 (LUT3=1 LUT4=1 LUT5=1) Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.326ns = ( 7.726 - 6.400 ) Source Clock Delay (SCD): 1.592ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.117ns (routing 0.114ns, distribution 1.003ns) Clock Net Delay (Destination): 0.928ns (routing 0.097ns, distribution 0.831ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.117 1.592 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X123Y38 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/C ------------------------------------------------------------------- ------------------- SLICE_X123Y38 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 1.732 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/Q net (fo=2, routed) 0.379 2.111 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/Q[28] SLICE_X120Y40 LUT4 (Prop_H6LUT_SLICEL_I0_O) 0.167 2.278 f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3/O net (fo=4, routed) 0.197 2.475 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3_n_0 SLICE_X121Y40 LUT5 (Prop_C5LUT_SLICEL_I0_O) 0.243 2.718 f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/wdth_conv_1stage[38]_i_2/O net (fo=1, routed) 0.404 3.122 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/wdth_conv_1stage[38]_i_2_n_0 SLICE_X121Y40 LUT3 (Prop_D5LUT_SLICEL_I1_O) 0.187 3.309 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/wdth_conv_1stage[38]_i_1/O net (fo=1, routed) 0.350 3.659 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/D[0] SLICE_X121Y42 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]/D ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.928 7.726 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X121Y42 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]/C clock pessimism 0.106 7.832 clock uncertainty -0.035 7.797 SLICE_X121Y42 FDRE (Setup_CFF_SLICEL_C_D) 0.063 7.860 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38] ------------------------------------------------------------------- required time 7.860 arrival time -3.659 ------------------------------------------------------------------- slack 4.201 Slack (MET) : 4.224ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[39]/D (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 2.065ns (logic 0.672ns (32.542%) route 1.393ns (67.458%)) Logic Levels: 3 (LUT3=1 LUT4=1 LUT5=1) Clock Path Skew: -0.138ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.348ns = ( 7.748 - 6.400 ) Source Clock Delay (SCD): 1.592ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.117ns (routing 0.114ns, distribution 1.003ns) Clock Net Delay (Destination): 0.950ns (routing 0.097ns, distribution 0.853ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.117 1.592 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X123Y38 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/C ------------------------------------------------------------------- ------------------- SLICE_X123Y38 FDRE (Prop_AFF_SLICEL_C_Q) 0.140 1.732 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/unscrambled_data_i_reg[28]/Q net (fo=2, routed) 0.379 2.111 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/Q[28] SLICE_X120Y40 LUT4 (Prop_H6LUT_SLICEL_I0_O) 0.167 2.278 f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3/O net (fo=4, routed) 0.197 2.475 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_dlyd1_i_3_n_0 SLICE_X121Y40 LUT5 (Prop_C6LUT_SLICEL_I4_O) 0.219 2.694 f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_2/O net (fo=1, routed) 0.332 3.026 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_2_n_0 SLICE_X121Y40 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 3.172 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/descrambler_64b66b_gtx0_i/CC_detect_pulse_r_i_1/O net (fo=2, routed) 0.485 3.657 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/D[1] SLICE_X120Y43 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[39]/D ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.950 7.748 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X120Y43 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[39]/C clock pessimism 0.106 7.854 clock uncertainty -0.035 7.819 SLICE_X120Y43 FDRE (Setup_BFF_SLICEL_C_D) 0.062 7.881 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[39] ------------------------------------------------------------------- required time 7.881 arrival time -3.657 ------------------------------------------------------------------- slack 4.224 Slack (MET) : 4.306ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[34]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[37]/CE (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 1.852ns (logic 0.283ns (15.281%) route 1.569ns (84.719%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.326ns = ( 7.726 - 6.400 ) Source Clock Delay (SCD): 1.585ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.110ns (routing 0.114ns, distribution 0.996ns) Clock Net Delay (Destination): 0.928ns (routing 0.097ns, distribution 0.831ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.110 1.585 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X119Y42 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[34]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y42 FDRE (Prop_DFF2_SLICEM_C_Q) 0.137 1.722 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[34]/Q net (fo=4, routed) 0.530 2.252 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/p_1_in SLICE_X121Y43 LUT6 (Prop_F6LUT_SLICEL_I4_O) 0.146 2.398 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage[39]_i_1/O net (fo=43, routed) 1.039 3.437 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/mod_do_wr_en SLICE_X121Y42 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[37]/CE ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.928 7.726 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X121Y42 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[37]/C clock pessimism 0.106 7.832 clock uncertainty -0.035 7.797 SLICE_X121Y42 FDRE (Setup_DFF_SLICEL_C_CE) -0.054 7.743 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[37] ------------------------------------------------------------------- required time 7.743 arrival time -3.437 ------------------------------------------------------------------- slack 4.306 Slack (MET) : 4.306ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[34]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]/CE (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 1.852ns (logic 0.283ns (15.281%) route 1.569ns (84.719%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.326ns = ( 7.726 - 6.400 ) Source Clock Delay (SCD): 1.585ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.110ns (routing 0.114ns, distribution 0.996ns) Clock Net Delay (Destination): 0.928ns (routing 0.097ns, distribution 0.831ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.110 1.585 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X119Y42 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[34]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y42 FDRE (Prop_DFF2_SLICEM_C_Q) 0.137 1.722 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[34]/Q net (fo=4, routed) 0.530 2.252 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/p_1_in SLICE_X121Y43 LUT6 (Prop_F6LUT_SLICEL_I4_O) 0.146 2.398 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage[39]_i_1/O net (fo=43, routed) 1.039 3.437 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/mod_do_wr_en SLICE_X121Y42 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]/CE ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.928 7.726 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X121Y42 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38]/C clock pessimism 0.106 7.832 clock uncertainty -0.035 7.797 SLICE_X121Y42 FDRE (Setup_CFF_SLICEL_C_CE) -0.054 7.743 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_1stage_reg[38] ------------------------------------------------------------------- required time 7.743 arrival time -3.437 ------------------------------------------------------------------- slack 4.306 Slack (MET) : 4.321ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/u_cdc_rx_elastic_buferr/p_level_in_d1_cdc_from_reg/D (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 2.082ns (logic 1.267ns (60.855%) route 0.815ns (39.145%)) Logic Levels: 0 Clock Path Skew: -0.027ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.323ns = ( 7.723 - 6.400 ) Source Clock Delay (SCD): 1.456ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 0.981ns (routing 0.114ns, distribution 0.867ns) Clock Net Delay (Destination): 0.925ns (routing 0.097ns, distribution 0.828ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.981 1.456 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk2_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXBUFSTATUS[2]) 1.267 2.723 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXBUFSTATUS[2] net (fo=1, routed) 0.815 3.538 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/u_cdc_rx_elastic_buferr/rxbufstatus_out[0] SLICE_X132Y16 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/u_cdc_rx_elastic_buferr/p_level_in_d1_cdc_from_reg/D ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.925 7.723 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/u_cdc_rx_elastic_buferr/gtwiz_userclk_rx_usrclk_out SLICE_X132Y16 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/u_cdc_rx_elastic_buferr/p_level_in_d1_cdc_from_reg/C clock pessimism 0.106 7.829 clock uncertainty -0.035 7.794 SLICE_X132Y16 FDRE (Setup_EFF2_SLICEL_C_D) 0.065 7.859 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/u_cdc_rx_elastic_buferr/p_level_in_d1_cdc_from_reg ------------------------------------------------------------------- required time 7.859 arrival time -3.538 ------------------------------------------------------------------- slack 4.321 Slack (MET) : 4.336ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 (rising edge-triggered cell GTHE3_CHANNEL clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r1_rxdata_from_gtx_i_reg[24]/D (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Setup (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 2.075ns (logic 1.173ns (56.530%) route 0.902ns (43.470%)) Logic Levels: 0 Clock Path Skew: -0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.332ns = ( 7.732 - 6.400 ) Source Clock Delay (SCD): 1.456ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 0.981ns (routing 0.114ns, distribution 0.867ns) Clock Net Delay (Destination): 0.934ns (routing 0.097ns, distribution 0.837ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.981 1.456 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk2_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[24]) 1.173 2.629 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[24] net (fo=1, routed) 0.902 3.531 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_rxdata_from_gtx_i[24] SLICE_X137Y15 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r1_rxdata_from_gtx_i_reg[24]/D ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.934 7.732 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/rxusrclk_out SLICE_X137Y15 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r1_rxdata_from_gtx_i_reg[24]/C clock pessimism 0.106 7.838 clock uncertainty -0.035 7.803 SLICE_X137Y15 FDRE (Setup_EFF_SLICEL_C_D) 0.064 7.867 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r1_rxdata_from_gtx_i_reg[24] ------------------------------------------------------------------- required time 7.867 arrival time -3.531 ------------------------------------------------------------------- slack 4.336 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[14]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[14] (rising edge-triggered cell FIFO36E2 clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.147ns (logic 0.049ns (33.333%) route 0.098ns (66.667%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.809ns Source Clock Delay (SCD): 0.610ns Clock Pessimism Removal (CPR): 0.111ns Clock Net Delay (Source): 0.492ns (routing 0.059ns, distribution 0.433ns) Clock Net Delay (Destination): 0.644ns (routing 0.075ns, distribution 0.569ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.492 0.610 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X117Y47 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y47 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 0.659 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[14]/Q net (fo=2, routed) 0.098 0.757 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/din[14] RAMB36_X14Y9 FIFO36E2 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[14] ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.644 0.809 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/wr_clk RAMB36_X14Y9 FIFO36E2 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK clock pessimism -0.111 0.698 RAMB36_X14Y9 FIFO36E2 (Hold_FIFO36E2_FIFO36_WRCLK_DIN[14]) 0.029 0.727 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2 ------------------------------------------------------------------- required time -0.727 arrival time 0.757 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.032ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[15]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[15] (rising edge-triggered cell FIFO36E2 clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.199ns (logic 0.048ns (24.121%) route 0.151ns (75.879%)) Logic Levels: 0 Clock Path Skew: 0.138ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.809ns Source Clock Delay (SCD): 0.604ns Clock Pessimism Removal (CPR): 0.067ns Clock Net Delay (Source): 0.486ns (routing 0.059ns, distribution 0.427ns) Clock Net Delay (Destination): 0.644ns (routing 0.075ns, distribution 0.569ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.486 0.604 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X118Y45 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X118Y45 FDRE (Prop_GFF2_SLICEM_C_Q) 0.048 0.652 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[15]/Q net (fo=2, routed) 0.151 0.803 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/din[15] RAMB36_X14Y9 FIFO36E2 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[15] ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.644 0.809 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/wr_clk RAMB36_X14Y9 FIFO36E2 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK clock pessimism -0.067 0.742 RAMB36_X14Y9 FIFO36E2 (Hold_FIFO36E2_FIFO36_WRCLK_DIN[15]) 0.029 0.771 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2 ------------------------------------------------------------------- required time -0.771 arrival time 0.803 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.033ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[24]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[24] (rising edge-triggered cell FIFO36E2 clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.253ns (logic 0.048ns (18.972%) route 0.205ns (81.028%)) Logic Levels: 0 Clock Path Skew: 0.191ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.809ns Source Clock Delay (SCD): 0.548ns Clock Pessimism Removal (CPR): 0.070ns Clock Net Delay (Source): 0.430ns (routing 0.059ns, distribution 0.371ns) Clock Net Delay (Destination): 0.644ns (routing 0.075ns, distribution 0.569ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.430 0.548 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X120Y43 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X120Y43 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 0.596 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[24]/Q net (fo=2, routed) 0.205 0.801 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/din[24] RAMB36_X14Y9 FIFO36E2 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[24] ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.644 0.809 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/wr_clk RAMB36_X14Y9 FIFO36E2 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK clock pessimism -0.070 0.739 RAMB36_X14Y9 FIFO36E2 (Hold_FIFO36E2_FIFO36_WRCLK_DIN[24]) 0.029 0.768 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2 ------------------------------------------------------------------- required time -0.768 arrival time 0.801 ------------------------------------------------------------------- slack 0.033 Slack (MET) : 0.035ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[30]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[30] (rising edge-triggered cell FIFO36E2 clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.260ns (logic 0.048ns (18.462%) route 0.212ns (81.538%)) Logic Levels: 0 Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.809ns Source Clock Delay (SCD): 0.543ns Clock Pessimism Removal (CPR): 0.070ns Clock Net Delay (Source): 0.425ns (routing 0.059ns, distribution 0.366ns) Clock Net Delay (Destination): 0.644ns (routing 0.075ns, distribution 0.569ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.425 0.543 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X119Y47 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[30]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y47 FDRE (Prop_FFF2_SLICEM_C_Q) 0.048 0.591 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[30]/Q net (fo=2, routed) 0.212 0.803 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/din[30] RAMB36_X14Y9 FIFO36E2 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[30] ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.644 0.809 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/wr_clk RAMB36_X14Y9 FIFO36E2 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK clock pessimism -0.070 0.739 RAMB36_X14Y9 FIFO36E2 (Hold_FIFO36E2_FIFO36_WRCLK_DIN[30]) 0.029 0.768 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2 ------------------------------------------------------------------- required time -0.768 arrival time 0.803 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.036ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[39]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DINP[7] (rising edge-triggered cell FIFO36E2 clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.191ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.809ns Source Clock Delay (SCD): 0.548ns Clock Pessimism Removal (CPR): 0.070ns Clock Net Delay (Source): 0.430ns (routing 0.059ns, distribution 0.371ns) Clock Net Delay (Destination): 0.644ns (routing 0.075ns, distribution 0.569ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.430 0.548 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X120Y43 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[39]/C ------------------------------------------------------------------- ------------------- SLICE_X120Y43 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 0.597 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[39]/Q net (fo=1, routed) 0.207 0.804 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/din[71] RAMB36_X14Y9 FIFO36E2 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DINP[7] ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.644 0.809 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/wr_clk RAMB36_X14Y9 FIFO36E2 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK clock pessimism -0.070 0.739 RAMB36_X14Y9 FIFO36E2 (Hold_FIFO36E2_FIFO36_WRCLK_DINP[7]) 0.029 0.768 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2 ------------------------------------------------------------------- required time -0.768 arrival time 0.804 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.036ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[4]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[4]/D (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.499ns (logic 0.123ns (24.649%) route 0.376ns (75.351%)) Logic Levels: 0 Clock Path Skew: 0.334ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.766ns Source Clock Delay (SCD): 1.336ns Clock Pessimism Removal (CPR): 0.096ns Clock Net Delay (Source): 0.938ns (routing 0.097ns, distribution 0.841ns) Clock Net Delay (Destination): 1.291ns (routing 0.114ns, distribution 1.177ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 0.052 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 0.398 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.938 1.336 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X119Y42 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y42 FDRE (Prop_FFF2_SLICEM_C_Q) 0.123 1.459 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg[4]/Q net (fo=1, routed) 0.376 1.835 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_reg_n_0_[4] SLICE_X117Y44 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[4]/D ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.291 1.766 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X117Y44 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[4]/C clock pessimism -0.096 1.670 SLICE_X117Y44 FDRE (Hold_AFF_SLICEL_C_D) 0.129 1.799 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/raw_data_r_r_reg[4] ------------------------------------------------------------------- required time -1.799 arrival time 1.835 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.036ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[25]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[25]/D (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.477ns (logic 0.122ns (25.577%) route 0.355ns (74.423%)) Logic Levels: 0 Clock Path Skew: 0.314ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.764ns Source Clock Delay (SCD): 1.354ns Clock Pessimism Removal (CPR): 0.096ns Clock Net Delay (Source): 0.956ns (routing 0.097ns, distribution 0.859ns) Clock Net Delay (Destination): 1.289ns (routing 0.114ns, distribution 1.175ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 0.052 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 0.398 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.956 1.354 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X119Y45 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[25]/C ------------------------------------------------------------------- ------------------- SLICE_X119Y45 FDRE (Prop_FFF_SLICEM_C_Q) 0.122 1.476 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[25]/Q net (fo=2, routed) 0.355 1.831 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/en32_fifo_din_i[25] SLICE_X117Y46 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[25]/D ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.289 1.764 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X117Y46 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[25]/C clock pessimism -0.096 1.668 SLICE_X117Y46 FDRE (Hold_FFF2_SLICEL_C_D) 0.127 1.795 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[25] ------------------------------------------------------------------- required time -1.795 arrival time 1.831 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.041ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/rxheader_to_fifo_i_reg[1]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[33].SRLC32E_inst_1/D (rising edge-triggered cell SRL16E clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.230ns (logic 0.049ns (21.304%) route 0.181ns (78.696%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.685ns Source Clock Delay (SCD): 0.527ns Clock Pessimism Removal (CPR): 0.092ns Clock Net Delay (Source): 0.409ns (routing 0.059ns, distribution 0.350ns) Clock Net Delay (Destination): 0.520ns (routing 0.075ns, distribution 0.445ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.409 0.527 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/rxusrclk_out SLICE_X120Y35 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/rxheader_to_fifo_i_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X120Y35 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 0.576 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/rxheader_to_fifo_i_reg[1]/Q net (fo=2, routed) 0.181 0.757 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/Q[1] SLICE_X119Y42 SRL16E r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[33].SRLC32E_inst_1/D ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.520 0.685 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X119Y42 SRL16E r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[33].SRLC32E_inst_1/CLK clock pessimism -0.092 0.593 SLICE_X119Y42 SRL16E (Hold_C5LUT_SLICEM_CLK_D) 0.123 0.716 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[33].SRLC32E_inst_1 ------------------------------------------------------------------- required time -0.716 arrival time 0.757 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[4]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[4]/D (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.143ns (logic 0.048ns (33.566%) route 0.095ns (66.434%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.749ns Source Clock Delay (SCD): 0.604ns Clock Pessimism Removal (CPR): 0.099ns Clock Net Delay (Source): 0.486ns (routing 0.059ns, distribution 0.427ns) Clock Net Delay (Destination): 0.584ns (routing 0.075ns, distribution 0.509ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.486 0.604 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X117Y44 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y44 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 0.652 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_2stage_reg[4]/Q net (fo=2, routed) 0.095 0.747 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/en32_fifo_din_i[4] SLICE_X117Y45 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[4]/D ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.584 0.749 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X117Y45 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[4]/C clock pessimism -0.099 0.650 SLICE_X117Y45 FDRE (Hold_AFF2_SLICEL_C_D) 0.056 0.706 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[4] ------------------------------------------------------------------- required time -0.706 arrival time 0.747 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.042ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[8]/C (rising edge-triggered cell FDRE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[40] (rising edge-triggered cell FIFO36E2 clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: rxoutclk_out[0] Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.177ns (logic 0.048ns (27.119%) route 0.129ns (72.881%)) Logic Levels: 0 Clock Path Skew: 0.106ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.809ns Source Clock Delay (SCD): 0.605ns Clock Pessimism Removal (CPR): 0.098ns Clock Net Delay (Source): 0.487ns (routing 0.059ns, distribution 0.428ns) Clock Net Delay (Destination): 0.644ns (routing 0.075ns, distribution 0.569ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.487 0.605 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/gtwiz_userclk_rx_usrclk_out SLICE_X117Y46 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X117Y46 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 0.653 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wdth_conv_3stage_reg[8]/Q net (fo=1, routed) 0.129 0.782 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/din[40] RAMB36_X14Y9 FIFO36E2 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/DIN[40] ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.644 0.809 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/wr_clk RAMB36_X14Y9 FIFO36E2 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK clock pessimism -0.098 0.711 RAMB36_X14Y9 FIFO36E2 (Hold_FIFO36E2_FIFO36_WRCLK_DIN[40]) 0.029 0.740 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2 ------------------------------------------------------------------- required time -0.740 arrival time 0.782 ------------------------------------------------------------------- slack 0.042 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxoutclk_out[0] Waveform(ns): { 0.000 3.200 } Period(ns): 6.400 Sources: { i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/RXUSRCLK n/a 2.560 6.400 3.840 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Min Period n/a GTHE3_CHANNEL/RXUSRCLK2 n/a 2.560 6.400 3.840 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Min Period n/a FIFO36E2/WRCLK n/a 1.905 6.400 4.495 RAMB36_X14Y9 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK Min Period n/a BUFG_GT/I n/a 1.587 6.400 4.813 BUFG_GT_X1Y3 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I Min Period n/a SRL16E/CLK n/a 1.356 6.400 5.044 SLICE_X118Y42 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/SRLC32E_inst_4/CLK Min Period n/a SRL16E/CLK n/a 1.356 6.400 5.044 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[0].SRLC32E_inst_1/CLK Min Period n/a SRL16E/CLK n/a 1.356 6.400 5.044 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[10].SRLC32E_inst_1/CLK Min Period n/a SRL16E/CLK n/a 1.356 6.400 5.044 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[11].SRLC32E_inst_1/CLK Min Period n/a SRL16E/CLK n/a 1.356 6.400 5.044 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[12].SRLC32E_inst_1/CLK Min Period n/a SRL16E/CLK n/a 1.356 6.400 5.044 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[13].SRLC32E_inst_1/CLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.152 3.200 2.048 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.152 3.200 2.048 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.152 3.200 2.048 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Low Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.152 3.200 2.048 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Low Pulse Width Fast FIFO36E2/WRCLK n/a 0.952 3.200 2.248 RAMB36_X14Y9 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK Low Pulse Width Slow FIFO36E2/WRCLK n/a 0.952 3.200 2.248 RAMB36_X14Y9 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK Low Pulse Width Slow SRL16E/CLK n/a 0.678 3.200 2.522 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[0].SRLC32E_inst_1/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.678 3.200 2.522 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[10].SRLC32E_inst_1/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.678 3.200 2.522 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[11].SRLC32E_inst_1/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.678 3.200 2.522 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[12].SRLC32E_inst_1/CLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK n/a 1.152 3.200 2.048 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK n/a 1.152 3.200 2.048 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK High Pulse Width Slow GTHE3_CHANNEL/RXUSRCLK2 n/a 1.152 3.200 2.048 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Fast GTHE3_CHANNEL/RXUSRCLK2 n/a 1.152 3.200 2.048 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 High Pulse Width Slow FIFO36E2/WRCLK n/a 0.952 3.200 2.248 RAMB36_X14Y9 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK High Pulse Width Fast FIFO36E2/WRCLK n/a 0.952 3.200 2.248 RAMB36_X14Y9 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/WRCLK High Pulse Width Fast SRL16E/CLK n/a 0.678 3.200 2.522 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[0].SRLC32E_inst_1/CLK High Pulse Width Fast SRL16E/CLK n/a 0.678 3.200 2.522 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[10].SRLC32E_inst_1/CLK High Pulse Width Fast SRL16E/CLK n/a 0.678 3.200 2.522 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[11].SRLC32E_inst_1/CLK High Pulse Width Fast SRL16E/CLK n/a 0.678 3.200 2.522 SLICE_X119Y41 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[12].SRLC32E_inst_1/CLK Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.035 0.495 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.016 0.503 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.016 0.866 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.035 1.293 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: txoutclk_out[0]_48 To Clock: txoutclk_out[0]_48 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.282ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txoutclk_out[0]_48 Waveform(ns): { 0.000 3.200 } Period(ns): 6.400 Sources: { i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG_GT/I n/a 1.587 6.400 4.813 BUFG_GT_X1Y16 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/I Min Period n/a BUFG_GT/I n/a 1.587 6.400 4.813 BUFG_GT_X1Y22 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I Max Skew Slow GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.613 0.331 0.282 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.186 0.334 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK --------------------------------------------------------------------------------------------------- From Clock: axi_c2c_phy_clk To Clock: axi_c2c_phy_clk Setup : 0 Failing Endpoints, Worst Slack 7.984ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.583ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 7.984ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_tdm_inst/tdm_data_valid_reg/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/REGCEAREGCE (rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 4.337ns (logic 0.764ns (17.616%) route 3.573ns (82.384%)) Logic Levels: 3 (LUT3=2 LUT6=1) Clock Path Skew: 0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.123ns = ( 14.923 - 12.800 ) Source Clock Delay (SCD): 2.287ns Clock Pessimism Removal (CPR): 0.201ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.812ns (routing 0.375ns, distribution 1.437ns) Clock Net Delay (Destination): 1.725ns (routing 0.339ns, distribution 1.386ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.812 2.287 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_tdm_inst/axi_c2c_phy_clk SLICE_X120Y29 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_tdm_inst/tdm_data_valid_reg/C ------------------------------------------------------------------- ------------------- SLICE_X120Y29 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 2.425 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_tdm_inst/tdm_data_valid_reg/Q net (fo=8, routed) 1.117 3.542 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_in_reg_slice_inst/tdm_user_data_valid SLICE_X131Y26 LUT3 (Prop_D5LUT_SLICEL_I1_O) 0.168 3.710 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_in_reg_slice_inst/FSM_onehot_state[0]_i_1/O net (fo=2, routed) 0.322 4.032 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_in_reg_slice_inst/FSM_onehot_state[0]_i_1_n_0 SLICE_X131Y26 LUT6 (Prop_B6LUT_SLICEL_I0_O) 0.219 4.251 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_in_reg_slice_inst/s_ready_i_i_1/O net (fo=2, routed) 1.193 5.444 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/pwropt SLICE_X121Y34 LUT3 (Prop_G6LUT_SLICEL_I1_O) 0.239 5.683 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_REGCEAREGCE_cooolgate_en_gate_1/O net (fo=1, routed) 0.941 6.624 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_REGCEAREGCE_cooolgate_en_sig_1 RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/REGCEAREGCE ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.725 14.923 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb RAMB36_X14Y8 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK clock pessimism 0.201 15.124 clock uncertainty -0.035 15.089 RAMB36_X14Y8 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_REGCEAREGCE) -0.481 14.608 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 14.608 arrival time -6.624 ------------------------------------------------------------------- slack 7.984 Slack (MET) : 8.487ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 3.430ns (logic 0.867ns (25.277%) route 2.563ns (74.723%)) Logic Levels: 3 (LUT2=1 LUT3=1 LUT4=1) Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.188ns = ( 14.988 - 12.800 ) Source Clock Delay (SCD): 2.542ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.067ns (routing 0.375ns, distribution 1.692ns) Clock Net Delay (Destination): 1.790ns (routing 0.339ns, distribution 1.451ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.067 2.542 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk SLICE_X107Y51 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y51 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 2.681 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Q net (fo=49, routed) 0.599 3.280 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy SLICE_X107Y52 LUT2 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.538 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/O net (fo=2, routed) 0.438 3.976 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy SLICE_X107Y52 LUT3 (Prop_D5LUT_SLICEM_I1_O) 0.247 4.223 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/O net (fo=4, routed) 0.260 4.483 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X107Y52 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 4.706 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=38, routed) 1.266 5.972 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.790 14.988 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.200 15.188 clock uncertainty -0.035 15.152 RAMB36_X12Y10 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[5]) -0.693 14.459 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 14.459 arrival time -5.972 ------------------------------------------------------------------- slack 8.487 Slack (MET) : 8.491ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 3.426ns (logic 0.867ns (25.306%) route 2.559ns (74.694%)) Logic Levels: 3 (LUT2=1 LUT3=1 LUT4=1) Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.188ns = ( 14.988 - 12.800 ) Source Clock Delay (SCD): 2.542ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.067ns (routing 0.375ns, distribution 1.692ns) Clock Net Delay (Destination): 1.790ns (routing 0.339ns, distribution 1.451ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.067 2.542 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk SLICE_X107Y51 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y51 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 2.681 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Q net (fo=49, routed) 0.599 3.280 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy SLICE_X107Y52 LUT2 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.538 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/O net (fo=2, routed) 0.438 3.976 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy SLICE_X107Y52 LUT3 (Prop_D5LUT_SLICEM_I1_O) 0.247 4.223 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/O net (fo=4, routed) 0.260 4.483 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X107Y52 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 4.706 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=38, routed) 1.262 5.968 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.790 14.988 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.200 15.188 clock uncertainty -0.035 15.152 RAMB36_X12Y10 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[6]) -0.693 14.459 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 14.459 arrival time -5.968 ------------------------------------------------------------------- slack 8.491 Slack (MET) : 8.492ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[7] (rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 3.425ns (logic 0.867ns (25.314%) route 2.558ns (74.686%)) Logic Levels: 3 (LUT2=1 LUT3=1 LUT4=1) Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.188ns = ( 14.988 - 12.800 ) Source Clock Delay (SCD): 2.542ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.067ns (routing 0.375ns, distribution 1.692ns) Clock Net Delay (Destination): 1.790ns (routing 0.339ns, distribution 1.451ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.067 2.542 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk SLICE_X107Y51 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y51 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 2.681 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Q net (fo=49, routed) 0.599 3.280 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy SLICE_X107Y52 LUT2 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.538 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/O net (fo=2, routed) 0.438 3.976 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy SLICE_X107Y52 LUT3 (Prop_D5LUT_SLICEM_I1_O) 0.247 4.223 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/O net (fo=4, routed) 0.260 4.483 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X107Y52 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 4.706 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=38, routed) 1.261 5.967 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[7] ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.790 14.988 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.200 15.188 clock uncertainty -0.035 15.152 RAMB36_X12Y10 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[7]) -0.693 14.459 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 14.459 arrival time -5.967 ------------------------------------------------------------------- slack 8.492 Slack (MET) : 8.506ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[4] (rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 3.411ns (logic 0.867ns (25.418%) route 2.544ns (74.582%)) Logic Levels: 3 (LUT2=1 LUT3=1 LUT4=1) Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.188ns = ( 14.988 - 12.800 ) Source Clock Delay (SCD): 2.542ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.067ns (routing 0.375ns, distribution 1.692ns) Clock Net Delay (Destination): 1.790ns (routing 0.339ns, distribution 1.451ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.067 2.542 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk SLICE_X107Y51 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y51 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 2.681 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Q net (fo=49, routed) 0.599 3.280 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy SLICE_X107Y52 LUT2 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.538 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/O net (fo=2, routed) 0.438 3.976 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy SLICE_X107Y52 LUT3 (Prop_D5LUT_SLICEM_I1_O) 0.247 4.223 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/O net (fo=4, routed) 0.260 4.483 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X107Y52 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 4.706 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=38, routed) 1.247 5.953 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[4] ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.790 14.988 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.200 15.188 clock uncertainty -0.035 15.152 RAMB36_X12Y10 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[4]) -0.693 14.459 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 14.459 arrival time -5.953 ------------------------------------------------------------------- slack 8.506 Slack (MET) : 8.539ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[1] (rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 3.378ns (logic 0.867ns (25.666%) route 2.511ns (74.334%)) Logic Levels: 3 (LUT2=1 LUT3=1 LUT4=1) Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.188ns = ( 14.988 - 12.800 ) Source Clock Delay (SCD): 2.542ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.067ns (routing 0.375ns, distribution 1.692ns) Clock Net Delay (Destination): 1.790ns (routing 0.339ns, distribution 1.451ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.067 2.542 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk SLICE_X107Y51 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y51 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 2.681 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Q net (fo=49, routed) 0.599 3.280 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy SLICE_X107Y52 LUT2 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.538 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/O net (fo=2, routed) 0.438 3.976 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy SLICE_X107Y52 LUT3 (Prop_D5LUT_SLICEM_I1_O) 0.247 4.223 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/O net (fo=4, routed) 0.260 4.483 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X107Y52 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 4.706 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=38, routed) 1.214 5.920 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[1] ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.790 14.988 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.200 15.188 clock uncertainty -0.035 15.152 RAMB36_X12Y10 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[1]) -0.693 14.459 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 14.459 arrival time -5.920 ------------------------------------------------------------------- slack 8.539 Slack (MET) : 8.544ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[0] (rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 3.373ns (logic 0.867ns (25.704%) route 2.506ns (74.296%)) Logic Levels: 3 (LUT2=1 LUT3=1 LUT4=1) Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.188ns = ( 14.988 - 12.800 ) Source Clock Delay (SCD): 2.542ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.067ns (routing 0.375ns, distribution 1.692ns) Clock Net Delay (Destination): 1.790ns (routing 0.339ns, distribution 1.451ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.067 2.542 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk SLICE_X107Y51 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y51 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 2.681 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Q net (fo=49, routed) 0.599 3.280 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy SLICE_X107Y52 LUT2 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.538 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/O net (fo=2, routed) 0.438 3.976 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy SLICE_X107Y52 LUT3 (Prop_D5LUT_SLICEM_I1_O) 0.247 4.223 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/O net (fo=4, routed) 0.260 4.483 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X107Y52 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 4.706 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=38, routed) 1.209 5.915 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[0] ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.790 14.988 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.200 15.188 clock uncertainty -0.035 15.152 RAMB36_X12Y10 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[0]) -0.693 14.459 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 14.459 arrival time -5.915 ------------------------------------------------------------------- slack 8.544 Slack (MET) : 8.610ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 3.465ns (logic 0.867ns (25.022%) route 2.598ns (74.978%)) Logic Levels: 3 (LUT2=1 LUT3=1 LUT4=1) Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.188ns = ( 14.988 - 12.800 ) Source Clock Delay (SCD): 2.542ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.067ns (routing 0.375ns, distribution 1.692ns) Clock Net Delay (Destination): 1.790ns (routing 0.339ns, distribution 1.451ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.067 2.542 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk SLICE_X107Y51 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y51 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 2.681 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Q net (fo=49, routed) 0.599 3.280 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy SLICE_X107Y52 LUT2 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.538 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/O net (fo=2, routed) 0.438 3.976 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy SLICE_X107Y52 LUT3 (Prop_D5LUT_SLICEM_I1_O) 0.247 4.223 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/O net (fo=4, routed) 0.260 4.483 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X107Y52 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 4.706 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=38, routed) 1.301 6.007 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.790 14.988 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.200 15.188 clock uncertainty -0.035 15.152 RAMB36_X12Y10 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN) -0.535 14.617 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 14.617 arrival time -6.007 ------------------------------------------------------------------- slack 8.610 Slack (MET) : 8.646ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[3] (rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 3.271ns (logic 0.867ns (26.506%) route 2.404ns (73.494%)) Logic Levels: 3 (LUT2=1 LUT3=1 LUT4=1) Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.188ns = ( 14.988 - 12.800 ) Source Clock Delay (SCD): 2.542ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.067ns (routing 0.375ns, distribution 1.692ns) Clock Net Delay (Destination): 1.790ns (routing 0.339ns, distribution 1.451ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.067 2.542 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk SLICE_X107Y51 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y51 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 2.681 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Q net (fo=49, routed) 0.599 3.280 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy SLICE_X107Y52 LUT2 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.538 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/O net (fo=2, routed) 0.438 3.976 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy SLICE_X107Y52 LUT3 (Prop_D5LUT_SLICEM_I1_O) 0.247 4.223 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/O net (fo=4, routed) 0.260 4.483 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X107Y52 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 4.706 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=38, routed) 1.107 5.813 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[3] ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.790 14.988 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.200 15.188 clock uncertainty -0.035 15.152 RAMB36_X12Y10 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[3]) -0.693 14.459 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 14.459 arrival time -5.813 ------------------------------------------------------------------- slack 8.646 Slack (MET) : 8.652ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[2] (rising edge-triggered cell RAMB36E2 clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 3.265ns (logic 0.867ns (26.554%) route 2.398ns (73.446%)) Logic Levels: 3 (LUT2=1 LUT3=1 LUT4=1) Clock Path Skew: -0.154ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.188ns = ( 14.988 - 12.800 ) Source Clock Delay (SCD): 2.542ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.067ns (routing 0.375ns, distribution 1.692ns) Clock Net Delay (Destination): 1.790ns (routing 0.339ns, distribution 1.451ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.067 2.542 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk SLICE_X107Y51 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y51 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 2.681 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wr_rst_busy_ic_reg/Q net (fo=49, routed) 0.599 3.280 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wrst_busy SLICE_X107Y52 LUT2 (Prop_B5LUT_SLICEM_I0_O) 0.258 3.538 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_rst_busy_INST_0/O net (fo=2, routed) 0.438 3.976 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/wr_rst_busy SLICE_X107Y52 LUT3 (Prop_D5LUT_SLICEM_I1_O) 0.247 4.223 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst_i_1__0/O net (fo=4, routed) 0.260 4.483 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_en SLICE_X107Y52 LUT4 (Prop_G6LUT_SLICEM_I0_O) 0.223 4.706 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_sdpram.xpm_memory_base_inst_i_1/O net (fo=38, routed) 1.101 5.807 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[2] ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.790 14.988 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka RAMB36_X12Y10 RAMB36E2 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK clock pessimism 0.200 15.188 clock uncertainty -0.035 15.152 RAMB36_X12Y10 RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[2]) -0.693 14.459 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg ------------------------------------------------------------------- required time 14.459 arrival time -5.807 ------------------------------------------------------------------- slack 8.652 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[22]/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[22] (rising edge-triggered cell GTHE3_CHANNEL clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.186ns (logic 0.048ns (25.806%) route 0.138ns (74.194%)) Logic Levels: 0 Clock Path Skew: -0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.894ns Source Clock Delay (SCD): 0.780ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.662ns (routing 0.164ns, distribution 0.498ns) Clock Net Delay (Destination): 0.729ns (routing 0.192ns, distribution 0.537ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.662 0.780 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[63]_1 SLICE_X139Y4 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y4 FDRE (Prop_EFF2_SLICEL_C_Q) 0.048 0.828 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[22]/Q net (fo=1, routed) 0.138 0.966 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[22] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[22] ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.729 0.894 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.122 0.772 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[22]) 0.164 0.936 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -0.936 arrival time 0.966 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.032ns (arrival time - required time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrp_inst/count_value_i_reg[7]/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]/D (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.241ns (logic 0.064ns (26.556%) route 0.177ns (73.444%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.153ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.104ns Source Clock Delay (SCD): 0.876ns Clock Pessimism Removal (CPR): 0.075ns Clock Net Delay (Source): 0.758ns (routing 0.164ns, distribution 0.594ns) Clock Net Delay (Destination): 0.939ns (routing 0.192ns, distribution 0.747ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.758 0.876 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrp_inst/wr_clk SLICE_X100Y58 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrp_inst/count_value_i_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X100Y58 FDRE (Prop_AFF2_SLICEM_C_Q) 0.049 0.925 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrp_inst/count_value_i_reg[7]/Q net (fo=4, routed) 0.162 1.087 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_in_bin[7] SLICE_X99Y60 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.015 1.102 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff[6]_i_1/O net (fo=1, routed) 0.015 1.117 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/gray_enc[6] SLICE_X99Y60 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]/D ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.939 1.104 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk SLICE_X99Y60 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]/C clock pessimism -0.075 1.029 SLICE_X99Y60 FDRE (Hold_BFF_SLICEL_C_D) 0.056 1.085 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6] ------------------------------------------------------------------- required time -1.085 arrival time 1.117 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.032ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[3]/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[3] (rising edge-triggered cell GTHE3_CHANNEL clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.179ns (logic 0.048ns (26.816%) route 0.131ns (73.184%)) Logic Levels: 0 Clock Path Skew: -0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.894ns Source Clock Delay (SCD): 0.782ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.664ns (routing 0.164ns, distribution 0.500ns) Clock Net Delay (Destination): 0.729ns (routing 0.192ns, distribution 0.537ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.664 0.782 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[63]_1 SLICE_X141Y3 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y3 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 0.830 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[3]/Q net (fo=1, routed) 0.131 0.961 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[3] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[3] ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.729 0.894 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.122 0.772 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[3]) 0.157 0.929 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -0.929 arrival time 0.961 ------------------------------------------------------------------- slack 0.032 Slack (MET) : 0.035ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[7]/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_dec_inst[0].axi_chip2chip_ecc_dec_inst/data_in_flop_reg[7]/D (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.181ns (logic 0.048ns (26.519%) route 0.133ns (73.481%)) Logic Levels: 0 Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.066ns Source Clock Delay (SCD): 0.850ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.732ns (routing 0.164ns, distribution 0.568ns) Clock Net Delay (Destination): 0.901ns (routing 0.192ns, distribution 0.709ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.732 0.850 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_SRC_RDY_N_reg_inv_1 SLICE_X116Y50 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X116Y50 FDRE (Prop_HFF2_SLICEL_C_Q) 0.048 0.898 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[7]/Q net (fo=3, routed) 0.133 1.031 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_dec_inst[0].axi_chip2chip_ecc_dec_inst/axi_c2c_aurora_rx_tdata[7] SLICE_X114Y50 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_dec_inst[0].axi_chip2chip_ecc_dec_inst/data_in_flop_reg[7]/D ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.901 1.066 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_dec_inst[0].axi_chip2chip_ecc_dec_inst/axi_c2c_phy_clk SLICE_X114Y50 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_dec_inst[0].axi_chip2chip_ecc_dec_inst/data_in_flop_reg[7]/C clock pessimism -0.125 0.941 SLICE_X114Y50 FDRE (Hold_FFF2_SLICEL_C_D) 0.055 0.996 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/aurora_ecc_io_stage.ecc_dec_inst[0].axi_chip2chip_ecc_dec_inst/data_in_flop_reg[7] ------------------------------------------------------------------- required time -0.996 arrival time 1.031 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.037ns (arrival time - required time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[4]/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[6]/D (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.153ns (logic 0.063ns (41.176%) route 0.090ns (58.824%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.061ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.093ns Source Clock Delay (SCD): 0.875ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 0.757ns (routing 0.164ns, distribution 0.593ns) Clock Net Delay (Destination): 0.928ns (routing 0.192ns, distribution 0.736ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.757 0.875 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/wr_clk SLICE_X102Y53 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X102Y53 FDRE (Prop_CFF2_SLICEL_C_Q) 0.048 0.923 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[4]/Q net (fo=5, routed) 0.075 0.998 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/Q[4] SLICE_X102Y52 LUT6 (Prop_B6LUT_SLICEL_I0_O) 0.015 1.013 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i[6]_i_1__1/O net (fo=1, routed) 0.015 1.028 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i[6]_i_1__1_n_0 SLICE_X102Y52 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[6]/D ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.928 1.093 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/wr_clk SLICE_X102Y52 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[6]/C clock pessimism -0.157 0.936 SLICE_X102Y52 FDRE (Hold_BFF_SLICEL_C_D) 0.056 0.992 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[6] ------------------------------------------------------------------- required time -0.992 arrival time 1.028 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.037ns (arrival time - required time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[3]/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[6]/D (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.151ns (logic 0.063ns (41.722%) route 0.088ns (58.278%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.075ns Source Clock Delay (SCD): 0.862ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.744ns (routing 0.164ns, distribution 0.580ns) Clock Net Delay (Destination): 0.910ns (routing 0.192ns, distribution 0.718ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.744 0.862 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/wr_clk SLICE_X108Y51 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y51 FDRE (Prop_CFF_SLICEL_C_Q) 0.048 0.910 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[3]/Q net (fo=8, routed) 0.072 0.982 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/Q[3] SLICE_X108Y52 LUT6 (Prop_D6LUT_SLICEL_I3_O) 0.015 0.997 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i[6]_i_1__0/O net (fo=1, routed) 0.016 1.013 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i[6]_i_1__0_n_0 SLICE_X108Y52 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[6]/D ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.910 1.075 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/wr_clk SLICE_X108Y52 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[6]/C clock pessimism -0.155 0.920 SLICE_X108Y52 FDRE (Hold_DFF_SLICEL_C_D) 0.056 0.976 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[6] ------------------------------------------------------------------- required time -0.976 arrival time 1.013 ------------------------------------------------------------------- slack 0.037 Slack (MET) : 0.040ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/txseq_counter_i_reg[4]/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXSEQUENCE[4] (rising edge-triggered cell GTHE3_CHANNEL clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.145ns (logic 0.049ns (33.793%) route 0.096ns (66.207%)) Logic Levels: 0 Clock Path Skew: -0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.894ns Source Clock Delay (SCD): 0.779ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 0.661ns (routing 0.164ns, distribution 0.497ns) Clock Net Delay (Destination): 0.729ns (routing 0.192ns, distribution 0.537ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.661 0.779 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/stg3_reg_0 SLICE_X142Y6 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/txseq_counter_i_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X142Y6 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 0.828 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/txseq_counter_i_reg[4]/Q net (fo=8, routed) 0.096 0.924 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txsequence_in[4] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXSEQUENCE[4] ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.729 0.894 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.148 0.746 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXSEQUENCE[4]) 0.138 0.884 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -0.884 arrival time 0.924 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.040ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[7]/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[7] (rising edge-triggered cell GTHE3_CHANNEL clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.049ns (24.873%) route 0.148ns (75.127%)) Logic Levels: 0 Clock Path Skew: -0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.894ns Source Clock Delay (SCD): 0.782ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.664ns (routing 0.164ns, distribution 0.500ns) Clock Net Delay (Destination): 0.729ns (routing 0.192ns, distribution 0.537ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.664 0.782 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[63]_1 SLICE_X139Y4 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y4 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 0.831 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[7]/Q net (fo=1, routed) 0.148 0.979 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[7] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[7] ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.729 0.894 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 clock pessimism -0.122 0.772 GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[7]) 0.167 0.939 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST ------------------------------------------------------------------- required time -0.939 arrival time 0.979 ------------------------------------------------------------------- slack 0.040 Slack (MET) : 0.041ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_lane_0_i/sym_dec_i/RX_PE_DATA_reg[34]/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[34]/D (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.176ns (logic 0.048ns (27.273%) route 0.128ns (72.727%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.053ns Source Clock Delay (SCD): 0.849ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.731ns (routing 0.164ns, distribution 0.567ns) Clock Net Delay (Destination): 0.888ns (routing 0.192ns, distribution 0.696ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.731 0.849 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_lane_0_i/sym_dec_i/RX_DATA_REG_reg[0]_0 SLICE_X116Y49 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_lane_0_i/sym_dec_i/RX_PE_DATA_reg[34]/C ------------------------------------------------------------------- ------------------- SLICE_X116Y49 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 0.897 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_lane_0_i/sym_dec_i/RX_PE_DATA_reg[34]/Q net (fo=1, routed) 0.128 1.025 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/D[29] SLICE_X114Y49 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[34]/D ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.888 1.053 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_SRC_RDY_N_reg_inv_1 SLICE_X114Y49 FDRE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[34]/C clock pessimism -0.125 0.928 SLICE_X114Y49 FDRE (Hold_AFF2_SLICEL_C_D) 0.056 0.984 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/rx_stream_i/rx_stream_datapath_i/RX_D_reg[34] ------------------------------------------------------------------- required time -0.984 arrival time 1.025 ------------------------------------------------------------------- slack 0.041 Slack (MET) : 0.041ns (arrival time - required time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg_pipe_25_reg/C (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][2]/D (rising edge-triggered cell FDRE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: axi_c2c_phy_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.147ns (logic 0.064ns (43.537%) route 0.083ns (56.463%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.050ns Source Clock Delay (SCD): 0.843ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 0.725ns (routing 0.164ns, distribution 0.561ns) Clock Net Delay (Destination): 0.885ns (routing 0.192ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.725 0.843 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb SLICE_X114Y37 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg_pipe_25_reg/C ------------------------------------------------------------------- ------------------- SLICE_X114Y37 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 0.892 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg_pipe_25_reg/Q net (fo=1, routed) 0.067 0.959 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg_pipe_25_reg_n_0 SLICE_X114Y36 LUT6 (Prop_C6LUT_SLICEL_I1_O) 0.015 0.974 r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe[0][2]_i_1/O net (fo=1, routed) 0.016 0.990 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg[2] SLICE_X114Y36 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][2]/D ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.885 1.050 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb SLICE_X114Y36 FDRE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][2]/C clock pessimism -0.157 0.893 SLICE_X114Y36 FDRE (Hold_CFF_SLICEL_C_D) 0.056 0.949 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_b_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][2] ------------------------------------------------------------------- required time -0.949 arrival time 0.990 ------------------------------------------------------------------- slack 0.041 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: axi_c2c_phy_clk Waveform(ns): { 0.000 6.400 } Period(ns): 12.800 Sources: { i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a FIFO36E2/RDCLK n/a 1.905 12.800 10.895 RAMB36_X14Y9 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/RDCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.905 12.800 10.895 RAMB36_X12Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.905 12.800 10.895 RAMB36_X12Y11 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Min Period n/a RAMB36E2/CLKARDCLK n/a 1.905 12.800 10.895 RAMB36_X14Y8 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Min Period n/a RAMB36E2/CLKBWRCLK n/a 1.905 12.800 10.895 RAMB36_X13Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Min Period n/a SRL16E/CLK n/a 1.356 12.800 11.444 SLICE_X119Y44 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_rd_clk/stg5_reg_srl2/CLK Min Period n/a SRLC32E/CLK n/a 1.356 12.800 11.444 SLICE_X118Y39 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_to_fifo_rd_clk/stg30_reg_srl27/CLK Min Period n/a SRL16E/CLK n/a 1.356 12.800 11.444 SLICE_X119Y31 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_lane_0_i/lane_init_sm_i/SRLC32E_inst_0/CLK Min Period n/a FDRE/C n/a 0.550 12.800 12.250 SLICE_X127Y20 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/FSM_RESETDONE_j_reg/C Min Period n/a FDCE/C n/a 0.550 12.800 12.250 SLICE_X137Y9 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_meta_reg/C Low Pulse Width Fast FIFO36E2/RDCLK n/a 0.952 6.400 5.448 RAMB36_X14Y9 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/RDCLK Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 6.400 5.448 RAMB36_X12Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 6.400 5.448 RAMB36_X12Y11 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 6.400 5.448 RAMB36_X12Y11 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Low Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 6.400 5.448 RAMB36_X14Y8 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Low Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 6.400 5.448 RAMB36_X13Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Low Pulse Width Slow FIFO36E2/RDCLK n/a 0.952 6.400 5.448 RAMB36_X14Y9 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/RDCLK Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 6.400 5.448 RAMB36_X12Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Low Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 6.400 5.448 RAMB36_X14Y8 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Low Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 6.400 5.448 RAMB36_X13Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Slow FIFO36E2/RDCLK n/a 0.952 6.400 5.448 RAMB36_X14Y9 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/RDCLK High Pulse Width Fast FIFO36E2/RDCLK n/a 0.952 6.400 5.448 RAMB36_X14Y9 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/master_fifo.data_fifo/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_sym.gextw_sym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2/RDCLK High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 6.400 5.448 RAMB36_X12Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 6.400 5.448 RAMB36_X12Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_ar_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 6.400 5.448 RAMB36_X12Y11 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Slow RAMB36E2/CLKARDCLK n/a 0.952 6.400 5.448 RAMB36_X14Y8 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK High Pulse Width Fast RAMB36E2/CLKARDCLK n/a 0.952 6.400 5.448 RAMB36_X14Y8 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_r_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK High Pulse Width Slow RAMB36E2/CLKBWRCLK n/a 0.952 6.400 5.448 RAMB36_X13Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 6.400 5.448 RAMB36_X13Y10 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_w_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK High Pulse Width Fast RAMB36E2/CLKBWRCLK n/a 0.952 6.400 5.448 RAMB36_X12Y11 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_inst/axi_chip2chip_aw_fifo_inst/axi_chip2chip_async_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Max Skew Slow GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.864 0.281 0.583 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 Max Skew Fast GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.914 0.149 0.765 GTHE3_CHANNEL_X1Y0 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 --------------------------------------------------------------------------------------------------- From Clock: tx_wordclk To Clock: tx_wordclk Setup : 0 Failing Endpoints, Worst Slack 0.167ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.495ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.167ns (required time - arrival time) Source: TX_CLKEN_reg_replica_45/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[0]/CE (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.854ns (logic 0.139ns (1.770%) route 7.715ns (98.230%)) Logic Levels: 0 Clock Path Skew: 0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.653ns = ( 11.970 - 8.317 ) Source Clock Delay (SCD): 3.481ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.394ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.653ns Common Clock Delay (CCD): 1.026ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.481ns (routing 1.114ns, distribution 2.367ns) Clock Net Delay (Destination): 3.653ns (routing 1.026ns, distribution 2.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.481 3.481 tx_wordclk SLICE_X59Y267 FDRE r TX_CLKEN_reg_replica_45/C ------------------------------------------------------------------- ------------------- SLICE_X59Y267 FDRE (Prop_FFF_SLICEM_C_Q) 0.139 3.620 r TX_CLKEN_reg_replica_45/Q net (fo=94, routed) 7.715 11.335 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias SLR Crossing[0->1] SLICE_X111Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.653 11.970 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X111Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[0]/C clock pessimism 0.088 12.058 inter-SLR compensation -0.394 11.664 clock uncertainty -0.107 11.557 SLICE_X111Y501 FDCE (Setup_GFF_SLICEL_C_CE) -0.055 11.502 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time 11.502 arrival time -11.335 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.167ns (required time - arrival time) Source: TX_CLKEN_reg_replica_45/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/CE (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.854ns (logic 0.139ns (1.770%) route 7.715ns (98.230%)) Logic Levels: 0 Clock Path Skew: 0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.653ns = ( 11.970 - 8.317 ) Source Clock Delay (SCD): 3.481ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.394ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.653ns Common Clock Delay (CCD): 1.026ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.481ns (routing 1.114ns, distribution 2.367ns) Clock Net Delay (Destination): 3.653ns (routing 1.026ns, distribution 2.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.481 3.481 tx_wordclk SLICE_X59Y267 FDRE r TX_CLKEN_reg_replica_45/C ------------------------------------------------------------------- ------------------- SLICE_X59Y267 FDRE (Prop_FFF_SLICEM_C_Q) 0.139 3.620 r TX_CLKEN_reg_replica_45/Q net (fo=94, routed) 7.715 11.335 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias SLR Crossing[0->1] SLICE_X111Y501 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/CE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.653 11.970 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X111Y501 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/C clock pessimism 0.088 12.058 inter-SLR compensation -0.394 11.664 clock uncertainty -0.107 11.557 SLICE_X111Y501 FDPE (Setup_FFF_SLICEL_C_CE) -0.055 11.502 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time 11.502 arrival time -11.335 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.167ns (required time - arrival time) Source: TX_CLKEN_reg_replica_45/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[19]/CE (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.854ns (logic 0.139ns (1.770%) route 7.715ns (98.230%)) Logic Levels: 0 Clock Path Skew: 0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.653ns = ( 11.970 - 8.317 ) Source Clock Delay (SCD): 3.481ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.394ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.653ns Common Clock Delay (CCD): 1.026ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.481ns (routing 1.114ns, distribution 2.367ns) Clock Net Delay (Destination): 3.653ns (routing 1.026ns, distribution 2.627ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.481 3.481 tx_wordclk SLICE_X59Y267 FDRE r TX_CLKEN_reg_replica_45/C ------------------------------------------------------------------- ------------------- SLICE_X59Y267 FDRE (Prop_FFF_SLICEM_C_Q) 0.139 3.620 r TX_CLKEN_reg_replica_45/Q net (fo=94, routed) 7.715 11.335 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias SLR Crossing[0->1] SLICE_X111Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[19]/CE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.653 11.970 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X111Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[19]/C clock pessimism 0.088 12.058 inter-SLR compensation -0.394 11.664 clock uncertainty -0.107 11.557 SLICE_X111Y501 FDCE (Setup_EFF_SLICEL_C_CE) -0.055 11.502 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time 11.502 arrival time -11.335 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.172ns (required time - arrival time) Source: TX_CLKEN_reg_replica_45/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/CE (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.856ns (logic 0.139ns (1.769%) route 7.717ns (98.231%)) Logic Levels: 0 Clock Path Skew: 0.268ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.661ns = ( 11.978 - 8.317 ) Source Clock Delay (SCD): 3.481ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.395ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.661ns Common Clock Delay (CCD): 1.026ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.481ns (routing 1.114ns, distribution 2.367ns) Clock Net Delay (Destination): 3.661ns (routing 1.026ns, distribution 2.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.481 3.481 tx_wordclk SLICE_X59Y267 FDRE r TX_CLKEN_reg_replica_45/C ------------------------------------------------------------------- ------------------- SLICE_X59Y267 FDRE (Prop_FFF_SLICEM_C_Q) 0.139 3.620 r TX_CLKEN_reg_replica_45/Q net (fo=94, routed) 7.717 11.337 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias SLR Crossing[0->1] SLICE_X115Y514 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/CE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.661 11.978 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X115Y514 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/C clock pessimism 0.088 12.066 inter-SLR compensation -0.395 11.671 clock uncertainty -0.107 11.564 SLICE_X115Y514 FDCE (Setup_HFF_SLICEM_C_CE) -0.055 11.509 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time 11.509 arrival time -11.337 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (required time - arrival time) Source: TX_CLKEN_reg_replica_45/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[5]/CE (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.856ns (logic 0.139ns (1.769%) route 7.717ns (98.231%)) Logic Levels: 0 Clock Path Skew: 0.268ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.661ns = ( 11.978 - 8.317 ) Source Clock Delay (SCD): 3.481ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.395ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.661ns Common Clock Delay (CCD): 1.026ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.481ns (routing 1.114ns, distribution 2.367ns) Clock Net Delay (Destination): 3.661ns (routing 1.026ns, distribution 2.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.481 3.481 tx_wordclk SLICE_X59Y267 FDRE r TX_CLKEN_reg_replica_45/C ------------------------------------------------------------------- ------------------- SLICE_X59Y267 FDRE (Prop_FFF_SLICEM_C_Q) 0.139 3.620 r TX_CLKEN_reg_replica_45/Q net (fo=94, routed) 7.717 11.337 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias SLR Crossing[0->1] SLICE_X115Y514 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.661 11.978 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X115Y514 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[5]/C clock pessimism 0.088 12.066 inter-SLR compensation -0.395 11.671 clock uncertainty -0.107 11.564 SLICE_X115Y514 FDPE (Setup_GFF_SLICEM_C_CE) -0.055 11.509 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time 11.509 arrival time -11.337 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (required time - arrival time) Source: TX_CLKEN_reg_replica_45/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/CE (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.856ns (logic 0.139ns (1.769%) route 7.717ns (98.231%)) Logic Levels: 0 Clock Path Skew: 0.268ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.661ns = ( 11.978 - 8.317 ) Source Clock Delay (SCD): 3.481ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.395ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.661ns Common Clock Delay (CCD): 1.026ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.481ns (routing 1.114ns, distribution 2.367ns) Clock Net Delay (Destination): 3.661ns (routing 1.026ns, distribution 2.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.481 3.481 tx_wordclk SLICE_X59Y267 FDRE r TX_CLKEN_reg_replica_45/C ------------------------------------------------------------------- ------------------- SLICE_X59Y267 FDRE (Prop_FFF_SLICEM_C_Q) 0.139 3.620 r TX_CLKEN_reg_replica_45/Q net (fo=94, routed) 7.717 11.337 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias SLR Crossing[0->1] SLICE_X115Y514 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.661 11.978 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X115Y514 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/C clock pessimism 0.088 12.066 inter-SLR compensation -0.395 11.671 clock uncertainty -0.107 11.564 SLICE_X115Y514 FDCE (Setup_FFF_SLICEM_C_CE) -0.055 11.509 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time 11.509 arrival time -11.337 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.190ns (required time - arrival time) Source: TX_CLKEN_reg_replica_45/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[1]/CE (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.815ns (logic 0.139ns (1.779%) route 7.676ns (98.221%)) Logic Levels: 0 Clock Path Skew: 0.240ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.633ns = ( 11.950 - 8.317 ) Source Clock Delay (SCD): 3.481ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.391ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.633ns Common Clock Delay (CCD): 1.026ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.481ns (routing 1.114ns, distribution 2.367ns) Clock Net Delay (Destination): 3.633ns (routing 1.026ns, distribution 2.607ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.481 3.481 tx_wordclk SLICE_X59Y267 FDRE r TX_CLKEN_reg_replica_45/C ------------------------------------------------------------------- ------------------- SLICE_X59Y267 FDRE (Prop_FFF_SLICEM_C_Q) 0.139 3.620 r TX_CLKEN_reg_replica_45/Q net (fo=94, routed) 7.676 11.296 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias SLR Crossing[0->1] SLICE_X105Y502 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.633 11.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X105Y502 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[1]/C clock pessimism 0.088 12.038 inter-SLR compensation -0.391 11.647 clock uncertainty -0.107 11.540 SLICE_X105Y502 FDCE (Setup_DFF_SLICEL_C_CE) -0.054 11.486 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time 11.486 arrival time -11.296 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.190ns (required time - arrival time) Source: TX_CLKEN_reg_replica_45/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]/CE (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.815ns (logic 0.139ns (1.779%) route 7.676ns (98.221%)) Logic Levels: 0 Clock Path Skew: 0.240ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.633ns = ( 11.950 - 8.317 ) Source Clock Delay (SCD): 3.481ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.391ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.633ns Common Clock Delay (CCD): 1.026ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.481ns (routing 1.114ns, distribution 2.367ns) Clock Net Delay (Destination): 3.633ns (routing 1.026ns, distribution 2.607ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.481 3.481 tx_wordclk SLICE_X59Y267 FDRE r TX_CLKEN_reg_replica_45/C ------------------------------------------------------------------- ------------------- SLICE_X59Y267 FDRE (Prop_FFF_SLICEM_C_Q) 0.139 3.620 r TX_CLKEN_reg_replica_45/Q net (fo=94, routed) 7.676 11.296 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias SLR Crossing[0->1] SLICE_X105Y502 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]/CE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.633 11.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X105Y502 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]/C clock pessimism 0.088 12.038 inter-SLR compensation -0.391 11.647 clock uncertainty -0.107 11.540 SLICE_X105Y502 FDCE (Setup_CFF_SLICEL_C_CE) -0.054 11.486 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time 11.486 arrival time -11.296 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.260ns (required time - arrival time) Source: TX_CLKEN_reg_replica_45/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[11]/CE (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.742ns (logic 0.139ns (1.795%) route 7.603ns (98.205%)) Logic Levels: 0 Clock Path Skew: 0.238ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.631ns = ( 11.948 - 8.317 ) Source Clock Delay (SCD): 3.481ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.391ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.631ns Common Clock Delay (CCD): 1.026ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.481ns (routing 1.114ns, distribution 2.367ns) Clock Net Delay (Destination): 3.631ns (routing 1.026ns, distribution 2.605ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.481 3.481 tx_wordclk SLICE_X59Y267 FDRE r TX_CLKEN_reg_replica_45/C ------------------------------------------------------------------- ------------------- SLICE_X59Y267 FDRE (Prop_FFF_SLICEM_C_Q) 0.139 3.620 r TX_CLKEN_reg_replica_45/Q net (fo=94, routed) 7.603 11.223 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias SLR Crossing[0->1] SLICE_X106Y502 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[11]/CE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.631 11.948 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X106Y502 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[11]/C clock pessimism 0.088 12.036 inter-SLR compensation -0.391 11.645 clock uncertainty -0.107 11.538 SLICE_X106Y502 FDPE (Setup_HFF_SLICEM_C_CE) -0.055 11.483 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time 11.483 arrival time -11.223 ------------------------------------------------------------------- slack 0.260 Slack (MET) : 0.260ns (required time - arrival time) Source: TX_CLKEN_reg_replica_45/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]/CE (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.742ns (logic 0.139ns (1.795%) route 7.603ns (98.205%)) Logic Levels: 0 Clock Path Skew: 0.238ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.631ns = ( 11.948 - 8.317 ) Source Clock Delay (SCD): 3.481ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.391ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.631ns Common Clock Delay (CCD): 1.026ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.481ns (routing 1.114ns, distribution 2.367ns) Clock Net Delay (Destination): 3.631ns (routing 1.026ns, distribution 2.605ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.481 3.481 tx_wordclk SLICE_X59Y267 FDRE r TX_CLKEN_reg_replica_45/C ------------------------------------------------------------------- ------------------- SLICE_X59Y267 FDRE (Prop_FFF_SLICEM_C_Q) 0.139 3.620 r TX_CLKEN_reg_replica_45/Q net (fo=94, routed) 7.603 11.223 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/TX_CLKEN_repN_45_alias SLR Crossing[0->1] SLICE_X106Y502 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]/CE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.631 11.948 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X106Y502 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]/C clock pessimism 0.088 12.036 inter-SLR compensation -0.391 11.645 clock uncertainty -0.107 11.538 SLICE_X106Y502 FDPE (Setup_GFF_SLICEM_C_CE) -0.055 11.483 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time 11.483 arrival time -11.223 ------------------------------------------------------------------- slack 0.260 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]/C (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[4]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.169ns (logic 0.078ns (46.154%) route 0.091ns (53.846%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.895ns Source Clock Delay (SCD): 1.645ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.645ns (routing 0.447ns, distribution 1.198ns) Clock Net Delay (Destination): 1.895ns (routing 0.493ns, distribution 1.402ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.645 1.645 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X136Y470 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X136Y470 FDCE (Prop_CFF_SLICEM_C_Q) 0.048 1.693 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]/Q net (fo=12, routed) 0.079 1.772 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/Q[6] SLICE_X135Y470 LUT3 (Prop_A6LUT_SLICEL_I0_O) 0.030 1.802 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[4]_i_1__122/O net (fo=1, routed) 0.012 1.814 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[4] SLICE_X135Y470 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[4]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.895 1.895 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X135Y470 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.167 1.728 SLICE_X135Y470 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.784 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.784 arrival time 1.814 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[88]/C (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.283ns (logic 0.143ns (50.530%) route 0.140ns (49.470%)) Logic Levels: 2 (LUT4=1 MUXF7=1) Clock Path Skew: 0.197ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.767ns Source Clock Delay (SCD): 1.524ns Clock Pessimism Removal (CPR): 0.046ns Clock Net Delay (Source): 1.524ns (routing 0.447ns, distribution 1.077ns) Clock Net Delay (Destination): 1.767ns (routing 0.493ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.524 1.524 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X112Y355 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[88]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y355 FDCE (Prop_DFF_SLICEM_C_Q) 0.049 1.573 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[88]/Q net (fo=1, routed) 0.127 1.700 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/data4[8] SLICE_X112Y360 LUT4 (Prop_A6LUT_SLICEM_I0_O) 0.071 1.771 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O[8]_i_3__20/O net (fo=1, routed) 0.000 1.771 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O[8]_i_3__20_n_0 SLICE_X112Y360 MUXF7 (Prop_F7MUX_AB_SLICEM_I1_O) 0.023 1.794 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8]_i_1__20/O net (fo=1, routed) 0.013 1.807 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8]_i_1__20_n_0 SLICE_X112Y360 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.767 1.767 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X112Y360 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8]/C clock pessimism -0.046 1.721 SLICE_X112Y360 FDCE (Hold_BFF_SLICEM_C_D) 0.056 1.777 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[8] ------------------------------------------------------------------- required time -1.777 arrival time 1.807 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[3]/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.232ns (logic 0.174ns (75.000%) route 0.058ns (25.000%)) Logic Levels: 3 (CARRY8=3) Clock Path Skew: 0.146ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.721ns Source Clock Delay (SCD): 1.513ns Clock Pessimism Removal (CPR): 0.062ns Clock Net Delay (Source): 1.513ns (routing 0.447ns, distribution 1.066ns) Clock Net Delay (Destination): 1.721ns (routing 0.493ns, distribution 1.228ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.513 1.513 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk SLICE_X2Y118 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y118 FDRE (Prop_DFF_SLICEL_C_Q) 0.049 1.562 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[3]/Q net (fo=1, routed) 0.048 1.610 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg_n_0_[3] SLICE_X2Y118 CARRY8 (Prop_CARRY8_SLICEL_S[3]_CO[7]) 0.075 1.685 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[0]_i_1__23/CO[7] net (fo=1, routed) 0.000 1.685 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[0]_i_1__23_n_0 SLICE_X2Y119 CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7]) 0.016 1.701 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1__23/CO[7] net (fo=1, routed) 0.000 1.701 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1__23_n_0 SLICE_X2Y120 CARRY8 (Prop_CARRY8_SLICEL_CI_O[0]) 0.034 1.735 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]_i_1__23/O[0] net (fo=1, routed) 0.010 1.745 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]_i_1__23_n_15 SLICE_X2Y120 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.721 1.721 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk SLICE_X2Y120 FDRE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]/C clock pessimism -0.062 1.659 SLICE_X2Y120 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.715 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16] ------------------------------------------------------------------- required time -1.715 arrival time 1.745 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[7].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[39]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (tx_wordclk rise@41.585ns - tx_wordclk rise@41.585ns) Data Path Delay: 0.493ns (logic 0.124ns (25.152%) route 0.369ns (74.848%)) Logic Levels: 0 Clock Path Skew: 0.334ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 4.226ns Source Clock Delay (SCD): 3.604ns Clock Pessimism Removal (CPR): 0.288ns Clock Net Delay (Source): 3.604ns (routing 1.026ns, distribution 2.578ns) Clock Net Delay (Destination): 4.226ns (routing 1.114ns, distribution 3.112ns) Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 41.585 41.585 r BUFGCE_X2Y98 BUFGCE 0.000 41.585 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.604 45.189 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLICE_X116Y93 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X116Y93 FDCE (Prop_GFF_SLICEL_C_Q) 0.124 45.313 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[3]/Q net (fo=15, routed) 0.369 45.682 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[7].gbt_txgearbox_inst/TX_FRAME_I[80] SLICE_X120Y93 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[7].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[39]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 41.585 41.585 r BUFGCE_X2Y98 BUFGCE 0.000 41.585 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 4.226 45.811 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[7].gbt_txgearbox_inst/tx_wordclk SLICE_X120Y93 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[7].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[39]/C clock pessimism -0.288 45.523 SLICE_X120Y93 FDCE (Hold_GFF_SLICEL_C_D) 0.129 45.652 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[7].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[39] ------------------------------------------------------------------- required time -45.652 arrival time 45.682 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: fabric_clk_div2_q_reg[3]__0/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: TX_CLKEN_reg_replica_20/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.125ns (logic 0.065ns (52.000%) route 0.060ns (48.000%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.438ns Source Clock Delay (SCD): 1.231ns Clock Pessimism Removal (CPR): 0.168ns Clock Net Delay (Source): 1.231ns (routing 0.447ns, distribution 0.784ns) Clock Net Delay (Destination): 1.438ns (routing 0.493ns, distribution 0.945ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.231 1.231 tx_wordclk SLICE_X59Y267 FDRE r fabric_clk_div2_q_reg[3]__0/C ------------------------------------------------------------------- ------------------- SLICE_X59Y267 FDRE (Prop_AFF_SLICEM_C_Q) 0.049 1.280 r fabric_clk_div2_q_reg[3]__0/Q net (fo=70, routed) 0.044 1.324 fabric_clk_div2_q[3] SLICE_X59Y266 LUT2 (Prop_H6LUT_SLICEM_I0_O) 0.016 1.340 r TX_CLKEN_i_1_replica_20/O net (fo=1, routed) 0.016 1.356 TX_CLKEN_i_1_n_0_repN_20 SLICE_X59Y266 FDRE r TX_CLKEN_reg_replica_20/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.438 1.438 tx_wordclk SLICE_X59Y266 FDRE r TX_CLKEN_reg_replica_20/C clock pessimism -0.168 1.270 SLICE_X59Y266 FDRE (Hold_HFF_SLICEM_C_D) 0.056 1.326 TX_CLKEN_reg_replica_20 ------------------------------------------------------------------- required time -1.326 arrival time 1.356 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[10].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[45]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@41.585ns - tx_wordclk rise@41.585ns) Data Path Delay: 0.165ns (logic 0.049ns (29.697%) route 0.116ns (70.303%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.601ns Source Clock Delay (SCD): 1.386ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.386ns (routing 0.447ns, distribution 0.939ns) Clock Net Delay (Destination): 1.601ns (routing 0.493ns, distribution 1.108ns) Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 41.585 41.585 r BUFGCE_X2Y98 BUFGCE 0.000 41.585 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.386 42.971 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X75Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y569 FDCE (Prop_DFF_SLICEL_C_Q) 0.049 43.020 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]/Q net (fo=9, routed) 0.116 43.136 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[10].gbt_txgearbox_inst/TX_FRAME_I[74] SLICE_X75Y570 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[10].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[45]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 41.585 41.585 r BUFGCE_X2Y98 BUFGCE 0.000 41.585 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.601 43.186 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[10].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X75Y570 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[10].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[45]/C clock pessimism -0.136 43.050 SLICE_X75Y570 FDCE (Hold_CFF2_SLICEL_C_D) 0.056 43.106 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[10].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[45] ------------------------------------------------------------------- required time -43.106 arrival time 43.136 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[21]/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[21]/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.167ns (logic 0.049ns (29.341%) route 0.118ns (70.659%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.796ns Source Clock Delay (SCD): 1.551ns Clock Pessimism Removal (CPR): 0.165ns Clock Net Delay (Source): 1.551ns (routing 0.447ns, distribution 1.104ns) Clock Net Delay (Destination): 1.796ns (routing 0.493ns, distribution 1.303ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.551 1.551 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk SLICE_X141Y231 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[21]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y231 FDRE (Prop_FFF_SLICEL_C_Q) 0.049 1.600 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[21]/Q net (fo=2, routed) 0.118 1.718 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[21] SLICE_X142Y231 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[21]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.796 1.796 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk SLICE_X142Y231 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[21]/C clock pessimism -0.165 1.631 SLICE_X142Y231 FDRE (Hold_AFF2_SLICEM_C_D) 0.056 1.687 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[21] ------------------------------------------------------------------- required time -1.687 arrival time 1.718 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_rx_reg[2]/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/rxuserrdy_out_reg/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.177ns (logic 0.079ns (44.633%) route 0.098ns (55.367%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.090ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.771ns Source Clock Delay (SCD): 1.527ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 1.527ns (routing 0.447ns, distribution 1.080ns) Clock Net Delay (Destination): 1.771ns (routing 0.493ns, distribution 1.278ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.527 1.527 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_clk_freerun_in[0] SLR Crossing[0->1] SLICE_X7Y518 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_rx_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X7Y518 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.576 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_rx_reg[2]/Q net (fo=16, routed) 0.082 1.658 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_userclk_rx_active_inst/Q[2] SLICE_X6Y518 LUT6 (Prop_D6LUT_SLICEL_I0_O) 0.030 1.688 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_userclk_rx_active_inst/rxuserrdy_out_i_1/O net (fo=1, routed) 0.016 1.704 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1 SLICE_X6Y518 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/rxuserrdy_out_reg/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.771 1.771 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_clk_freerun_in[0] SLR Crossing[0->1] SLICE_X6Y518 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/rxuserrdy_out_reg/C clock pessimism -0.154 1.617 SLICE_X6Y518 FDRE (Hold_DFF_SLICEL_C_D) 0.056 1.673 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/rxuserrdy_out_reg ------------------------------------------------------------------- required time -1.673 arrival time 1.704 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/address_reg[2]/C (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.472ns (logic 0.178ns (37.712%) route 0.294ns (62.288%)) Logic Levels: 1 (MUXF7=1) Clock Path Skew: 0.314ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.708ns Source Clock Delay (SCD): 3.275ns Clock Pessimism Removal (CPR): 0.119ns Clock Net Delay (Source): 3.275ns (routing 1.026ns, distribution 2.249ns) Clock Net Delay (Destination): 3.708ns (routing 1.114ns, distribution 2.594ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.275 3.275 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/tx_wordclk SLICE_X82Y118 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/address_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y118 FDCE (Prop_DFF2_SLICEM_C_Q) 0.123 3.398 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/address_reg[2]/Q net (fo=21, routed) 0.267 3.665 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/address[2] SLICE_X82Y120 MUXF7 (Prop_F7MUX_CD_SLICEM_S_O) 0.055 3.720 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1]_i_1__6/O net (fo=1, routed) 0.027 3.747 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1]_i_1__6_n_0 SLICE_X82Y120 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.708 3.708 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/tx_wordclk SLICE_X82Y120 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1]/C clock pessimism -0.119 3.589 SLICE_X82Y120 FDCE (Hold_DFF_SLICEM_C_D) 0.127 3.716 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[5].gbt_txgearbox_inst/TX_WORD_O_reg[1] ------------------------------------------------------------------- required time -3.716 arrival time 3.747 ------------------------------------------------------------------- slack 0.031 Slack (MET) : 0.031ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_sync3_reg/C (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/D (rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.458ns (logic 0.123ns (26.856%) route 0.335ns (73.144%)) Logic Levels: 0 Clock Path Skew: 0.298ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 4.078ns Source Clock Delay (SCD): 3.644ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 3.644ns (routing 1.026ns, distribution 2.618ns) Clock Net Delay (Destination): 4.078ns (routing 1.114ns, distribution 2.964ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.644 3.644 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/gtwiz_reset_clk_freerun_in[0] SLR Crossing[0->1] SLICE_X1Y543 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_sync3_reg/C ------------------------------------------------------------------- ------------------- SLICE_X1Y543 FDRE (Prop_CFF2_SLICEM_C_Q) 0.123 3.767 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_sync3_reg/Q net (fo=1, routed) 0.335 4.102 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_sync3 SLICE_X1Y539 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 4.078 4.078 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/gtwiz_reset_clk_freerun_in[0] SLR Crossing[0->1] SLICE_X1Y539 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg/C clock pessimism -0.136 3.942 SLICE_X1Y539 FDRE (Hold_EFF_SLICEM_C_D) 0.129 4.071 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst/i_in_out_reg ------------------------------------------------------------------- required time -4.071 arrival time 4.102 ------------------------------------------------------------------- slack 0.031 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: tx_wordclk Waveform(ns): { 0.000 4.159 } Period(ns): 8.317 Sources: { tx_wordclk_bufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Min Period n/a GTHE3_CHANNEL/DRPCLK n/a 4.000 8.317 4.317 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y7 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y11 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y4 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y5 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y9 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Low Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y30 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y31 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Fast GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y32 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK High Pulse Width Slow GTHE3_CHANNEL/DRPCLK n/a 1.800 4.158 2.358 GTHE3_CHANNEL_X1Y33 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y14 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y15 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y6 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y8 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y10 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y12 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y13 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y28 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y38 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.025 0.495 GTHE3_CHANNEL_X1Y29 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK --------------------------------------------------------------------------------------------------- From Clock: ipb_clk To Clock: clk250 Setup : 0 Failing Endpoints, Worst Slack 1.298ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.298ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][0]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 2.109ns (logic 0.137ns (6.496%) route 1.972ns (93.504%)) Logic Levels: 0 Clock Path Skew: -0.452ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.551ns = ( 6.551 - 4.000 ) Source Clock Delay (SCD): 3.003ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.003ns (routing 0.563ns, distribution 2.440ns) Clock Net Delay (Destination): 2.551ns (routing 1.071ns, distribution 1.480ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.003 3.003 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y319 FDCE r ctrl_regs_inst/regs_reg[7][0]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y319 FDCE (Prop_HFF2_SLICEM_C_Q) 0.137 3.140 r ctrl_regs_inst/regs_reg[7][0]/Q net (fo=2, routed) 1.972 5.112 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[0] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.551 6.551 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]/C clock pessimism 0.000 6.551 clock uncertainty -0.205 6.346 SLICE_X60Y354 FDCE (Setup_EFF_SLICEL_C_D) 0.064 6.410 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0] ------------------------------------------------------------------- required time 6.410 arrival time -5.112 ------------------------------------------------------------------- slack 1.298 Slack (MET) : 1.338ns (required time - arrival time) Source: stat_regs_inst/ipb_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/clk_phase_reg[2]_srl3/D (rising edge-triggered cell SRL16E clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 1.999ns (logic 0.327ns (16.358%) route 1.672ns (83.642%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.403ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.545ns = ( 6.545 - 4.000 ) Source Clock Delay (SCD): 2.948ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.948ns (routing 0.563ns, distribution 2.385ns) Clock Net Delay (Destination): 2.545ns (routing 1.071ns, distribution 1.474ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.948 2.948 stat_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X60Y369 FDRE r stat_regs_inst/ipb_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y369 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 3.086 r stat_regs_inst/ipb_clk_div2_reg/Q net (fo=3, routed) 1.120 4.206 stat_regs_inst/ipb_clk_div2 SLICE_X60Y369 LUT2 (Prop_H5LUT_SLICEL_I0_O) 0.189 4.395 r stat_regs_inst/clk_phase_reg[2]_srl3_i_1/O net (fo=1, routed) 0.552 4.947 stat_regs_inst/p_1_out[0] SLICE_X59Y369 SRL16E r stat_regs_inst/clk_phase_reg[2]_srl3/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.545 6.545 stat_regs_inst/clk250 SLR Crossing[0->1] SLICE_X59Y369 SRL16E r stat_regs_inst/clk_phase_reg[2]_srl3/CLK clock pessimism 0.000 6.545 clock uncertainty -0.205 6.340 SLICE_X59Y369 SRL16E (Setup_A6LUT_SLICEM_CLK_D) -0.055 6.285 stat_regs_inst/clk_phase_reg[2]_srl3 ------------------------------------------------------------------- required time 6.285 arrival time -4.947 ------------------------------------------------------------------- slack 1.338 Slack (MET) : 1.559ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 1.709ns (logic 0.190ns (11.118%) route 1.519ns (88.882%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.469ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.534ns = ( 6.534 - 4.000 ) Source Clock Delay (SCD): 3.003ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.003ns (routing 0.563ns, distribution 2.440ns) Clock Net Delay (Destination): 2.534ns (routing 1.071ns, distribution 1.463ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.003 3.003 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y319 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y319 FDCE (Prop_GFF2_SLICEM_C_Q) 0.139 3.142 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 1.032 4.174 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X61Y356 LUT3 (Prop_E6LUT_SLICEM_I1_O) 0.051 4.225 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 0.487 4.712 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X59Y353 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.534 6.534 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X59Y353 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/C clock pessimism 0.000 6.534 clock uncertainty -0.205 6.329 SLICE_X59Y353 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 6.271 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6] ------------------------------------------------------------------- required time 6.271 arrival time -4.712 ------------------------------------------------------------------- slack 1.559 Slack (MET) : 1.565ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 1.706ns (logic 0.190ns (11.137%) route 1.516ns (88.863%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.469ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.534ns = ( 6.534 - 4.000 ) Source Clock Delay (SCD): 3.003ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.003ns (routing 0.563ns, distribution 2.440ns) Clock Net Delay (Destination): 2.534ns (routing 1.071ns, distribution 1.463ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.003 3.003 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y319 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y319 FDCE (Prop_GFF2_SLICEM_C_Q) 0.139 3.142 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 1.032 4.174 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X61Y356 LUT3 (Prop_E6LUT_SLICEM_I1_O) 0.051 4.225 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 0.484 4.709 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X59Y353 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.534 6.534 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X59Y353 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/C clock pessimism 0.000 6.534 clock uncertainty -0.205 6.329 SLICE_X59Y353 FDCE (Setup_EFF_SLICEM_C_CE) -0.055 6.274 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3] ------------------------------------------------------------------- required time 6.274 arrival time -4.709 ------------------------------------------------------------------- slack 1.565 Slack (MET) : 1.568ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 1.723ns (logic 0.190ns (11.027%) route 1.533ns (88.973%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.450ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.553ns = ( 6.553 - 4.000 ) Source Clock Delay (SCD): 3.003ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.003ns (routing 0.563ns, distribution 2.440ns) Clock Net Delay (Destination): 2.553ns (routing 1.071ns, distribution 1.482ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.003 3.003 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y319 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y319 FDCE (Prop_GFF2_SLICEM_C_Q) 0.139 3.142 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 1.032 4.174 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X61Y356 LUT3 (Prop_E6LUT_SLICEM_I1_O) 0.051 4.225 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 0.501 4.726 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.553 6.553 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/C clock pessimism 0.000 6.553 clock uncertainty -0.205 6.348 SLICE_X60Y354 FDCE (Setup_AFF_SLICEL_C_CE) -0.054 6.294 stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0] ------------------------------------------------------------------- required time 6.294 arrival time -4.726 ------------------------------------------------------------------- slack 1.568 Slack (MET) : 1.647ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 1.613ns (logic 0.190ns (11.779%) route 1.423ns (88.221%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.477ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.526ns = ( 6.526 - 4.000 ) Source Clock Delay (SCD): 3.003ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.003ns (routing 0.563ns, distribution 2.440ns) Clock Net Delay (Destination): 2.526ns (routing 1.071ns, distribution 1.455ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.003 3.003 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y319 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y319 FDCE (Prop_GFF2_SLICEM_C_Q) 0.139 3.142 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 1.032 4.174 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X61Y356 LUT3 (Prop_E6LUT_SLICEM_I1_O) 0.051 4.225 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 0.391 4.616 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X59Y357 FDCE r stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.526 6.526 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X59Y357 FDCE r stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]/C clock pessimism 0.000 6.526 clock uncertainty -0.205 6.321 SLICE_X59Y357 FDCE (Setup_EFF2_SLICEM_C_CE) -0.058 6.263 stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1] ------------------------------------------------------------------- required time 6.263 arrival time -4.616 ------------------------------------------------------------------- slack 1.647 Slack (MET) : 1.648ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 1.637ns (logic 0.190ns (11.607%) route 1.447ns (88.393%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.452ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.551ns = ( 6.551 - 4.000 ) Source Clock Delay (SCD): 3.003ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.003ns (routing 0.563ns, distribution 2.440ns) Clock Net Delay (Destination): 2.551ns (routing 1.071ns, distribution 1.480ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.003 3.003 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y319 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y319 FDCE (Prop_GFF2_SLICEM_C_Q) 0.139 3.142 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 1.032 4.174 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X61Y356 LUT3 (Prop_E6LUT_SLICEM_I1_O) 0.051 4.225 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 0.415 4.640 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.551 6.551 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]/C clock pessimism 0.000 6.551 clock uncertainty -0.205 6.346 SLICE_X60Y354 FDCE (Setup_EFF2_SLICEL_C_CE) -0.058 6.288 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1] ------------------------------------------------------------------- required time 6.288 arrival time -4.640 ------------------------------------------------------------------- slack 1.648 Slack (MET) : 1.648ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 1.637ns (logic 0.190ns (11.607%) route 1.447ns (88.393%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.452ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.551ns = ( 6.551 - 4.000 ) Source Clock Delay (SCD): 3.003ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.003ns (routing 0.563ns, distribution 2.440ns) Clock Net Delay (Destination): 2.551ns (routing 1.071ns, distribution 1.480ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.003 3.003 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y319 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y319 FDCE (Prop_GFF2_SLICEM_C_Q) 0.139 3.142 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 1.032 4.174 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X61Y356 LUT3 (Prop_E6LUT_SLICEM_I1_O) 0.051 4.225 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 0.415 4.640 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.551 6.551 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/C clock pessimism 0.000 6.551 clock uncertainty -0.205 6.346 SLICE_X60Y354 FDCE (Setup_FFF2_SLICEL_C_CE) -0.058 6.288 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4] ------------------------------------------------------------------- required time 6.288 arrival time -4.640 ------------------------------------------------------------------- slack 1.648 Slack (MET) : 1.648ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 1.637ns (logic 0.190ns (11.607%) route 1.447ns (88.393%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.452ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.551ns = ( 6.551 - 4.000 ) Source Clock Delay (SCD): 3.003ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.003ns (routing 0.563ns, distribution 2.440ns) Clock Net Delay (Destination): 2.551ns (routing 1.071ns, distribution 1.480ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.003 3.003 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y319 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y319 FDCE (Prop_GFF2_SLICEM_C_Q) 0.139 3.142 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 1.032 4.174 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X61Y356 LUT3 (Prop_E6LUT_SLICEM_I1_O) 0.051 4.225 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 0.415 4.640 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.551 6.551 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/C clock pessimism 0.000 6.551 clock uncertainty -0.205 6.346 SLICE_X60Y354 FDCE (Setup_GFF2_SLICEL_C_CE) -0.058 6.288 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7] ------------------------------------------------------------------- required time 6.288 arrival time -4.640 ------------------------------------------------------------------- slack 1.648 Slack (MET) : 1.648ns (required time - arrival time) Source: ctrl_regs_inst/regs_reg[7][31]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/CE (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (clk250 rise@4.000ns - ipb_clk rise@0.000ns) Data Path Delay: 1.637ns (logic 0.190ns (11.607%) route 1.447ns (88.393%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.452ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.551ns = ( 6.551 - 4.000 ) Source Clock Delay (SCD): 3.003ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.003ns (routing 0.563ns, distribution 2.440ns) Clock Net Delay (Destination): 2.551ns (routing 1.071ns, distribution 1.480ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.003 3.003 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y319 FDCE r ctrl_regs_inst/regs_reg[7][31]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y319 FDCE (Prop_GFF2_SLICEM_C_Q) 0.139 3.142 r ctrl_regs_inst/regs_reg[7][31]/Q net (fo=3, routed) 1.032 4.174 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] SLICE_X61Y356 LUT3 (Prop_E6LUT_SLICEM_I1_O) 0.051 4.225 r stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/O net (fo=20, routed) 0.415 4.640 stat_regs_inst/i_cntr_rst_ctrl/reset_type SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 4.000 4.000 r BUFGCE_X1Y118 BUFGCE 0.000 4.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.551 6.551 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/C clock pessimism 0.000 6.551 clock uncertainty -0.205 6.346 SLICE_X60Y354 FDCE (Setup_HFF2_SLICEL_C_CE) -0.058 6.288 stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1] ------------------------------------------------------------------- required time 6.288 arrival time -4.640 ------------------------------------------------------------------- slack 1.648 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.036ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][3]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.479ns (logic 0.048ns (10.021%) route 0.431ns (89.979%)) Logic Levels: 0 Clock Path Skew: 0.182ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.211ns Source Clock Delay (SCD): 1.029ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.029ns (routing 0.185ns, distribution 0.844ns) Clock Net Delay (Destination): 1.211ns (routing 0.488ns, distribution 0.723ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.029 1.029 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X59Y312 FDCE r ctrl_regs_inst/regs_reg[7][3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y312 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.077 r ctrl_regs_inst/regs_reg[7][3]/Q net (fo=2, routed) 0.431 1.508 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[3] SLICE_X59Y353 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.211 1.211 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X59Y353 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/C clock pessimism 0.000 1.211 clock uncertainty 0.205 1.416 SLICE_X59Y353 FDCE (Hold_EFF_SLICEM_C_D) 0.056 1.472 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3] ------------------------------------------------------------------- required time -1.472 arrival time 1.508 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.051ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][2]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.508ns (logic 0.048ns (9.449%) route 0.460ns (90.551%)) Logic Levels: 0 Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.225ns Source Clock Delay (SCD): 1.029ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.029ns (routing 0.185ns, distribution 0.844ns) Clock Net Delay (Destination): 1.225ns (routing 0.488ns, distribution 0.737ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.029 1.029 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X59Y312 FDCE r ctrl_regs_inst/regs_reg[7][2]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y312 FDCE (Prop_GFF2_SLICEM_C_Q) 0.048 1.077 r ctrl_regs_inst/regs_reg[7][2]/Q net (fo=2, routed) 0.460 1.537 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[2] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.225 1.225 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]/C clock pessimism 0.000 1.225 clock uncertainty 0.205 1.430 SLICE_X60Y354 FDCE (Hold_FFF_SLICEL_C_D) 0.056 1.486 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2] ------------------------------------------------------------------- required time -1.486 arrival time 1.537 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.056ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][1]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.532ns (logic 0.049ns (9.211%) route 0.483ns (90.789%)) Logic Levels: 0 Clock Path Skew: 0.216ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.225ns Source Clock Delay (SCD): 1.009ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.009ns (routing 0.185ns, distribution 0.824ns) Clock Net Delay (Destination): 1.225ns (routing 0.488ns, distribution 0.737ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.009 1.009 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y324 FDCE r ctrl_regs_inst/regs_reg[7][1]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y324 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.058 r ctrl_regs_inst/regs_reg[7][1]/Q net (fo=2, routed) 0.483 1.541 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.225 1.225 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1]/C clock pessimism 0.000 1.225 clock uncertainty 0.205 1.430 SLICE_X60Y354 FDCE (Hold_EFF2_SLICEL_C_D) 0.055 1.485 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[1] ------------------------------------------------------------------- required time -1.485 arrival time 1.541 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.089ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][6]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.542ns (logic 0.048ns (8.856%) route 0.494ns (91.144%)) Logic Levels: 0 Clock Path Skew: 0.193ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.211ns Source Clock Delay (SCD): 1.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.018ns (routing 0.185ns, distribution 0.833ns) Clock Net Delay (Destination): 1.211ns (routing 0.488ns, distribution 0.723ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.018 1.018 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y320 FDCE r ctrl_regs_inst/regs_reg[7][6]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y320 FDCE (Prop_CFF2_SLICEM_C_Q) 0.048 1.066 r ctrl_regs_inst/regs_reg[7][6]/Q net (fo=2, routed) 0.494 1.560 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[6] SLICE_X59Y353 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.211 1.211 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X59Y353 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/C clock pessimism 0.000 1.211 clock uncertainty 0.205 1.416 SLICE_X59Y353 FDCE (Hold_EFF2_SLICEM_C_D) 0.055 1.471 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6] ------------------------------------------------------------------- required time -1.471 arrival time 1.560 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.111ns (arrival time - required time) Source: stat_regs_inst/ipb_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/ipb_clk_div2_r_reg/D (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.572ns (logic 0.048ns (8.392%) route 0.524ns (91.608%)) Logic Levels: 0 Clock Path Skew: 0.200ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.217ns Source Clock Delay (SCD): 1.017ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.017ns (routing 0.185ns, distribution 0.832ns) Clock Net Delay (Destination): 1.217ns (routing 0.488ns, distribution 0.729ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.017 1.017 stat_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X60Y369 FDRE r stat_regs_inst/ipb_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X60Y369 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.065 r stat_regs_inst/ipb_clk_div2_reg/Q net (fo=3, routed) 0.524 1.589 stat_regs_inst/ipb_clk_div2 SLICE_X60Y369 FDRE r stat_regs_inst/ipb_clk_div2_r_reg/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.217 1.217 stat_regs_inst/clk250 SLR Crossing[0->1] SLICE_X60Y369 FDRE r stat_regs_inst/ipb_clk_div2_r_reg/C clock pessimism 0.000 1.217 clock uncertainty 0.205 1.422 SLICE_X60Y369 FDRE (Hold_AFF_SLICEL_C_D) 0.056 1.478 stat_regs_inst/ipb_clk_div2_r_reg ------------------------------------------------------------------- required time -1.478 arrival time 1.589 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.126ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][4]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.594ns (logic 0.048ns (8.081%) route 0.546ns (91.919%)) Logic Levels: 0 Clock Path Skew: 0.208ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.225ns Source Clock Delay (SCD): 1.017ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.017ns (routing 0.185ns, distribution 0.832ns) Clock Net Delay (Destination): 1.225ns (routing 0.488ns, distribution 0.737ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.017 1.017 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y320 FDCE r ctrl_regs_inst/regs_reg[7][4]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y320 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.065 r ctrl_regs_inst/regs_reg[7][4]/Q net (fo=2, routed) 0.546 1.611 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[4] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.225 1.225 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/C clock pessimism 0.000 1.225 clock uncertainty 0.205 1.430 SLICE_X60Y354 FDCE (Hold_FFF2_SLICEL_C_D) 0.055 1.485 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4] ------------------------------------------------------------------- required time -1.485 arrival time 1.611 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.145ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][30]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.614ns (logic 0.048ns (7.818%) route 0.566ns (92.182%)) Logic Levels: 0 Clock Path Skew: 0.208ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.225ns Source Clock Delay (SCD): 1.017ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.017ns (routing 0.185ns, distribution 0.832ns) Clock Net Delay (Destination): 1.225ns (routing 0.488ns, distribution 0.737ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.017 1.017 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y320 FDCE r ctrl_regs_inst/regs_reg[7][30]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y320 FDCE (Prop_GFF2_SLICEM_C_Q) 0.048 1.065 r ctrl_regs_inst/regs_reg[7][30]/Q net (fo=2, routed) 0.566 1.631 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[10] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.225 1.225 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/C clock pessimism 0.000 1.225 clock uncertainty 0.205 1.430 SLICE_X60Y354 FDCE (Hold_HFF2_SLICEL_C_D) 0.056 1.486 stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1] ------------------------------------------------------------------- required time -1.486 arrival time 1.631 ------------------------------------------------------------------- slack 0.145 Slack (MET) : 0.147ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][8]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.618ns (logic 0.049ns (7.929%) route 0.569ns (92.071%)) Logic Levels: 0 Clock Path Skew: 0.210ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.225ns Source Clock Delay (SCD): 1.015ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.015ns (routing 0.185ns, distribution 0.830ns) Clock Net Delay (Destination): 1.225ns (routing 0.488ns, distribution 0.737ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.015 1.015 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X60Y320 FDCE r ctrl_regs_inst/regs_reg[7][8]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y320 FDCE (Prop_AFF_SLICEL_C_Q) 0.049 1.064 r ctrl_regs_inst/regs_reg[7][8]/Q net (fo=2, routed) 0.569 1.633 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[8] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.225 1.225 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]/C clock pessimism 0.000 1.225 clock uncertainty 0.205 1.430 SLICE_X60Y354 FDCE (Hold_HFF_SLICEL_C_D) 0.056 1.486 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8] ------------------------------------------------------------------- required time -1.486 arrival time 1.633 ------------------------------------------------------------------- slack 0.147 Slack (MET) : 0.180ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][7]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.648ns (logic 0.048ns (7.407%) route 0.600ns (92.593%)) Logic Levels: 0 Clock Path Skew: 0.207ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.225ns Source Clock Delay (SCD): 1.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.018ns (routing 0.185ns, distribution 0.833ns) Clock Net Delay (Destination): 1.225ns (routing 0.488ns, distribution 0.737ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.018 1.018 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y319 FDCE r ctrl_regs_inst/regs_reg[7][7]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y319 FDCE (Prop_FFF2_SLICEM_C_Q) 0.048 1.066 r ctrl_regs_inst/regs_reg[7][7]/Q net (fo=2, routed) 0.600 1.666 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[7] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.225 1.225 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/C clock pessimism 0.000 1.225 clock uncertainty 0.205 1.430 SLICE_X60Y354 FDCE (Hold_GFF2_SLICEL_C_D) 0.056 1.486 stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7] ------------------------------------------------------------------- required time -1.486 arrival time 1.666 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.187ns (arrival time - required time) Source: ctrl_regs_inst/regs_reg[7][29]/C (rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/D (rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: clk250 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk250 rise@0.000ns - ipb_clk rise@0.000ns) Data Path Delay: 0.659ns (logic 0.048ns (7.284%) route 0.611ns (92.716%)) Logic Levels: 0 Clock Path Skew: 0.211ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.228ns Source Clock Delay (SCD): 1.017ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.017ns (routing 0.185ns, distribution 0.832ns) Clock Net Delay (Destination): 1.228ns (routing 0.488ns, distribution 0.740ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.017 1.017 ctrl_regs_inst/ipb_clk SLR Crossing[0->1] SLICE_X61Y320 FDCE r ctrl_regs_inst/regs_reg[7][29]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y320 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.065 r ctrl_regs_inst/regs_reg[7][29]/Q net (fo=2, routed) 0.611 1.676 stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[9] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.228 1.228 stat_regs_inst/i_cntr_rst_ctrl/clk250 SLR Crossing[0->1] SLICE_X60Y354 FDCE r stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/C clock pessimism 0.000 1.228 clock uncertainty 0.205 1.433 SLICE_X60Y354 FDCE (Hold_AFF_SLICEL_C_D) 0.056 1.489 stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0] ------------------------------------------------------------------- required time -1.489 arrival time 1.676 ------------------------------------------------------------------- slack 0.187 --------------------------------------------------------------------------------------------------- From Clock: clk250 To Clock: ipb_clk Setup : 0 Failing Endpoints, Worst Slack 0.625ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.625ns (required time - arrival time) Source: g_clock_rate_din[1].i_rate_ngccm_status0/rate_i_reg[24]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[1].i_rate_ngccm_status0/rate_reg[24]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.941ns (logic 0.139ns (4.726%) route 2.802ns (95.274%)) Logic Levels: 0 Clock Path Skew: -0.293ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.587ns = ( 34.587 - 32.000 ) Source Clock Delay (SCD): 2.880ns = ( 30.880 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.880ns (routing 1.166ns, distribution 1.714ns) Clock Net Delay (Destination): 2.587ns (routing 0.519ns, distribution 2.068ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y118 BUFGCE 0.000 28.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.880 30.880 g_clock_rate_din[1].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X61Y373 FDRE r g_clock_rate_din[1].i_rate_ngccm_status0/rate_i_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y373 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 31.019 r g_clock_rate_din[1].i_rate_ngccm_status0/rate_i_reg[24]/Q net (fo=1, routed) 2.802 33.821 g_clock_rate_din[1].i_rate_ngccm_status0/rate_i_reg_n_0_[24] SLICE_X62Y373 FDRE r g_clock_rate_din[1].i_rate_ngccm_status0/rate_reg[24]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.587 34.587 g_clock_rate_din[1].i_rate_ngccm_status0/ipb_clk SLR Crossing[0->1] SLICE_X62Y373 FDRE r g_clock_rate_din[1].i_rate_ngccm_status0/rate_reg[24]/C clock pessimism 0.000 34.587 clock uncertainty -0.205 34.382 SLICE_X62Y373 FDRE (Setup_EFF_SLICEM_C_D) 0.064 34.446 g_clock_rate_din[1].i_rate_ngccm_status0/rate_reg[24] ------------------------------------------------------------------- required time 34.446 arrival time -33.821 ------------------------------------------------------------------- slack 0.625 Slack (MET) : 0.635ns (required time - arrival time) Source: g_clock_rate_din[30].i_rate_ngccm_status2/rate_i_reg[7]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[30].i_rate_ngccm_status2/rate_reg[7]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.897ns (logic 0.139ns (4.798%) route 2.758ns (95.202%)) Logic Levels: 0 Clock Path Skew: -0.329ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.598ns = ( 34.598 - 32.000 ) Source Clock Delay (SCD): 2.927ns = ( 30.927 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.927ns (routing 1.166ns, distribution 1.761ns) Clock Net Delay (Destination): 2.598ns (routing 0.519ns, distribution 2.079ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y118 BUFGCE 0.000 28.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.927 30.927 g_clock_rate_din[30].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X63Y437 FDRE r g_clock_rate_din[30].i_rate_ngccm_status2/rate_i_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y437 FDRE (Prop_BFF_SLICEL_C_Q) 0.139 31.066 r g_clock_rate_din[30].i_rate_ngccm_status2/rate_i_reg[7]/Q net (fo=1, routed) 2.758 33.824 g_clock_rate_din[30].i_rate_ngccm_status2/rate_i_reg_n_0_[7] SLICE_X64Y437 FDRE r g_clock_rate_din[30].i_rate_ngccm_status2/rate_reg[7]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.598 34.598 g_clock_rate_din[30].i_rate_ngccm_status2/ipb_clk SLR Crossing[0->1] SLICE_X64Y437 FDRE r g_clock_rate_din[30].i_rate_ngccm_status2/rate_reg[7]/C clock pessimism 0.000 34.598 clock uncertainty -0.205 34.393 SLICE_X64Y437 FDRE (Setup_BFF2_SLICEM_C_D) 0.066 34.459 g_clock_rate_din[30].i_rate_ngccm_status2/rate_reg[7] ------------------------------------------------------------------- required time 34.459 arrival time -33.824 ------------------------------------------------------------------- slack 0.635 Slack (MET) : 0.640ns (required time - arrival time) Source: g_clock_rate_din[36].i_rate_ngccm_status2/rate_i_reg[5]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[36].i_rate_ngccm_status2/rate_reg[5]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.877ns (logic 0.138ns (4.797%) route 2.739ns (95.203%)) Logic Levels: 0 Clock Path Skew: -0.341ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.577ns = ( 34.577 - 32.000 ) Source Clock Delay (SCD): 2.918ns = ( 30.918 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.918ns (routing 1.166ns, distribution 1.752ns) Clock Net Delay (Destination): 2.577ns (routing 0.519ns, distribution 2.058ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y118 BUFGCE 0.000 28.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.918 30.918 g_clock_rate_din[36].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X59Y431 FDRE r g_clock_rate_din[36].i_rate_ngccm_status2/rate_i_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y431 FDRE (Prop_FFF2_SLICEM_C_Q) 0.138 31.056 r g_clock_rate_din[36].i_rate_ngccm_status2/rate_i_reg[5]/Q net (fo=1, routed) 2.739 33.795 g_clock_rate_din[36].i_rate_ngccm_status2/rate_i_reg_n_0_[5] SLICE_X60Y431 FDRE r g_clock_rate_din[36].i_rate_ngccm_status2/rate_reg[5]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.577 34.577 g_clock_rate_din[36].i_rate_ngccm_status2/ipb_clk SLR Crossing[0->1] SLICE_X60Y431 FDRE r g_clock_rate_din[36].i_rate_ngccm_status2/rate_reg[5]/C clock pessimism 0.000 34.577 clock uncertainty -0.205 34.372 SLICE_X60Y431 FDRE (Setup_DFF_SLICEL_C_D) 0.063 34.435 g_clock_rate_din[36].i_rate_ngccm_status2/rate_reg[5] ------------------------------------------------------------------- required time 34.435 arrival time -33.795 ------------------------------------------------------------------- slack 0.640 Slack (MET) : 0.641ns (required time - arrival time) Source: g_clock_rate_din[34].i_rate_ngccm_status2/rate_i_reg[36]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[34].i_rate_ngccm_status2/rate_reg[36]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.862ns (logic 0.140ns (4.892%) route 2.722ns (95.108%)) Logic Levels: 0 Clock Path Skew: -0.356ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.575ns = ( 34.575 - 32.000 ) Source Clock Delay (SCD): 2.931ns = ( 30.931 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.931ns (routing 1.166ns, distribution 1.765ns) Clock Net Delay (Destination): 2.575ns (routing 0.519ns, distribution 2.056ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y118 BUFGCE 0.000 28.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.931 30.931 g_clock_rate_din[34].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X55Y428 FDRE r g_clock_rate_din[34].i_rate_ngccm_status2/rate_i_reg[36]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y428 FDRE (Prop_AFF_SLICEM_C_Q) 0.140 31.071 r g_clock_rate_din[34].i_rate_ngccm_status2/rate_i_reg[36]/Q net (fo=1, routed) 2.722 33.793 g_clock_rate_din[34].i_rate_ngccm_status2/rate_i_reg_n_0_[36] SLICE_X54Y428 FDRE r g_clock_rate_din[34].i_rate_ngccm_status2/rate_reg[36]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.575 34.575 g_clock_rate_din[34].i_rate_ngccm_status2/ipb_clk SLR Crossing[0->1] SLICE_X54Y428 FDRE r g_clock_rate_din[34].i_rate_ngccm_status2/rate_reg[36]/C clock pessimism 0.000 34.575 clock uncertainty -0.205 34.370 SLICE_X54Y428 FDRE (Setup_EFF_SLICEL_C_D) 0.064 34.434 g_clock_rate_din[34].i_rate_ngccm_status2/rate_reg[36] ------------------------------------------------------------------- required time 34.434 arrival time -33.793 ------------------------------------------------------------------- slack 0.641 Slack (MET) : 0.657ns (required time - arrival time) Source: g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg[12]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[12]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.938ns (logic 0.139ns (4.731%) route 2.799ns (95.269%)) Logic Levels: 0 Clock Path Skew: -0.265ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.804ns = ( 34.804 - 32.000 ) Source Clock Delay (SCD): 3.069ns = ( 31.069 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.069ns (routing 1.166ns, distribution 1.903ns) Clock Net Delay (Destination): 2.804ns (routing 0.519ns, distribution 2.285ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y118 BUFGCE 0.000 28.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 3.069 31.069 g_clock_rate_din[22].i_rate_ngccm_status1/clk250 SLR Crossing[0->1] SLICE_X83Y464 FDRE r g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X83Y464 FDRE (Prop_AFF2_SLICEM_C_Q) 0.139 31.208 r g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg[12]/Q net (fo=1, routed) 2.799 34.007 g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg_n_0_[12] SLICE_X83Y463 FDRE r g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[12]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.804 34.804 g_clock_rate_din[22].i_rate_ngccm_status1/ipb_clk SLR Crossing[0->1] SLICE_X83Y463 FDRE r g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[12]/C clock pessimism 0.000 34.804 clock uncertainty -0.205 34.599 SLICE_X83Y463 FDRE (Setup_GFF2_SLICEM_C_D) 0.065 34.664 g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[12] ------------------------------------------------------------------- required time 34.664 arrival time -34.007 ------------------------------------------------------------------- slack 0.657 Slack (MET) : 0.671ns (required time - arrival time) Source: g_clock_rate_din[42].i_rate_test_comm/rate_i_reg[7]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[42].i_rate_test_comm/rate_reg[7]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.765ns (logic 0.139ns (5.027%) route 2.626ns (94.973%)) Logic Levels: 0 Clock Path Skew: -0.424ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.896ns = ( 34.896 - 32.000 ) Source Clock Delay (SCD): 3.320ns = ( 31.320 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.320ns (routing 1.166ns, distribution 2.154ns) Clock Net Delay (Destination): 2.896ns (routing 0.519ns, distribution 2.377ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y118 BUFGCE 0.000 28.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 3.320 31.320 g_clock_rate_din[42].i_rate_test_comm/clk250 SLR Crossing[0->1] SLICE_X42Y424 FDRE r g_clock_rate_din[42].i_rate_test_comm/rate_i_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y424 FDRE (Prop_FFF_SLICEM_C_Q) 0.139 31.459 r g_clock_rate_din[42].i_rate_test_comm/rate_i_reg[7]/Q net (fo=1, routed) 2.626 34.085 g_clock_rate_din[42].i_rate_test_comm/rate_i_reg_n_0_[7] SLICE_X41Y426 FDRE r g_clock_rate_din[42].i_rate_test_comm/rate_reg[7]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.896 34.896 g_clock_rate_din[42].i_rate_test_comm/ipb_clk SLR Crossing[0->1] SLICE_X41Y426 FDRE r g_clock_rate_din[42].i_rate_test_comm/rate_reg[7]/C clock pessimism 0.000 34.896 clock uncertainty -0.205 34.691 SLICE_X41Y426 FDRE (Setup_GFF2_SLICEM_C_D) 0.065 34.756 g_clock_rate_din[42].i_rate_test_comm/rate_reg[7] ------------------------------------------------------------------- required time 34.756 arrival time -34.085 ------------------------------------------------------------------- slack 0.671 Slack (MET) : 0.675ns (required time - arrival time) Source: g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[17]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[17]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.932ns (logic 0.139ns (4.741%) route 2.793ns (95.259%)) Logic Levels: 0 Clock Path Skew: -0.253ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.801ns = ( 34.801 - 32.000 ) Source Clock Delay (SCD): 3.054ns = ( 31.054 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.054ns (routing 1.166ns, distribution 1.888ns) Clock Net Delay (Destination): 2.801ns (routing 0.519ns, distribution 2.282ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y118 BUFGCE 0.000 28.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 3.054 31.054 g_clock_rate_din[10].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X88Y413 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y413 FDRE (Prop_GFF_SLICEL_C_Q) 0.139 31.193 r g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[17]/Q net (fo=1, routed) 2.793 33.986 g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg_n_0_[17] SLICE_X85Y413 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[17]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.801 34.801 g_clock_rate_din[10].i_rate_ngccm_status2/ipb_clk SLR Crossing[0->1] SLICE_X85Y413 FDRE r g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[17]/C clock pessimism 0.000 34.801 clock uncertainty -0.205 34.596 SLICE_X85Y413 FDRE (Setup_EFF2_SLICEM_C_D) 0.065 34.661 g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[17] ------------------------------------------------------------------- required time 34.661 arrival time -33.986 ------------------------------------------------------------------- slack 0.675 Slack (MET) : 0.678ns (required time - arrival time) Source: g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[28]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[28]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.907ns (logic 0.139ns (4.782%) route 2.768ns (95.218%)) Logic Levels: 0 Clock Path Skew: -0.273ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.795ns = ( 34.795 - 32.000 ) Source Clock Delay (SCD): 3.068ns = ( 31.068 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.068ns (routing 1.166ns, distribution 1.902ns) Clock Net Delay (Destination): 2.795ns (routing 0.519ns, distribution 2.276ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y118 BUFGCE 0.000 28.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 3.068 31.068 g_clock_rate_din[18].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X82Y438 FDRE r g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[28]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y438 FDRE (Prop_CFF2_SLICEM_C_Q) 0.139 31.207 r g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[28]/Q net (fo=1, routed) 2.768 33.975 g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg_n_0_[28] SLICE_X82Y438 FDRE r g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[28]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.795 34.795 g_clock_rate_din[18].i_rate_ngccm_status2/ipb_clk SLR Crossing[0->1] SLICE_X82Y438 FDRE r g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[28]/C clock pessimism 0.000 34.795 clock uncertainty -0.205 34.590 SLICE_X82Y438 FDRE (Setup_HFF_SLICEM_C_D) 0.063 34.653 g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[28] ------------------------------------------------------------------- required time 34.653 arrival time -33.975 ------------------------------------------------------------------- slack 0.678 Slack (MET) : 0.690ns (required time - arrival time) Source: g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[15]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[15]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.832ns (logic 0.138ns (4.873%) route 2.694ns (95.127%)) Logic Levels: 0 Clock Path Skew: -0.340ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.573ns = ( 34.573 - 32.000 ) Source Clock Delay (SCD): 2.913ns = ( 30.913 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.913ns (routing 1.166ns, distribution 1.747ns) Clock Net Delay (Destination): 2.573ns (routing 0.519ns, distribution 2.054ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y118 BUFGCE 0.000 28.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.913 30.913 g_clock_rate_din[43].i_rate_ngccm_status1/clk250 SLR Crossing[0->1] SLICE_X56Y444 FDRE r g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y444 FDRE (Prop_HFF_SLICEL_C_Q) 0.138 31.051 r g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[15]/Q net (fo=1, routed) 2.694 33.745 g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg_n_0_[15] SLICE_X54Y444 FDRE r g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[15]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.573 34.573 g_clock_rate_din[43].i_rate_ngccm_status1/ipb_clk SLR Crossing[0->1] SLICE_X54Y444 FDRE r g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[15]/C clock pessimism 0.000 34.573 clock uncertainty -0.205 34.368 SLICE_X54Y444 FDRE (Setup_DFF2_SLICEL_C_D) 0.067 34.435 g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[15] ------------------------------------------------------------------- required time 34.435 arrival time -33.745 ------------------------------------------------------------------- slack 0.690 Slack (MET) : 0.692ns (required time - arrival time) Source: g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg[2]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[2]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (ipb_clk rise@32.000ns - clk250 rise@28.000ns) Data Path Delay: 2.798ns (logic 0.138ns (4.932%) route 2.660ns (95.068%)) Logic Levels: 0 Clock Path Skew: -0.369ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.539ns = ( 34.539 - 32.000 ) Source Clock Delay (SCD): 2.908ns = ( 30.908 - 28.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.908ns (routing 1.166ns, distribution 1.742ns) Clock Net Delay (Destination): 2.539ns (routing 0.519ns, distribution 2.020ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 28.000 28.000 r BUFGCE_X1Y118 BUFGCE 0.000 28.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.908 30.908 g_clock_rate_din[34].i_rate_ngccm_status1/clk250 SLR Crossing[0->1] SLICE_X52Y391 FDRE r g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y391 FDRE (Prop_CFF_SLICEM_C_Q) 0.138 31.046 r g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg[2]/Q net (fo=1, routed) 2.660 33.706 g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg_n_0_[2] SLICE_X56Y391 FDRE r g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[2]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 32.000 32.000 r BUFGCE_X1Y96 BUFGCE 0.000 32.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 2.539 34.539 g_clock_rate_din[34].i_rate_ngccm_status1/ipb_clk SLR Crossing[0->1] SLICE_X56Y391 FDRE r g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[2]/C clock pessimism 0.000 34.539 clock uncertainty -0.205 34.334 SLICE_X56Y391 FDRE (Setup_EFF_SLICEL_C_D) 0.064 34.398 g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[2] ------------------------------------------------------------------- required time 34.398 arrival time -33.706 ------------------------------------------------------------------- slack 0.692 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[5].i_rate_ngccm_status1/rate_i_reg[33]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[5].i_rate_ngccm_status1/rate_reg[33]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.933ns (logic 0.123ns (13.183%) route 0.810ns (86.817%)) Logic Levels: 0 Clock Path Skew: 0.570ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.226ns Source Clock Delay (SCD): 2.656ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 2.656ns (routing 1.071ns, distribution 1.585ns) Clock Net Delay (Destination): 3.226ns (routing 0.563ns, distribution 2.663ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 2.656 2.656 g_clock_rate_din[5].i_rate_ngccm_status1/clk250 SLR Crossing[0->1] SLICE_X82Y344 FDRE r g_clock_rate_din[5].i_rate_ngccm_status1/rate_i_reg[33]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y344 FDRE (Prop_HFF_SLICEM_C_Q) 0.123 2.779 r g_clock_rate_din[5].i_rate_ngccm_status1/rate_i_reg[33]/Q net (fo=1, routed) 0.810 3.589 g_clock_rate_din[5].i_rate_ngccm_status1/rate_i_reg_n_0_[33] SLICE_X75Y349 FDRE r g_clock_rate_din[5].i_rate_ngccm_status1/rate_reg[33]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 3.226 3.226 g_clock_rate_din[5].i_rate_ngccm_status1/ipb_clk SLR Crossing[0->1] SLICE_X75Y349 FDRE r g_clock_rate_din[5].i_rate_ngccm_status1/rate_reg[33]/C clock pessimism 0.000 3.226 clock uncertainty 0.205 3.431 SLICE_X75Y349 FDRE (Hold_HFF2_SLICEL_C_D) 0.128 3.559 g_clock_rate_din[5].i_rate_ngccm_status1/rate_reg[33] ------------------------------------------------------------------- required time -3.559 arrival time 3.589 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[3].i_rate_ngccm_status0/rate_i_reg[3]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[3].i_rate_ngccm_status0/rate_reg[3]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.474ns (logic 0.049ns (10.338%) route 0.425ns (89.662%)) Logic Levels: 0 Clock Path Skew: 0.183ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.202ns Source Clock Delay (SCD): 1.019ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.019ns (routing 0.441ns, distribution 0.578ns) Clock Net Delay (Destination): 1.202ns (routing 0.206ns, distribution 0.996ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.019 1.019 g_clock_rate_din[3].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X61Y377 FDRE r g_clock_rate_din[3].i_rate_ngccm_status0/rate_i_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y377 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.068 r g_clock_rate_din[3].i_rate_ngccm_status0/rate_i_reg[3]/Q net (fo=1, routed) 0.425 1.493 g_clock_rate_din[3].i_rate_ngccm_status0/rate_i_reg_n_0_[3] SLICE_X61Y380 FDRE r g_clock_rate_din[3].i_rate_ngccm_status0/rate_reg[3]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.202 1.202 g_clock_rate_din[3].i_rate_ngccm_status0/ipb_clk SLR Crossing[0->1] SLICE_X61Y380 FDRE r g_clock_rate_din[3].i_rate_ngccm_status0/rate_reg[3]/C clock pessimism 0.000 1.202 clock uncertainty 0.205 1.407 SLICE_X61Y380 FDRE (Hold_HFF2_SLICEM_C_D) 0.056 1.463 g_clock_rate_din[3].i_rate_ngccm_status0/rate_reg[3] ------------------------------------------------------------------- required time -1.463 arrival time 1.493 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[14].i_rate_ngccm_status0/rate_i_reg[18]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[14].i_rate_ngccm_status0/rate_reg[18]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.475ns (logic 0.049ns (10.316%) route 0.426ns (89.684%)) Logic Levels: 0 Clock Path Skew: 0.184ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.227ns Source Clock Delay (SCD): 1.043ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.043ns (routing 0.441ns, distribution 0.602ns) Clock Net Delay (Destination): 1.227ns (routing 0.206ns, distribution 1.021ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.043 1.043 g_clock_rate_din[14].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X72Y385 FDRE r g_clock_rate_din[14].i_rate_ngccm_status0/rate_i_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y385 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 1.092 r g_clock_rate_din[14].i_rate_ngccm_status0/rate_i_reg[18]/Q net (fo=1, routed) 0.426 1.518 g_clock_rate_din[14].i_rate_ngccm_status0/rate_i_reg_n_0_[18] SLICE_X70Y381 FDRE r g_clock_rate_din[14].i_rate_ngccm_status0/rate_reg[18]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.227 1.227 g_clock_rate_din[14].i_rate_ngccm_status0/ipb_clk SLR Crossing[0->1] SLICE_X70Y381 FDRE r g_clock_rate_din[14].i_rate_ngccm_status0/rate_reg[18]/C clock pessimism 0.000 1.227 clock uncertainty 0.205 1.432 SLICE_X70Y381 FDRE (Hold_EFF_SLICEM_C_D) 0.056 1.488 g_clock_rate_din[14].i_rate_ngccm_status0/rate_reg[18] ------------------------------------------------------------------- required time -1.488 arrival time 1.518 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[33]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[33]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.486ns (logic 0.049ns (10.082%) route 0.437ns (89.918%)) Logic Levels: 0 Clock Path Skew: 0.195ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.284ns Source Clock Delay (SCD): 1.089ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.089ns (routing 0.441ns, distribution 0.648ns) Clock Net Delay (Destination): 1.284ns (routing 0.206ns, distribution 1.078ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.089 1.089 g_clock_rate_din[18].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X76Y439 FDRE r g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[33]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y439 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 1.138 r g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[33]/Q net (fo=1, routed) 0.437 1.575 g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg_n_0_[33] SLICE_X76Y441 FDRE r g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[33]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.284 1.284 g_clock_rate_din[18].i_rate_ngccm_status2/ipb_clk SLR Crossing[0->1] SLICE_X76Y441 FDRE r g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[33]/C clock pessimism 0.000 1.284 clock uncertainty 0.205 1.489 SLICE_X76Y441 FDRE (Hold_FFF_SLICEM_C_D) 0.056 1.545 g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[33] ------------------------------------------------------------------- required time -1.545 arrival time 1.575 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[19].i_rate_ngccm_status2/rate_i_reg[46]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[19].i_rate_ngccm_status2/rate_reg[46]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.489ns (logic 0.049ns (10.020%) route 0.440ns (89.980%)) Logic Levels: 0 Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.286ns Source Clock Delay (SCD): 1.087ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.087ns (routing 0.441ns, distribution 0.646ns) Clock Net Delay (Destination): 1.286ns (routing 0.206ns, distribution 1.080ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.087 1.087 g_clock_rate_din[19].i_rate_ngccm_status2/clk250 SLR Crossing[0->1] SLICE_X76Y441 FDRE r g_clock_rate_din[19].i_rate_ngccm_status2/rate_i_reg[46]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y441 FDRE (Prop_DFF2_SLICEM_C_Q) 0.049 1.136 r g_clock_rate_din[19].i_rate_ngccm_status2/rate_i_reg[46]/Q net (fo=1, routed) 0.440 1.576 g_clock_rate_din[19].i_rate_ngccm_status2/rate_i_reg_n_0_[46] SLICE_X75Y441 FDRE r g_clock_rate_din[19].i_rate_ngccm_status2/rate_reg[46]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.286 1.286 g_clock_rate_din[19].i_rate_ngccm_status2/ipb_clk SLR Crossing[0->1] SLICE_X75Y441 FDRE r g_clock_rate_din[19].i_rate_ngccm_status2/rate_reg[46]/C clock pessimism 0.000 1.286 clock uncertainty 0.205 1.491 SLICE_X75Y441 FDRE (Hold_EFF2_SLICEL_C_D) 0.055 1.546 g_clock_rate_din[19].i_rate_ngccm_status2/rate_reg[46] ------------------------------------------------------------------- required time -1.546 arrival time 1.576 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[21].i_rate_ngccm_status0/rate_i_reg[14]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[21].i_rate_ngccm_status0/rate_reg[14]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.462ns (logic 0.049ns (10.606%) route 0.413ns (89.394%)) Logic Levels: 0 Clock Path Skew: 0.171ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.229ns Source Clock Delay (SCD): 1.058ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.058ns (routing 0.441ns, distribution 0.617ns) Clock Net Delay (Destination): 1.229ns (routing 0.206ns, distribution 1.023ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.058 1.058 g_clock_rate_din[21].i_rate_ngccm_status0/clk250 SLR Crossing[0->1] SLICE_X72Y413 FDRE r g_clock_rate_din[21].i_rate_ngccm_status0/rate_i_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y413 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 1.107 r g_clock_rate_din[21].i_rate_ngccm_status0/rate_i_reg[14]/Q net (fo=1, routed) 0.413 1.520 g_clock_rate_din[21].i_rate_ngccm_status0/rate_i_reg_n_0_[14] SLICE_X66Y404 FDRE r g_clock_rate_din[21].i_rate_ngccm_status0/rate_reg[14]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.229 1.229 g_clock_rate_din[21].i_rate_ngccm_status0/ipb_clk SLR Crossing[0->1] SLICE_X66Y404 FDRE r g_clock_rate_din[21].i_rate_ngccm_status0/rate_reg[14]/C clock pessimism 0.000 1.229 clock uncertainty 0.205 1.434 SLICE_X66Y404 FDRE (Hold_HFF2_SLICEL_C_D) 0.056 1.490 g_clock_rate_din[21].i_rate_ngccm_status0/rate_reg[14] ------------------------------------------------------------------- required time -1.490 arrival time 1.520 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[34].i_rate_test_comm/rate_i_reg[7]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[34].i_rate_test_comm/rate_reg[7]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.441ns (logic 0.049ns (11.111%) route 0.392ns (88.889%)) Logic Levels: 0 Clock Path Skew: 0.150ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.352ns Source Clock Delay (SCD): 1.202ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.202ns (routing 0.441ns, distribution 0.761ns) Clock Net Delay (Destination): 1.352ns (routing 0.206ns, distribution 1.146ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.202 1.202 g_clock_rate_din[34].i_rate_test_comm/clk250 SLR Crossing[0->1] SLICE_X41Y417 FDRE r g_clock_rate_din[34].i_rate_test_comm/rate_i_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y417 FDRE (Prop_DFF_SLICEM_C_Q) 0.049 1.251 r g_clock_rate_din[34].i_rate_test_comm/rate_i_reg[7]/Q net (fo=1, routed) 0.392 1.643 g_clock_rate_din[34].i_rate_test_comm/rate_i_reg_n_0_[7] SLICE_X41Y418 FDRE r g_clock_rate_din[34].i_rate_test_comm/rate_reg[7]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.352 1.352 g_clock_rate_din[34].i_rate_test_comm/ipb_clk SLR Crossing[0->1] SLICE_X41Y418 FDRE r g_clock_rate_din[34].i_rate_test_comm/rate_reg[7]/C clock pessimism 0.000 1.352 clock uncertainty 0.205 1.557 SLICE_X41Y418 FDRE (Hold_DFF_SLICEM_C_D) 0.056 1.613 g_clock_rate_din[34].i_rate_test_comm/rate_reg[7] ------------------------------------------------------------------- required time -1.613 arrival time 1.643 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[40].i_rate_ngccm_status1/rate_i_reg[37]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[40].i_rate_ngccm_status1/rate_reg[37]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.459ns (logic 0.049ns (10.675%) route 0.410ns (89.325%)) Logic Levels: 0 Clock Path Skew: 0.169ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.213ns Source Clock Delay (SCD): 1.044ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.044ns (routing 0.441ns, distribution 0.603ns) Clock Net Delay (Destination): 1.213ns (routing 0.206ns, distribution 1.007ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.044 1.044 g_clock_rate_din[40].i_rate_ngccm_status1/clk250 SLR Crossing[0->1] SLICE_X58Y443 FDRE r g_clock_rate_din[40].i_rate_ngccm_status1/rate_i_reg[37]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y443 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.093 r g_clock_rate_din[40].i_rate_ngccm_status1/rate_i_reg[37]/Q net (fo=1, routed) 0.410 1.503 g_clock_rate_din[40].i_rate_ngccm_status1/rate_i_reg_n_0_[37] SLICE_X57Y443 FDRE r g_clock_rate_din[40].i_rate_ngccm_status1/rate_reg[37]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.213 1.213 g_clock_rate_din[40].i_rate_ngccm_status1/ipb_clk SLR Crossing[0->1] SLICE_X57Y443 FDRE r g_clock_rate_din[40].i_rate_ngccm_status1/rate_reg[37]/C clock pessimism 0.000 1.213 clock uncertainty 0.205 1.418 SLICE_X57Y443 FDRE (Hold_EFF2_SLICEL_C_D) 0.055 1.473 g_clock_rate_din[40].i_rate_ngccm_status1/rate_reg[37] ------------------------------------------------------------------- required time -1.473 arrival time 1.503 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[14]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[14]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.423ns (logic 0.048ns (11.348%) route 0.375ns (88.652%)) Logic Levels: 0 Clock Path Skew: 0.133ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.192ns Source Clock Delay (SCD): 1.059ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.059ns (routing 0.441ns, distribution 0.618ns) Clock Net Delay (Destination): 1.192ns (routing 0.206ns, distribution 0.986ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.059 1.059 g_clock_rate_din[43].i_rate_ngccm_status1/clk250 SLR Crossing[0->1] SLICE_X54Y442 FDRE r g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y442 FDRE (Prop_FFF2_SLICEL_C_Q) 0.048 1.107 r g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[14]/Q net (fo=1, routed) 0.375 1.482 g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg_n_0_[14] SLICE_X52Y443 FDRE r g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[14]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.192 1.192 g_clock_rate_din[43].i_rate_ngccm_status1/ipb_clk SLR Crossing[0->1] SLICE_X52Y443 FDRE r g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[14]/C clock pessimism 0.000 1.192 clock uncertainty 0.205 1.397 SLICE_X52Y443 FDRE (Hold_FFF2_SLICEM_C_D) 0.055 1.452 g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[14] ------------------------------------------------------------------- required time -1.452 arrival time 1.482 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: g_clock_rate_din[47].i_rate_ngccm_status1/rate_i_reg[20]/C (rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns}) Destination: g_clock_rate_din[47].i_rate_ngccm_status1/rate_reg[20]/D (rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: ipb_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ipb_clk rise@0.000ns - clk250 rise@0.000ns) Data Path Delay: 0.456ns (logic 0.049ns (10.746%) route 0.407ns (89.254%)) Logic Levels: 0 Clock Path Skew: 0.165ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.212ns Source Clock Delay (SCD): 1.047ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.205ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.047ns (routing 0.441ns, distribution 0.606ns) Clock Net Delay (Destination): 1.212ns (routing 0.206ns, distribution 1.006ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk250 rise edge) 0.000 0.000 r BUFGCE_X1Y118 BUFGCE 0.000 0.000 r i_clk250_bufg/O X2Y6 (CLOCK_ROOT) net (fo=17693, routed) 1.047 1.047 g_clock_rate_din[47].i_rate_ngccm_status1/clk250 SLR Crossing[0->1] SLICE_X58Y462 FDRE r g_clock_rate_din[47].i_rate_ngccm_status1/rate_i_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y462 FDRE (Prop_BFF_SLICEM_C_Q) 0.049 1.096 r g_clock_rate_din[47].i_rate_ngccm_status1/rate_i_reg[20]/Q net (fo=1, routed) 0.407 1.503 g_clock_rate_din[47].i_rate_ngccm_status1/rate_i_reg_n_0_[20] SLICE_X58Y464 FDRE r g_clock_rate_din[47].i_rate_ngccm_status1/rate_reg[20]/D ------------------------------------------------------------------- ------------------- (clock ipb_clk rise edge) 0.000 0.000 r BUFGCE_X1Y96 BUFGCE 0.000 0.000 r i_ipb_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=204768, routed) 1.212 1.212 g_clock_rate_din[47].i_rate_ngccm_status1/ipb_clk SLR Crossing[0->1] SLICE_X58Y464 FDRE r g_clock_rate_din[47].i_rate_ngccm_status1/rate_reg[20]/C clock pessimism 0.000 1.212 clock uncertainty 0.205 1.417 SLICE_X58Y464 FDRE (Hold_FFF_SLICEM_C_D) 0.056 1.473 g_clock_rate_din[47].i_rate_ngccm_status1/rate_reg[20] ------------------------------------------------------------------- required time -1.473 arrival time 1.503 ------------------------------------------------------------------- slack 0.030 --------------------------------------------------------------------------------------------------- From Clock: fabric_clk To Clock: tx_wordclk Setup : 0 Failing Endpoints, Worst Slack 4.096ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.029ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.096ns (required time - arrival time) Source: fabric_clk_div2_reg_replica/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: fabric_clk_div2_q_reg[2]_srl3/D (rising edge-triggered cell SRL16E clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 2.922ns (logic 0.139ns (4.757%) route 2.783ns (95.243%)) Logic Levels: 0 Clock Path Skew: -0.543ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.018ns = ( 11.335 - 8.317 ) Source Clock Delay (SCD): 3.561ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Inter-SLR Compensation: 0.453ns (DCD * PF) Destination Clock Delay (DCD): 3.018ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.561ns (routing 1.005ns, distribution 2.556ns) Clock Net Delay (Destination): 3.018ns (routing 1.026ns, distribution 1.992ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.561 3.561 fabric_clk SLR Crossing[0->1] SLICE_X74Y352 FDRE r fabric_clk_div2_reg_replica/C ------------------------------------------------------------------- ------------------- SLICE_X74Y352 FDRE (Prop_AFF2_SLICEL_C_Q) 0.139 3.700 r fabric_clk_div2_reg_replica/Q net (fo=51, routed) 2.783 6.483 fabric_clk_div2_bufg_place_replica SLR Crossing[1->0] SLICE_X59Y267 SRL16E r fabric_clk_div2_q_reg[2]_srl3/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.018 11.335 tx_wordclk SLICE_X59Y267 SRL16E r fabric_clk_div2_q_reg[2]_srl3/CLK clock pessimism 0.000 11.335 inter-SLR compensation -0.453 10.882 clock uncertainty -0.248 10.634 SLICE_X59Y267 SRL16E (Setup_A6LUT_SLICEM_CLK_D) -0.055 10.579 fabric_clk_div2_q_reg[2]_srl3 ------------------------------------------------------------------- required time 10.579 arrival time -6.483 ------------------------------------------------------------------- slack 4.096 Slack (MET) : 4.320ns (required time - arrival time) Source: SFP_GEN[42].ngCCM_gbt/TX_Word_o_reg[1]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.451ns (logic 0.375ns (10.866%) route 3.076ns (89.134%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.361ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.419ns = ( 11.736 - 8.317 ) Source Clock Delay (SCD): 3.780ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.780ns (routing 1.005ns, distribution 2.775ns) Clock Net Delay (Destination): 3.419ns (routing 1.026ns, distribution 2.393ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.780 3.780 SFP_GEN[42].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X41Y374 FDRE r SFP_GEN[42].ngCCM_gbt/TX_Word_o_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y374 FDRE (Prop_HFF2_SLICEM_C_Q) 0.137 3.917 r SFP_GEN[42].ngCCM_gbt/TX_Word_o_reg[1]/Q net (fo=2, routed) 3.041 6.958 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_1[1] SLICE_X43Y373 LUT5 (Prop_D6LUT_SLICEL_I1_O) 0.238 7.196 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[20]_i_1__335/O net (fo=1, routed) 0.035 7.231 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[20] SLICE_X43Y373 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.419 11.736 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X43Y373 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]/C clock pessimism 0.000 11.736 clock uncertainty -0.248 11.488 SLICE_X43Y373 FDPE (Setup_DFF_SLICEL_C_D) 0.063 11.551 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time 11.551 arrival time -7.231 ------------------------------------------------------------------- slack 4.320 Slack (MET) : 4.440ns (required time - arrival time) Source: SFP_GEN[27].ngCCM_gbt/TX_Word_o_reg[32]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.371ns (logic 0.382ns (11.332%) route 2.989ns (88.668%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.320ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.395ns = ( 11.712 - 8.317 ) Source Clock Delay (SCD): 3.715ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.715ns (routing 1.005ns, distribution 2.710ns) Clock Net Delay (Destination): 3.395ns (routing 1.026ns, distribution 2.369ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.715 3.715 SFP_GEN[27].ngCCM_gbt/fabric_clk SLICE_X34Y167 FDRE r SFP_GEN[27].ngCCM_gbt/TX_Word_o_reg[32]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y167 FDRE (Prop_EFF_SLICEM_C_Q) 0.139 3.854 r SFP_GEN[27].ngCCM_gbt/TX_Word_o_reg[32]/Q net (fo=1, routed) 2.955 6.809 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[11] SLICE_X34Y166 LUT3 (Prop_B6LUT_SLICEM_I1_O) 0.243 7.052 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[11]_i_1__232/O net (fo=1, routed) 0.034 7.086 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[11] SLICE_X34Y166 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.395 11.712 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLICE_X34Y166 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]/C clock pessimism 0.000 11.712 clock uncertainty -0.248 11.464 SLICE_X34Y166 FDCE (Setup_BFF_SLICEM_C_D) 0.062 11.526 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time 11.526 arrival time -7.086 ------------------------------------------------------------------- slack 4.440 Slack (MET) : 4.487ns (required time - arrival time) Source: SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[69]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.053ns (logic 0.372ns (12.185%) route 2.681ns (87.815%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.592ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.335ns = ( 11.652 - 8.317 ) Source Clock Delay (SCD): 3.927ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.927ns (routing 1.005ns, distribution 2.922ns) Clock Net Delay (Destination): 3.335ns (routing 1.026ns, distribution 2.309ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.927 3.927 SFP_GEN[19].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X116Y470 FDRE r SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[69]/C ------------------------------------------------------------------- ------------------- SLICE_X116Y470 FDRE (Prop_HFF2_SLICEL_C_Q) 0.137 4.064 r SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[69]/Q net (fo=1, routed) 2.644 6.708 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]_2[6] SLICE_X93Y377 LUT3 (Prop_C6LUT_SLICEL_I1_O) 0.235 6.943 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[6]_i_1__130/O net (fo=1, routed) 0.037 6.980 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[6] SLICE_X93Y377 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.335 11.652 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X93Y377 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6]/C clock pessimism 0.000 11.652 clock uncertainty -0.248 11.404 SLICE_X93Y377 FDCE (Setup_CFF_SLICEL_C_D) 0.063 11.467 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time 11.467 arrival time -6.980 ------------------------------------------------------------------- slack 4.487 Slack (MET) : 4.687ns (required time - arrival time) Source: SFP_GEN[42].ngCCM_gbt/TX_Word_o_reg[1]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[1]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.091ns (logic 0.229ns (7.409%) route 2.862ns (92.591%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.354ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.426ns = ( 11.743 - 8.317 ) Source Clock Delay (SCD): 3.780ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.780ns (routing 1.005ns, distribution 2.775ns) Clock Net Delay (Destination): 3.426ns (routing 1.026ns, distribution 2.400ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.780 3.780 SFP_GEN[42].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X41Y374 FDRE r SFP_GEN[42].ngCCM_gbt/TX_Word_o_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y374 FDRE (Prop_HFF2_SLICEM_C_Q) 0.137 3.917 r SFP_GEN[42].ngCCM_gbt/TX_Word_o_reg[1]/Q net (fo=2, routed) 2.827 6.744 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_1[1] SLICE_X41Y373 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.836 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[1]_i_1__287/O net (fo=1, routed) 0.035 6.871 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[1] SLICE_X41Y373 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[1]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.426 11.743 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X41Y373 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[1]/C clock pessimism 0.000 11.743 clock uncertainty -0.248 11.495 SLICE_X41Y373 FDCE (Setup_DFF_SLICEM_C_D) 0.063 11.558 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time 11.558 arrival time -6.871 ------------------------------------------------------------------- slack 4.687 Slack (MET) : 4.703ns (required time - arrival time) Source: SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[14]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[14]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.228ns (logic 0.362ns (11.214%) route 2.866ns (88.786%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.201ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.701ns = ( 12.018 - 8.317 ) Source Clock Delay (SCD): 3.902ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.902ns (routing 1.005ns, distribution 2.897ns) Clock Net Delay (Destination): 3.701ns (routing 1.026ns, distribution 2.675ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.902 3.902 SFP_GEN[22].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X107Y549 FDRE r SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y549 FDRE (Prop_HFF2_SLICEM_C_Q) 0.137 4.039 r SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[14]/Q net (fo=1, routed) 2.831 6.870 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/TX_DATA_I[14] SLICE_X110Y550 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 7.095 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[14]_i_1__123/O net (fo=1, routed) 0.035 7.130 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[14] SLICE_X110Y550 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[14]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.701 12.018 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X110Y550 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[14]/C clock pessimism 0.000 12.018 clock uncertainty -0.248 11.770 SLICE_X110Y550 FDCE (Setup_DFF_SLICEM_C_D) 0.063 11.833 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time 11.833 arrival time -7.130 ------------------------------------------------------------------- slack 4.703 Slack (MET) : 4.726ns (required time - arrival time) Source: SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[60]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 2.804ns (logic 0.384ns (13.695%) route 2.420ns (86.305%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.603ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.309ns = ( 11.626 - 8.317 ) Source Clock Delay (SCD): 3.912ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.912ns (routing 1.005ns, distribution 2.907ns) Clock Net Delay (Destination): 3.309ns (routing 1.026ns, distribution 2.283ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.912 3.912 SFP_GEN[19].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X107Y465 FDRE r SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[60]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y465 FDRE (Prop_EFF2_SLICEM_C_Q) 0.138 4.050 r SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[60]/Q net (fo=1, routed) 2.386 6.436 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[16] SLICE_X90Y388 LUT3 (Prop_G6LUT_SLICEM_I2_O) 0.246 6.682 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[18]_i_1__129/O net (fo=1, routed) 0.034 6.716 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[18] SLICE_X90Y388 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.309 11.626 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X90Y388 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/C clock pessimism 0.000 11.626 clock uncertainty -0.248 11.378 SLICE_X90Y388 FDCE (Setup_GFF_SLICEM_C_D) 0.064 11.442 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time 11.442 arrival time -6.716 ------------------------------------------------------------------- slack 4.726 Slack (MET) : 4.744ns (required time - arrival time) Source: SFP_GEN[41].ngCCM_gbt/TX_Word_o_reg[38]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[17]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.104ns (logic 0.304ns (9.794%) route 2.800ns (90.206%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.086ns = ( 11.403 - 8.317 ) Source Clock Delay (SCD): 3.369ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.369ns (routing 1.005ns, distribution 2.364ns) Clock Net Delay (Destination): 3.086ns (routing 1.026ns, distribution 2.060ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.369 3.369 SFP_GEN[41].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X58Y390 FDRE r SFP_GEN[41].ngCCM_gbt/TX_Word_o_reg[38]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y390 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.507 r SFP_GEN[41].ngCCM_gbt/TX_Word_o_reg[38]/Q net (fo=1, routed) 2.767 6.274 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[17] SLICE_X60Y363 LUT3 (Prop_B6LUT_SLICEL_I1_O) 0.166 6.440 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[17]_i_1__308/O net (fo=1, routed) 0.033 6.473 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[17] SLICE_X60Y363 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[17]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.086 11.403 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X60Y363 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[17]/C clock pessimism 0.000 11.403 clock uncertainty -0.248 11.155 SLICE_X60Y363 FDPE (Setup_BFF_SLICEL_C_D) 0.062 11.217 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time 11.217 arrival time -6.473 ------------------------------------------------------------------- slack 4.744 Slack (MET) : 4.767ns (required time - arrival time) Source: SFP_GEN[14].ngCCM_gbt/TX_Word_o_reg[32]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.104ns (logic 0.372ns (11.985%) route 2.732ns (88.015%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.261ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.671ns = ( 11.988 - 8.317 ) Source Clock Delay (SCD): 3.932ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.932ns (routing 1.005ns, distribution 2.927ns) Clock Net Delay (Destination): 3.671ns (routing 1.026ns, distribution 2.645ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.932 3.932 SFP_GEN[14].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X112Y368 FDRE r SFP_GEN[14].ngCCM_gbt/TX_Word_o_reg[32]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y368 FDRE (Prop_HFF2_SLICEM_C_Q) 0.137 4.069 r SFP_GEN[14].ngCCM_gbt/TX_Word_o_reg[32]/Q net (fo=1, routed) 2.695 6.764 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[11] SLICE_X114Y367 LUT3 (Prop_C6LUT_SLICEL_I1_O) 0.235 6.999 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[11]_i_1__152/O net (fo=1, routed) 0.037 7.036 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[11] SLICE_X114Y367 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.671 11.988 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X114Y367 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11]/C clock pessimism 0.000 11.988 clock uncertainty -0.248 11.740 SLICE_X114Y367 FDCE (Setup_CFF_SLICEL_C_D) 0.063 11.803 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time 11.803 arrival time -7.036 ------------------------------------------------------------------- slack 4.767 Slack (MET) : 4.775ns (required time - arrival time) Source: SFP_GEN[31].ngCCM_gbt/TX_Word_o_reg[7]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[7]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Setup (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - fabric_clk rise@0.000ns) Data Path Delay: 3.030ns (logic 0.362ns (11.947%) route 2.668ns (88.053%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.327ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.033ns = ( 11.350 - 8.317 ) Source Clock Delay (SCD): 3.360ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 3.360ns (routing 1.005ns, distribution 2.355ns) Clock Net Delay (Destination): 3.033ns (routing 1.026ns, distribution 2.007ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.360 3.360 SFP_GEN[31].ngCCM_gbt/fabric_clk SLICE_X61Y255 FDRE r SFP_GEN[31].ngCCM_gbt/TX_Word_o_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y255 FDRE (Prop_FFF2_SLICEM_C_Q) 0.138 3.498 r SFP_GEN[31].ngCCM_gbt/TX_Word_o_reg[7]/Q net (fo=1, routed) 2.630 6.128 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[7] SLICE_X61Y255 LUT3 (Prop_C6LUT_SLICEM_I2_O) 0.224 6.352 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[7]_i_1__247/O net (fo=1, routed) 0.038 6.390 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[7] SLICE_X61Y255 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[7]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.033 11.350 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk SLICE_X61Y255 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[7]/C clock pessimism 0.000 11.350 clock uncertainty -0.248 11.102 SLICE_X61Y255 FDPE (Setup_CFF_SLICEM_C_D) 0.063 11.165 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time 11.165 arrival time -6.390 ------------------------------------------------------------------- slack 4.775 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.029ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/TX_Word_o_reg[52]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.604ns (logic 0.101ns (16.722%) route 0.503ns (83.278%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.271ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.650ns Source Clock Delay (SCD): 1.379ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.379ns (routing 0.393ns, distribution 0.986ns) Clock Net Delay (Destination): 1.650ns (routing 0.493ns, distribution 1.157ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.379 1.379 SFP_GEN[27].ngCCM_gbt/fabric_clk SLICE_X30Y160 FDRE r SFP_GEN[27].ngCCM_gbt/TX_Word_o_reg[52]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y160 FDRE (Prop_GFF_SLICEL_C_Q) 0.048 1.427 r SFP_GEN[27].ngCCM_gbt/TX_Word_o_reg[52]/Q net (fo=1, routed) 0.487 1.914 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[8] SLICE_X30Y160 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.053 1.967 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[10]_i_1__233/O net (fo=1, routed) 0.016 1.983 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[10] SLICE_X30Y160 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.650 1.650 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLICE_X30Y160 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/C clock pessimism 0.000 1.650 clock uncertainty 0.248 1.898 SLICE_X30Y160 FDPE (Hold_DFF_SLICEL_C_D) 0.056 1.954 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -1.954 arrival time 1.983 ------------------------------------------------------------------- slack 0.029 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/TX_Word_o_reg[29]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[8]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.667ns (logic 0.102ns (15.292%) route 0.565ns (84.708%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.728ns Source Clock Delay (SCD): 1.395ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.395ns (routing 0.393ns, distribution 1.002ns) Clock Net Delay (Destination): 1.728ns (routing 0.493ns, distribution 1.235ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.395 1.395 SFP_GEN[9].ngCCM_gbt/fabric_clk SLICE_X113Y205 FDRE r SFP_GEN[9].ngCCM_gbt/TX_Word_o_reg[29]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y205 FDRE (Prop_EFF_SLICEM_C_Q) 0.049 1.444 r SFP_GEN[9].ngCCM_gbt/TX_Word_o_reg[29]/Q net (fo=1, routed) 0.553 1.997 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[8] SLICE_X114Y136 LUT3 (Prop_A6LUT_SLICEL_I2_O) 0.053 2.050 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[8]_i_1__64/O net (fo=1, routed) 0.012 2.062 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[8] SLICE_X114Y136 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[8]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.728 1.728 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLICE_X114Y136 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[8]/C clock pessimism 0.000 1.728 clock uncertainty 0.248 1.976 SLICE_X114Y136 FDPE (Hold_AFF_SLICEL_C_D) 0.056 2.032 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -2.032 arrival time 2.062 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[8].ngCCM_gbt/TX_Word_o_reg[70]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.669ns (logic 0.112ns (16.741%) route 0.557ns (83.259%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.833ns Source Clock Delay (SCD): 1.498ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.498ns (routing 0.393ns, distribution 1.105ns) Clock Net Delay (Destination): 1.833ns (routing 0.493ns, distribution 1.340ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.498 1.498 SFP_GEN[8].ngCCM_gbt/fabric_clk SLICE_X133Y138 FDRE r SFP_GEN[8].ngCCM_gbt/TX_Word_o_reg[70]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y138 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.546 r SFP_GEN[8].ngCCM_gbt/TX_Word_o_reg[70]/Q net (fo=1, routed) 0.542 2.088 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]_2[7] SLICE_X133Y138 LUT3 (Prop_B6LUT_SLICEL_I2_O) 0.064 2.152 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[7]_i_1__62/O net (fo=1, routed) 0.015 2.167 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[7] SLICE_X133Y138 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.833 1.833 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLICE_X133Y138 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/C clock pessimism 0.000 1.833 clock uncertainty 0.248 2.081 SLICE_X133Y138 FDCE (Hold_BFF_SLICEL_C_D) 0.056 2.137 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[8].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -2.137 arrival time 2.167 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[56]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.644ns (logic 0.100ns (15.528%) route 0.544ns (84.472%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.310ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.772ns Source Clock Delay (SCD): 1.462ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.462ns (routing 0.393ns, distribution 1.069ns) Clock Net Delay (Destination): 1.772ns (routing 0.493ns, distribution 1.279ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.462 1.462 SFP_GEN[22].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X105Y540 FDRE r SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[56]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y540 FDRE (Prop_EFF2_SLICEL_C_Q) 0.048 1.510 r SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[56]/Q net (fo=1, routed) 0.528 2.038 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/TX_DATA_I[12] SLICE_X105Y541 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.052 2.090 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[14]_i_1__125/O net (fo=1, routed) 0.016 2.106 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[14] SLICE_X105Y541 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.772 1.772 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X105Y541 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]/C clock pessimism 0.000 1.772 clock uncertainty 0.248 2.020 SLICE_X105Y541 FDPE (Hold_HFF_SLICEL_C_D) 0.056 2.076 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -2.076 arrival time 2.106 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[18]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[18]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.700ns (logic 0.113ns (16.143%) route 0.587ns (83.857%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.366ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.864ns Source Clock Delay (SCD): 1.498ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.498ns (routing 0.393ns, distribution 1.105ns) Clock Net Delay (Destination): 1.864ns (routing 0.493ns, distribution 1.371ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.498 1.498 SFP_GEN[13].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X127Y364 FDRE r SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y364 FDRE (Prop_AFF_SLICEL_C_Q) 0.049 1.547 r SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[18]/Q net (fo=1, routed) 0.571 2.118 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[18] SLICE_X137Y340 LUT3 (Prop_C6LUT_SLICEL_I2_O) 0.064 2.182 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[18]_i_1__159/O net (fo=1, routed) 0.016 2.198 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[18] SLICE_X137Y340 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[18]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.864 1.864 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X137Y340 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[18]/C clock pessimism 0.000 1.864 clock uncertainty 0.248 2.112 SLICE_X137Y340 FDCE (Hold_CFF_SLICEL_C_D) 0.056 2.168 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -2.168 arrival time 2.198 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[16].ngCCM_gbt/TX_Word_o_reg[2]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.671ns (logic 0.093ns (13.860%) route 0.578ns (86.140%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.337ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.868ns Source Clock Delay (SCD): 1.531ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.531ns (routing 0.393ns, distribution 1.138ns) Clock Net Delay (Destination): 1.868ns (routing 0.493ns, distribution 1.375ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.531 1.531 SFP_GEN[16].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X130Y442 FDRE r SFP_GEN[16].ngCCM_gbt/TX_Word_o_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y442 FDRE (Prop_GFF2_SLICEL_C_Q) 0.048 1.579 r SFP_GEN[16].ngCCM_gbt/TX_Word_o_reg[2]/Q net (fo=1, routed) 0.563 2.142 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[2] SLICE_X130Y442 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.045 2.187 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[2]_i_1__143/O net (fo=1, routed) 0.015 2.202 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[2] SLICE_X130Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.868 1.868 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X130Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]/C clock pessimism 0.000 1.868 clock uncertainty 0.248 2.116 SLICE_X130Y442 FDCE (Hold_BFF_SLICEL_C_D) 0.056 2.172 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -2.172 arrival time 2.202 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[55]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.584ns (logic 0.112ns (19.178%) route 0.472ns (80.822%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.250ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.768ns Source Clock Delay (SCD): 1.518ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.518ns (routing 0.393ns, distribution 1.125ns) Clock Net Delay (Destination): 1.768ns (routing 0.493ns, distribution 1.275ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.518 1.518 SFP_GEN[19].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X126Y471 FDRE r SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[55]/C ------------------------------------------------------------------- ------------------- SLICE_X126Y471 FDRE (Prop_FFF2_SLICEM_C_Q) 0.048 1.566 r SFP_GEN[19].ngCCM_gbt/TX_Word_o_reg[55]/Q net (fo=1, routed) 0.456 2.022 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[11] SLICE_X117Y456 LUT3 (Prop_D6LUT_SLICEL_I1_O) 0.064 2.086 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[13]_i_1__129/O net (fo=1, routed) 0.016 2.102 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[13] SLICE_X117Y456 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.768 1.768 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X117Y456 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13]/C clock pessimism 0.000 1.768 clock uncertainty 0.248 2.016 SLICE_X117Y456 FDPE (Hold_DFF_SLICEL_C_D) 0.056 2.072 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[7].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -2.072 arrival time 2.102 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[21].ngCCM_gbt/TX_Word_o_reg[64]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]/D (rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.633ns (logic 0.113ns (17.852%) route 0.520ns (82.148%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.299ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.747ns Source Clock Delay (SCD): 1.448ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.448ns (routing 0.393ns, distribution 1.055ns) Clock Net Delay (Destination): 1.747ns (routing 0.493ns, distribution 1.254ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.448 1.448 SFP_GEN[21].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X105Y526 FDRE r SFP_GEN[21].ngCCM_gbt/TX_Word_o_reg[64]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y526 FDRE (Prop_EFF_SLICEL_C_Q) 0.049 1.497 r SFP_GEN[21].ngCCM_gbt/TX_Word_o_reg[64]/Q net (fo=2, routed) 0.504 2.001 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]_2[1] SLICE_X105Y502 LUT5 (Prop_C6LUT_SLICEL_I1_O) 0.064 2.065 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[20]_i_1__162/O net (fo=1, routed) 0.016 2.081 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[20] SLICE_X105Y502 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.747 1.747 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X105Y502 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]/C clock pessimism 0.000 1.747 clock uncertainty 0.248 1.995 SLICE_X105Y502 FDCE (Hold_CFF_SLICEL_C_D) 0.056 2.051 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -2.051 arrival time 2.081 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[35].ngCCM_gbt/TX_Word_o_reg[52]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.623ns (logic 0.112ns (17.978%) route 0.511ns (82.022%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.289ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.719ns Source Clock Delay (SCD): 1.430ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.430ns (routing 0.393ns, distribution 1.037ns) Clock Net Delay (Destination): 1.719ns (routing 0.493ns, distribution 1.226ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.430 1.430 SFP_GEN[35].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X8Y331 FDRE r SFP_GEN[35].ngCCM_gbt/TX_Word_o_reg[52]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y331 FDRE (Prop_HFF_SLICEL_C_Q) 0.048 1.478 r SFP_GEN[35].ngCCM_gbt/TX_Word_o_reg[52]/Q net (fo=1, routed) 0.495 1.973 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[8] SLICE_X8Y331 LUT3 (Prop_C6LUT_SLICEL_I1_O) 0.064 2.037 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[10]_i_1__241/O net (fo=1, routed) 0.016 2.053 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[10] SLICE_X8Y331 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.719 1.719 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X8Y331 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/C clock pessimism 0.000 1.719 clock uncertainty 0.248 1.967 SLICE_X8Y331 FDPE (Hold_CFF_SLICEL_C_D) 0.056 2.023 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -2.023 arrival time 2.053 ------------------------------------------------------------------- slack 0.030 Slack (MET) : 0.030ns (arrival time - required time) Source: SFP_GEN[29].ngCCM_gbt/TX_Word_o_reg[35]/C (rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]/D (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: tx_wordclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.604ns (logic 0.121ns (20.033%) route 0.483ns (79.967%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.270ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.634ns Source Clock Delay (SCD): 1.364ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.248ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.120ns Clock Net Delay (Source): 1.364ns (routing 0.393ns, distribution 0.971ns) Clock Net Delay (Destination): 1.634ns (routing 0.493ns, distribution 1.141ns) Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.364 1.364 SFP_GEN[29].ngCCM_gbt/fabric_clk SLICE_X34Y237 FDRE r SFP_GEN[29].ngCCM_gbt/TX_Word_o_reg[35]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y237 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.413 r SFP_GEN[29].ngCCM_gbt/TX_Word_o_reg[35]/Q net (fo=1, routed) 0.468 1.881 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[14] SLICE_X34Y237 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.072 1.953 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[14]_i_1__224/O net (fo=1, routed) 0.015 1.968 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[14] SLICE_X34Y237 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]/D ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.634 1.634 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk SLICE_X34Y237 FDPE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]/C clock pessimism 0.000 1.634 clock uncertainty 0.248 1.882 SLICE_X34Y237 FDPE (Hold_BFF_SLICEM_C_D) 0.056 1.938 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[5].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.938 arrival time 1.968 ------------------------------------------------------------------- slack 0.030 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: DRPclk To Clock: DRPclk Setup : 0 Failing Endpoints, Worst Slack 15.411ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.250ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 15.411ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.258ns (logic 0.385ns (9.042%) route 3.873ns (90.958%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.706ns = ( 22.706 - 20.000 ) Source Clock Delay (SCD): 3.063ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.063ns (routing 0.701ns, distribution 2.362ns) Clock Net Delay (Destination): 2.706ns (routing 0.646ns, distribution 2.060ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.063 3.063 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X64Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X64Y598 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.201 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.886 5.087 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 SLICE_X42Y567 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.247 5.334 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/O net (fo=10, routed) 1.987 7.321 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X61Y599 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.706 22.706 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X61Y599 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C clock pessimism 0.198 22.904 clock uncertainty -0.079 22.825 SLICE_X61Y599 FDPE (Recov_DFF2_SLICEM_C_PRE) -0.093 22.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg ------------------------------------------------------------------- required time 22.732 arrival time -7.321 ------------------------------------------------------------------- slack 15.411 Slack (MET) : 15.411ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.258ns (logic 0.385ns (9.042%) route 3.873ns (90.958%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.706ns = ( 22.706 - 20.000 ) Source Clock Delay (SCD): 3.063ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.063ns (routing 0.701ns, distribution 2.362ns) Clock Net Delay (Destination): 2.706ns (routing 0.646ns, distribution 2.060ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.063 3.063 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X64Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X64Y598 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.201 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.886 5.087 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 SLICE_X42Y567 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.247 5.334 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/O net (fo=10, routed) 1.987 7.321 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X61Y599 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.706 22.706 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X61Y599 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C clock pessimism 0.198 22.904 clock uncertainty -0.079 22.825 SLICE_X61Y599 FDPE (Recov_AFF2_SLICEM_C_PRE) -0.093 22.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time 22.732 arrival time -7.321 ------------------------------------------------------------------- slack 15.411 Slack (MET) : 15.411ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.258ns (logic 0.385ns (9.042%) route 3.873ns (90.958%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.706ns = ( 22.706 - 20.000 ) Source Clock Delay (SCD): 3.063ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.063ns (routing 0.701ns, distribution 2.362ns) Clock Net Delay (Destination): 2.706ns (routing 0.646ns, distribution 2.060ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.063 3.063 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X64Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X64Y598 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.201 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.886 5.087 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 SLICE_X42Y567 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.247 5.334 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/O net (fo=10, routed) 1.987 7.321 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X61Y599 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.706 22.706 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X61Y599 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C clock pessimism 0.198 22.904 clock uncertainty -0.079 22.825 SLICE_X61Y599 FDPE (Recov_BFF2_SLICEM_C_PRE) -0.093 22.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time 22.732 arrival time -7.321 ------------------------------------------------------------------- slack 15.411 Slack (MET) : 15.411ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.258ns (logic 0.385ns (9.042%) route 3.873ns (90.958%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.159ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.706ns = ( 22.706 - 20.000 ) Source Clock Delay (SCD): 3.063ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.063ns (routing 0.701ns, distribution 2.362ns) Clock Net Delay (Destination): 2.706ns (routing 0.646ns, distribution 2.060ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.063 3.063 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X64Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X64Y598 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.201 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.886 5.087 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 SLICE_X42Y567 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.247 5.334 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/O net (fo=10, routed) 1.987 7.321 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X61Y599 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.706 22.706 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X61Y599 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C clock pessimism 0.198 22.904 clock uncertainty -0.079 22.825 SLICE_X61Y599 FDPE (Recov_CFF2_SLICEM_C_PRE) -0.093 22.732 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time 22.732 arrival time -7.321 ------------------------------------------------------------------- slack 15.411 Slack (MET) : 15.417ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.251ns (logic 0.385ns (9.057%) route 3.866ns (90.943%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.704ns = ( 22.704 - 20.000 ) Source Clock Delay (SCD): 3.063ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.063ns (routing 0.701ns, distribution 2.362ns) Clock Net Delay (Destination): 2.704ns (routing 0.646ns, distribution 2.058ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.063 3.063 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X64Y598 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X64Y598 FDRE (Prop_HFF_SLICEM_C_Q) 0.138 3.201 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.886 5.087 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 SLICE_X42Y567 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.247 5.334 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35/O net (fo=10, routed) 1.980 7.314 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X61Y599 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.704 22.704 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X61Y599 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C clock pessimism 0.198 22.902 clock uncertainty -0.079 22.824 SLICE_X61Y599 FDPE (Recov_EFF_SLICEM_C_PRE) -0.093 22.731 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time 22.731 arrival time -7.314 ------------------------------------------------------------------- slack 15.417 Slack (MET) : 15.500ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.074ns (logic 0.231ns (5.670%) route 3.843ns (94.330%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.254ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.724ns = ( 22.724 - 20.000 ) Source Clock Delay (SCD): 3.175ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.175ns (routing 0.701ns, distribution 2.474ns) Clock Net Delay (Destination): 2.724ns (routing 0.646ns, distribution 2.078ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.175 3.175 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X71Y555 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y555 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 3.314 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.996 5.310 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_10 SLICE_X42Y567 LUT2 (Prop_D6LUT_SLICEM_I1_O) 0.092 5.402 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/O net (fo=10, routed) 1.847 7.249 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X66Y555 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.724 22.724 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X66Y555 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C clock pessimism 0.197 22.921 clock uncertainty -0.079 22.842 SLICE_X66Y555 FDPE (Recov_DFF2_SLICEL_C_PRE) -0.093 22.749 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg ------------------------------------------------------------------- required time 22.749 arrival time -7.249 ------------------------------------------------------------------- slack 15.500 Slack (MET) : 15.500ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.074ns (logic 0.231ns (5.670%) route 3.843ns (94.330%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.254ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.724ns = ( 22.724 - 20.000 ) Source Clock Delay (SCD): 3.175ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.175ns (routing 0.701ns, distribution 2.474ns) Clock Net Delay (Destination): 2.724ns (routing 0.646ns, distribution 2.078ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.175 3.175 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X71Y555 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y555 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 3.314 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.996 5.310 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_10 SLICE_X42Y567 LUT2 (Prop_D6LUT_SLICEM_I1_O) 0.092 5.402 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/O net (fo=10, routed) 1.847 7.249 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X66Y555 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.724 22.724 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X66Y555 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C clock pessimism 0.197 22.921 clock uncertainty -0.079 22.842 SLICE_X66Y555 FDPE (Recov_AFF2_SLICEL_C_PRE) -0.093 22.749 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time 22.749 arrival time -7.249 ------------------------------------------------------------------- slack 15.500 Slack (MET) : 15.500ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.074ns (logic 0.231ns (5.670%) route 3.843ns (94.330%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.254ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.724ns = ( 22.724 - 20.000 ) Source Clock Delay (SCD): 3.175ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.175ns (routing 0.701ns, distribution 2.474ns) Clock Net Delay (Destination): 2.724ns (routing 0.646ns, distribution 2.078ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.175 3.175 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X71Y555 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y555 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 3.314 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.996 5.310 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_10 SLICE_X42Y567 LUT2 (Prop_D6LUT_SLICEM_I1_O) 0.092 5.402 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/O net (fo=10, routed) 1.847 7.249 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X66Y555 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.724 22.724 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X66Y555 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C clock pessimism 0.197 22.921 clock uncertainty -0.079 22.842 SLICE_X66Y555 FDPE (Recov_BFF2_SLICEL_C_PRE) -0.093 22.749 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time 22.749 arrival time -7.249 ------------------------------------------------------------------- slack 15.500 Slack (MET) : 15.500ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.074ns (logic 0.231ns (5.670%) route 3.843ns (94.330%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.254ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.724ns = ( 22.724 - 20.000 ) Source Clock Delay (SCD): 3.175ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.175ns (routing 0.701ns, distribution 2.474ns) Clock Net Delay (Destination): 2.724ns (routing 0.646ns, distribution 2.078ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.175 3.175 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X71Y555 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y555 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 3.314 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.996 5.310 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_10 SLICE_X42Y567 LUT2 (Prop_D6LUT_SLICEM_I1_O) 0.092 5.402 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/O net (fo=10, routed) 1.847 7.249 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X66Y555 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.724 22.724 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X66Y555 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C clock pessimism 0.197 22.921 clock uncertainty -0.079 22.842 SLICE_X66Y555 FDPE (Recov_CFF2_SLICEL_C_PRE) -0.093 22.749 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time 22.749 arrival time -7.249 ------------------------------------------------------------------- slack 15.500 Slack (MET) : 15.508ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE (recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (DRPclk rise@20.000ns - DRPclk rise@0.000ns) Data Path Delay: 4.064ns (logic 0.231ns (5.684%) route 3.833ns (94.316%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.256ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.722ns = ( 22.722 - 20.000 ) Source Clock Delay (SCD): 3.175ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.141ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.175ns (routing 0.701ns, distribution 2.474ns) Clock Net Delay (Destination): 2.722ns (routing 0.646ns, distribution 2.076ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 3.175 3.175 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X71Y555 FDRE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X71Y555 FDRE (Prop_BFF_SLICEM_C_Q) 0.139 3.314 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_all_out_reg/Q net (fo=2, routed) 1.996 5.310 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_10 SLICE_X42Y567 LUT2 (Prop_D6LUT_SLICEM_I1_O) 0.092 5.402 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45/O net (fo=10, routed) 1.837 7.239 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X66Y555 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 20.000 20.000 r BUFGCE_X1Y109 BUFGCE 0.000 20.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 2.722 22.722 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X66Y555 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C clock pessimism 0.197 22.919 clock uncertainty -0.079 22.840 SLICE_X66Y555 FDPE (Recov_EFF_SLICEL_C_PRE) -0.093 22.747 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time 22.747 arrival time -7.239 ------------------------------------------------------------------- slack 15.508 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.250ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.291ns (logic 0.088ns (30.241%) route 0.203ns (69.759%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.468ns Source Clock Delay (SCD): 1.252ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 1.252ns (routing 0.240ns, distribution 1.012ns) Clock Net Delay (Destination): 1.468ns (routing 0.266ns, distribution 1.202ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.252 1.252 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/aurora_init_clk SLICE_X110Y144 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X110Y144 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.300 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.039 1.339 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_5 SLICE_X110Y144 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.040 1.379 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/O net (fo=10, routed) 0.164 1.543 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X111Y144 FDPE f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.468 1.468 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X111Y144 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C clock pessimism -0.180 1.288 SLICE_X111Y144 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.293 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time -1.293 arrival time 1.543 ------------------------------------------------------------------- slack 0.250 Slack (MET) : 0.253ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.297ns (logic 0.088ns (29.630%) route 0.209ns (70.370%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.471ns Source Clock Delay (SCD): 1.252ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 1.252ns (routing 0.240ns, distribution 1.012ns) Clock Net Delay (Destination): 1.471ns (routing 0.266ns, distribution 1.205ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.252 1.252 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/aurora_init_clk SLICE_X110Y144 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X110Y144 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.300 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.039 1.339 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_5 SLICE_X110Y144 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.040 1.379 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/O net (fo=10, routed) 0.170 1.549 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X111Y144 FDPE f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.471 1.471 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X111Y144 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C clock pessimism -0.180 1.291 SLICE_X111Y144 FDPE (Remov_DFF2_SLICEL_C_PRE) 0.005 1.296 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg ------------------------------------------------------------------- required time -1.296 arrival time 1.549 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.253ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.297ns (logic 0.088ns (29.630%) route 0.209ns (70.370%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.471ns Source Clock Delay (SCD): 1.252ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 1.252ns (routing 0.240ns, distribution 1.012ns) Clock Net Delay (Destination): 1.471ns (routing 0.266ns, distribution 1.205ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.252 1.252 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/aurora_init_clk SLICE_X110Y144 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X110Y144 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.300 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.039 1.339 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_5 SLICE_X110Y144 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.040 1.379 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/O net (fo=10, routed) 0.170 1.549 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X111Y144 FDPE f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.471 1.471 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X111Y144 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C clock pessimism -0.180 1.291 SLICE_X111Y144 FDPE (Remov_AFF2_SLICEL_C_PRE) 0.005 1.296 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time -1.296 arrival time 1.549 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.253ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.297ns (logic 0.088ns (29.630%) route 0.209ns (70.370%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.471ns Source Clock Delay (SCD): 1.252ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 1.252ns (routing 0.240ns, distribution 1.012ns) Clock Net Delay (Destination): 1.471ns (routing 0.266ns, distribution 1.205ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.252 1.252 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/aurora_init_clk SLICE_X110Y144 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X110Y144 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.300 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.039 1.339 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_5 SLICE_X110Y144 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.040 1.379 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/O net (fo=10, routed) 0.170 1.549 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X111Y144 FDPE f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.471 1.471 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X111Y144 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C clock pessimism -0.180 1.291 SLICE_X111Y144 FDPE (Remov_BFF2_SLICEL_C_PRE) 0.005 1.296 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time -1.296 arrival time 1.549 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.253ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.297ns (logic 0.088ns (29.630%) route 0.209ns (70.370%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.471ns Source Clock Delay (SCD): 1.252ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 1.252ns (routing 0.240ns, distribution 1.012ns) Clock Net Delay (Destination): 1.471ns (routing 0.266ns, distribution 1.205ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.252 1.252 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/aurora_init_clk SLICE_X110Y144 FDRE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X110Y144 FDRE (Prop_CFF_SLICEM_C_Q) 0.048 1.300 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.039 1.339 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_5 SLICE_X110Y144 LUT2 (Prop_D5LUT_SLICEM_I1_O) 0.040 1.379 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4/O net (fo=10, routed) 0.170 1.549 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X111Y144 FDPE f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.471 1.471 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X111Y144 FDPE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C clock pessimism -0.180 1.291 SLICE_X111Y144 FDPE (Remov_CFF2_SLICEL_C_PRE) 0.005 1.296 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time -1.296 arrival time 1.549 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.262ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.348ns (logic 0.095ns (27.299%) route 0.253ns (72.701%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.511ns Source Clock Delay (SCD): 1.293ns Clock Pessimism Removal (CPR): 0.137ns Clock Net Delay (Source): 1.293ns (routing 0.240ns, distribution 1.053ns) Clock Net Delay (Destination): 1.511ns (routing 0.266ns, distribution 1.245ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.293 1.293 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X107Y524 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y524 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.342 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.077 1.419 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_6 SLICE_X107Y526 LUT2 (Prop_D6LUT_SLICEM_I1_O) 0.046 1.465 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/O net (fo=10, routed) 0.176 1.641 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X109Y526 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.511 1.511 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X109Y526 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C clock pessimism -0.137 1.374 SLICE_X109Y526 FDPE (Remov_DFF2_SLICEM_C_PRE) 0.005 1.379 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg ------------------------------------------------------------------- required time -1.379 arrival time 1.641 ------------------------------------------------------------------- slack 0.262 Slack (MET) : 0.262ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.348ns (logic 0.095ns (27.299%) route 0.253ns (72.701%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.511ns Source Clock Delay (SCD): 1.293ns Clock Pessimism Removal (CPR): 0.137ns Clock Net Delay (Source): 1.293ns (routing 0.240ns, distribution 1.053ns) Clock Net Delay (Destination): 1.511ns (routing 0.266ns, distribution 1.245ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.293 1.293 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X107Y524 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y524 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.342 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.077 1.419 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_6 SLICE_X107Y526 LUT2 (Prop_D6LUT_SLICEM_I1_O) 0.046 1.465 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/O net (fo=10, routed) 0.176 1.641 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X109Y526 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.511 1.511 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X109Y526 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C clock pessimism -0.137 1.374 SLICE_X109Y526 FDPE (Remov_AFF_SLICEM_C_PRE) 0.005 1.379 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time -1.379 arrival time 1.641 ------------------------------------------------------------------- slack 0.262 Slack (MET) : 0.262ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.348ns (logic 0.095ns (27.299%) route 0.253ns (72.701%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.511ns Source Clock Delay (SCD): 1.293ns Clock Pessimism Removal (CPR): 0.137ns Clock Net Delay (Source): 1.293ns (routing 0.240ns, distribution 1.053ns) Clock Net Delay (Destination): 1.511ns (routing 0.266ns, distribution 1.245ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.293 1.293 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X107Y524 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y524 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.342 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.077 1.419 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_6 SLICE_X107Y526 LUT2 (Prop_D6LUT_SLICEM_I1_O) 0.046 1.465 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/O net (fo=10, routed) 0.176 1.641 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X109Y526 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.511 1.511 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X109Y526 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C clock pessimism -0.137 1.374 SLICE_X109Y526 FDPE (Remov_AFF2_SLICEM_C_PRE) 0.005 1.379 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time -1.379 arrival time 1.641 ------------------------------------------------------------------- slack 0.262 Slack (MET) : 0.262ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.348ns (logic 0.095ns (27.299%) route 0.253ns (72.701%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.511ns Source Clock Delay (SCD): 1.293ns Clock Pessimism Removal (CPR): 0.137ns Clock Net Delay (Source): 1.293ns (routing 0.240ns, distribution 1.053ns) Clock Net Delay (Destination): 1.511ns (routing 0.266ns, distribution 1.245ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.293 1.293 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X107Y524 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y524 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.342 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.077 1.419 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_6 SLICE_X107Y526 LUT2 (Prop_D6LUT_SLICEM_I1_O) 0.046 1.465 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/O net (fo=10, routed) 0.176 1.641 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X109Y526 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.511 1.511 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X109Y526 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C clock pessimism -0.137 1.374 SLICE_X109Y526 FDPE (Remov_BFF2_SLICEM_C_PRE) 0.005 1.379 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time -1.379 arrival time 1.641 ------------------------------------------------------------------- slack 0.262 Slack (MET) : 0.262ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE (removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (DRPclk rise@0.000ns - DRPclk rise@0.000ns) Data Path Delay: 0.348ns (logic 0.095ns (27.299%) route 0.253ns (72.701%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.511ns Source Clock Delay (SCD): 1.293ns Clock Pessimism Removal (CPR): 0.137ns Clock Net Delay (Source): 1.293ns (routing 0.240ns, distribution 1.053ns) Clock Net Delay (Destination): 1.511ns (routing 0.266ns, distribution 1.245ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.293 1.293 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/aurora_init_clk SLR Crossing[0->1] SLICE_X107Y524 FDRE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y524 FDRE (Prop_FFF_SLICEM_C_Q) 0.049 1.342 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_all_out_reg/Q net (fo=2, routed) 0.077 1.419 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_6 SLICE_X107Y526 LUT2 (Prop_D6LUT_SLICEM_I1_O) 0.046 1.465 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17/O net (fo=10, routed) 0.176 1.641 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X109Y526 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock DRPclk rise edge) 0.000 0.000 r BUFGCE_X1Y109 BUFGCE 0.000 0.000 r i_DRPclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=4215, routed) 1.511 1.511 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/clk_in SLR Crossing[0->1] SLICE_X109Y526 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C clock pessimism -0.137 1.374 SLICE_X109Y526 FDPE (Remov_CFF2_SLICEM_C_PRE) 0.005 1.379 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time -1.379 arrival time 1.641 ------------------------------------------------------------------- slack 0.262 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: TTC_rxusrclk To Clock: TTC_rxusrclk Setup : 0 Failing Endpoints, Worst Slack 0.154ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.107ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.154ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[247]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.947ns (logic 0.140ns (4.751%) route 2.807ns (95.249%)) Logic Levels: 0 Clock Path Skew: 0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.691ns = ( 6.810 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.691ns (routing 1.487ns, distribution 2.204ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.807 6.816 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X134Y94 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[247]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.691 6.810 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X134Y94 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[247]/C clock pessimism 0.288 7.098 clock uncertainty -0.035 7.063 SLICE_X134Y94 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 6.970 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[247] ------------------------------------------------------------------- required time 6.970 arrival time -6.816 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.157ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[142]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.947ns (logic 0.140ns (4.751%) route 2.807ns (95.249%)) Logic Levels: 0 Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.694ns = ( 6.813 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.694ns (routing 1.487ns, distribution 2.207ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.807 6.816 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X132Y70 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[142]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.694 6.813 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X132Y70 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[142]/C clock pessimism 0.288 7.101 clock uncertainty -0.035 7.066 SLICE_X132Y70 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 6.973 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[142] ------------------------------------------------------------------- required time 6.973 arrival time -6.816 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.157ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[152]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.947ns (logic 0.140ns (4.751%) route 2.807ns (95.249%)) Logic Levels: 0 Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.694ns = ( 6.813 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.694ns (routing 1.487ns, distribution 2.207ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.807 6.816 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X132Y70 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[152]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.694 6.813 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X132Y70 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[152]/C clock pessimism 0.288 7.101 clock uncertainty -0.035 7.066 SLICE_X132Y70 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 6.973 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[152] ------------------------------------------------------------------- required time 6.973 arrival time -6.816 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.157ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[182]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.947ns (logic 0.140ns (4.751%) route 2.807ns (95.249%)) Logic Levels: 0 Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.694ns = ( 6.813 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.694ns (routing 1.487ns, distribution 2.207ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.807 6.816 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X132Y70 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[182]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.694 6.813 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X132Y70 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[182]/C clock pessimism 0.288 7.101 clock uncertainty -0.035 7.066 SLICE_X132Y70 FDCE (Recov_FFF_SLICEL_C_CLR) -0.093 6.973 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[182] ------------------------------------------------------------------- required time 6.973 arrival time -6.816 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.157ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[24]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.947ns (logic 0.140ns (4.751%) route 2.807ns (95.249%)) Logic Levels: 0 Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.694ns = ( 6.813 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.694ns (routing 1.487ns, distribution 2.207ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.807 6.816 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X132Y70 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[24]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.694 6.813 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X132Y70 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[24]/C clock pessimism 0.288 7.101 clock uncertainty -0.035 7.066 SLICE_X132Y70 FDCE (Recov_FFF2_SLICEL_C_CLR) -0.093 6.973 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[24] ------------------------------------------------------------------- required time 6.973 arrival time -6.816 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.157ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[53]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.947ns (logic 0.140ns (4.751%) route 2.807ns (95.249%)) Logic Levels: 0 Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.694ns = ( 6.813 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.694ns (routing 1.487ns, distribution 2.207ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.807 6.816 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X132Y70 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[53]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.694 6.813 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X132Y70 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[53]/C clock pessimism 0.288 7.101 clock uncertainty -0.035 7.066 SLICE_X132Y70 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 6.973 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[53] ------------------------------------------------------------------- required time 6.973 arrival time -6.816 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.157ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[72]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.947ns (logic 0.140ns (4.751%) route 2.807ns (95.249%)) Logic Levels: 0 Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.694ns = ( 6.813 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.694ns (routing 1.487ns, distribution 2.207ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.807 6.816 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X132Y70 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[72]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.694 6.813 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X132Y70 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[72]/C clock pessimism 0.288 7.101 clock uncertainty -0.035 7.066 SLICE_X132Y70 FDCE (Recov_GFF2_SLICEL_C_CLR) -0.093 6.973 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[72] ------------------------------------------------------------------- required time 6.973 arrival time -6.816 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.157ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[73]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.947ns (logic 0.140ns (4.751%) route 2.807ns (95.249%)) Logic Levels: 0 Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.694ns = ( 6.813 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.694ns (routing 1.487ns, distribution 2.207ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.807 6.816 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X132Y70 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[73]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.694 6.813 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X132Y70 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[73]/C clock pessimism 0.288 7.101 clock uncertainty -0.035 7.066 SLICE_X132Y70 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 6.973 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[73] ------------------------------------------------------------------- required time 6.973 arrival time -6.816 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.157ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[74]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.947ns (logic 0.140ns (4.751%) route 2.807ns (95.249%)) Logic Levels: 0 Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.694ns = ( 6.813 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.694ns (routing 1.487ns, distribution 2.207ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.807 6.816 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X132Y70 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[74]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.694 6.813 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X132Y70 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[74]/C clock pessimism 0.288 7.101 clock uncertainty -0.035 7.066 SLICE_X132Y70 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 6.973 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[74] ------------------------------------------------------------------- required time 6.973 arrival time -6.816 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.160ns (required time - arrival time) Source: i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[203]/CLR (recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 3.119ns (TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 2.944ns (logic 0.140ns (4.755%) route 2.804ns (95.245%)) Logic Levels: 0 Clock Path Skew: 0.113ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.694ns = ( 6.813 - 3.119 ) Source Clock Delay (SCD): 3.869ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.869ns (routing 1.628ns, distribution 2.241ns) Clock Net Delay (Destination): 3.694ns (routing 1.487ns, distribution 2.207ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.869 3.869 i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out SLICE_X98Y99 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X98Y99 FDCE (Prop_AFF_SLICEL_C_Q) 0.140 4.009 r i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/Q net (fo=731, routed) 2.804 6.813 i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i SLICE_X131Y70 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[203]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 3.119 3.119 r BUFG_GT_X1Y4 BUFG_GT 0.000 3.119 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 3.694 6.813 i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out SLICE_X131Y70 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[203]/C clock pessimism 0.288 7.101 clock uncertainty -0.035 7.066 SLICE_X131Y70 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 6.973 i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[203] ------------------------------------------------------------------- required time 6.973 arrival time -6.813 ------------------------------------------------------------------- slack 0.160 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.107ns (arrival time - required time) Source: i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[1]/CLR (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.194ns (logic 0.049ns (25.258%) route 0.145ns (74.742%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.873ns Source Clock Delay (SCD): 1.622ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.622ns (routing 0.696ns, distribution 0.926ns) Clock Net Delay (Destination): 1.873ns (routing 0.779ns, distribution 1.094ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.622 1.622 i_tcds2_if/rx_uplinkRst_n_bit_sync_320/rxusrclk_out SLICE_X130Y58 FDRE r i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y58 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 1.671 r i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/Q net (fo=29, routed) 0.145 1.816 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/AR[0] SLICE_X131Y58 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.873 1.873 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/rxusrclk_out SLICE_X131Y58 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[1]/C clock pessimism -0.169 1.704 SLICE_X131Y58 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.709 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[1] ------------------------------------------------------------------- required time -1.709 arrival time 1.816 ------------------------------------------------------------------- slack 0.107 Slack (MET) : 0.110ns (arrival time - required time) Source: i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[0]/CLR (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.199ns (logic 0.049ns (24.623%) route 0.150ns (75.377%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.875ns Source Clock Delay (SCD): 1.622ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.622ns (routing 0.696ns, distribution 0.926ns) Clock Net Delay (Destination): 1.875ns (routing 0.779ns, distribution 1.096ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.622 1.622 i_tcds2_if/rx_uplinkRst_n_bit_sync_320/rxusrclk_out SLICE_X130Y58 FDRE r i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y58 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 1.671 r i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/Q net (fo=29, routed) 0.150 1.821 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/AR[0] SLICE_X131Y58 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.875 1.875 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/rxusrclk_out SLICE_X131Y58 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[0]/C clock pessimism -0.169 1.706 SLICE_X131Y58 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.711 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[0] ------------------------------------------------------------------- required time -1.711 arrival time 1.821 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.110ns (arrival time - required time) Source: i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[2]/CLR (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.199ns (logic 0.049ns (24.623%) route 0.150ns (75.377%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.875ns Source Clock Delay (SCD): 1.622ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.622ns (routing 0.696ns, distribution 0.926ns) Clock Net Delay (Destination): 1.875ns (routing 0.779ns, distribution 1.096ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.622 1.622 i_tcds2_if/rx_uplinkRst_n_bit_sync_320/rxusrclk_out SLICE_X130Y58 FDRE r i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y58 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 1.671 r i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/Q net (fo=29, routed) 0.150 1.821 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/AR[0] SLICE_X131Y58 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.875 1.875 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/rxusrclk_out SLICE_X131Y58 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[2]/C clock pessimism -0.169 1.706 SLICE_X131Y58 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.711 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[2] ------------------------------------------------------------------- required time -1.711 arrival time 1.821 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.110ns (arrival time - required time) Source: i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[3]/CLR (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.199ns (logic 0.049ns (24.623%) route 0.150ns (75.377%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.875ns Source Clock Delay (SCD): 1.622ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.622ns (routing 0.696ns, distribution 0.926ns) Clock Net Delay (Destination): 1.875ns (routing 0.779ns, distribution 1.096ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.622 1.622 i_tcds2_if/rx_uplinkRst_n_bit_sync_320/rxusrclk_out SLICE_X130Y58 FDRE r i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y58 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 1.671 r i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/Q net (fo=29, routed) 0.150 1.821 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/AR[0] SLICE_X131Y58 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.875 1.875 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/rxusrclk_out SLICE_X131Y58 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[3]/C clock pessimism -0.169 1.706 SLICE_X131Y58 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.711 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[3] ------------------------------------------------------------------- required time -1.711 arrival time 1.821 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.110ns (arrival time - required time) Source: i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[4]/CLR (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.199ns (logic 0.049ns (24.623%) route 0.150ns (75.377%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.875ns Source Clock Delay (SCD): 1.622ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.622ns (routing 0.696ns, distribution 0.926ns) Clock Net Delay (Destination): 1.875ns (routing 0.779ns, distribution 1.096ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.622 1.622 i_tcds2_if/rx_uplinkRst_n_bit_sync_320/rxusrclk_out SLICE_X130Y58 FDRE r i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y58 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 1.671 r i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/Q net (fo=29, routed) 0.150 1.821 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/AR[0] SLICE_X131Y58 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.875 1.875 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/rxusrclk_out SLICE_X131Y58 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[4]/C clock pessimism -0.169 1.706 SLICE_X131Y58 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.711 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[4] ------------------------------------------------------------------- required time -1.711 arrival time 1.821 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.110ns (arrival time - required time) Source: i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C (rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[5]/CLR (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.199ns (logic 0.049ns (24.623%) route 0.150ns (75.377%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.875ns Source Clock Delay (SCD): 1.622ns Clock Pessimism Removal (CPR): 0.169ns Clock Net Delay (Source): 1.622ns (routing 0.696ns, distribution 0.926ns) Clock Net Delay (Destination): 1.875ns (routing 0.779ns, distribution 1.096ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.622 1.622 i_tcds2_if/rx_uplinkRst_n_bit_sync_320/rxusrclk_out SLICE_X130Y58 FDRE r i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y58 FDRE (Prop_AFF2_SLICEL_C_Q) 0.049 1.671 r i_tcds2_if/rx_uplinkRst_n_bit_sync_320/i_in_out_reg/Q net (fo=29, routed) 0.150 1.821 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/AR[0] SLICE_X131Y58 FDCE f i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.875 1.875 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/rxusrclk_out SLICE_X131Y58 FDCE r i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[5]/C clock pessimism -0.169 1.706 SLICE_X131Y58 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.711 i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/bitSlipCounter_s_reg[5] ------------------------------------------------------------------- required time -1.711 arrival time 1.821 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.119ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg/PRE (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.271ns (logic 0.048ns (17.712%) route 0.223ns (82.288%)) Logic Levels: 0 Clock Path Skew: 0.147ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.862ns Source Clock Delay (SCD): 1.623ns Clock Pessimism Removal (CPR): 0.092ns Clock Net Delay (Source): 1.623ns (routing 0.696ns, distribution 0.927ns) Clock Net Delay (Destination): 1.862ns (routing 0.779ns, distribution 1.083ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.623 1.623 i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.671 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/Q net (fo=6, routed) 0.223 1.894 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n SLICE_X133Y62 FDPE f i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.862 1.862 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 SLICE_X133Y62 FDPE r i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg/C clock pessimism -0.092 1.770 SLICE_X133Y62 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.775 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg ------------------------------------------------------------------- required time -1.775 arrival time 1.894 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.122ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg/PRE (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.277ns (logic 0.048ns (17.329%) route 0.229ns (82.671%)) Logic Levels: 0 Clock Path Skew: 0.150ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.865ns Source Clock Delay (SCD): 1.623ns Clock Pessimism Removal (CPR): 0.092ns Clock Net Delay (Source): 1.623ns (routing 0.696ns, distribution 0.927ns) Clock Net Delay (Destination): 1.865ns (routing 0.779ns, distribution 1.086ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.623 1.623 i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.671 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/Q net (fo=6, routed) 0.229 1.900 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n SLICE_X133Y62 FDPE f i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.865 1.865 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 SLICE_X133Y62 FDPE r i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg/C clock pessimism -0.092 1.773 SLICE_X133Y62 FDPE (Remov_DFF2_SLICEL_C_PRE) 0.005 1.778 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg ------------------------------------------------------------------- required time -1.778 arrival time 1.900 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg/PRE (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.277ns (logic 0.048ns (17.329%) route 0.229ns (82.671%)) Logic Levels: 0 Clock Path Skew: 0.150ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.865ns Source Clock Delay (SCD): 1.623ns Clock Pessimism Removal (CPR): 0.092ns Clock Net Delay (Source): 1.623ns (routing 0.696ns, distribution 0.927ns) Clock Net Delay (Destination): 1.865ns (routing 0.779ns, distribution 1.086ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.623 1.623 i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.671 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/Q net (fo=6, routed) 0.229 1.900 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n SLICE_X133Y62 FDPE f i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.865 1.865 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 SLICE_X133Y62 FDPE r i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg/C clock pessimism -0.092 1.773 SLICE_X133Y62 FDPE (Remov_AFF2_SLICEL_C_PRE) 0.005 1.778 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg ------------------------------------------------------------------- required time -1.778 arrival time 1.900 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C (rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg/PRE (removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000ns) Data Path Delay: 0.277ns (logic 0.048ns (17.329%) route 0.229ns (82.671%)) Logic Levels: 0 Clock Path Skew: 0.150ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.865ns Source Clock Delay (SCD): 1.623ns Clock Pessimism Removal (CPR): 0.092ns Clock Net Delay (Source): 1.623ns (routing 0.696ns, distribution 0.927ns) Clock Net Delay (Destination): 1.865ns (routing 0.779ns, distribution 1.086ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.623 1.623 i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] SLICE_X135Y57 FDCE r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y57 FDCE (Prop_BFF2_SLICEL_C_Q) 0.048 1.671 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/Q net (fo=6, routed) 0.229 1.900 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n SLICE_X133Y62 FDPE f i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock TTC_rxusrclk rise edge) 0.000 0.000 r BUFG_GT_X1Y4 BUFG_GT 0.000 0.000 r i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y2 (CLOCK_ROOT) net (fo=1861, routed) 1.865 1.865 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 SLICE_X133Y62 FDPE r i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg/C clock pessimism -0.092 1.773 SLICE_X133Y62 FDPE (Remov_BFF2_SLICEL_C_PRE) 0.005 1.778 i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg ------------------------------------------------------------------- required time -1.778 arrival time 1.900 ------------------------------------------------------------------- slack 0.122 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: axi_c2c_phy_clk To Clock: axi_c2c_phy_clk Setup : 0 Failing Endpoints, Worst Slack 10.643ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 10.643ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C (rising edge-triggered cell FDPE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/calib_done_flop_reg/CLR (recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 1.883ns (logic 0.139ns (7.382%) route 1.744ns (92.618%)) Logic Levels: 0 Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.157ns = ( 14.957 - 12.800 ) Source Clock Delay (SCD): 2.503ns Clock Pessimism Removal (CPR): 0.201ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.028ns (routing 0.375ns, distribution 1.653ns) Clock Net Delay (Destination): 1.759ns (routing 0.339ns, distribution 1.420ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.028 2.503 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/axi_c2c_phy_clk SLICE_X112Y27 FDPE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y27 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.642 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/Q net (fo=144, routed) 1.744 4.386 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/AS[0] SLICE_X116Y44 FDCE f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/calib_done_flop_reg/CLR ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.759 14.957 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_c2c_phy_clk SLICE_X116Y44 FDCE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/calib_done_flop_reg/C clock pessimism 0.201 15.158 clock uncertainty -0.035 15.122 SLICE_X116Y44 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 15.029 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/calib_done_flop_reg ------------------------------------------------------------------- required time 15.029 arrival time -4.386 ------------------------------------------------------------------- slack 10.643 Slack (MET) : 10.643ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C (rising edge-triggered cell FDPE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/rx_phy_ready_reg/CLR (recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 1.883ns (logic 0.139ns (7.382%) route 1.744ns (92.618%)) Logic Levels: 0 Clock Path Skew: -0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.157ns = ( 14.957 - 12.800 ) Source Clock Delay (SCD): 2.503ns Clock Pessimism Removal (CPR): 0.201ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.028ns (routing 0.375ns, distribution 1.653ns) Clock Net Delay (Destination): 1.759ns (routing 0.339ns, distribution 1.420ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.028 2.503 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/axi_c2c_phy_clk SLICE_X112Y27 FDPE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y27 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.642 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/Q net (fo=144, routed) 1.744 4.386 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/AS[0] SLICE_X116Y44 FDCE f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/rx_phy_ready_reg/CLR ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.759 14.957 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_c2c_phy_clk SLICE_X116Y44 FDCE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/rx_phy_ready_reg/C clock pessimism 0.201 15.158 clock uncertainty -0.035 15.122 SLICE_X116Y44 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 15.029 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/rx_phy_ready_reg ------------------------------------------------------------------- required time 15.029 arrival time -4.386 ------------------------------------------------------------------- slack 10.643 Slack (MET) : 10.713ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C (rising edge-triggered cell FDPE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[0]/PRE (recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 1.814ns (logic 0.139ns (7.663%) route 1.675ns (92.337%)) Logic Levels: 0 Clock Path Skew: -0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.158ns = ( 14.958 - 12.800 ) Source Clock Delay (SCD): 2.503ns Clock Pessimism Removal (CPR): 0.201ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.028ns (routing 0.375ns, distribution 1.653ns) Clock Net Delay (Destination): 1.760ns (routing 0.339ns, distribution 1.421ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.028 2.503 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/axi_c2c_phy_clk SLICE_X112Y27 FDPE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y27 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.642 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/Q net (fo=144, routed) 1.675 4.317 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/AS[0] SLICE_X116Y43 FDPE f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[0]/PRE ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.760 14.958 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_c2c_phy_clk SLICE_X116Y43 FDPE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[0]/C clock pessimism 0.201 15.158 clock uncertainty -0.035 15.123 SLICE_X116Y43 FDPE (Recov_DFF2_SLICEL_C_PRE) -0.093 15.030 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[0] ------------------------------------------------------------------- required time 15.030 arrival time -4.317 ------------------------------------------------------------------- slack 10.713 Slack (MET) : 10.721ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C (rising edge-triggered cell FDPE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[1]/CLR (recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 1.804ns (logic 0.139ns (7.705%) route 1.665ns (92.295%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.156ns = ( 14.956 - 12.800 ) Source Clock Delay (SCD): 2.503ns Clock Pessimism Removal (CPR): 0.201ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.028ns (routing 0.375ns, distribution 1.653ns) Clock Net Delay (Destination): 1.758ns (routing 0.339ns, distribution 1.419ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.028 2.503 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/axi_c2c_phy_clk SLICE_X112Y27 FDPE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y27 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.642 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/Q net (fo=144, routed) 1.665 4.307 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/AS[0] SLICE_X116Y43 FDCE f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.758 14.956 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_c2c_phy_clk SLICE_X116Y43 FDCE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[1]/C clock pessimism 0.201 15.157 clock uncertainty -0.035 15.121 SLICE_X116Y43 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 15.028 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ctrl_reg[1] ------------------------------------------------------------------- required time 15.028 arrival time -4.307 ------------------------------------------------------------------- slack 10.721 Slack (MET) : 10.721ns (required time - arrival time) Source: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C (rising edge-triggered cell FDPE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ready_reg/CLR (recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 1.804ns (logic 0.139ns (7.705%) route 1.665ns (92.295%)) Logic Levels: 0 Clock Path Skew: -0.146ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.156ns = ( 14.956 - 12.800 ) Source Clock Delay (SCD): 2.503ns Clock Pessimism Removal (CPR): 0.201ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.028ns (routing 0.375ns, distribution 1.653ns) Clock Net Delay (Destination): 1.758ns (routing 0.339ns, distribution 1.419ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 2.028 2.503 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/axi_c2c_phy_clk SLICE_X112Y27 FDPE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y27 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.642 f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/aurora_phy.user_reset_sync_inst/sync_reset_out_reg/Q net (fo=144, routed) 1.665 4.307 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/AS[0] SLICE_X116Y43 FDCE f i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ready_reg/CLR ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.758 14.956 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/axi_c2c_phy_clk SLICE_X116Y43 FDCE r i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ready_reg/C clock pessimism 0.201 15.157 clock uncertainty -0.035 15.121 SLICE_X116Y43 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 15.028 i_axi_slave/i_axi_chip2chip/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/axi_chip2chip_phy_init_inst/tx_phy_ready_reg ------------------------------------------------------------------- required time 15.028 arrival time -4.307 ------------------------------------------------------------------- slack 10.721 Slack (MET) : 11.467ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[1]/CLR (recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.137ns (12.816%) route 0.932ns (87.184%)) Logic Levels: 0 Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.986ns = ( 14.786 - 12.800 ) Source Clock Delay (SCD): 2.316ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.841ns (routing 0.375ns, distribution 1.466ns) Clock Net Delay (Destination): 1.588ns (routing 0.339ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.841 2.316 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 2.453 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.932 3.385 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X132Y7 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.588 14.786 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X132Y7 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[1]/C clock pessimism 0.194 14.980 clock uncertainty -0.035 14.945 SLICE_X132Y7 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 14.852 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[1] ------------------------------------------------------------------- required time 14.852 arrival time -3.385 ------------------------------------------------------------------- slack 11.467 Slack (MET) : 11.467ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[2]/CLR (recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.137ns (12.816%) route 0.932ns (87.184%)) Logic Levels: 0 Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.986ns = ( 14.786 - 12.800 ) Source Clock Delay (SCD): 2.316ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.841ns (routing 0.375ns, distribution 1.466ns) Clock Net Delay (Destination): 1.588ns (routing 0.339ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.841 2.316 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 2.453 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.932 3.385 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X132Y7 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.588 14.786 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X132Y7 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[2]/C clock pessimism 0.194 14.980 clock uncertainty -0.035 14.945 SLICE_X132Y7 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 14.852 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[2] ------------------------------------------------------------------- required time 14.852 arrival time -3.385 ------------------------------------------------------------------- slack 11.467 Slack (MET) : 11.467ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[3]/CLR (recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.137ns (12.816%) route 0.932ns (87.184%)) Logic Levels: 0 Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.986ns = ( 14.786 - 12.800 ) Source Clock Delay (SCD): 2.316ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.841ns (routing 0.375ns, distribution 1.466ns) Clock Net Delay (Destination): 1.588ns (routing 0.339ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.841 2.316 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 2.453 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.932 3.385 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X132Y7 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.588 14.786 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X132Y7 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[3]/C clock pessimism 0.194 14.980 clock uncertainty -0.035 14.945 SLICE_X132Y7 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 14.852 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[3] ------------------------------------------------------------------- required time 14.852 arrival time -3.385 ------------------------------------------------------------------- slack 11.467 Slack (MET) : 11.467ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[4]/CLR (recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 1.069ns (logic 0.137ns (12.816%) route 0.932ns (87.184%)) Logic Levels: 0 Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.986ns = ( 14.786 - 12.800 ) Source Clock Delay (SCD): 2.316ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.841ns (routing 0.375ns, distribution 1.466ns) Clock Net Delay (Destination): 1.588ns (routing 0.339ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.841 2.316 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 2.453 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.932 3.385 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X132Y7 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.588 14.786 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X132Y7 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[4]/C clock pessimism 0.194 14.980 clock uncertainty -0.035 14.945 SLICE_X132Y7 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 14.852 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[4] ------------------------------------------------------------------- required time 14.852 arrival time -3.385 ------------------------------------------------------------------- slack 11.467 Slack (MET) : 11.599ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[6]/CLR (recovery check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 12.800ns (axi_c2c_phy_clk rise@12.800ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.948ns (logic 0.137ns (14.451%) route 0.811ns (85.549%)) Logic Levels: 0 Clock Path Skew: -0.125ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.997ns = ( 14.797 - 12.800 ) Source Clock Delay (SCD): 2.316ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.841ns (routing 0.375ns, distribution 1.466ns) Clock Net Delay (Destination): 1.599ns (routing 0.339ns, distribution 1.260ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.841 2.316 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 2.453 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.811 3.264 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X133Y7 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 12.800 12.800 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 12.800 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.052 12.852 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 13.198 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 1.599 14.797 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X133Y7 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[6]/C clock pessimism 0.194 14.991 clock uncertainty -0.035 14.956 SLICE_X133Y7 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 14.863 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[6] ------------------------------------------------------------------- required time 14.863 arrival time -3.264 ------------------------------------------------------------------- slack 11.599 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.264ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[6]/CLR (removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.334ns (logic 0.049ns (14.671%) route 0.285ns (85.329%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.966ns Source Clock Delay (SCD): 0.779ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.661ns (routing 0.164ns, distribution 0.497ns) Clock Net Delay (Destination): 0.801ns (routing 0.192ns, distribution 0.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.661 0.779 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.828 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.285 1.113 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X134Y7 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.801 0.966 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X134Y7 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[6]/C clock pessimism -0.122 0.844 SLICE_X134Y7 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 0.849 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[6] ------------------------------------------------------------------- required time -0.849 arrival time 1.113 ------------------------------------------------------------------- slack 0.264 Slack (MET) : 0.264ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[7]/CLR (removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.334ns (logic 0.049ns (14.671%) route 0.285ns (85.329%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.966ns Source Clock Delay (SCD): 0.779ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.661ns (routing 0.164ns, distribution 0.497ns) Clock Net Delay (Destination): 0.801ns (routing 0.192ns, distribution 0.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.661 0.779 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.828 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.285 1.113 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X134Y7 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.801 0.966 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X134Y7 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[7]/C clock pessimism -0.122 0.844 SLICE_X134Y7 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 0.849 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[7] ------------------------------------------------------------------- required time -0.849 arrival time 1.113 ------------------------------------------------------------------- slack 0.264 Slack (MET) : 0.279ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[0]/CLR (removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.049ns (13.462%) route 0.315ns (86.538%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.981ns Source Clock Delay (SCD): 0.779ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.661ns (routing 0.164ns, distribution 0.497ns) Clock Net Delay (Destination): 0.816ns (routing 0.192ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.661 0.779 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.828 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.315 1.143 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X134Y8 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.816 0.981 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X134Y8 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[0]/C clock pessimism -0.122 0.859 SLICE_X134Y8 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 0.864 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[0] ------------------------------------------------------------------- required time -0.864 arrival time 1.143 ------------------------------------------------------------------- slack 0.279 Slack (MET) : 0.279ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[1]/CLR (removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.049ns (13.462%) route 0.315ns (86.538%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.981ns Source Clock Delay (SCD): 0.779ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.661ns (routing 0.164ns, distribution 0.497ns) Clock Net Delay (Destination): 0.816ns (routing 0.192ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.661 0.779 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.828 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.315 1.143 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X134Y8 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.816 0.981 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X134Y8 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[1]/C clock pessimism -0.122 0.859 SLICE_X134Y8 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 0.864 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[1] ------------------------------------------------------------------- required time -0.864 arrival time 1.143 ------------------------------------------------------------------- slack 0.279 Slack (MET) : 0.279ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[2]/CLR (removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.049ns (13.462%) route 0.315ns (86.538%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.981ns Source Clock Delay (SCD): 0.779ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.661ns (routing 0.164ns, distribution 0.497ns) Clock Net Delay (Destination): 0.816ns (routing 0.192ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.661 0.779 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.828 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.315 1.143 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X134Y8 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.816 0.981 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X134Y8 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[2]/C clock pessimism -0.122 0.859 SLICE_X134Y8 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 0.864 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[2] ------------------------------------------------------------------- required time -0.864 arrival time 1.143 ------------------------------------------------------------------- slack 0.279 Slack (MET) : 0.279ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[3]/CLR (removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.049ns (13.462%) route 0.315ns (86.538%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.981ns Source Clock Delay (SCD): 0.779ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.661ns (routing 0.164ns, distribution 0.497ns) Clock Net Delay (Destination): 0.816ns (routing 0.192ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.661 0.779 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.828 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.315 1.143 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X134Y8 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.816 0.981 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X134Y8 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[3]/C clock pessimism -0.122 0.859 SLICE_X134Y8 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 0.864 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[3] ------------------------------------------------------------------- required time -0.864 arrival time 1.143 ------------------------------------------------------------------- slack 0.279 Slack (MET) : 0.279ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[4]/CLR (removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.049ns (13.462%) route 0.315ns (86.538%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.981ns Source Clock Delay (SCD): 0.779ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.661ns (routing 0.164ns, distribution 0.497ns) Clock Net Delay (Destination): 0.816ns (routing 0.192ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.661 0.779 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.828 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.315 1.143 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X134Y8 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.816 0.981 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X134Y8 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[4]/C clock pessimism -0.122 0.859 SLICE_X134Y8 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 0.864 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[4] ------------------------------------------------------------------- required time -0.864 arrival time 1.143 ------------------------------------------------------------------- slack 0.279 Slack (MET) : 0.279ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[5]/CLR (removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.049ns (13.462%) route 0.315ns (86.538%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.981ns Source Clock Delay (SCD): 0.779ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.661ns (routing 0.164ns, distribution 0.497ns) Clock Net Delay (Destination): 0.816ns (routing 0.192ns, distribution 0.624ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.661 0.779 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.828 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.315 1.143 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X134Y8 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.816 0.981 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X134Y8 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[5]/C clock pessimism -0.122 0.859 SLICE_X134Y8 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 0.864 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_tx_active_in_extend_cntr_reg[5] ------------------------------------------------------------------- required time -0.864 arrival time 1.143 ------------------------------------------------------------------- slack 0.279 Slack (MET) : 0.298ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[0]/CLR (removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.376ns (logic 0.049ns (13.032%) route 0.327ns (86.968%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.974ns Source Clock Delay (SCD): 0.779ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.661ns (routing 0.164ns, distribution 0.497ns) Clock Net Delay (Destination): 0.809ns (routing 0.192ns, distribution 0.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.661 0.779 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.828 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.327 1.155 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X133Y7 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.809 0.974 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X133Y7 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[0]/C clock pessimism -0.122 0.852 SLICE_X133Y7 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 0.857 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[0] ------------------------------------------------------------------- required time -0.857 arrival time 1.155 ------------------------------------------------------------------- slack 0.298 Slack (MET) : 0.298ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C (rising edge-triggered cell FDCE clocked by axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[5]/CLR (removal check against rising-edge clock axi_c2c_phy_clk {rise@0.000ns fall@6.400ns period=12.800ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axi_c2c_phy_clk rise@0.000ns - axi_c2c_phy_clk rise@0.000ns) Data Path Delay: 0.376ns (logic 0.049ns (13.032%) route 0.327ns (86.968%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.974ns Source Clock Delay (SCD): 0.779ns Clock Pessimism Removal (CPR): 0.122ns Clock Net Delay (Source): 0.661ns (routing 0.164ns, distribution 0.497ns) Clock Net Delay (Destination): 0.809ns (routing 0.192ns, distribution 0.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.661 0.779 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/init_clk SLICE_X141Y2 FDCE r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y2 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.828 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg/Q net (fo=19, routed) 0.327 1.155 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/mmcm_not_locked_out2 SLICE_X133Y7 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock axi_c2c_phy_clk rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK net (fo=3, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/tx_out_clk BUFG_GT_X1Y16 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst/O X5Y0 (CLOCK_ROOT) net (fo=1684, routed) 0.809 0.974 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/rst_in_out_reg_1 SLICE_X133Y7 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[5]/C clock pessimism -0.122 0.852 SLICE_X133Y7 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 0.857 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/fabric_pcs_rst_extend_cntr_reg[5] ------------------------------------------------------------------- required time -0.857 arrival time 1.155 ------------------------------------------------------------------- slack 0.298 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk125 To Clock: clk125 Setup : 0 Failing Endpoints, Worst Slack 2.056ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.230ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.056ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.903ns (logic 0.399ns (8.138%) route 4.504ns (91.862%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.895ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.810ns = ( 10.810 - 8.000 ) Source Clock Delay (SCD): 3.776ns Clock Pessimism Removal (CPR): 0.071ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.776ns (routing 0.705ns, distribution 3.071ns) Clock Net Delay (Destination): 2.810ns (routing 0.650ns, distribution 2.160ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.776 3.776 i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN SLICE_X130Y65 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y65 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.915 f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Q net (fo=2, routed) 3.824 7.739 ctrl_regs_inst/reset_all_out SLICE_X91Y208 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.260 7.999 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.680 8.679 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X90Y210 FDPE f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 2.810 10.810 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X90Y210 FDPE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C clock pessimism 0.071 10.881 clock uncertainty -0.053 10.828 SLICE_X90Y210 FDPE (Recov_DFF2_SLICEM_C_PRE) -0.093 10.735 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg ------------------------------------------------------------------- required time 10.735 arrival time -8.679 ------------------------------------------------------------------- slack 2.056 Slack (MET) : 2.056ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.903ns (logic 0.399ns (8.138%) route 4.504ns (91.862%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.895ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.810ns = ( 10.810 - 8.000 ) Source Clock Delay (SCD): 3.776ns Clock Pessimism Removal (CPR): 0.071ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.776ns (routing 0.705ns, distribution 3.071ns) Clock Net Delay (Destination): 2.810ns (routing 0.650ns, distribution 2.160ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.776 3.776 i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN SLICE_X130Y65 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y65 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.915 f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Q net (fo=2, routed) 3.824 7.739 ctrl_regs_inst/reset_all_out SLICE_X91Y208 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.260 7.999 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.680 8.679 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X90Y210 FDPE f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 2.810 10.810 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X90Y210 FDPE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C clock pessimism 0.071 10.881 clock uncertainty -0.053 10.828 SLICE_X90Y210 FDPE (Recov_AFF2_SLICEM_C_PRE) -0.093 10.735 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time 10.735 arrival time -8.679 ------------------------------------------------------------------- slack 2.056 Slack (MET) : 2.056ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.903ns (logic 0.399ns (8.138%) route 4.504ns (91.862%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.895ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.810ns = ( 10.810 - 8.000 ) Source Clock Delay (SCD): 3.776ns Clock Pessimism Removal (CPR): 0.071ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.776ns (routing 0.705ns, distribution 3.071ns) Clock Net Delay (Destination): 2.810ns (routing 0.650ns, distribution 2.160ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.776 3.776 i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN SLICE_X130Y65 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y65 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.915 f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Q net (fo=2, routed) 3.824 7.739 ctrl_regs_inst/reset_all_out SLICE_X91Y208 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.260 7.999 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.680 8.679 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X90Y210 FDPE f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 2.810 10.810 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X90Y210 FDPE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C clock pessimism 0.071 10.881 clock uncertainty -0.053 10.828 SLICE_X90Y210 FDPE (Recov_BFF2_SLICEM_C_PRE) -0.093 10.735 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time 10.735 arrival time -8.679 ------------------------------------------------------------------- slack 2.056 Slack (MET) : 2.056ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.903ns (logic 0.399ns (8.138%) route 4.504ns (91.862%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.895ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.810ns = ( 10.810 - 8.000 ) Source Clock Delay (SCD): 3.776ns Clock Pessimism Removal (CPR): 0.071ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.776ns (routing 0.705ns, distribution 3.071ns) Clock Net Delay (Destination): 2.810ns (routing 0.650ns, distribution 2.160ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.776 3.776 i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN SLICE_X130Y65 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y65 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.915 f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Q net (fo=2, routed) 3.824 7.739 ctrl_regs_inst/reset_all_out SLICE_X91Y208 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.260 7.999 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.680 8.679 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X90Y210 FDPE f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 2.810 10.810 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X90Y210 FDPE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C clock pessimism 0.071 10.881 clock uncertainty -0.053 10.828 SLICE_X90Y210 FDPE (Recov_CFF2_SLICEM_C_PRE) -0.093 10.735 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time 10.735 arrival time -8.679 ------------------------------------------------------------------- slack 2.056 Slack (MET) : 2.061ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.896ns (logic 0.399ns (8.150%) route 4.497ns (91.850%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.897ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.808ns = ( 10.808 - 8.000 ) Source Clock Delay (SCD): 3.776ns Clock Pessimism Removal (CPR): 0.071ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.776ns (routing 0.705ns, distribution 3.071ns) Clock Net Delay (Destination): 2.808ns (routing 0.650ns, distribution 2.158ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.776 3.776 i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN SLICE_X130Y65 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y65 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.915 f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Q net (fo=2, routed) 3.824 7.739 ctrl_regs_inst/reset_all_out SLICE_X91Y208 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.260 7.999 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.673 8.672 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in SLICE_X90Y210 FDPE f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 2.808 10.808 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in SLICE_X90Y210 FDPE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C clock pessimism 0.071 10.879 clock uncertainty -0.053 10.826 SLICE_X90Y210 FDPE (Recov_EFF_SLICEM_C_PRE) -0.093 10.733 i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time 10.733 arrival time -8.672 ------------------------------------------------------------------- slack 2.061 Slack (MET) : 2.177ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.783ns (logic 0.399ns (8.342%) route 4.384ns (91.658%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.894ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.811ns = ( 10.811 - 8.000 ) Source Clock Delay (SCD): 3.776ns Clock Pessimism Removal (CPR): 0.071ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.776ns (routing 0.705ns, distribution 3.071ns) Clock Net Delay (Destination): 2.811ns (routing 0.650ns, distribution 2.161ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.776 3.776 i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN SLICE_X130Y65 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y65 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.915 f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Q net (fo=2, routed) 3.824 7.739 ctrl_regs_inst/reset_all_out SLICE_X91Y208 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.260 7.999 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.560 8.559 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in SLICE_X90Y209 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 2.811 10.811 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in SLICE_X90Y209 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/C clock pessimism 0.071 10.882 clock uncertainty -0.053 10.829 SLICE_X90Y209 FDPE (Recov_DFF2_SLICEM_C_PRE) -0.093 10.736 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg ------------------------------------------------------------------- required time 10.736 arrival time -8.559 ------------------------------------------------------------------- slack 2.177 Slack (MET) : 2.177ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.783ns (logic 0.399ns (8.342%) route 4.384ns (91.658%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.894ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.811ns = ( 10.811 - 8.000 ) Source Clock Delay (SCD): 3.776ns Clock Pessimism Removal (CPR): 0.071ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.776ns (routing 0.705ns, distribution 3.071ns) Clock Net Delay (Destination): 2.811ns (routing 0.650ns, distribution 2.161ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.776 3.776 i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN SLICE_X130Y65 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y65 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.915 f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Q net (fo=2, routed) 3.824 7.739 ctrl_regs_inst/reset_all_out SLICE_X91Y208 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.260 7.999 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.560 8.559 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in SLICE_X90Y209 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 2.811 10.811 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in SLICE_X90Y209 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/C clock pessimism 0.071 10.882 clock uncertainty -0.053 10.829 SLICE_X90Y209 FDPE (Recov_AFF2_SLICEM_C_PRE) -0.093 10.736 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time 10.736 arrival time -8.559 ------------------------------------------------------------------- slack 2.177 Slack (MET) : 2.177ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.783ns (logic 0.399ns (8.342%) route 4.384ns (91.658%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.894ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.811ns = ( 10.811 - 8.000 ) Source Clock Delay (SCD): 3.776ns Clock Pessimism Removal (CPR): 0.071ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.776ns (routing 0.705ns, distribution 3.071ns) Clock Net Delay (Destination): 2.811ns (routing 0.650ns, distribution 2.161ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.776 3.776 i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN SLICE_X130Y65 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y65 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.915 f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Q net (fo=2, routed) 3.824 7.739 ctrl_regs_inst/reset_all_out SLICE_X91Y208 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.260 7.999 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.560 8.559 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in SLICE_X90Y209 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 2.811 10.811 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in SLICE_X90Y209 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/C clock pessimism 0.071 10.882 clock uncertainty -0.053 10.829 SLICE_X90Y209 FDPE (Recov_BFF2_SLICEM_C_PRE) -0.093 10.736 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time 10.736 arrival time -8.559 ------------------------------------------------------------------- slack 2.177 Slack (MET) : 2.177ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.783ns (logic 0.399ns (8.342%) route 4.384ns (91.658%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.894ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.811ns = ( 10.811 - 8.000 ) Source Clock Delay (SCD): 3.776ns Clock Pessimism Removal (CPR): 0.071ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.776ns (routing 0.705ns, distribution 3.071ns) Clock Net Delay (Destination): 2.811ns (routing 0.650ns, distribution 2.161ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.776 3.776 i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN SLICE_X130Y65 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y65 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.915 f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Q net (fo=2, routed) 3.824 7.739 ctrl_regs_inst/reset_all_out SLICE_X91Y208 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.260 7.999 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.560 8.559 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in SLICE_X90Y209 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 2.811 10.811 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in SLICE_X90Y209 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/C clock pessimism 0.071 10.882 clock uncertainty -0.053 10.829 SLICE_X90Y209 FDPE (Recov_CFF2_SLICEM_C_PRE) -0.093 10.736 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time 10.736 arrival time -8.559 ------------------------------------------------------------------- slack 2.177 Slack (MET) : 2.182ns (required time - arrival time) Source: i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE (recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125 rise@8.000ns - clk125 rise@0.000ns) Data Path Delay: 4.776ns (logic 0.399ns (8.354%) route 4.377ns (91.646%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.896ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.809ns = ( 10.809 - 8.000 ) Source Clock Delay (SCD): 3.776ns Clock Pessimism Removal (CPR): 0.071ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.776ns (routing 0.705ns, distribution 3.071ns) Clock Net Delay (Destination): 2.809ns (routing 0.650ns, distribution 2.159ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 3.776 3.776 i_tcds2_if/i_mgt_wrapper/i_mgt_init/CLKFBIN SLICE_X130Y65 FDRE r i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X130Y65 FDRE (Prop_DFF_SLICEL_C_Q) 0.139 3.915 f i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_all_out_reg/Q net (fo=2, routed) 3.824 7.739 ctrl_regs_inst/reset_all_out SLICE_X91Y208 LUT3 (Prop_D5LUT_SLICEL_I2_O) 0.260 7.999 f ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/O net (fo=10, routed) 0.553 8.552 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in SLICE_X90Y209 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 8.000 8.000 r BUFGCE_X1Y111 BUFGCE 0.000 8.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 2.809 10.809 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in SLICE_X90Y209 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/C clock pessimism 0.071 10.880 clock uncertainty -0.053 10.827 SLICE_X90Y209 FDPE (Recov_EFF_SLICEM_C_PRE) -0.093 10.734 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg ------------------------------------------------------------------- required time 10.734 arrival time -8.552 ------------------------------------------------------------------- slack 2.182 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.230ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.049ns (17.949%) route 0.224ns (82.051%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.593ns Source Clock Delay (SCD): 1.375ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 1.375ns (routing 0.241ns, distribution 1.134ns) Clock Net Delay (Destination): 1.593ns (routing 0.268ns, distribution 1.325ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.375 1.375 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X135Y62 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y62 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.424 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.224 1.648 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in SLICE_X135Y60 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.593 1.593 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in SLICE_X135Y60 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/C clock pessimism -0.180 1.413 SLICE_X135Y60 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.418 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg ------------------------------------------------------------------- required time -1.418 arrival time 1.648 ------------------------------------------------------------------- slack 0.230 Slack (MET) : 0.233ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.279ns (logic 0.049ns (17.563%) route 0.230ns (82.437%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.596ns Source Clock Delay (SCD): 1.375ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 1.375ns (routing 0.241ns, distribution 1.134ns) Clock Net Delay (Destination): 1.596ns (routing 0.268ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.375 1.375 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X135Y62 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y62 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.424 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.230 1.654 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in SLICE_X135Y60 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.596 1.596 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in SLICE_X135Y60 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/C clock pessimism -0.180 1.416 SLICE_X135Y60 FDPE (Remov_DFF2_SLICEL_C_PRE) 0.005 1.421 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg ------------------------------------------------------------------- required time -1.421 arrival time 1.654 ------------------------------------------------------------------- slack 0.233 Slack (MET) : 0.233ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.279ns (logic 0.049ns (17.563%) route 0.230ns (82.437%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.596ns Source Clock Delay (SCD): 1.375ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 1.375ns (routing 0.241ns, distribution 1.134ns) Clock Net Delay (Destination): 1.596ns (routing 0.268ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.375 1.375 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X135Y62 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y62 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.424 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.230 1.654 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in SLICE_X135Y60 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.596 1.596 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in SLICE_X135Y60 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/C clock pessimism -0.180 1.416 SLICE_X135Y60 FDPE (Remov_AFF2_SLICEL_C_PRE) 0.005 1.421 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time -1.421 arrival time 1.654 ------------------------------------------------------------------- slack 0.233 Slack (MET) : 0.233ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.279ns (logic 0.049ns (17.563%) route 0.230ns (82.437%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.596ns Source Clock Delay (SCD): 1.375ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 1.375ns (routing 0.241ns, distribution 1.134ns) Clock Net Delay (Destination): 1.596ns (routing 0.268ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.375 1.375 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X135Y62 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y62 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.424 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.230 1.654 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in SLICE_X135Y60 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.596 1.596 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in SLICE_X135Y60 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/C clock pessimism -0.180 1.416 SLICE_X135Y60 FDPE (Remov_BFF2_SLICEL_C_PRE) 0.005 1.421 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time -1.421 arrival time 1.654 ------------------------------------------------------------------- slack 0.233 Slack (MET) : 0.233ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.279ns (logic 0.049ns (17.563%) route 0.230ns (82.437%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.596ns Source Clock Delay (SCD): 1.375ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 1.375ns (routing 0.241ns, distribution 1.134ns) Clock Net Delay (Destination): 1.596ns (routing 0.268ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.375 1.375 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X135Y62 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y62 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.424 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.230 1.654 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in SLICE_X135Y60 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.596 1.596 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in SLICE_X135Y60 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/C clock pessimism -0.180 1.416 SLICE_X135Y60 FDPE (Remov_CFF2_SLICEL_C_PRE) 0.005 1.421 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time -1.421 arrival time 1.654 ------------------------------------------------------------------- slack 0.233 Slack (MET) : 0.281ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.364ns (logic 0.079ns (21.703%) route 0.285ns (78.297%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.602ns Source Clock Delay (SCD): 1.375ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 1.375ns (routing 0.241ns, distribution 1.134ns) Clock Net Delay (Destination): 1.602ns (routing 0.268ns, distribution 1.334ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.375 1.375 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X135Y62 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y62 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.424 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.078 1.502 i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg_n_0 SLICE_X133Y62 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.030 1.532 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/O net (fo=5, routed) 0.207 1.739 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in SLICE_X137Y61 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.602 1.602 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in SLICE_X137Y61 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/C clock pessimism -0.149 1.453 SLICE_X137Y61 FDPE (Remov_HFF2_SLICEL_C_PRE) 0.005 1.458 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg ------------------------------------------------------------------- required time -1.458 arrival time 1.739 ------------------------------------------------------------------- slack 0.281 Slack (MET) : 0.281ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.364ns (logic 0.079ns (21.703%) route 0.285ns (78.297%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.602ns Source Clock Delay (SCD): 1.375ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 1.375ns (routing 0.241ns, distribution 1.134ns) Clock Net Delay (Destination): 1.602ns (routing 0.268ns, distribution 1.334ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.375 1.375 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X135Y62 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y62 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.424 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.078 1.502 i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg_n_0 SLICE_X133Y62 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.030 1.532 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/O net (fo=5, routed) 0.207 1.739 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in SLICE_X137Y61 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.602 1.602 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in SLICE_X137Y61 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/C clock pessimism -0.149 1.453 SLICE_X137Y61 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.458 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg ------------------------------------------------------------------- required time -1.458 arrival time 1.739 ------------------------------------------------------------------- slack 0.281 Slack (MET) : 0.281ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.364ns (logic 0.079ns (21.703%) route 0.285ns (78.297%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.602ns Source Clock Delay (SCD): 1.375ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 1.375ns (routing 0.241ns, distribution 1.134ns) Clock Net Delay (Destination): 1.602ns (routing 0.268ns, distribution 1.334ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.375 1.375 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X135Y62 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y62 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.424 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.078 1.502 i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg_n_0 SLICE_X133Y62 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.030 1.532 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/O net (fo=5, routed) 0.207 1.739 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in SLICE_X137Y61 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.602 1.602 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in SLICE_X137Y61 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/C clock pessimism -0.149 1.453 SLICE_X137Y61 FDPE (Remov_EFF2_SLICEL_C_PRE) 0.005 1.458 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg ------------------------------------------------------------------- required time -1.458 arrival time 1.739 ------------------------------------------------------------------- slack 0.281 Slack (MET) : 0.281ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.364ns (logic 0.079ns (21.703%) route 0.285ns (78.297%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.602ns Source Clock Delay (SCD): 1.375ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 1.375ns (routing 0.241ns, distribution 1.134ns) Clock Net Delay (Destination): 1.602ns (routing 0.268ns, distribution 1.334ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.375 1.375 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X135Y62 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y62 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.424 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.078 1.502 i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg_n_0 SLICE_X133Y62 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.030 1.532 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/O net (fo=5, routed) 0.207 1.739 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in SLICE_X137Y61 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.602 1.602 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in SLICE_X137Y61 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/C clock pessimism -0.149 1.453 SLICE_X137Y61 FDPE (Remov_FFF2_SLICEL_C_PRE) 0.005 1.458 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg ------------------------------------------------------------------- required time -1.458 arrival time 1.739 ------------------------------------------------------------------- slack 0.281 Slack (MET) : 0.281ns (arrival time - required time) Source: i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C (rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE (removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125 rise@0.000ns - clk125 rise@0.000ns) Data Path Delay: 0.364ns (logic 0.079ns (21.703%) route 0.285ns (78.297%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.602ns Source Clock Delay (SCD): 1.375ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 1.375ns (routing 0.241ns, distribution 1.134ns) Clock Net Delay (Destination): 1.602ns (routing 0.268ns, distribution 1.334ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.375 1.375 i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN SLICE_X135Y62 FDRE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y62 FDRE (Prop_DFF2_SLICEL_C_Q) 0.049 1.424 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Q net (fo=7, routed) 0.078 1.502 i_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg_n_0 SLICE_X133Y62 LUT4 (Prop_D6LUT_SLICEL_I0_O) 0.030 1.532 f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/O net (fo=5, routed) 0.207 1.739 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in SLICE_X137Y61 FDPE f i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125 rise edge) 0.000 0.000 r BUFGCE_X1Y111 BUFGCE 0.000 0.000 r i_clk125_bufg/O X2Y4 (CLOCK_ROOT) net (fo=930, routed) 1.602 1.602 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in SLICE_X137Y61 FDPE r i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/C clock pessimism -0.149 1.453 SLICE_X137Y61 FDPE (Remov_GFF2_SLICEL_C_PRE) 0.005 1.458 i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg ------------------------------------------------------------------- required time -1.458 arrival time 1.739 ------------------------------------------------------------------- slack 0.281 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: fabric_clk To Clock: fabric_clk Setup : 0 Failing Endpoints, Worst Slack 8.583ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.081ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 8.583ns (required time - arrival time) Source: SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 15.206ns (logic 0.139ns (0.914%) route 15.067ns (99.086%)) Logic Levels: 0 Clock Path Skew: -0.611ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.138ns = ( 28.090 - 24.952 ) Source Clock Delay (SCD): 3.825ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.331ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.138ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.825ns (routing 1.005ns, distribution 2.820ns) Clock Net Delay (Destination): 3.138ns (routing 0.929ns, distribution 2.209ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.825 3.825 SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X14Y67 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y67 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.964 f SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 15.067 19.031 SFP_GEN[2].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X78Y352 FDCE f SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.138 28.090 SFP_GEN[2].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X78Y352 FDCE r SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]/C clock pessimism 0.076 28.166 inter-SLR compensation -0.331 27.835 clock uncertainty -0.128 27.707 SLICE_X78Y352 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 27.614 SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7] ------------------------------------------------------------------- required time 27.614 arrival time -19.031 ------------------------------------------------------------------- slack 8.583 Slack (MET) : 8.583ns (required time - arrival time) Source: SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 15.206ns (logic 0.139ns (0.914%) route 15.067ns (99.086%)) Logic Levels: 0 Clock Path Skew: -0.611ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.138ns = ( 28.090 - 24.952 ) Source Clock Delay (SCD): 3.825ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.331ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.138ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.825ns (routing 1.005ns, distribution 2.820ns) Clock Net Delay (Destination): 3.138ns (routing 0.929ns, distribution 2.209ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.825 3.825 SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X14Y67 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y67 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.964 f SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 15.067 19.031 SFP_GEN[2].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X78Y352 FDCE f SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.138 28.090 SFP_GEN[2].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X78Y352 FDCE r SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]/C clock pessimism 0.076 28.166 inter-SLR compensation -0.331 27.835 clock uncertainty -0.128 27.707 SLICE_X78Y352 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 27.614 SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8] ------------------------------------------------------------------- required time 27.614 arrival time -19.031 ------------------------------------------------------------------- slack 8.583 Slack (MET) : 8.747ns (required time - arrival time) Source: SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/PRE (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 15.070ns (logic 0.139ns (0.922%) route 14.931ns (99.078%)) Logic Levels: 0 Clock Path Skew: -0.578ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.171ns = ( 28.123 - 24.952 ) Source Clock Delay (SCD): 3.825ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.336ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.171ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.825ns (routing 1.005ns, distribution 2.820ns) Clock Net Delay (Destination): 3.171ns (routing 0.929ns, distribution 2.242ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.825 3.825 SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X14Y67 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y67 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.964 f SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.931 18.895 SFP_GEN[2].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X90Y364 FDPE f SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.171 28.123 SFP_GEN[2].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X90Y364 FDPE r SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/C clock pessimism 0.076 28.199 inter-SLR compensation -0.336 27.863 clock uncertainty -0.128 27.735 SLICE_X90Y364 FDPE (Recov_AFF_SLICEM_C_PRE) -0.093 27.642 SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17] ------------------------------------------------------------------- required time 27.642 arrival time -18.895 ------------------------------------------------------------------- slack 8.747 Slack (MET) : 8.872ns (required time - arrival time) Source: SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][11]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 14.916ns (logic 0.139ns (0.932%) route 14.777ns (99.068%)) Logic Levels: 0 Clock Path Skew: -0.612ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.137ns = ( 28.089 - 24.952 ) Source Clock Delay (SCD): 3.825ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.331ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.137ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.825ns (routing 1.005ns, distribution 2.820ns) Clock Net Delay (Destination): 3.137ns (routing 0.929ns, distribution 2.208ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.825 3.825 SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X14Y67 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y67 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.964 f SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.777 18.741 SFP_GEN[2].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X78Y358 FDCE f SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][11]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.137 28.089 SFP_GEN[2].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X78Y358 FDCE r SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][11]/C clock pessimism 0.076 28.165 inter-SLR compensation -0.331 27.834 clock uncertainty -0.128 27.706 SLICE_X78Y358 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 27.613 SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][11] ------------------------------------------------------------------- required time 27.613 arrival time -18.741 ------------------------------------------------------------------- slack 8.872 Slack (MET) : 8.872ns (required time - arrival time) Source: SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][12]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 14.916ns (logic 0.139ns (0.932%) route 14.777ns (99.068%)) Logic Levels: 0 Clock Path Skew: -0.612ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.137ns = ( 28.089 - 24.952 ) Source Clock Delay (SCD): 3.825ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.331ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.137ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.825ns (routing 1.005ns, distribution 2.820ns) Clock Net Delay (Destination): 3.137ns (routing 0.929ns, distribution 2.208ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.825 3.825 SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X14Y67 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y67 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.964 f SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.777 18.741 SFP_GEN[2].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X78Y358 FDCE f SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][12]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.137 28.089 SFP_GEN[2].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X78Y358 FDCE r SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][12]/C clock pessimism 0.076 28.165 inter-SLR compensation -0.331 27.834 clock uncertainty -0.128 27.706 SLICE_X78Y358 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 27.613 SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][12] ------------------------------------------------------------------- required time 27.613 arrival time -18.741 ------------------------------------------------------------------- slack 8.872 Slack (MET) : 8.872ns (required time - arrival time) Source: SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][13]/PRE (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 14.916ns (logic 0.139ns (0.932%) route 14.777ns (99.068%)) Logic Levels: 0 Clock Path Skew: -0.612ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.137ns = ( 28.089 - 24.952 ) Source Clock Delay (SCD): 3.825ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.331ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.137ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.825ns (routing 1.005ns, distribution 2.820ns) Clock Net Delay (Destination): 3.137ns (routing 0.929ns, distribution 2.208ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.825 3.825 SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X14Y67 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y67 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.964 f SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.777 18.741 SFP_GEN[2].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X78Y358 FDPE f SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][13]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.137 28.089 SFP_GEN[2].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X78Y358 FDPE r SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][13]/C clock pessimism 0.076 28.165 inter-SLR compensation -0.331 27.834 clock uncertainty -0.128 27.706 SLICE_X78Y358 FDPE (Recov_FFF_SLICEL_C_PRE) -0.093 27.613 SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][13] ------------------------------------------------------------------- required time 27.613 arrival time -18.741 ------------------------------------------------------------------- slack 8.872 Slack (MET) : 8.872ns (required time - arrival time) Source: SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/PRE (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 14.916ns (logic 0.139ns (0.932%) route 14.777ns (99.068%)) Logic Levels: 0 Clock Path Skew: -0.612ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.137ns = ( 28.089 - 24.952 ) Source Clock Delay (SCD): 3.825ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.331ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.137ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.825ns (routing 1.005ns, distribution 2.820ns) Clock Net Delay (Destination): 3.137ns (routing 0.929ns, distribution 2.208ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.825 3.825 SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X14Y67 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y67 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.964 f SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.777 18.741 SFP_GEN[2].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X78Y358 FDPE f SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.137 28.089 SFP_GEN[2].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X78Y358 FDPE r SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/C clock pessimism 0.076 28.165 inter-SLR compensation -0.331 27.834 clock uncertainty -0.128 27.706 SLICE_X78Y358 FDPE (Recov_FFF2_SLICEL_C_PRE) -0.093 27.613 SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15] ------------------------------------------------------------------- required time 27.613 arrival time -18.741 ------------------------------------------------------------------- slack 8.872 Slack (MET) : 8.872ns (required time - arrival time) Source: SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 14.916ns (logic 0.139ns (0.932%) route 14.777ns (99.068%)) Logic Levels: 0 Clock Path Skew: -0.612ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.137ns = ( 28.089 - 24.952 ) Source Clock Delay (SCD): 3.825ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.331ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.137ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.825ns (routing 1.005ns, distribution 2.820ns) Clock Net Delay (Destination): 3.137ns (routing 0.929ns, distribution 2.208ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.825 3.825 SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X14Y67 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y67 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.964 f SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.777 18.741 SFP_GEN[2].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X78Y358 FDCE f SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.137 28.089 SFP_GEN[2].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X78Y358 FDCE r SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/C clock pessimism 0.076 28.165 inter-SLR compensation -0.331 27.834 clock uncertainty -0.128 27.706 SLICE_X78Y358 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 27.613 SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2] ------------------------------------------------------------------- required time 27.613 arrival time -18.741 ------------------------------------------------------------------- slack 8.872 Slack (MET) : 8.872ns (required time - arrival time) Source: SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 14.916ns (logic 0.139ns (0.932%) route 14.777ns (99.068%)) Logic Levels: 0 Clock Path Skew: -0.612ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.137ns = ( 28.089 - 24.952 ) Source Clock Delay (SCD): 3.825ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.331ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.137ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.825ns (routing 1.005ns, distribution 2.820ns) Clock Net Delay (Destination): 3.137ns (routing 0.929ns, distribution 2.208ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.825 3.825 SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X14Y67 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y67 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.964 f SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.777 18.741 SFP_GEN[2].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X78Y358 FDCE f SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.137 28.089 SFP_GEN[2].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X78Y358 FDCE r SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]/C clock pessimism 0.076 28.165 inter-SLR compensation -0.331 27.834 clock uncertainty -0.128 27.706 SLICE_X78Y358 FDCE (Recov_GFF2_SLICEL_C_CLR) -0.093 27.613 SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3] ------------------------------------------------------------------- required time 27.613 arrival time -18.741 ------------------------------------------------------------------- slack 8.872 Slack (MET) : 8.872ns (required time - arrival time) Source: SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][5]/CLR (recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.952ns (fabric_clk rise@24.952ns - fabric_clk rise@0.000ns) Data Path Delay: 14.916ns (logic 0.139ns (0.932%) route 14.777ns (99.068%)) Logic Levels: 0 Clock Path Skew: -0.612ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.137ns = ( 28.089 - 24.952 ) Source Clock Delay (SCD): 3.825ns Clock Pessimism Removal (CPR): 0.076ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.331ns ((DCD - CCD) * PF) Destination Clock Delay (DCD): 3.137ns Common Clock Delay (CCD): 0.929ns Prorating Factor (PF): 0.150 Clock Net Delay (Source): 3.825ns (routing 1.005ns, distribution 2.820ns) Clock Net Delay (Destination): 3.137ns (routing 0.929ns, distribution 2.208ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.825 3.825 SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X14Y67 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y67 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.964 f SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 14.777 18.741 SFP_GEN[2].ngCCM_gbt/out[0] SLR Crossing[0->1] SLICE_X78Y358 FDCE f SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][5]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 24.952 24.952 r BUFGCE_X2Y110 BUFGCE 0.000 24.952 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 3.137 28.089 SFP_GEN[2].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X78Y358 FDCE r SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][5]/C clock pessimism 0.076 28.165 inter-SLR compensation -0.331 27.834 clock uncertainty -0.128 27.706 SLICE_X78Y358 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 27.613 SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][5] ------------------------------------------------------------------- required time 27.613 arrival time -18.741 ------------------------------------------------------------------- slack 8.872 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.081ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_wr_reg/CLR (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.273ns (logic 0.048ns (17.582%) route 0.225ns (82.418%)) Logic Levels: 0 Clock Path Skew: 0.187ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.676ns Source Clock Delay (SCD): 1.428ns Clock Pessimism Removal (CPR): 0.061ns Clock Net Delay (Source): 1.428ns (routing 0.393ns, distribution 1.035ns) Clock Net Delay (Destination): 1.676ns (routing 0.434ns, distribution 1.242ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.428 1.428 SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLR Crossing[0->1] SLICE_X28Y478 FDPE r SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y478 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.476 f SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.225 1.701 SFP_GEN[39].ngCCM_gbt/out[0] SLICE_X26Y480 FDCE f SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_wr_reg/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.676 1.676 SFP_GEN[39].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X26Y480 FDCE r SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_wr_reg/C clock pessimism -0.061 1.615 SLICE_X26Y480 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.620 SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_wr_reg ------------------------------------------------------------------- required time -1.620 arrival time 1.701 ------------------------------------------------------------------- slack 0.081 Slack (MET) : 0.153ns (arrival time - required time) Source: SFP_GEN[16].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[16].ngCCM_gbt/ngccmPinsOutReg_reg[peltier][2]/CLR (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.063ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.748ns Source Clock Delay (SCD): 1.489ns Clock Pessimism Removal (CPR): 0.196ns Clock Net Delay (Source): 1.489ns (routing 0.393ns, distribution 1.096ns) Clock Net Delay (Destination): 1.748ns (routing 0.434ns, distribution 1.314ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.489 1.489 SFP_GEN[16].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLR Crossing[0->1] SLICE_X124Y444 FDPE r SFP_GEN[16].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X124Y444 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.537 f SFP_GEN[16].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.173 1.710 SFP_GEN[16].ngCCM_gbt/out[0] SLICE_X124Y442 FDCE f SFP_GEN[16].ngCCM_gbt/ngccmPinsOutReg_reg[peltier][2]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.748 1.748 SFP_GEN[16].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X124Y442 FDCE r SFP_GEN[16].ngCCM_gbt/ngccmPinsOutReg_reg[peltier][2]/C clock pessimism -0.196 1.552 SLICE_X124Y442 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.557 SFP_GEN[16].ngCCM_gbt/ngccmPinsOutReg_reg[peltier][2] ------------------------------------------------------------------- required time -1.557 arrival time 1.710 ------------------------------------------------------------------- slack 0.153 Slack (MET) : 0.160ns (arrival time - required time) Source: SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][1]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.227ns (logic 0.048ns (21.145%) route 0.179ns (78.855%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.686ns Source Clock Delay (SCD): 1.465ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.465ns (routing 0.393ns, distribution 1.072ns) Clock Net Delay (Destination): 1.686ns (routing 0.434ns, distribution 1.252ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.465 1.465 SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLR Crossing[0->1] SLICE_X2Y378 FDPE r SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y378 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.513 f SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.179 1.692 SFP_GEN[36].ngCCM_gbt/out[0] SLICE_X0Y378 FDPE f SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][1]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.686 1.686 SFP_GEN[36].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X0Y378 FDPE r SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][1]/C clock pessimism -0.159 1.527 SLICE_X0Y378 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.532 SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][1] ------------------------------------------------------------------- required time -1.532 arrival time 1.692 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.161ns (arrival time - required time) Source: SFP_GEN[24].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[24].ngCCM_gbt/ngccmPinsOutReg_reg[bkp_reset_qie]/CLR (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.237ns (logic 0.048ns (20.253%) route 0.189ns (79.747%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.433ns Source Clock Delay (SCD): 1.226ns Clock Pessimism Removal (CPR): 0.136ns Clock Net Delay (Source): 1.226ns (routing 0.393ns, distribution 0.833ns) Clock Net Delay (Destination): 1.433ns (routing 0.434ns, distribution 0.999ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.226 1.226 SFP_GEN[24].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLR Crossing[0->1] SLICE_X56Y349 FDPE r SFP_GEN[24].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y349 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.274 f SFP_GEN[24].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=377, routed) 0.189 1.463 SFP_GEN[24].ngCCM_gbt/out[0] SLICE_X54Y353 FDCE f SFP_GEN[24].ngCCM_gbt/ngccmPinsOutReg_reg[bkp_reset_qie]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.433 1.433 SFP_GEN[24].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X54Y353 FDCE r SFP_GEN[24].ngCCM_gbt/ngccmPinsOutReg_reg[bkp_reset_qie]/C clock pessimism -0.136 1.297 SLICE_X54Y353 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.302 SFP_GEN[24].ngCCM_gbt/ngccmPinsOutReg_reg[bkp_reset_qie] ------------------------------------------------------------------- required time -1.302 arrival time 1.463 ------------------------------------------------------------------- slack 0.161 Slack (MET) : 0.162ns (arrival time - required time) Source: SFP_GEN[7].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.213ns (logic 0.048ns (22.535%) route 0.165ns (77.465%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.701ns Source Clock Delay (SCD): 1.467ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.467ns (routing 0.393ns, distribution 1.074ns) Clock Net Delay (Destination): 1.701ns (routing 0.434ns, distribution 1.267ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.467 1.467 SFP_GEN[7].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLICE_X122Y70 FDPE r SFP_GEN[7].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y70 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.515 f SFP_GEN[7].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.165 1.680 SFP_GEN[7].ngCCM_gbt/out[0] SLICE_X122Y71 FDPE f SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.701 1.701 SFP_GEN[7].ngCCM_gbt/fabric_clk SLICE_X122Y71 FDPE r SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/C clock pessimism -0.188 1.513 SLICE_X122Y71 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.518 SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6] ------------------------------------------------------------------- required time -1.518 arrival time 1.680 ------------------------------------------------------------------- slack 0.162 Slack (MET) : 0.172ns (arrival time - required time) Source: SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.215ns (logic 0.048ns (22.326%) route 0.167ns (77.674%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.556ns Source Clock Delay (SCD): 1.351ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.351ns (routing 0.393ns, distribution 0.958ns) Clock Net Delay (Destination): 1.556ns (routing 0.434ns, distribution 1.122ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.351 1.351 SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLR Crossing[0->1] SLICE_X86Y546 FDPE r SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y546 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.399 f SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.167 1.566 SFP_GEN[46].ngCCM_gbt/out[0] SLICE_X86Y548 FDPE f SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.556 1.556 SFP_GEN[46].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X86Y548 FDPE r SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/C clock pessimism -0.167 1.389 SLICE_X86Y548 FDPE (Remov_EFF_SLICEL_C_PRE) 0.005 1.394 SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6] ------------------------------------------------------------------- required time -1.394 arrival time 1.566 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][8]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.215ns (logic 0.048ns (22.326%) route 0.167ns (77.674%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.556ns Source Clock Delay (SCD): 1.351ns Clock Pessimism Removal (CPR): 0.167ns Clock Net Delay (Source): 1.351ns (routing 0.393ns, distribution 0.958ns) Clock Net Delay (Destination): 1.556ns (routing 0.434ns, distribution 1.122ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.351 1.351 SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLR Crossing[0->1] SLICE_X86Y546 FDPE r SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y546 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.399 f SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.167 1.566 SFP_GEN[46].ngCCM_gbt/out[0] SLICE_X86Y548 FDPE f SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][8]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.556 1.556 SFP_GEN[46].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X86Y548 FDPE r SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][8]/C clock pessimism -0.167 1.389 SLICE_X86Y548 FDPE (Remov_EFF2_SLICEL_C_PRE) 0.005 1.394 SFP_GEN[46].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][8] ------------------------------------------------------------------- required time -1.394 arrival time 1.566 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.173ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.256ns (logic 0.048ns (18.750%) route 0.208ns (81.250%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.698ns Source Clock Delay (SCD): 1.461ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.461ns (routing 0.393ns, distribution 1.068ns) Clock Net Delay (Destination): 1.698ns (routing 0.434ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.461 1.461 SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLR Crossing[0->1] SLICE_X5Y419 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y419 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.509 f SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.208 1.717 SFP_GEN[37].ngCCM_gbt/out[0] SLICE_X7Y418 FDPE f SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.698 1.698 SFP_GEN[37].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X7Y418 FDPE r SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6]/C clock pessimism -0.159 1.539 SLICE_X7Y418 FDPE (Remov_EFF_SLICEM_C_PRE) 0.005 1.544 SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][6] ------------------------------------------------------------------- required time -1.544 arrival time 1.717 ------------------------------------------------------------------- slack 0.173 Slack (MET) : 0.173ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][7]/PRE (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.256ns (logic 0.048ns (18.750%) route 0.208ns (81.250%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.698ns Source Clock Delay (SCD): 1.461ns Clock Pessimism Removal (CPR): 0.159ns Clock Net Delay (Source): 1.461ns (routing 0.393ns, distribution 1.068ns) Clock Net Delay (Destination): 1.698ns (routing 0.434ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.461 1.461 SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLR Crossing[0->1] SLICE_X5Y419 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y419 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.509 f SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.208 1.717 SFP_GEN[37].ngCCM_gbt/out[0] SLICE_X7Y418 FDPE f SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][7]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.698 1.698 SFP_GEN[37].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X7Y418 FDPE r SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][7]/C clock pessimism -0.159 1.539 SLICE_X7Y418 FDPE (Remov_EFF2_SLICEM_C_PRE) 0.005 1.544 SFP_GEN[37].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][7] ------------------------------------------------------------------- required time -1.544 arrival time 1.717 ------------------------------------------------------------------- slack 0.173 Slack (MET) : 0.176ns (arrival time - required time) Source: SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Destination: SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_i_reg[27]/CLR (removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk rise@0.000ns - fabric_clk rise@0.000ns) Data Path Delay: 0.274ns (logic 0.048ns (17.518%) route 0.226ns (82.482%)) Logic Levels: 0 Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.674ns Source Clock Delay (SCD): 1.428ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.428ns (routing 0.393ns, distribution 1.035ns) Clock Net Delay (Destination): 1.674ns (routing 0.434ns, distribution 1.240ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.428 1.428 SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/fabric_clk SLR Crossing[0->1] SLICE_X28Y478 FDPE r SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y478 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.476 f SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/Q net (fo=375, routed) 0.226 1.702 SFP_GEN[39].ngCCM_gbt/out[0] SLICE_X24Y478 FDCE f SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_i_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk rise edge) 0.000 0.000 r BUFGCE_X2Y110 BUFGCE 0.000 0.000 r fabric_clk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=103803, routed) 1.674 1.674 SFP_GEN[39].ngCCM_gbt/fabric_clk SLR Crossing[0->1] SLICE_X24Y478 FDCE r SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_i_reg[27]/C clock pessimism -0.153 1.521 SLICE_X24Y478 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.526 SFP_GEN[39].ngCCM_gbt/reg_ngccm_jtag_i_reg[27] ------------------------------------------------------------------- required time -1.526 arrival time 1.702 ------------------------------------------------------------------- slack 0.176 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0] To Clock: gtwiz_userclk_rx_srcclk_out[0] Setup : 0 Failing Endpoints, Worst Slack 5.734ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.170ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.734ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 2.305ns (logic 0.374ns (16.226%) route 1.931ns (83.774%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.167ns = ( 11.484 - 8.317 ) Source Clock Delay (SCD): 3.610ns Clock Pessimism Removal (CPR): 0.293ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.135ns (routing 1.577ns, distribution 1.558ns) Clock Net Delay (Destination): 2.769ns (routing 1.441ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.135 3.610 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X89Y102 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y102 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.749 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.340 5.089 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X84Y68 LUT2 (Prop_C6LUT_SLICEL_I0_O) 0.235 5.324 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1/O net (fo=2, routed) 0.591 5.915 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 SLICE_X84Y68 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.769 11.484 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X84Y68 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.293 11.777 clock uncertainty -0.035 11.742 SLICE_X84Y68 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.649 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.649 arrival time -5.915 ------------------------------------------------------------------- slack 5.734 Slack (MET) : 5.734ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 2.305ns (logic 0.374ns (16.226%) route 1.931ns (83.774%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.150ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.167ns = ( 11.484 - 8.317 ) Source Clock Delay (SCD): 3.610ns Clock Pessimism Removal (CPR): 0.293ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.135ns (routing 1.577ns, distribution 1.558ns) Clock Net Delay (Destination): 2.769ns (routing 1.441ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.135 3.610 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X89Y102 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y102 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.749 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.340 5.089 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X84Y68 LUT2 (Prop_C6LUT_SLICEL_I0_O) 0.235 5.324 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1/O net (fo=2, routed) 0.591 5.915 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 SLICE_X84Y68 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.769 11.484 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X84Y68 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.293 11.777 clock uncertainty -0.035 11.742 SLICE_X84Y68 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.649 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.649 arrival time -5.915 ------------------------------------------------------------------- slack 5.734 Slack (MET) : 6.063ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 1.803ns (logic 0.137ns (7.598%) route 1.666ns (92.402%)) Logic Levels: 0 Clock Path Skew: -0.323ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.122ns = ( 11.439 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.577ns, distribution 1.606ns) Clock Net Delay (Destination): 2.724ns (routing 1.441ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y62 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 3.795 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 1.666 5.461 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X82Y57 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.724 11.439 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X82Y57 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism 0.213 11.652 clock uncertainty -0.035 11.617 SLICE_X82Y57 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.524 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time 11.524 arrival time -5.461 ------------------------------------------------------------------- slack 6.063 Slack (MET) : 6.063ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 1.803ns (logic 0.137ns (7.598%) route 1.666ns (92.402%)) Logic Levels: 0 Clock Path Skew: -0.323ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.122ns = ( 11.439 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.577ns, distribution 1.606ns) Clock Net Delay (Destination): 2.724ns (routing 1.441ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y62 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 3.795 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 1.666 5.461 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X82Y57 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.724 11.439 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X82Y57 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism 0.213 11.652 clock uncertainty -0.035 11.617 SLICE_X82Y57 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 11.524 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time 11.524 arrival time -5.461 ------------------------------------------------------------------- slack 6.063 Slack (MET) : 6.063ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 1.803ns (logic 0.137ns (7.598%) route 1.666ns (92.402%)) Logic Levels: 0 Clock Path Skew: -0.323ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.122ns = ( 11.439 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.577ns, distribution 1.606ns) Clock Net Delay (Destination): 2.724ns (routing 1.441ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y62 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 3.795 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 1.666 5.461 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X82Y57 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.724 11.439 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X82Y57 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism 0.213 11.652 clock uncertainty -0.035 11.617 SLICE_X82Y57 FDCE (Recov_FFF_SLICEM_C_CLR) -0.093 11.524 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time 11.524 arrival time -5.461 ------------------------------------------------------------------- slack 6.063 Slack (MET) : 6.146ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 1.718ns (logic 0.137ns (7.974%) route 1.581ns (92.026%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.120ns = ( 11.437 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.577ns, distribution 1.606ns) Clock Net Delay (Destination): 2.722ns (routing 1.441ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y62 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 3.795 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 1.581 5.376 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X81Y57 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.722 11.437 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X81Y57 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C clock pessimism 0.213 11.650 clock uncertainty -0.035 11.615 SLICE_X81Y57 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.522 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time 11.522 arrival time -5.376 ------------------------------------------------------------------- slack 6.146 Slack (MET) : 6.146ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 1.718ns (logic 0.137ns (7.974%) route 1.581ns (92.026%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.120ns = ( 11.437 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.577ns, distribution 1.606ns) Clock Net Delay (Destination): 2.722ns (routing 1.441ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y62 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 3.795 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 1.581 5.376 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X81Y57 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.722 11.437 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X81Y57 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism 0.213 11.650 clock uncertainty -0.035 11.615 SLICE_X81Y57 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.522 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time 11.522 arrival time -5.376 ------------------------------------------------------------------- slack 6.146 Slack (MET) : 6.146ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 1.718ns (logic 0.137ns (7.974%) route 1.581ns (92.026%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.120ns = ( 11.437 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.577ns, distribution 1.606ns) Clock Net Delay (Destination): 2.722ns (routing 1.441ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y62 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 3.795 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 1.581 5.376 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X81Y57 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.722 11.437 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X81Y57 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism 0.213 11.650 clock uncertainty -0.035 11.615 SLICE_X81Y57 FDCE (Recov_FFF_SLICEL_C_CLR) -0.093 11.522 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time 11.522 arrival time -5.376 ------------------------------------------------------------------- slack 6.146 Slack (MET) : 6.146ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 1.718ns (logic 0.137ns (7.974%) route 1.581ns (92.026%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.120ns = ( 11.437 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.577ns, distribution 1.606ns) Clock Net Delay (Destination): 2.722ns (routing 1.441ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y62 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 3.795 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 1.581 5.376 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X81Y57 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.722 11.437 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X81Y57 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism 0.213 11.650 clock uncertainty -0.035 11.615 SLICE_X81Y57 FDCE (Recov_FFF2_SLICEL_C_CLR) -0.093 11.522 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time 11.522 arrival time -5.376 ------------------------------------------------------------------- slack 6.146 Slack (MET) : 6.146ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 1.718ns (logic 0.137ns (7.974%) route 1.581ns (92.026%)) Logic Levels: 0 Clock Path Skew: -0.325ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.120ns = ( 11.437 - 8.317 ) Source Clock Delay (SCD): 3.658ns Clock Pessimism Removal (CPR): 0.213ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.183ns (routing 1.577ns, distribution 1.606ns) Clock Net Delay (Destination): 2.722ns (routing 1.441ns, distribution 1.281ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 3.183 3.658 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y62 FDCE (Prop_DFF2_SLICEL_C_Q) 0.137 3.795 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 1.581 5.376 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X81Y57 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 2.722 11.437 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X81Y57 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism 0.213 11.650 clock uncertainty -0.035 11.615 SLICE_X81Y57 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.522 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time 11.522 arrival time -5.376 ------------------------------------------------------------------- slack 6.146 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.170ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.278ns (logic 0.049ns (17.626%) route 0.229ns (82.374%)) Logic Levels: 0 Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.328ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 1.210ns (routing 0.667ns, distribution 0.543ns) Clock Net Delay (Destination): 1.441ns (routing 0.748ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.328 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X82Y67 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y67 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.377 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.229 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X84Y62 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.441 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C clock pessimism -0.175 1.431 SLICE_X84Y62 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.436 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] ------------------------------------------------------------------- required time -1.436 arrival time 1.606 ------------------------------------------------------------------- slack 0.170 Slack (MET) : 0.170ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.278ns (logic 0.049ns (17.626%) route 0.229ns (82.374%)) Logic Levels: 0 Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.328ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 1.210ns (routing 0.667ns, distribution 0.543ns) Clock Net Delay (Destination): 1.441ns (routing 0.748ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.328 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X82Y67 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y67 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.377 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.229 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X84Y62 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.441 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C clock pessimism -0.175 1.431 SLICE_X84Y62 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.436 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] ------------------------------------------------------------------- required time -1.436 arrival time 1.606 ------------------------------------------------------------------- slack 0.170 Slack (MET) : 0.170ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.278ns (logic 0.049ns (17.626%) route 0.229ns (82.374%)) Logic Levels: 0 Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.328ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 1.210ns (routing 0.667ns, distribution 0.543ns) Clock Net Delay (Destination): 1.441ns (routing 0.748ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.328 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X82Y67 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y67 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.377 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.229 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X84Y62 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.441 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C clock pessimism -0.175 1.431 SLICE_X84Y62 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.436 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] ------------------------------------------------------------------- required time -1.436 arrival time 1.606 ------------------------------------------------------------------- slack 0.170 Slack (MET) : 0.170ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.278ns (logic 0.049ns (17.626%) route 0.229ns (82.374%)) Logic Levels: 0 Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.328ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 1.210ns (routing 0.667ns, distribution 0.543ns) Clock Net Delay (Destination): 1.441ns (routing 0.748ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.328 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X82Y67 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y67 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.377 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.229 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X84Y62 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.441 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X84Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[20]/C clock pessimism -0.175 1.431 SLICE_X84Y62 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.436 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[20] ------------------------------------------------------------------- required time -1.436 arrival time 1.606 ------------------------------------------------------------------- slack 0.170 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.279ns (logic 0.049ns (17.563%) route 0.230ns (82.437%)) Logic Levels: 0 Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.328ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 1.210ns (routing 0.667ns, distribution 0.543ns) Clock Net Delay (Destination): 1.441ns (routing 0.748ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.328 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X82Y67 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y67 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.377 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.230 1.607 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X83Y62 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.441 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X83Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[0]/C clock pessimism -0.175 1.431 SLICE_X83Y62 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.436 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[0] ------------------------------------------------------------------- required time -1.436 arrival time 1.607 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.279ns (logic 0.049ns (17.563%) route 0.230ns (82.437%)) Logic Levels: 0 Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.328ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 1.210ns (routing 0.667ns, distribution 0.543ns) Clock Net Delay (Destination): 1.441ns (routing 0.748ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.328 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X82Y67 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y67 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.377 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.230 1.607 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X83Y62 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.441 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X83Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[1]/C clock pessimism -0.175 1.431 SLICE_X83Y62 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.436 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[1] ------------------------------------------------------------------- required time -1.436 arrival time 1.607 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.279ns (logic 0.049ns (17.563%) route 0.230ns (82.437%)) Logic Levels: 0 Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.328ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 1.210ns (routing 0.667ns, distribution 0.543ns) Clock Net Delay (Destination): 1.441ns (routing 0.748ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.328 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X82Y67 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y67 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.377 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.230 1.607 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X83Y62 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.441 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X83Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[3]/C clock pessimism -0.175 1.431 SLICE_X83Y62 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.436 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[3] ------------------------------------------------------------------- required time -1.436 arrival time 1.607 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.279ns (logic 0.049ns (17.563%) route 0.230ns (82.437%)) Logic Levels: 0 Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.328ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 1.210ns (routing 0.667ns, distribution 0.543ns) Clock Net Delay (Destination): 1.441ns (routing 0.748ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.328 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X82Y67 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y67 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.377 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.230 1.607 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X83Y62 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.441 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X83Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[0]/C clock pessimism -0.175 1.431 SLICE_X83Y62 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.436 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[0] ------------------------------------------------------------------- required time -1.436 arrival time 1.607 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.279ns (logic 0.049ns (17.563%) route 0.230ns (82.437%)) Logic Levels: 0 Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.328ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 1.210ns (routing 0.667ns, distribution 0.543ns) Clock Net Delay (Destination): 1.441ns (routing 0.748ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.328 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X82Y67 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y67 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.377 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.230 1.607 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X83Y62 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.441 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X83Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[1]/C clock pessimism -0.175 1.431 SLICE_X83Y62 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.436 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[1] ------------------------------------------------------------------- required time -1.436 arrival time 1.607 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000ns) Data Path Delay: 0.279ns (logic 0.049ns (17.563%) route 0.230ns (82.437%)) Logic Levels: 0 Clock Path Skew: 0.103ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.606ns Source Clock Delay (SCD): 1.328ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 1.210ns (routing 0.667ns, distribution 0.543ns) Clock Net Delay (Destination): 1.441ns (routing 0.748ns, distribution 0.693ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.210 1.328 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X82Y67 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y67 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.377 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.230 1.607 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X83Y62 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y4 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y29 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y0 (CLOCK_ROOT) net (fo=674, routed) 1.441 1.606 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X83Y62 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[3]/C clock pessimism -0.175 1.431 SLICE_X83Y62 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.436 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[3] ------------------------------------------------------------------- required time -1.436 arrival time 1.607 ------------------------------------------------------------------- slack 0.171 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_1 To Clock: gtwiz_userclk_rx_srcclk_out[0]_1 Setup : 0 Failing Endpoints, Worst Slack 5.232ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.188ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.232ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.652ns (logic 0.305ns (11.501%) route 2.347ns (88.499%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.305ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.751ns = ( 11.068 - 8.317 ) Source Clock Delay (SCD): 3.312ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.837ns (routing 1.142ns, distribution 1.695ns) Clock Net Delay (Destination): 2.353ns (routing 1.042ns, distribution 1.311ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.837 3.312 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y220 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y220 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.451 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.580 5.031 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X108Y223 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.166 5.197 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.767 5.964 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X108Y223 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.353 11.068 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X108Y223 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C clock pessimism 0.256 11.324 clock uncertainty -0.035 11.289 SLICE_X108Y223 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.196 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10] ------------------------------------------------------------------- required time 11.196 arrival time -5.964 ------------------------------------------------------------------- slack 5.232 Slack (MET) : 5.237ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.651ns (logic 0.305ns (11.505%) route 2.346ns (88.495%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.301ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.755ns = ( 11.072 - 8.317 ) Source Clock Delay (SCD): 3.312ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.837ns (routing 1.142ns, distribution 1.695ns) Clock Net Delay (Destination): 2.357ns (routing 1.042ns, distribution 1.315ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.837 3.312 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y220 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y220 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.451 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.580 5.031 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X108Y223 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.166 5.197 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.766 5.963 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X107Y223 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.357 11.072 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X107Y223 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C clock pessimism 0.256 11.328 clock uncertainty -0.035 11.293 SLICE_X107Y223 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.200 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4] ------------------------------------------------------------------- required time 11.200 arrival time -5.963 ------------------------------------------------------------------- slack 5.237 Slack (MET) : 5.237ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.651ns (logic 0.305ns (11.505%) route 2.346ns (88.495%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.301ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.755ns = ( 11.072 - 8.317 ) Source Clock Delay (SCD): 3.312ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.837ns (routing 1.142ns, distribution 1.695ns) Clock Net Delay (Destination): 2.357ns (routing 1.042ns, distribution 1.315ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.837 3.312 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y220 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y220 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.451 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.580 5.031 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X108Y223 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.166 5.197 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.766 5.963 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X107Y223 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.357 11.072 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X107Y223 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C clock pessimism 0.256 11.328 clock uncertainty -0.035 11.293 SLICE_X107Y223 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.200 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5] ------------------------------------------------------------------- required time 11.200 arrival time -5.963 ------------------------------------------------------------------- slack 5.237 Slack (MET) : 5.237ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.651ns (logic 0.305ns (11.505%) route 2.346ns (88.495%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.301ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.755ns = ( 11.072 - 8.317 ) Source Clock Delay (SCD): 3.312ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.837ns (routing 1.142ns, distribution 1.695ns) Clock Net Delay (Destination): 2.357ns (routing 1.042ns, distribution 1.315ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.837 3.312 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y220 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y220 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.451 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.580 5.031 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X108Y223 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.166 5.197 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.766 5.963 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X107Y223 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.357 11.072 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X107Y223 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C clock pessimism 0.256 11.328 clock uncertainty -0.035 11.293 SLICE_X107Y223 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.200 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6] ------------------------------------------------------------------- required time 11.200 arrival time -5.963 ------------------------------------------------------------------- slack 5.237 Slack (MET) : 5.243ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.644ns (logic 0.305ns (11.536%) route 2.339ns (88.464%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.302ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.754ns = ( 11.071 - 8.317 ) Source Clock Delay (SCD): 3.312ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.837ns (routing 1.142ns, distribution 1.695ns) Clock Net Delay (Destination): 2.356ns (routing 1.042ns, distribution 1.314ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.837 3.312 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y220 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y220 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.451 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.580 5.031 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X108Y223 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.166 5.197 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.759 5.956 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X107Y223 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 11.071 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X107Y223 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C clock pessimism 0.256 11.327 clock uncertainty -0.035 11.292 SLICE_X107Y223 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.199 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7] ------------------------------------------------------------------- required time 11.199 arrival time -5.956 ------------------------------------------------------------------- slack 5.243 Slack (MET) : 5.304ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.574ns (logic 0.305ns (11.849%) route 2.269ns (88.151%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.745ns = ( 11.062 - 8.317 ) Source Clock Delay (SCD): 3.312ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.837ns (routing 1.142ns, distribution 1.695ns) Clock Net Delay (Destination): 2.347ns (routing 1.042ns, distribution 1.305ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.837 3.312 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y220 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y220 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.451 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.580 5.031 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X108Y223 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.166 5.197 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.689 5.886 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X107Y220 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.347 11.062 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X107Y220 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C clock pessimism 0.256 11.318 clock uncertainty -0.035 11.283 SLICE_X107Y220 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.190 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1] ------------------------------------------------------------------- required time 11.190 arrival time -5.886 ------------------------------------------------------------------- slack 5.304 Slack (MET) : 5.304ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.574ns (logic 0.305ns (11.849%) route 2.269ns (88.151%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.745ns = ( 11.062 - 8.317 ) Source Clock Delay (SCD): 3.312ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.837ns (routing 1.142ns, distribution 1.695ns) Clock Net Delay (Destination): 2.347ns (routing 1.042ns, distribution 1.305ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.837 3.312 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y220 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y220 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.451 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.580 5.031 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X108Y223 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.166 5.197 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.689 5.886 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X107Y220 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.347 11.062 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X107Y220 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C clock pessimism 0.256 11.318 clock uncertainty -0.035 11.283 SLICE_X107Y220 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.190 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2] ------------------------------------------------------------------- required time 11.190 arrival time -5.886 ------------------------------------------------------------------- slack 5.304 Slack (MET) : 5.304ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.574ns (logic 0.305ns (11.849%) route 2.269ns (88.151%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.745ns = ( 11.062 - 8.317 ) Source Clock Delay (SCD): 3.312ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.837ns (routing 1.142ns, distribution 1.695ns) Clock Net Delay (Destination): 2.347ns (routing 1.042ns, distribution 1.305ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.837 3.312 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y220 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y220 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.451 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.580 5.031 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X108Y223 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.166 5.197 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.689 5.886 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X107Y220 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.347 11.062 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X107Y220 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C clock pessimism 0.256 11.318 clock uncertainty -0.035 11.283 SLICE_X107Y220 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.190 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3] ------------------------------------------------------------------- required time 11.190 arrival time -5.886 ------------------------------------------------------------------- slack 5.304 Slack (MET) : 5.304ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.574ns (logic 0.305ns (11.849%) route 2.269ns (88.151%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.745ns = ( 11.062 - 8.317 ) Source Clock Delay (SCD): 3.312ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.837ns (routing 1.142ns, distribution 1.695ns) Clock Net Delay (Destination): 2.347ns (routing 1.042ns, distribution 1.305ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.837 3.312 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y220 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y220 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.451 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.580 5.031 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X108Y223 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.166 5.197 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.689 5.886 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X107Y220 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.347 11.062 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X107Y220 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/C clock pessimism 0.256 11.318 clock uncertainty -0.035 11.283 SLICE_X107Y220 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.190 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4] ------------------------------------------------------------------- required time 11.190 arrival time -5.886 ------------------------------------------------------------------- slack 5.304 Slack (MET) : 5.371ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 2.515ns (logic 0.305ns (12.127%) route 2.210ns (87.873%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.303ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.753ns = ( 11.070 - 8.317 ) Source Clock Delay (SCD): 3.312ns Clock Pessimism Removal (CPR): 0.256ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.837ns (routing 1.142ns, distribution 1.695ns) Clock Net Delay (Destination): 2.355ns (routing 1.042ns, distribution 1.313ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.837 3.312 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y220 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y220 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.451 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.580 5.031 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X108Y223 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.166 5.197 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/O net (fo=15, routed) 0.630 5.827 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X107Y221 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.355 11.070 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] SLICE_X107Y221 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C clock pessimism 0.256 11.326 clock uncertainty -0.035 11.291 SLICE_X107Y221 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.198 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1] ------------------------------------------------------------------- required time 11.198 arrival time -5.827 ------------------------------------------------------------------- slack 5.371 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.049ns (18.992%) route 0.209ns (81.008%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.352ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 1.015ns (routing 0.477ns, distribution 0.538ns) Clock Net Delay (Destination): 1.187ns (routing 0.537ns, distribution 0.650ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.133 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y220 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y220 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.182 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.209 1.391 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y220 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.187 1.352 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X107Y220 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.154 1.198 SLICE_X107Y220 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.203 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.203 arrival time 1.391 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.189ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.271ns (logic 0.048ns (17.712%) route 0.223ns (82.288%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 1.008ns (routing 0.477ns, distribution 0.531ns) Clock Net Delay (Destination): 1.192ns (routing 0.537ns, distribution 0.655ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.126 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X108Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y214 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.174 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.223 1.397 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X111Y212 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.357 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK SLICE_X111Y212 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.154 1.203 SLICE_X111Y212 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.208 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -1.208 arrival time 1.397 ------------------------------------------------------------------- slack 0.189 Slack (MET) : 0.189ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.271ns (logic 0.048ns (17.712%) route 0.223ns (82.288%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.126ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 1.008ns (routing 0.477ns, distribution 0.531ns) Clock Net Delay (Destination): 1.192ns (routing 0.537ns, distribution 0.655ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.126 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X108Y214 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y214 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.174 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.223 1.397 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X111Y212 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.357 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK SLICE_X111Y212 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.154 1.203 SLICE_X111Y212 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.208 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.208 arrival time 1.397 ------------------------------------------------------------------- slack 0.189 Slack (MET) : 0.203ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[63]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.248ns (logic 0.049ns (19.758%) route 0.199ns (80.242%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.015ns (routing 0.477ns, distribution 0.538ns) Clock Net Delay (Destination): 1.193ns (routing 0.537ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.133 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y220 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y220 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.182 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.199 1.381 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y217 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[63]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.193 1.358 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X110Y217 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[63]/C clock pessimism -0.185 1.173 SLICE_X110Y217 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.178 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[63] ------------------------------------------------------------------- required time -1.178 arrival time 1.381 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.203ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[103]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.248ns (logic 0.049ns (19.758%) route 0.199ns (80.242%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.015ns (routing 0.477ns, distribution 0.538ns) Clock Net Delay (Destination): 1.193ns (routing 0.537ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.133 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y220 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y220 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.182 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.199 1.381 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y217 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[103]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.193 1.358 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X110Y217 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[103]/C clock pessimism -0.185 1.173 SLICE_X110Y217 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.178 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[103] ------------------------------------------------------------------- required time -1.178 arrival time 1.381 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.203ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[63]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.248ns (logic 0.049ns (19.758%) route 0.199ns (80.242%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.015ns (routing 0.477ns, distribution 0.538ns) Clock Net Delay (Destination): 1.193ns (routing 0.537ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.133 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y220 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y220 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.182 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.199 1.381 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X110Y217 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[63]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.193 1.358 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X110Y217 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[63]/C clock pessimism -0.185 1.173 SLICE_X110Y217 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.178 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[63] ------------------------------------------------------------------- required time -1.178 arrival time 1.381 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.215ns (arrival time - required time) Source: SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.300ns (logic 0.048ns (16.000%) route 0.252ns (84.000%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.354ns Source Clock Delay (SCD): 1.120ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 1.002ns (routing 0.477ns, distribution 0.525ns) Clock Net Delay (Destination): 1.189ns (routing 0.537ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.120 SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X98Y217 FDPE r SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y217 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.168 f SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.252 1.420 SFP_GEN[10].ngCCM_gbt/sync_m_reg[3][0] SLICE_X101Y217 FDCE f SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.189 1.354 SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X101Y217 FDCE r SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.154 1.200 SLICE_X101Y217 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.205 SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.205 arrival time 1.420 ------------------------------------------------------------------- slack 0.215 Slack (MET) : 0.231ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[71]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.299ns (logic 0.049ns (16.388%) route 0.250ns (83.612%)) Logic Levels: 0 Clock Path Skew: 0.063ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.350ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 1.015ns (routing 0.477ns, distribution 0.538ns) Clock Net Delay (Destination): 1.185ns (routing 0.537ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.133 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y220 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y220 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.182 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.250 1.432 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X109Y217 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[71]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.350 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X109Y217 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[71]/C clock pessimism -0.154 1.196 SLICE_X109Y217 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.201 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[71] ------------------------------------------------------------------- required time -1.201 arrival time 1.432 ------------------------------------------------------------------- slack 0.231 Slack (MET) : 0.231ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[78]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.299ns (logic 0.049ns (16.388%) route 0.250ns (83.612%)) Logic Levels: 0 Clock Path Skew: 0.063ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.350ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 1.015ns (routing 0.477ns, distribution 0.538ns) Clock Net Delay (Destination): 1.185ns (routing 0.537ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.133 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y220 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y220 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.182 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.250 1.432 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X109Y217 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[78]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.350 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X109Y217 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[78]/C clock pessimism -0.154 1.196 SLICE_X109Y217 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.201 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[78] ------------------------------------------------------------------- required time -1.201 arrival time 1.432 ------------------------------------------------------------------- slack 0.231 Slack (MET) : 0.231ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[111]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns) Data Path Delay: 0.299ns (logic 0.049ns (16.388%) route 0.250ns (83.612%)) Logic Levels: 0 Clock Path Skew: 0.063ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.350ns Source Clock Delay (SCD): 1.133ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 1.015ns (routing 0.477ns, distribution 0.538ns) Clock Net Delay (Destination): 1.185ns (routing 0.537ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.133 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X111Y220 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y220 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.182 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.250 1.432 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X109Y217 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[111]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.350 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X109Y217 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[111]/C clock pessimism -0.154 1.196 SLICE_X109Y217 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.201 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[111] ------------------------------------------------------------------- required time -1.201 arrival time 1.432 ------------------------------------------------------------------- slack 0.231 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_10 To Clock: gtwiz_userclk_rx_srcclk_out[0]_10 Setup : 0 Failing Endpoints, Worst Slack 5.023ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.146ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.023ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.790ns (logic 0.357ns (12.796%) route 2.433ns (87.204%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.376ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.317ns = ( 10.634 - 8.317 ) Source Clock Delay (SCD): 2.913ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.438ns (routing 0.723ns, distribution 1.715ns) Clock Net Delay (Destination): 1.919ns (routing 0.655ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.438 2.913 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y194 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.052 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.747 4.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y196 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.218 5.017 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.686 5.703 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X109Y198 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.919 10.634 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X109Y198 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C clock pessimism 0.220 10.855 clock uncertainty -0.035 10.819 SLICE_X109Y198 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.726 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5] ------------------------------------------------------------------- required time 10.726 arrival time -5.703 ------------------------------------------------------------------- slack 5.023 Slack (MET) : 5.023ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.790ns (logic 0.357ns (12.796%) route 2.433ns (87.204%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.376ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.317ns = ( 10.634 - 8.317 ) Source Clock Delay (SCD): 2.913ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.438ns (routing 0.723ns, distribution 1.715ns) Clock Net Delay (Destination): 1.919ns (routing 0.655ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.438 2.913 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y194 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.052 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.747 4.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y196 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.218 5.017 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.686 5.703 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X109Y198 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.919 10.634 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X109Y198 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/C clock pessimism 0.220 10.855 clock uncertainty -0.035 10.819 SLICE_X109Y198 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.726 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6] ------------------------------------------------------------------- required time 10.726 arrival time -5.703 ------------------------------------------------------------------- slack 5.023 Slack (MET) : 5.023ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.790ns (logic 0.357ns (12.796%) route 2.433ns (87.204%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.376ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.317ns = ( 10.634 - 8.317 ) Source Clock Delay (SCD): 2.913ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.438ns (routing 0.723ns, distribution 1.715ns) Clock Net Delay (Destination): 1.919ns (routing 0.655ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.438 2.913 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y194 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.052 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.747 4.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y196 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.218 5.017 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.686 5.703 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X109Y198 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.919 10.634 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X109Y198 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/C clock pessimism 0.220 10.855 clock uncertainty -0.035 10.819 SLICE_X109Y198 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.726 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7] ------------------------------------------------------------------- required time 10.726 arrival time -5.703 ------------------------------------------------------------------- slack 5.023 Slack (MET) : 5.084ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.737ns (logic 0.357ns (13.043%) route 2.380ns (86.957%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.368ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.325ns = ( 10.642 - 8.317 ) Source Clock Delay (SCD): 2.913ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.438ns (routing 0.723ns, distribution 1.715ns) Clock Net Delay (Destination): 1.927ns (routing 0.655ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.438 2.913 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y194 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.052 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.747 4.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y196 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.218 5.017 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.633 5.650 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X110Y197 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.927 10.642 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X110Y197 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/C clock pessimism 0.220 10.863 clock uncertainty -0.035 10.827 SLICE_X110Y197 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.734 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0] ------------------------------------------------------------------- required time 10.734 arrival time -5.650 ------------------------------------------------------------------- slack 5.084 Slack (MET) : 5.117ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.705ns (logic 0.357ns (13.198%) route 2.348ns (86.802%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.367ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.326ns = ( 10.643 - 8.317 ) Source Clock Delay (SCD): 2.913ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.438ns (routing 0.723ns, distribution 1.715ns) Clock Net Delay (Destination): 1.928ns (routing 0.655ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.438 2.913 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y194 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.052 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.747 4.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y196 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.218 5.017 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.601 5.618 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X109Y197 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.928 10.643 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X109Y197 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/C clock pessimism 0.220 10.864 clock uncertainty -0.035 10.828 SLICE_X109Y197 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.735 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4] ------------------------------------------------------------------- required time 10.735 arrival time -5.618 ------------------------------------------------------------------- slack 5.117 Slack (MET) : 5.141ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.719ns (logic 0.357ns (13.130%) route 2.362ns (86.870%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.329ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.364ns = ( 10.681 - 8.317 ) Source Clock Delay (SCD): 2.913ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.438ns (routing 0.723ns, distribution 1.715ns) Clock Net Delay (Destination): 1.966ns (routing 0.655ns, distribution 1.311ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.438 2.913 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y194 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.052 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.747 4.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y196 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.218 5.017 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.615 5.632 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X113Y194 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.966 10.681 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X113Y194 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/C clock pessimism 0.220 10.901 clock uncertainty -0.035 10.866 SLICE_X113Y194 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.773 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1] ------------------------------------------------------------------- required time 10.773 arrival time -5.632 ------------------------------------------------------------------- slack 5.141 Slack (MET) : 5.141ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.719ns (logic 0.357ns (13.130%) route 2.362ns (86.870%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.329ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.364ns = ( 10.681 - 8.317 ) Source Clock Delay (SCD): 2.913ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.438ns (routing 0.723ns, distribution 1.715ns) Clock Net Delay (Destination): 1.966ns (routing 0.655ns, distribution 1.311ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.438 2.913 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y194 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.052 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.747 4.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y196 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.218 5.017 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.615 5.632 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X113Y194 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.966 10.681 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X113Y194 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/C clock pessimism 0.220 10.901 clock uncertainty -0.035 10.866 SLICE_X113Y194 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 10.773 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2] ------------------------------------------------------------------- required time 10.773 arrival time -5.632 ------------------------------------------------------------------- slack 5.141 Slack (MET) : 5.141ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.719ns (logic 0.357ns (13.130%) route 2.362ns (86.870%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.329ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.364ns = ( 10.681 - 8.317 ) Source Clock Delay (SCD): 2.913ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.438ns (routing 0.723ns, distribution 1.715ns) Clock Net Delay (Destination): 1.966ns (routing 0.655ns, distribution 1.311ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.438 2.913 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y194 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.052 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.747 4.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y196 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.218 5.017 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.615 5.632 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X113Y194 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.966 10.681 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X113Y194 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C clock pessimism 0.220 10.901 clock uncertainty -0.035 10.866 SLICE_X113Y194 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.773 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3] ------------------------------------------------------------------- required time 10.773 arrival time -5.632 ------------------------------------------------------------------- slack 5.141 Slack (MET) : 5.141ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.719ns (logic 0.357ns (13.130%) route 2.362ns (86.870%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.329ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.364ns = ( 10.681 - 8.317 ) Source Clock Delay (SCD): 2.913ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.438ns (routing 0.723ns, distribution 1.715ns) Clock Net Delay (Destination): 1.966ns (routing 0.655ns, distribution 1.311ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.438 2.913 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y194 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.052 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.747 4.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y196 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.218 5.017 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.615 5.632 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X113Y194 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.966 10.681 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X113Y194 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/C clock pessimism 0.220 10.901 clock uncertainty -0.035 10.866 SLICE_X113Y194 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.773 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4] ------------------------------------------------------------------- required time 10.773 arrival time -5.632 ------------------------------------------------------------------- slack 5.141 Slack (MET) : 5.366ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 2.466ns (logic 0.357ns (14.477%) route 2.109ns (85.523%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.357ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.336ns = ( 10.653 - 8.317 ) Source Clock Delay (SCD): 2.913ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.438ns (routing 0.723ns, distribution 1.715ns) Clock Net Delay (Destination): 1.938ns (routing 0.655ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.438 2.913 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y194 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.052 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.747 4.799 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X111Y196 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.218 5.017 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/O net (fo=15, routed) 0.362 5.379 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X110Y196 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.653 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] SLICE_X110Y196 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/C clock pessimism 0.220 10.873 clock uncertainty -0.035 10.838 SLICE_X110Y196 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.745 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1] ------------------------------------------------------------------- required time 10.745 arrival time -5.379 ------------------------------------------------------------------- slack 5.366 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.146ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.049ns (27.072%) route 0.132ns (72.928%)) Logic Levels: 0 Clock Path Skew: 0.030ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.154ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.171ns Clock Net Delay (Source): 0.835ns (routing 0.315ns, distribution 0.520ns) Clock Net Delay (Destination): 0.989ns (routing 0.355ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.835 0.953 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X112Y194 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y194 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.002 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.132 1.134 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X112Y194 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.154 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X112Y194 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.171 0.983 SLICE_X112Y194 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.988 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.988 arrival time 1.134 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.168ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.241ns (logic 0.049ns (20.332%) route 0.192ns (79.668%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.975ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.857ns (routing 0.315ns, distribution 0.542ns) Clock Net Delay (Destination): 1.008ns (routing 0.355ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.857 0.975 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X113Y190 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y190 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.024 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.192 1.216 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X111Y190 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.173 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X111Y190 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.130 1.043 SLICE_X111Y190 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.048 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.048 arrival time 1.216 ------------------------------------------------------------------- slack 0.168 Slack (MET) : 0.168ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.241ns (logic 0.049ns (20.332%) route 0.192ns (79.668%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.975ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.857ns (routing 0.315ns, distribution 0.542ns) Clock Net Delay (Destination): 1.008ns (routing 0.355ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.857 0.975 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X113Y190 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y190 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.024 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.192 1.216 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X111Y190 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.173 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X111Y190 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.130 1.043 SLICE_X111Y190 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.048 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.048 arrival time 1.216 ------------------------------------------------------------------- slack 0.168 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[37]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.172ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.835ns (routing 0.315ns, distribution 0.520ns) Clock Net Delay (Destination): 1.007ns (routing 0.355ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.835 0.953 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X112Y194 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y194 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.002 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.223 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X113Y192 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[37]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.172 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X113Y192 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[37]/C clock pessimism -0.130 1.042 SLICE_X113Y192 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.047 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[37] ------------------------------------------------------------------- required time -1.047 arrival time 1.223 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[38]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.172ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.835ns (routing 0.315ns, distribution 0.520ns) Clock Net Delay (Destination): 1.007ns (routing 0.355ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.835 0.953 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X112Y194 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y194 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.002 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.223 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X113Y192 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.172 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X113Y192 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[38]/C clock pessimism -0.130 1.042 SLICE_X113Y192 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.047 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[38] ------------------------------------------------------------------- required time -1.047 arrival time 1.223 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.178ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[37]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.275ns (logic 0.049ns (17.818%) route 0.226ns (82.182%)) Logic Levels: 0 Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.175ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.835ns (routing 0.315ns, distribution 0.520ns) Clock Net Delay (Destination): 1.010ns (routing 0.355ns, distribution 0.655ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.835 0.953 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X112Y194 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y194 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.002 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.226 1.228 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X114Y192 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[37]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.175 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X114Y192 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[37]/C clock pessimism -0.130 1.045 SLICE_X114Y192 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.050 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[37] ------------------------------------------------------------------- required time -1.050 arrival time 1.228 ------------------------------------------------------------------- slack 0.178 Slack (MET) : 0.178ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[38]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.275ns (logic 0.049ns (17.818%) route 0.226ns (82.182%)) Logic Levels: 0 Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.175ns Source Clock Delay (SCD): 0.953ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.835ns (routing 0.315ns, distribution 0.520ns) Clock Net Delay (Destination): 1.010ns (routing 0.355ns, distribution 0.655ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.835 0.953 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X112Y194 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y194 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.002 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.226 1.228 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X114Y192 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.010 1.175 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X114Y192 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[38]/C clock pessimism -0.130 1.045 SLICE_X114Y192 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.050 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[38] ------------------------------------------------------------------- required time -1.050 arrival time 1.228 ------------------------------------------------------------------- slack 0.178 Slack (MET) : 0.186ns (arrival time - required time) Source: SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.156ns Source Clock Delay (SCD): 0.952ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.834ns (routing 0.315ns, distribution 0.519ns) Clock Net Delay (Destination): 0.991ns (routing 0.355ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.834 0.952 SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y184 FDPE r SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y184 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.000 f SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.217 1.217 SFP_GEN[8].ngCCM_gbt/sync_m_reg[3][0] SLICE_X109Y185 FDCE f SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.156 SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y185 FDCE r SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[80]/C clock pessimism -0.130 1.026 SLICE_X109Y185 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.031 SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[80] ------------------------------------------------------------------- required time -1.031 arrival time 1.217 ------------------------------------------------------------------- slack 0.186 Slack (MET) : 0.186ns (arrival time - required time) Source: SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.156ns Source Clock Delay (SCD): 0.952ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.834ns (routing 0.315ns, distribution 0.519ns) Clock Net Delay (Destination): 0.991ns (routing 0.355ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.834 0.952 SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y184 FDPE r SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y184 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.000 f SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.217 1.217 SFP_GEN[8].ngCCM_gbt/sync_m_reg[3][0] SLICE_X109Y185 FDCE f SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.156 SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y185 FDCE r SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[81]/C clock pessimism -0.130 1.026 SLICE_X109Y185 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.031 SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[81] ------------------------------------------------------------------- required time -1.031 arrival time 1.217 ------------------------------------------------------------------- slack 0.186 Slack (MET) : 0.186ns (arrival time - required time) Source: SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[82]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.156ns Source Clock Delay (SCD): 0.952ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.834ns (routing 0.315ns, distribution 0.519ns) Clock Net Delay (Destination): 0.991ns (routing 0.355ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.834 0.952 SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X108Y184 FDPE r SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y184 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.000 f SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.217 1.217 SFP_GEN[8].ngCCM_gbt/sync_m_reg[3][0] SLICE_X109Y185 FDCE f SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[82]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.156 SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y185 FDCE r SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[82]/C clock pessimism -0.130 1.026 SLICE_X109Y185 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.031 SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[82] ------------------------------------------------------------------- required time -1.031 arrival time 1.217 ------------------------------------------------------------------- slack 0.186 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_11 To Clock: gtwiz_userclk_rx_srcclk_out[0]_11 Setup : 0 Failing Endpoints, Worst Slack 4.913ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.154ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.913ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.946ns (logic 0.285ns (9.674%) route 2.661ns (90.326%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.330ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.320ns = ( 10.637 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.396ns (routing 0.728ns, distribution 1.668ns) Clock Net Delay (Destination): 1.922ns (routing 0.660ns, distribution 1.262ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.396 2.871 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y207 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y207 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.951 4.961 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X99Y210 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.107 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.710 5.817 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X98Y211 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.922 10.637 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X98Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C clock pessimism 0.221 10.858 clock uncertainty -0.035 10.823 SLICE_X98Y211 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.730 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1] ------------------------------------------------------------------- required time 10.730 arrival time -5.817 ------------------------------------------------------------------- slack 4.913 Slack (MET) : 4.913ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.946ns (logic 0.285ns (9.674%) route 2.661ns (90.326%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.330ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.320ns = ( 10.637 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.396ns (routing 0.728ns, distribution 1.668ns) Clock Net Delay (Destination): 1.922ns (routing 0.660ns, distribution 1.262ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.396 2.871 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y207 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y207 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.951 4.961 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X99Y210 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.107 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.710 5.817 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X98Y211 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.922 10.637 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X98Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/C clock pessimism 0.221 10.858 clock uncertainty -0.035 10.823 SLICE_X98Y211 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.730 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2] ------------------------------------------------------------------- required time 10.730 arrival time -5.817 ------------------------------------------------------------------- slack 4.913 Slack (MET) : 4.913ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.946ns (logic 0.285ns (9.674%) route 2.661ns (90.326%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.330ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.320ns = ( 10.637 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.396ns (routing 0.728ns, distribution 1.668ns) Clock Net Delay (Destination): 1.922ns (routing 0.660ns, distribution 1.262ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.396 2.871 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y207 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y207 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.951 4.961 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X99Y210 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.107 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.710 5.817 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X98Y211 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.922 10.637 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X98Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/C clock pessimism 0.221 10.858 clock uncertainty -0.035 10.823 SLICE_X98Y211 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.730 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3] ------------------------------------------------------------------- required time 10.730 arrival time -5.817 ------------------------------------------------------------------- slack 4.913 Slack (MET) : 4.918ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.945ns (logic 0.285ns (9.677%) route 2.660ns (90.323%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.326ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.324ns = ( 10.641 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.396ns (routing 0.728ns, distribution 1.668ns) Clock Net Delay (Destination): 1.926ns (routing 0.660ns, distribution 1.266ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.396 2.871 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y207 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y207 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.951 4.961 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X99Y210 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.107 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.709 5.816 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X97Y211 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.641 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X97Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/C clock pessimism 0.221 10.862 clock uncertainty -0.035 10.827 SLICE_X97Y211 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.734 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4] ------------------------------------------------------------------- required time 10.734 arrival time -5.816 ------------------------------------------------------------------- slack 4.918 Slack (MET) : 4.918ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.945ns (logic 0.285ns (9.677%) route 2.660ns (90.323%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.326ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.324ns = ( 10.641 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.396ns (routing 0.728ns, distribution 1.668ns) Clock Net Delay (Destination): 1.926ns (routing 0.660ns, distribution 1.266ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.396 2.871 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y207 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y207 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.951 4.961 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X99Y210 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.107 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.709 5.816 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X97Y211 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.641 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X97Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/C clock pessimism 0.221 10.862 clock uncertainty -0.035 10.827 SLICE_X97Y211 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.734 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5] ------------------------------------------------------------------- required time 10.734 arrival time -5.816 ------------------------------------------------------------------- slack 4.918 Slack (MET) : 4.918ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.945ns (logic 0.285ns (9.677%) route 2.660ns (90.323%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.326ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.324ns = ( 10.641 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.396ns (routing 0.728ns, distribution 1.668ns) Clock Net Delay (Destination): 1.926ns (routing 0.660ns, distribution 1.266ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.396 2.871 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y207 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y207 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.951 4.961 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X99Y210 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.107 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.709 5.816 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X97Y211 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.641 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X97Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/C clock pessimism 0.221 10.862 clock uncertainty -0.035 10.827 SLICE_X97Y211 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.734 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6] ------------------------------------------------------------------- required time 10.734 arrival time -5.816 ------------------------------------------------------------------- slack 4.918 Slack (MET) : 4.918ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.945ns (logic 0.285ns (9.677%) route 2.660ns (90.323%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.326ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.324ns = ( 10.641 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.396ns (routing 0.728ns, distribution 1.668ns) Clock Net Delay (Destination): 1.926ns (routing 0.660ns, distribution 1.266ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.396 2.871 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y207 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y207 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.951 4.961 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X99Y210 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.107 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.709 5.816 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X97Y211 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.641 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X97Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/C clock pessimism 0.221 10.862 clock uncertainty -0.035 10.827 SLICE_X97Y211 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.734 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7] ------------------------------------------------------------------- required time 10.734 arrival time -5.816 ------------------------------------------------------------------- slack 4.918 Slack (MET) : 4.921ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.936ns (logic 0.285ns (9.707%) route 2.651ns (90.293%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.332ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.318ns = ( 10.635 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.396ns (routing 0.728ns, distribution 1.668ns) Clock Net Delay (Destination): 1.920ns (routing 0.660ns, distribution 1.260ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.396 2.871 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y207 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y207 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.951 4.961 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X99Y210 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.107 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.700 5.807 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X98Y211 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.920 10.635 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X98Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C clock pessimism 0.221 10.856 clock uncertainty -0.035 10.821 SLICE_X98Y211 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.728 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0] ------------------------------------------------------------------- required time 10.728 arrival time -5.807 ------------------------------------------------------------------- slack 4.921 Slack (MET) : 4.921ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.936ns (logic 0.285ns (9.707%) route 2.651ns (90.293%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.332ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.318ns = ( 10.635 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.396ns (routing 0.728ns, distribution 1.668ns) Clock Net Delay (Destination): 1.920ns (routing 0.660ns, distribution 1.260ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.396 2.871 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y207 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y207 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.951 4.961 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X99Y210 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.107 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.700 5.807 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X98Y211 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.920 10.635 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X98Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/C clock pessimism 0.221 10.856 clock uncertainty -0.035 10.821 SLICE_X98Y211 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.728 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0] ------------------------------------------------------------------- required time 10.728 arrival time -5.807 ------------------------------------------------------------------- slack 4.921 Slack (MET) : 4.921ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 2.936ns (logic 0.285ns (9.707%) route 2.651ns (90.293%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.332ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.318ns = ( 10.635 - 8.317 ) Source Clock Delay (SCD): 2.871ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.396ns (routing 0.728ns, distribution 1.668ns) Clock Net Delay (Destination): 1.920ns (routing 0.660ns, distribution 1.260ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.396 2.871 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X137Y207 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X137Y207 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.010 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.951 4.961 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X99Y210 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.107 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/O net (fo=15, routed) 0.700 5.807 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X98Y211 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.920 10.635 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] SLICE_X98Y211 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/C clock pessimism 0.221 10.856 clock uncertainty -0.035 10.821 SLICE_X98Y211 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 10.728 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5] ------------------------------------------------------------------- required time 10.728 arrival time -5.807 ------------------------------------------------------------------- slack 4.921 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.154ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.131ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.815ns (routing 0.314ns, distribution 0.501ns) Clock Net Delay (Destination): 0.966ns (routing 0.355ns, distribution 0.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X100Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X100Y201 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.176 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X99Y200 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.966 1.131 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X99Y200 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.132 0.999 SLICE_X99Y200 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.004 arrival time 1.158 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.154ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.131ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.815ns (routing 0.314ns, distribution 0.501ns) Clock Net Delay (Destination): 0.966ns (routing 0.355ns, distribution 0.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X100Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X100Y201 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.176 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X99Y200 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.966 1.131 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X99Y200 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.132 0.999 SLICE_X99Y200 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.004 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.004 arrival time 1.158 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.171ns (arrival time - required time) Source: SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[9].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.048ns (22.967%) route 0.161ns (77.033%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.121ns Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.166ns Clock Net Delay (Source): 0.804ns (routing 0.314ns, distribution 0.490ns) Clock Net Delay (Destination): 0.956ns (routing 0.355ns, distribution 0.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.804 0.922 SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y208 FDPE r SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X96Y208 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 0.970 f SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.161 1.131 SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] SLICE_X96Y209 FDCE f SFP_GEN[9].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.956 1.121 SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X96Y209 FDCE r SFP_GEN[9].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.166 0.955 SLICE_X96Y209 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.960 SFP_GEN[9].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -0.960 arrival time 1.131 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.174ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.049ns (22.072%) route 0.173ns (77.928%)) Logic Levels: 0 Clock Path Skew: 0.043ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.139ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.815ns (routing 0.314ns, distribution 0.501ns) Clock Net Delay (Destination): 0.974ns (routing 0.355ns, distribution 0.619ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X100Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X100Y201 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.173 1.155 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X100Y199 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.139 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/CLK SLICE_X100Y199 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.163 0.976 SLICE_X100Y199 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.981 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -0.981 arrival time 1.155 ------------------------------------------------------------------- slack 0.174 Slack (MET) : 0.175ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.141ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.163ns Clock Net Delay (Source): 0.815ns (routing 0.314ns, distribution 0.501ns) Clock Net Delay (Destination): 0.976ns (routing 0.355ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X100Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X100Y201 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.176 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X100Y199 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.976 1.141 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/CLK SLICE_X100Y199 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.163 0.978 SLICE_X100Y199 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 0.983 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -0.983 arrival time 1.158 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.185ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.276ns (logic 0.049ns (17.754%) route 0.227ns (82.246%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.815ns (routing 0.314ns, distribution 0.501ns) Clock Net Delay (Destination): 0.986ns (routing 0.355ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X100Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X100Y201 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.227 1.209 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X98Y201 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X98Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.132 1.019 SLICE_X98Y201 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.024 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.024 arrival time 1.209 ------------------------------------------------------------------- slack 0.185 Slack (MET) : 0.185ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.276ns (logic 0.049ns (17.754%) route 0.227ns (82.246%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.815ns (routing 0.314ns, distribution 0.501ns) Clock Net Delay (Destination): 0.986ns (routing 0.355ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X100Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X100Y201 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.227 1.209 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X98Y201 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X98Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.132 1.019 SLICE_X98Y201 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.024 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.024 arrival time 1.209 ------------------------------------------------------------------- slack 0.185 Slack (MET) : 0.185ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.276ns (logic 0.049ns (17.754%) route 0.227ns (82.246%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.815ns (routing 0.314ns, distribution 0.501ns) Clock Net Delay (Destination): 0.986ns (routing 0.355ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X100Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X100Y201 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.227 1.209 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X98Y201 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X98Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.132 1.019 SLICE_X98Y201 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.024 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.024 arrival time 1.209 ------------------------------------------------------------------- slack 0.185 Slack (MET) : 0.185ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.276ns (logic 0.049ns (17.754%) route 0.227ns (82.246%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.815ns (routing 0.314ns, distribution 0.501ns) Clock Net Delay (Destination): 0.986ns (routing 0.355ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X100Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X100Y201 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.227 1.209 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X98Y201 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X98Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.132 1.019 SLICE_X98Y201 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.024 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.024 arrival time 1.209 ------------------------------------------------------------------- slack 0.185 Slack (MET) : 0.185ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns) Data Path Delay: 0.276ns (logic 0.049ns (17.754%) route 0.227ns (82.246%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.815ns (routing 0.314ns, distribution 0.501ns) Clock Net Delay (Destination): 0.986ns (routing 0.355ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.815 0.933 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X100Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X100Y201 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.982 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.227 1.209 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X98Y201 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X98Y201 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.132 1.019 SLICE_X98Y201 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.024 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.024 arrival time 1.209 ------------------------------------------------------------------- slack 0.185 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_12 To Clock: gtwiz_userclk_rx_srcclk_out[0]_12 Setup : 0 Failing Endpoints, Worst Slack 4.286ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.138ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.286ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.685ns (logic 0.383ns (10.393%) route 3.302ns (89.607%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.255ns = ( 11.572 - 8.317 ) Source Clock Delay (SCD): 3.648ns Clock Pessimism Removal (CPR): 0.175ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.173ns (routing 1.143ns, distribution 2.030ns) Clock Net Delay (Destination): 2.857ns (routing 1.045ns, distribution 1.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.173 3.648 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y429 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.787 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 6.402 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y420 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.646 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.687 7.333 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X81Y417 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.857 11.572 g_gbt_bank[1].gbtbank/CLK SLICE_X81Y417 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/C clock pessimism 0.175 11.747 clock uncertainty -0.035 11.712 SLICE_X81Y417 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.619 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4] ------------------------------------------------------------------- required time 11.619 arrival time -7.333 ------------------------------------------------------------------- slack 4.286 Slack (MET) : 4.286ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.685ns (logic 0.383ns (10.393%) route 3.302ns (89.607%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.255ns = ( 11.572 - 8.317 ) Source Clock Delay (SCD): 3.648ns Clock Pessimism Removal (CPR): 0.175ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.173ns (routing 1.143ns, distribution 2.030ns) Clock Net Delay (Destination): 2.857ns (routing 1.045ns, distribution 1.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.173 3.648 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y429 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.787 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 6.402 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y420 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.646 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.687 7.333 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X81Y417 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.857 11.572 g_gbt_bank[1].gbtbank/CLK SLICE_X81Y417 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/C clock pessimism 0.175 11.747 clock uncertainty -0.035 11.712 SLICE_X81Y417 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.619 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6] ------------------------------------------------------------------- required time 11.619 arrival time -7.333 ------------------------------------------------------------------- slack 4.286 Slack (MET) : 4.286ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.685ns (logic 0.383ns (10.393%) route 3.302ns (89.607%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.255ns = ( 11.572 - 8.317 ) Source Clock Delay (SCD): 3.648ns Clock Pessimism Removal (CPR): 0.175ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.173ns (routing 1.143ns, distribution 2.030ns) Clock Net Delay (Destination): 2.857ns (routing 1.045ns, distribution 1.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.173 3.648 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y429 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.787 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 6.402 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y420 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.646 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.687 7.333 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X81Y417 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.857 11.572 g_gbt_bank[1].gbtbank/CLK SLICE_X81Y417 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/C clock pessimism 0.175 11.747 clock uncertainty -0.035 11.712 SLICE_X81Y417 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.619 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7] ------------------------------------------------------------------- required time 11.619 arrival time -7.333 ------------------------------------------------------------------- slack 4.286 Slack (MET) : 4.294ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.675ns (logic 0.383ns (10.422%) route 3.292ns (89.578%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.253ns = ( 11.570 - 8.317 ) Source Clock Delay (SCD): 3.648ns Clock Pessimism Removal (CPR): 0.175ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.173ns (routing 1.143ns, distribution 2.030ns) Clock Net Delay (Destination): 2.855ns (routing 1.045ns, distribution 1.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.173 3.648 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y429 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.787 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 6.402 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y420 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.646 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.677 7.323 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X81Y417 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.855 11.570 g_gbt_bank[1].gbtbank/CLK SLICE_X81Y417 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/C clock pessimism 0.175 11.745 clock uncertainty -0.035 11.710 SLICE_X81Y417 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.617 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3] ------------------------------------------------------------------- required time 11.617 arrival time -7.323 ------------------------------------------------------------------- slack 4.294 Slack (MET) : 4.294ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.675ns (logic 0.383ns (10.422%) route 3.292ns (89.578%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.253ns = ( 11.570 - 8.317 ) Source Clock Delay (SCD): 3.648ns Clock Pessimism Removal (CPR): 0.175ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.173ns (routing 1.143ns, distribution 2.030ns) Clock Net Delay (Destination): 2.855ns (routing 1.045ns, distribution 1.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.173 3.648 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y429 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.787 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 6.402 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y420 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.646 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.677 7.323 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X81Y417 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.855 11.570 g_gbt_bank[1].gbtbank/CLK SLICE_X81Y417 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/C clock pessimism 0.175 11.745 clock uncertainty -0.035 11.710 SLICE_X81Y417 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.617 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5] ------------------------------------------------------------------- required time 11.617 arrival time -7.323 ------------------------------------------------------------------- slack 4.294 Slack (MET) : 4.439ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.532ns (logic 0.383ns (10.844%) route 3.149ns (89.156%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.255ns = ( 11.572 - 8.317 ) Source Clock Delay (SCD): 3.648ns Clock Pessimism Removal (CPR): 0.175ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.173ns (routing 1.143ns, distribution 2.030ns) Clock Net Delay (Destination): 2.857ns (routing 1.045ns, distribution 1.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.173 3.648 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y429 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.787 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 6.402 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y420 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.646 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.534 7.180 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X81Y418 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.857 11.572 g_gbt_bank[1].gbtbank/CLK SLICE_X81Y418 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/C clock pessimism 0.175 11.747 clock uncertainty -0.035 11.712 SLICE_X81Y418 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.619 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1] ------------------------------------------------------------------- required time 11.619 arrival time -7.180 ------------------------------------------------------------------- slack 4.439 Slack (MET) : 4.439ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.532ns (logic 0.383ns (10.844%) route 3.149ns (89.156%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.218ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.255ns = ( 11.572 - 8.317 ) Source Clock Delay (SCD): 3.648ns Clock Pessimism Removal (CPR): 0.175ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.173ns (routing 1.143ns, distribution 2.030ns) Clock Net Delay (Destination): 2.857ns (routing 1.045ns, distribution 1.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.173 3.648 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y429 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.787 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 6.402 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y420 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.646 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.534 7.180 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X81Y418 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.857 11.572 g_gbt_bank[1].gbtbank/CLK SLICE_X81Y418 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/C clock pessimism 0.175 11.747 clock uncertainty -0.035 11.712 SLICE_X81Y418 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.619 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2] ------------------------------------------------------------------- required time 11.619 arrival time -7.180 ------------------------------------------------------------------- slack 4.439 Slack (MET) : 4.447ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.522ns (logic 0.383ns (10.875%) route 3.139ns (89.126%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.253ns = ( 11.570 - 8.317 ) Source Clock Delay (SCD): 3.648ns Clock Pessimism Removal (CPR): 0.175ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.173ns (routing 1.143ns, distribution 2.030ns) Clock Net Delay (Destination): 2.855ns (routing 1.045ns, distribution 1.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.173 3.648 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y429 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.787 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 6.402 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y420 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.646 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.524 7.170 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X81Y418 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.855 11.570 g_gbt_bank[1].gbtbank/CLK SLICE_X81Y418 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C clock pessimism 0.175 11.745 clock uncertainty -0.035 11.710 SLICE_X81Y418 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.617 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0] ------------------------------------------------------------------- required time 11.617 arrival time -7.170 ------------------------------------------------------------------- slack 4.447 Slack (MET) : 4.447ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.522ns (logic 0.383ns (10.875%) route 3.139ns (89.126%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.253ns = ( 11.570 - 8.317 ) Source Clock Delay (SCD): 3.648ns Clock Pessimism Removal (CPR): 0.175ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.173ns (routing 1.143ns, distribution 2.030ns) Clock Net Delay (Destination): 2.855ns (routing 1.045ns, distribution 1.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.173 3.648 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y429 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.787 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 6.402 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y420 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.646 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.524 7.170 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X81Y418 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.855 11.570 g_gbt_bank[1].gbtbank/CLK SLICE_X81Y418 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/C clock pessimism 0.175 11.745 clock uncertainty -0.035 11.710 SLICE_X81Y418 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 11.617 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0] ------------------------------------------------------------------- required time 11.617 arrival time -7.170 ------------------------------------------------------------------- slack 4.447 Slack (MET) : 4.447ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 3.522ns (logic 0.383ns (10.875%) route 3.139ns (89.126%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.253ns = ( 11.570 - 8.317 ) Source Clock Delay (SCD): 3.648ns Clock Pessimism Removal (CPR): 0.175ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.173ns (routing 1.143ns, distribution 2.030ns) Clock Net Delay (Destination): 2.855ns (routing 1.045ns, distribution 1.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 3.173 3.648 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y429 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y429 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.787 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 6.402 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y420 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 6.646 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/O net (fo=15, routed) 0.524 7.170 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X81Y418 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.855 11.570 g_gbt_bank[1].gbtbank/CLK SLICE_X81Y418 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/C clock pessimism 0.175 11.745 clock uncertainty -0.035 11.710 SLICE_X81Y418 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.617 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0] ------------------------------------------------------------------- required time 11.617 arrival time -7.170 ------------------------------------------------------------------- slack 4.447 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.229ns (logic 0.049ns (21.397%) route 0.180ns (78.603%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.637ns Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.248ns (routing 0.484ns, distribution 0.764ns) Clock Net Delay (Destination): 1.472ns (routing 0.544ns, distribution 0.928ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.248 1.366 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X82Y422 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y422 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.415 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.180 1.595 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X83Y422 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.472 1.637 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y422 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C clock pessimism -0.185 1.452 SLICE_X83Y422 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.457 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg ------------------------------------------------------------------- required time -1.457 arrival time 1.595 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.229ns (logic 0.049ns (21.397%) route 0.180ns (78.603%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.637ns Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.248ns (routing 0.484ns, distribution 0.764ns) Clock Net Delay (Destination): 1.472ns (routing 0.544ns, distribution 0.928ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.248 1.366 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X82Y422 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y422 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.415 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.180 1.595 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X83Y422 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.472 1.637 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y422 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[36]/C clock pessimism -0.185 1.452 SLICE_X83Y422 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.457 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[36] ------------------------------------------------------------------- required time -1.457 arrival time 1.595 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.139ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.049ns (21.121%) route 0.183ns (78.879%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.639ns Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.248ns (routing 0.484ns, distribution 0.764ns) Clock Net Delay (Destination): 1.474ns (routing 0.544ns, distribution 0.930ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.248 1.366 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X82Y422 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y422 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.415 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.183 1.598 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X83Y422 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.474 1.639 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y422 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C clock pessimism -0.185 1.454 SLICE_X83Y422 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.459 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] ------------------------------------------------------------------- required time -1.459 arrival time 1.598 ------------------------------------------------------------------- slack 0.139 Slack (MET) : 0.139ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.049ns (21.121%) route 0.183ns (78.879%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.639ns Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.248ns (routing 0.484ns, distribution 0.764ns) Clock Net Delay (Destination): 1.474ns (routing 0.544ns, distribution 0.930ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.248 1.366 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X82Y422 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y422 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.415 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.183 1.598 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X83Y422 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.474 1.639 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y422 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C clock pessimism -0.185 1.454 SLICE_X83Y422 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.459 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] ------------------------------------------------------------------- required time -1.459 arrival time 1.598 ------------------------------------------------------------------- slack 0.139 Slack (MET) : 0.139ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.049ns (21.121%) route 0.183ns (78.879%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.639ns Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.248ns (routing 0.484ns, distribution 0.764ns) Clock Net Delay (Destination): 1.474ns (routing 0.544ns, distribution 0.930ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.248 1.366 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X82Y422 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y422 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.415 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.183 1.598 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X83Y422 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.474 1.639 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y422 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C clock pessimism -0.185 1.454 SLICE_X83Y422 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.459 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] ------------------------------------------------------------------- required time -1.459 arrival time 1.598 ------------------------------------------------------------------- slack 0.139 Slack (MET) : 0.139ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.049ns (21.121%) route 0.183ns (78.879%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.639ns Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.248ns (routing 0.484ns, distribution 0.764ns) Clock Net Delay (Destination): 1.474ns (routing 0.544ns, distribution 0.930ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.248 1.366 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X82Y422 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y422 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.415 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.183 1.598 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X83Y422 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.474 1.639 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X83Y422 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[36]/C clock pessimism -0.185 1.454 SLICE_X83Y422 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.459 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[36] ------------------------------------------------------------------- required time -1.459 arrival time 1.598 ------------------------------------------------------------------- slack 0.139 Slack (MET) : 0.139ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.228ns (logic 0.049ns (21.491%) route 0.179ns (78.509%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.635ns Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.248ns (routing 0.484ns, distribution 0.764ns) Clock Net Delay (Destination): 1.470ns (routing 0.544ns, distribution 0.926ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.248 1.366 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X82Y422 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y422 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.415 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.179 1.594 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X84Y422 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.470 1.635 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y422 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[32]/C clock pessimism -0.185 1.450 SLICE_X84Y422 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.455 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[32] ------------------------------------------------------------------- required time -1.455 arrival time 1.594 ------------------------------------------------------------------- slack 0.139 Slack (MET) : 0.139ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.228ns (logic 0.049ns (21.491%) route 0.179ns (78.509%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.635ns Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.185ns Clock Net Delay (Source): 1.248ns (routing 0.484ns, distribution 0.764ns) Clock Net Delay (Destination): 1.470ns (routing 0.544ns, distribution 0.926ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.248 1.366 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X82Y422 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y422 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.415 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.179 1.594 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X84Y422 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.470 1.635 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X84Y422 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[32]/C clock pessimism -0.185 1.450 SLICE_X84Y422 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.455 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[32] ------------------------------------------------------------------- required time -1.455 arrival time 1.594 ------------------------------------------------------------------- slack 0.139 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.211ns (logic 0.049ns (23.223%) route 0.162ns (76.777%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.618ns Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.186ns Clock Net Delay (Source): 1.248ns (routing 0.484ns, distribution 0.764ns) Clock Net Delay (Destination): 1.453ns (routing 0.544ns, distribution 0.909ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.248 1.366 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X82Y422 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X82Y422 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.415 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.162 1.577 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X81Y421 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.453 1.618 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y421 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.186 1.432 SLICE_X81Y421 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.437 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.437 arrival time 1.577 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.167ns (arrival time - required time) Source: SFP_GEN[12].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[12].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns) Data Path Delay: 0.219ns (logic 0.048ns (21.918%) route 0.171ns (78.082%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.610ns Source Clock Delay (SCD): 1.352ns Clock Pessimism Removal (CPR): 0.211ns Clock Net Delay (Source): 1.234ns (routing 0.484ns, distribution 0.750ns) Clock Net Delay (Destination): 1.445ns (routing 0.544ns, distribution 0.901ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.352 SFP_GEN[12].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y417 FDPE r SFP_GEN[12].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y417 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.400 f SFP_GEN[12].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.171 1.571 SFP_GEN[12].ngCCM_gbt/sync_m_reg[3][0] SLICE_X80Y416 FDCE f SFP_GEN[12].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.445 1.610 SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y416 FDCE r SFP_GEN[12].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.211 1.399 SLICE_X80Y416 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.404 SFP_GEN[12].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.404 arrival time 1.571 ------------------------------------------------------------------- slack 0.167 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_13 To Clock: gtwiz_userclk_rx_srcclk_out[0]_13 Setup : 0 Failing Endpoints, Worst Slack 3.923ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.142ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.923ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.162ns (logic 0.377ns (9.058%) route 3.785ns (90.942%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.104ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.619ns = ( 10.936 - 8.317 ) Source Clock Delay (SCD): 2.945ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.470ns (routing 0.723ns, distribution 1.747ns) Clock Net Delay (Destination): 2.221ns (routing 0.658ns, distribution 1.563ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.470 2.945 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y572 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y572 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.084 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.692 5.776 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X98Y540 LUT2 (Prop_H6LUT_SLICEL_I0_O) 0.238 6.014 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__21/O net (fo=2, routed) 1.093 7.107 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X94Y540 FDCE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.221 10.936 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK SLICE_X94Y540 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.222 11.158 clock uncertainty -0.035 11.123 SLICE_X94Y540 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.030 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.030 arrival time -7.107 ------------------------------------------------------------------- slack 3.923 Slack (MET) : 3.923ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 4.162ns (logic 0.377ns (9.058%) route 3.785ns (90.942%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.104ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.619ns = ( 10.936 - 8.317 ) Source Clock Delay (SCD): 2.945ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.470ns (routing 0.723ns, distribution 1.747ns) Clock Net Delay (Destination): 2.221ns (routing 0.658ns, distribution 1.563ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.470 2.945 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y572 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y572 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.084 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.692 5.776 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X98Y540 LUT2 (Prop_H6LUT_SLICEL_I0_O) 0.238 6.014 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__21/O net (fo=2, routed) 1.093 7.107 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X94Y540 FDCE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.221 10.936 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK SLICE_X94Y540 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.222 11.158 clock uncertainty -0.035 11.123 SLICE_X94Y540 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.030 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.030 arrival time -7.107 ------------------------------------------------------------------- slack 3.923 Slack (MET) : 3.975ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 3.789ns (logic 0.229ns (6.044%) route 3.560ns (93.956%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.425ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.305ns = ( 10.622 - 8.317 ) Source Clock Delay (SCD): 2.945ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.470ns (routing 0.723ns, distribution 1.747ns) Clock Net Delay (Destination): 1.907ns (routing 0.658ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.470 2.945 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y572 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y572 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.084 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.781 5.865 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X98Y541 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 5.955 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 0.779 6.734 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X96Y547 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.907 10.622 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X96Y547 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C clock pessimism 0.215 10.837 clock uncertainty -0.035 10.802 SLICE_X96Y547 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.709 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2] ------------------------------------------------------------------- required time 10.709 arrival time -6.734 ------------------------------------------------------------------- slack 3.975 Slack (MET) : 3.975ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 3.789ns (logic 0.229ns (6.044%) route 3.560ns (93.956%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.425ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.305ns = ( 10.622 - 8.317 ) Source Clock Delay (SCD): 2.945ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.470ns (routing 0.723ns, distribution 1.747ns) Clock Net Delay (Destination): 1.907ns (routing 0.658ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.470 2.945 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y572 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y572 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.084 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.781 5.865 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X98Y541 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 5.955 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 0.779 6.734 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X96Y547 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.907 10.622 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X96Y547 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C clock pessimism 0.215 10.837 clock uncertainty -0.035 10.802 SLICE_X96Y547 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.709 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3] ------------------------------------------------------------------- required time 10.709 arrival time -6.734 ------------------------------------------------------------------- slack 3.975 Slack (MET) : 3.975ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 3.789ns (logic 0.229ns (6.044%) route 3.560ns (93.956%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.425ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.305ns = ( 10.622 - 8.317 ) Source Clock Delay (SCD): 2.945ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.470ns (routing 0.723ns, distribution 1.747ns) Clock Net Delay (Destination): 1.907ns (routing 0.658ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.470 2.945 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y572 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y572 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.084 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.781 5.865 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X98Y541 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 5.955 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 0.779 6.734 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X96Y547 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.907 10.622 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X96Y547 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C clock pessimism 0.215 10.837 clock uncertainty -0.035 10.802 SLICE_X96Y547 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.709 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6] ------------------------------------------------------------------- required time 10.709 arrival time -6.734 ------------------------------------------------------------------- slack 3.975 Slack (MET) : 3.975ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 3.789ns (logic 0.229ns (6.044%) route 3.560ns (93.956%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.425ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.305ns = ( 10.622 - 8.317 ) Source Clock Delay (SCD): 2.945ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.470ns (routing 0.723ns, distribution 1.747ns) Clock Net Delay (Destination): 1.907ns (routing 0.658ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.470 2.945 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y572 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y572 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.084 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.781 5.865 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X98Y541 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 5.955 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 0.779 6.734 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X96Y547 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.907 10.622 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X96Y547 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C clock pessimism 0.215 10.837 clock uncertainty -0.035 10.802 SLICE_X96Y547 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.709 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7] ------------------------------------------------------------------- required time 10.709 arrival time -6.734 ------------------------------------------------------------------- slack 3.975 Slack (MET) : 3.983ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 3.779ns (logic 0.229ns (6.060%) route 3.550ns (93.940%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.427ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.303ns = ( 10.620 - 8.317 ) Source Clock Delay (SCD): 2.945ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.470ns (routing 0.723ns, distribution 1.747ns) Clock Net Delay (Destination): 1.905ns (routing 0.658ns, distribution 1.247ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.470 2.945 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y572 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y572 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.084 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.781 5.865 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X98Y541 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 5.955 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 0.769 6.724 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X96Y547 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.905 10.620 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X96Y547 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C clock pessimism 0.215 10.835 clock uncertainty -0.035 10.800 SLICE_X96Y547 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 10.707 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4] ------------------------------------------------------------------- required time 10.707 arrival time -6.724 ------------------------------------------------------------------- slack 3.983 Slack (MET) : 3.983ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 3.779ns (logic 0.229ns (6.060%) route 3.550ns (93.940%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.427ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.303ns = ( 10.620 - 8.317 ) Source Clock Delay (SCD): 2.945ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.470ns (routing 0.723ns, distribution 1.747ns) Clock Net Delay (Destination): 1.905ns (routing 0.658ns, distribution 1.247ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.470 2.945 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y572 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y572 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.084 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.781 5.865 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X98Y541 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 5.955 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 0.769 6.724 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X96Y547 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.905 10.620 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X96Y547 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C clock pessimism 0.215 10.835 clock uncertainty -0.035 10.800 SLICE_X96Y547 FDCE (Recov_FFF_SLICEL_C_CLR) -0.093 10.707 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5] ------------------------------------------------------------------- required time 10.707 arrival time -6.724 ------------------------------------------------------------------- slack 3.983 Slack (MET) : 4.078ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 3.677ns (logic 0.229ns (6.228%) route 3.448ns (93.772%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.434ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.296ns = ( 10.613 - 8.317 ) Source Clock Delay (SCD): 2.945ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.470ns (routing 0.723ns, distribution 1.747ns) Clock Net Delay (Destination): 1.898ns (routing 0.658ns, distribution 1.240ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.470 2.945 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y572 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y572 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.084 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.781 5.865 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X98Y541 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 5.955 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 0.667 6.622 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X96Y543 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.898 10.613 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X96Y543 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C clock pessimism 0.215 10.828 clock uncertainty -0.035 10.793 SLICE_X96Y543 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.700 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1] ------------------------------------------------------------------- required time 10.700 arrival time -6.622 ------------------------------------------------------------------- slack 4.078 Slack (MET) : 4.078ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 3.677ns (logic 0.229ns (6.228%) route 3.448ns (93.772%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.434ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.296ns = ( 10.613 - 8.317 ) Source Clock Delay (SCD): 2.945ns Clock Pessimism Removal (CPR): 0.215ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.470ns (routing 0.723ns, distribution 1.747ns) Clock Net Delay (Destination): 1.898ns (routing 0.658ns, distribution 1.240ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.470 2.945 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y572 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y572 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.084 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.781 5.865 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X98Y541 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.090 5.955 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/O net (fo=15, routed) 0.667 6.622 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X96Y543 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.898 10.613 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X96Y543 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C clock pessimism 0.215 10.828 clock uncertainty -0.035 10.793 SLICE_X96Y543 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.700 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2] ------------------------------------------------------------------- required time 10.700 arrival time -6.622 ------------------------------------------------------------------- slack 4.078 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.186ns (logic 0.049ns (26.344%) route 0.137ns (73.656%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.949ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.831ns (routing 0.318ns, distribution 0.513ns) Clock Net Delay (Destination): 0.997ns (routing 0.359ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.831 0.949 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK SLICE_X97Y544 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X97Y544 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 0.998 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.137 1.135 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X98Y544 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X98Y544 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.174 0.988 SLICE_X98Y544 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 0.993 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.993 arrival time 1.135 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.200ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.267ns (logic 0.048ns (17.978%) route 0.219ns (82.022%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.140ns Source Clock Delay (SCD): 0.948ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.830ns (routing 0.318ns, distribution 0.512ns) Clock Net Delay (Destination): 0.975ns (routing 0.359ns, distribution 0.616ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.830 0.948 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y552 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y552 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.219 1.215 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X100Y550 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.975 1.140 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X100Y550 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.130 1.010 SLICE_X100Y550 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.015 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.015 arrival time 1.215 ------------------------------------------------------------------- slack 0.200 Slack (MET) : 0.222ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.285ns (logic 0.048ns (16.842%) route 0.237ns (83.158%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.136ns Source Clock Delay (SCD): 0.948ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.830ns (routing 0.318ns, distribution 0.512ns) Clock Net Delay (Destination): 0.971ns (routing 0.359ns, distribution 0.612ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.830 0.948 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y552 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y552 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.237 1.233 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X97Y552 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.971 1.136 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X97Y552 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.130 1.006 SLICE_X97Y552 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.011 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.011 arrival time 1.233 ------------------------------------------------------------------- slack 0.222 Slack (MET) : 0.236ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.268ns (logic 0.048ns (17.910%) route 0.220ns (82.090%)) Logic Levels: 0 Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.137ns Source Clock Delay (SCD): 0.948ns Clock Pessimism Removal (CPR): 0.162ns Clock Net Delay (Source): 0.830ns (routing 0.318ns, distribution 0.512ns) Clock Net Delay (Destination): 0.972ns (routing 0.359ns, distribution 0.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.830 0.948 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y552 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y552 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.220 1.216 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X102Y553 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.137 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X102Y553 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.162 0.975 SLICE_X102Y553 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.980 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -0.980 arrival time 1.216 ------------------------------------------------------------------- slack 0.236 Slack (MET) : 0.237ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.048ns (17.778%) route 0.222ns (82.222%)) Logic Levels: 0 Clock Path Skew: 0.028ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.138ns Source Clock Delay (SCD): 0.948ns Clock Pessimism Removal (CPR): 0.162ns Clock Net Delay (Source): 0.830ns (routing 0.318ns, distribution 0.512ns) Clock Net Delay (Destination): 0.973ns (routing 0.359ns, distribution 0.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.830 0.948 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y552 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y552 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.222 1.218 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X102Y551 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.973 1.138 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X102Y551 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.162 0.976 SLICE_X102Y551 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.981 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -0.981 arrival time 1.218 ------------------------------------------------------------------- slack 0.237 Slack (MET) : 0.237ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.048ns (17.778%) route 0.222ns (82.222%)) Logic Levels: 0 Clock Path Skew: 0.028ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.138ns Source Clock Delay (SCD): 0.948ns Clock Pessimism Removal (CPR): 0.162ns Clock Net Delay (Source): 0.830ns (routing 0.318ns, distribution 0.512ns) Clock Net Delay (Destination): 0.973ns (routing 0.359ns, distribution 0.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.830 0.948 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y552 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y552 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.222 1.218 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X102Y551 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.973 1.138 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X102Y551 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.162 0.976 SLICE_X102Y551 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 0.981 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -0.981 arrival time 1.218 ------------------------------------------------------------------- slack 0.237 Slack (MET) : 0.240ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.308ns (logic 0.048ns (15.584%) route 0.260ns (84.416%)) Logic Levels: 0 Clock Path Skew: 0.063ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.141ns Source Clock Delay (SCD): 0.948ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.830ns (routing 0.318ns, distribution 0.512ns) Clock Net Delay (Destination): 0.976ns (routing 0.359ns, distribution 0.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.830 0.948 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y552 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y552 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.260 1.256 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X106Y553 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.976 1.141 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK SLICE_X106Y553 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.130 1.011 SLICE_X106Y553 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.016 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.016 arrival time 1.256 ------------------------------------------------------------------- slack 0.240 Slack (MET) : 0.253ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.323ns (logic 0.048ns (14.861%) route 0.275ns (85.139%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.143ns Source Clock Delay (SCD): 0.948ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.830ns (routing 0.318ns, distribution 0.512ns) Clock Net Delay (Destination): 0.978ns (routing 0.359ns, distribution 0.619ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.830 0.948 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y552 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y552 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.275 1.271 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X97Y550 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.143 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X97Y550 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.130 1.013 SLICE_X97Y550 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.018 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.018 arrival time 1.271 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.253ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.323ns (logic 0.048ns (14.861%) route 0.275ns (85.139%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.143ns Source Clock Delay (SCD): 0.948ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.830ns (routing 0.318ns, distribution 0.512ns) Clock Net Delay (Destination): 0.978ns (routing 0.359ns, distribution 0.619ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.830 0.948 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y552 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y552 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.275 1.271 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X97Y550 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.143 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X97Y550 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.130 1.013 SLICE_X97Y550 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.018 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.018 arrival time 1.271 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.253ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns) Data Path Delay: 0.323ns (logic 0.048ns (14.861%) route 0.275ns (85.139%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.143ns Source Clock Delay (SCD): 0.948ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.830ns (routing 0.318ns, distribution 0.512ns) Clock Net Delay (Destination): 0.978ns (routing 0.359ns, distribution 0.619ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.830 0.948 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X102Y552 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y552 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.996 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.275 1.271 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X97Y550 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.143 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X97Y550 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.130 1.013 SLICE_X97Y550 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.018 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.018 arrival time 1.271 ------------------------------------------------------------------- slack 0.253 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_14 To Clock: gtwiz_userclk_rx_srcclk_out[0]_14 Setup : 0 Failing Endpoints, Worst Slack 2.177ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.176ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.177ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 5.609ns (logic 0.364ns (6.490%) route 5.245ns (93.510%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.403ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.929ns = ( 11.246 - 8.317 ) Source Clock Delay (SCD): 3.618ns Clock Pessimism Removal (CPR): 0.286ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.143ns (routing 1.148ns, distribution 1.995ns) Clock Net Delay (Destination): 2.531ns (routing 1.049ns, distribution 1.482ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.143 3.618 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y593 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y593 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.713 7.470 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y563 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 7.695 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/O net (fo=15, routed) 1.532 9.227 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X97Y569 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.531 11.246 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X97Y569 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C clock pessimism 0.286 11.532 clock uncertainty -0.035 11.497 SLICE_X97Y569 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.404 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11] ------------------------------------------------------------------- required time 11.404 arrival time -9.227 ------------------------------------------------------------------- slack 2.177 Slack (MET) : 2.183ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 5.602ns (logic 0.364ns (6.498%) route 5.238ns (93.502%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.404ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.928ns = ( 11.245 - 8.317 ) Source Clock Delay (SCD): 3.618ns Clock Pessimism Removal (CPR): 0.286ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.143ns (routing 1.148ns, distribution 1.995ns) Clock Net Delay (Destination): 2.530ns (routing 1.049ns, distribution 1.481ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.143 3.618 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y593 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y593 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.713 7.470 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y563 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 7.695 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/O net (fo=15, routed) 1.525 9.220 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X97Y569 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.530 11.245 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X97Y569 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C clock pessimism 0.286 11.531 clock uncertainty -0.035 11.496 SLICE_X97Y569 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.403 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0] ------------------------------------------------------------------- required time 11.403 arrival time -9.220 ------------------------------------------------------------------- slack 2.183 Slack (MET) : 2.183ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 5.602ns (logic 0.364ns (6.498%) route 5.238ns (93.502%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.404ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.928ns = ( 11.245 - 8.317 ) Source Clock Delay (SCD): 3.618ns Clock Pessimism Removal (CPR): 0.286ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.143ns (routing 1.148ns, distribution 1.995ns) Clock Net Delay (Destination): 2.530ns (routing 1.049ns, distribution 1.481ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.143 3.618 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y593 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y593 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.713 7.470 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y563 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 7.695 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/O net (fo=15, routed) 1.525 9.220 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X97Y569 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.530 11.245 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X97Y569 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C clock pessimism 0.286 11.531 clock uncertainty -0.035 11.496 SLICE_X97Y569 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.403 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4] ------------------------------------------------------------------- required time 11.403 arrival time -9.220 ------------------------------------------------------------------- slack 2.183 Slack (MET) : 2.183ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 5.602ns (logic 0.364ns (6.498%) route 5.238ns (93.502%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.404ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.928ns = ( 11.245 - 8.317 ) Source Clock Delay (SCD): 3.618ns Clock Pessimism Removal (CPR): 0.286ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.143ns (routing 1.148ns, distribution 1.995ns) Clock Net Delay (Destination): 2.530ns (routing 1.049ns, distribution 1.481ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.143 3.618 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y593 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y593 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.713 7.470 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y563 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 7.695 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/O net (fo=15, routed) 1.525 9.220 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X97Y569 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.530 11.245 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X97Y569 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C clock pessimism 0.286 11.531 clock uncertainty -0.035 11.496 SLICE_X97Y569 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 11.403 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5] ------------------------------------------------------------------- required time 11.403 arrival time -9.220 ------------------------------------------------------------------- slack 2.183 Slack (MET) : 2.187ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 5.601ns (logic 0.364ns (6.499%) route 5.237ns (93.501%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.401ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.931ns = ( 11.248 - 8.317 ) Source Clock Delay (SCD): 3.618ns Clock Pessimism Removal (CPR): 0.286ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.143ns (routing 1.148ns, distribution 1.995ns) Clock Net Delay (Destination): 2.533ns (routing 1.049ns, distribution 1.484ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.143 3.618 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y593 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y593 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.713 7.470 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y563 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 7.695 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/O net (fo=15, routed) 1.524 9.219 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X97Y568 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.533 11.248 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X97Y568 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/C clock pessimism 0.286 11.534 clock uncertainty -0.035 11.499 SLICE_X97Y568 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.406 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1] ------------------------------------------------------------------- required time 11.406 arrival time -9.219 ------------------------------------------------------------------- slack 2.187 Slack (MET) : 2.187ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 5.601ns (logic 0.364ns (6.499%) route 5.237ns (93.501%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.401ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.931ns = ( 11.248 - 8.317 ) Source Clock Delay (SCD): 3.618ns Clock Pessimism Removal (CPR): 0.286ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.143ns (routing 1.148ns, distribution 1.995ns) Clock Net Delay (Destination): 2.533ns (routing 1.049ns, distribution 1.484ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.143 3.618 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y593 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y593 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.713 7.470 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y563 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 7.695 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/O net (fo=15, routed) 1.524 9.219 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X97Y568 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.533 11.248 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X97Y568 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/C clock pessimism 0.286 11.534 clock uncertainty -0.035 11.499 SLICE_X97Y568 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.406 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2] ------------------------------------------------------------------- required time 11.406 arrival time -9.219 ------------------------------------------------------------------- slack 2.187 Slack (MET) : 2.187ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 5.601ns (logic 0.364ns (6.499%) route 5.237ns (93.501%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.401ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.931ns = ( 11.248 - 8.317 ) Source Clock Delay (SCD): 3.618ns Clock Pessimism Removal (CPR): 0.286ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.143ns (routing 1.148ns, distribution 1.995ns) Clock Net Delay (Destination): 2.533ns (routing 1.049ns, distribution 1.484ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.143 3.618 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y593 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y593 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.713 7.470 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y563 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 7.695 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/O net (fo=15, routed) 1.524 9.219 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X97Y568 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.533 11.248 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X97Y568 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C clock pessimism 0.286 11.534 clock uncertainty -0.035 11.499 SLICE_X97Y568 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.406 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3] ------------------------------------------------------------------- required time 11.406 arrival time -9.219 ------------------------------------------------------------------- slack 2.187 Slack (MET) : 2.193ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 5.594ns (logic 0.364ns (6.507%) route 5.230ns (93.493%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.402ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.930ns = ( 11.247 - 8.317 ) Source Clock Delay (SCD): 3.618ns Clock Pessimism Removal (CPR): 0.286ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.143ns (routing 1.148ns, distribution 1.995ns) Clock Net Delay (Destination): 2.532ns (routing 1.049ns, distribution 1.483ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.143 3.618 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y593 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y593 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.713 7.470 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y563 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 7.695 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/O net (fo=15, routed) 1.517 9.212 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X97Y568 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.532 11.247 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X97Y568 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C clock pessimism 0.286 11.533 clock uncertainty -0.035 11.498 SLICE_X97Y568 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.405 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6] ------------------------------------------------------------------- required time 11.405 arrival time -9.212 ------------------------------------------------------------------- slack 2.193 Slack (MET) : 2.193ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 5.594ns (logic 0.364ns (6.507%) route 5.230ns (93.493%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.402ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.930ns = ( 11.247 - 8.317 ) Source Clock Delay (SCD): 3.618ns Clock Pessimism Removal (CPR): 0.286ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.143ns (routing 1.148ns, distribution 1.995ns) Clock Net Delay (Destination): 2.532ns (routing 1.049ns, distribution 1.483ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.143 3.618 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y593 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y593 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.713 7.470 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y563 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 7.695 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/O net (fo=15, routed) 1.517 9.212 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X97Y568 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.532 11.247 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X97Y568 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C clock pessimism 0.286 11.533 clock uncertainty -0.035 11.498 SLICE_X97Y568 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 11.405 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7] ------------------------------------------------------------------- required time 11.405 arrival time -9.212 ------------------------------------------------------------------- slack 2.193 Slack (MET) : 2.342ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 5.447ns (logic 0.364ns (6.683%) route 5.083ns (93.317%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.400ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.932ns = ( 11.249 - 8.317 ) Source Clock Delay (SCD): 3.618ns Clock Pessimism Removal (CPR): 0.286ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.143ns (routing 1.148ns, distribution 1.995ns) Clock Net Delay (Destination): 2.534ns (routing 1.049ns, distribution 1.485ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 3.143 3.618 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X138Y593 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X138Y593 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.757 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.713 7.470 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y563 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.225 7.695 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0/O net (fo=15, routed) 1.370 9.065 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X97Y567 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.534 11.249 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X97Y567 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/C clock pessimism 0.286 11.535 clock uncertainty -0.035 11.500 SLICE_X97Y567 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.407 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5] ------------------------------------------------------------------- required time 11.407 arrival time -9.065 ------------------------------------------------------------------- slack 2.342 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.176ns (arrival time - required time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.251ns (logic 0.048ns (19.123%) route 0.203ns (80.876%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.604ns Source Clock Delay (SCD): 1.346ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.228ns (routing 0.485ns, distribution 0.743ns) Clock Net Delay (Destination): 1.439ns (routing 0.546ns, distribution 0.893ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.346 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y554 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y554 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.394 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.203 1.597 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X87Y553 FDCE f SFP_GEN[23].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.439 1.604 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X87Y553 FDCE r SFP_GEN[23].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.188 1.416 SLICE_X87Y553 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.421 SFP_GEN[23].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.421 arrival time 1.597 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.193ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.257ns (logic 0.049ns (19.066%) route 0.208ns (80.934%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.569ns Source Clock Delay (SCD): 1.322ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 1.204ns (routing 0.485ns, distribution 0.719ns) Clock Net Delay (Destination): 1.404ns (routing 0.546ns, distribution 0.858ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.204 1.322 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X94Y566 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X94Y566 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.371 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.208 1.579 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X93Y566 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.404 1.569 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X93Y566 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.188 1.381 SLICE_X93Y566 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.386 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.386 arrival time 1.579 ------------------------------------------------------------------- slack 0.193 Slack (MET) : 0.229ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[113]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.388ns (logic 0.049ns (12.629%) route 0.339ns (87.371%)) Logic Levels: 0 Clock Path Skew: 0.154ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.598ns Source Clock Delay (SCD): 1.336ns Clock Pessimism Removal (CPR): 0.108ns Clock Net Delay (Source): 1.218ns (routing 0.485ns, distribution 0.733ns) Clock Net Delay (Destination): 1.433ns (routing 0.546ns, distribution 0.887ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.336 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X84Y536 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y536 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.385 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.339 1.724 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X87Y565 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[113]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.433 1.598 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X87Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[113]/C clock pessimism -0.108 1.490 SLICE_X87Y565 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.495 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[113] ------------------------------------------------------------------- required time -1.495 arrival time 1.724 ------------------------------------------------------------------- slack 0.229 Slack (MET) : 0.229ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[115]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.388ns (logic 0.049ns (12.629%) route 0.339ns (87.371%)) Logic Levels: 0 Clock Path Skew: 0.154ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.598ns Source Clock Delay (SCD): 1.336ns Clock Pessimism Removal (CPR): 0.108ns Clock Net Delay (Source): 1.218ns (routing 0.485ns, distribution 0.733ns) Clock Net Delay (Destination): 1.433ns (routing 0.546ns, distribution 0.887ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.336 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X84Y536 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y536 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.385 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.339 1.724 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X87Y565 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[115]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.433 1.598 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X87Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[115]/C clock pessimism -0.108 1.490 SLICE_X87Y565 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.495 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[115] ------------------------------------------------------------------- required time -1.495 arrival time 1.724 ------------------------------------------------------------------- slack 0.229 Slack (MET) : 0.230ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[82]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.387ns (logic 0.049ns (12.661%) route 0.338ns (87.339%)) Logic Levels: 0 Clock Path Skew: 0.152ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.596ns Source Clock Delay (SCD): 1.336ns Clock Pessimism Removal (CPR): 0.108ns Clock Net Delay (Source): 1.218ns (routing 0.485ns, distribution 0.733ns) Clock Net Delay (Destination): 1.431ns (routing 0.546ns, distribution 0.885ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.336 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X84Y536 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y536 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.385 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.338 1.723 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y565 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[82]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.431 1.596 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X88Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[82]/C clock pessimism -0.108 1.488 SLICE_X88Y565 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.493 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[82] ------------------------------------------------------------------- required time -1.493 arrival time 1.723 ------------------------------------------------------------------- slack 0.230 Slack (MET) : 0.230ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[64]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.387ns (logic 0.049ns (12.661%) route 0.338ns (87.339%)) Logic Levels: 0 Clock Path Skew: 0.152ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.596ns Source Clock Delay (SCD): 1.336ns Clock Pessimism Removal (CPR): 0.108ns Clock Net Delay (Source): 1.218ns (routing 0.485ns, distribution 0.733ns) Clock Net Delay (Destination): 1.431ns (routing 0.546ns, distribution 0.885ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.336 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X84Y536 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y536 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.385 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.338 1.723 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y565 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[64]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.431 1.596 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X88Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[64]/C clock pessimism -0.108 1.488 SLICE_X88Y565 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.493 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[64] ------------------------------------------------------------------- required time -1.493 arrival time 1.723 ------------------------------------------------------------------- slack 0.230 Slack (MET) : 0.230ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[67]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.387ns (logic 0.049ns (12.661%) route 0.338ns (87.339%)) Logic Levels: 0 Clock Path Skew: 0.152ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.596ns Source Clock Delay (SCD): 1.336ns Clock Pessimism Removal (CPR): 0.108ns Clock Net Delay (Source): 1.218ns (routing 0.485ns, distribution 0.733ns) Clock Net Delay (Destination): 1.431ns (routing 0.546ns, distribution 0.885ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.336 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X84Y536 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y536 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.385 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.338 1.723 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y565 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[67]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.431 1.596 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X88Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[67]/C clock pessimism -0.108 1.488 SLICE_X88Y565 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.493 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[67] ------------------------------------------------------------------- required time -1.493 arrival time 1.723 ------------------------------------------------------------------- slack 0.230 Slack (MET) : 0.230ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[82]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.387ns (logic 0.049ns (12.661%) route 0.338ns (87.339%)) Logic Levels: 0 Clock Path Skew: 0.152ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.596ns Source Clock Delay (SCD): 1.336ns Clock Pessimism Removal (CPR): 0.108ns Clock Net Delay (Source): 1.218ns (routing 0.485ns, distribution 0.733ns) Clock Net Delay (Destination): 1.431ns (routing 0.546ns, distribution 0.885ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.336 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X84Y536 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X84Y536 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.385 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.338 1.723 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X88Y565 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[82]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.431 1.596 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X88Y565 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[82]/C clock pessimism -0.108 1.488 SLICE_X88Y565 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.493 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[82] ------------------------------------------------------------------- required time -1.493 arrival time 1.723 ------------------------------------------------------------------- slack 0.230 Slack (MET) : 0.241ns (arrival time - required time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.291ns (logic 0.048ns (16.495%) route 0.243ns (83.505%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.605ns Source Clock Delay (SCD): 1.346ns Clock Pessimism Removal (CPR): 0.214ns Clock Net Delay (Source): 1.228ns (routing 0.485ns, distribution 0.743ns) Clock Net Delay (Destination): 1.440ns (routing 0.546ns, distribution 0.894ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.346 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y554 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y554 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.394 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.243 1.637 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X89Y557 FDCE f SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.440 1.605 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y557 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism -0.214 1.391 SLICE_X89Y557 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.396 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time -1.396 arrival time 1.637 ------------------------------------------------------------------- slack 0.241 Slack (MET) : 0.241ns (arrival time - required time) Source: SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns) Data Path Delay: 0.291ns (logic 0.048ns (16.495%) route 0.243ns (83.505%)) Logic Levels: 0 Clock Path Skew: 0.045ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.605ns Source Clock Delay (SCD): 1.346ns Clock Pessimism Removal (CPR): 0.214ns Clock Net Delay (Source): 1.228ns (routing 0.485ns, distribution 0.743ns) Clock Net Delay (Destination): 1.440ns (routing 0.546ns, distribution 0.894ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.228 1.346 SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y554 FDPE r SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y554 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.394 f SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.243 1.637 SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] SLICE_X89Y557 FDCE f SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y222 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.440 1.605 SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y557 FDCE r SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[54]/C clock pessimism -0.214 1.391 SLICE_X89Y557 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.396 SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[54] ------------------------------------------------------------------- required time -1.396 arrival time 1.637 ------------------------------------------------------------------- slack 0.241 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_15 To Clock: gtwiz_userclk_rx_srcclk_out[0]_15 Setup : 0 Failing Endpoints, Worst Slack 5.622ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.154ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.622ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[83]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 2.406ns (logic 0.140ns (5.819%) route 2.266ns (94.181%)) Logic Levels: 0 Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.698ns = ( 11.015 - 8.317 ) Source Clock Delay (SCD): 3.106ns Clock Pessimism Removal (CPR): 0.247ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.631ns (routing 1.082ns, distribution 1.549ns) Clock Net Delay (Destination): 2.300ns (routing 0.990ns, distribution 1.310ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.631 3.106 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X101Y436 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y436 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 3.246 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.266 5.512 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X114Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.300 11.015 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[83]/C clock pessimism 0.247 11.262 clock uncertainty -0.035 11.227 SLICE_X114Y442 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.134 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[83] ------------------------------------------------------------------- required time 11.134 arrival time -5.512 ------------------------------------------------------------------- slack 5.622 Slack (MET) : 5.622ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[83]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 2.406ns (logic 0.140ns (5.819%) route 2.266ns (94.181%)) Logic Levels: 0 Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.698ns = ( 11.015 - 8.317 ) Source Clock Delay (SCD): 3.106ns Clock Pessimism Removal (CPR): 0.247ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.631ns (routing 1.082ns, distribution 1.549ns) Clock Net Delay (Destination): 2.300ns (routing 0.990ns, distribution 1.310ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.631 3.106 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X101Y436 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y436 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 3.246 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.266 5.512 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X114Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.300 11.015 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X114Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[83]/C clock pessimism 0.247 11.262 clock uncertainty -0.035 11.227 SLICE_X114Y442 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 11.134 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[83] ------------------------------------------------------------------- required time 11.134 arrival time -5.512 ------------------------------------------------------------------- slack 5.622 Slack (MET) : 5.622ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[41]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 2.405ns (logic 0.140ns (5.821%) route 2.265ns (94.179%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.106ns Clock Pessimism Removal (CPR): 0.247ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.631ns (routing 1.082ns, distribution 1.549ns) Clock Net Delay (Destination): 2.299ns (routing 0.990ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.631 3.106 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X101Y436 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y436 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 3.246 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.265 5.511 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X113Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[41]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.299 11.014 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X113Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[41]/C clock pessimism 0.247 11.261 clock uncertainty -0.035 11.226 SLICE_X113Y442 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[41] ------------------------------------------------------------------- required time 11.133 arrival time -5.511 ------------------------------------------------------------------- slack 5.622 Slack (MET) : 5.622ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[42]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 2.405ns (logic 0.140ns (5.821%) route 2.265ns (94.179%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.106ns Clock Pessimism Removal (CPR): 0.247ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.631ns (routing 1.082ns, distribution 1.549ns) Clock Net Delay (Destination): 2.299ns (routing 0.990ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.631 3.106 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X101Y436 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y436 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 3.246 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.265 5.511 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X113Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[42]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.299 11.014 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X113Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[42]/C clock pessimism 0.247 11.261 clock uncertainty -0.035 11.226 SLICE_X113Y442 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[42] ------------------------------------------------------------------- required time 11.133 arrival time -5.511 ------------------------------------------------------------------- slack 5.622 Slack (MET) : 5.622ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[49]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 2.405ns (logic 0.140ns (5.821%) route 2.265ns (94.179%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.106ns Clock Pessimism Removal (CPR): 0.247ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.631ns (routing 1.082ns, distribution 1.549ns) Clock Net Delay (Destination): 2.299ns (routing 0.990ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.631 3.106 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X101Y436 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y436 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 3.246 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.265 5.511 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X113Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[49]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.299 11.014 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X113Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[49]/C clock pessimism 0.247 11.261 clock uncertainty -0.035 11.226 SLICE_X113Y442 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[49] ------------------------------------------------------------------- required time 11.133 arrival time -5.511 ------------------------------------------------------------------- slack 5.622 Slack (MET) : 5.622ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[50]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 2.405ns (logic 0.140ns (5.821%) route 2.265ns (94.179%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.106ns Clock Pessimism Removal (CPR): 0.247ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.631ns (routing 1.082ns, distribution 1.549ns) Clock Net Delay (Destination): 2.299ns (routing 0.990ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.631 3.106 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X101Y436 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y436 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 3.246 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.265 5.511 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X113Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[50]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.299 11.014 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X113Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[50]/C clock pessimism 0.247 11.261 clock uncertainty -0.035 11.226 SLICE_X113Y442 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[50] ------------------------------------------------------------------- required time 11.133 arrival time -5.511 ------------------------------------------------------------------- slack 5.622 Slack (MET) : 5.622ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[41]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 2.405ns (logic 0.140ns (5.821%) route 2.265ns (94.179%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.106ns Clock Pessimism Removal (CPR): 0.247ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.631ns (routing 1.082ns, distribution 1.549ns) Clock Net Delay (Destination): 2.299ns (routing 0.990ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.631 3.106 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X101Y436 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y436 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 3.246 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.265 5.511 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X113Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[41]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.299 11.014 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X113Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[41]/C clock pessimism 0.247 11.261 clock uncertainty -0.035 11.226 SLICE_X113Y442 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[41] ------------------------------------------------------------------- required time 11.133 arrival time -5.511 ------------------------------------------------------------------- slack 5.622 Slack (MET) : 5.622ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[42]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 2.405ns (logic 0.140ns (5.821%) route 2.265ns (94.179%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.106ns Clock Pessimism Removal (CPR): 0.247ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.631ns (routing 1.082ns, distribution 1.549ns) Clock Net Delay (Destination): 2.299ns (routing 0.990ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.631 3.106 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X101Y436 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y436 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 3.246 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.265 5.511 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X113Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[42]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.299 11.014 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X113Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[42]/C clock pessimism 0.247 11.261 clock uncertainty -0.035 11.226 SLICE_X113Y442 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[42] ------------------------------------------------------------------- required time 11.133 arrival time -5.511 ------------------------------------------------------------------- slack 5.622 Slack (MET) : 5.622ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[49]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 2.405ns (logic 0.140ns (5.821%) route 2.265ns (94.179%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.106ns Clock Pessimism Removal (CPR): 0.247ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.631ns (routing 1.082ns, distribution 1.549ns) Clock Net Delay (Destination): 2.299ns (routing 0.990ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.631 3.106 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X101Y436 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y436 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 3.246 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.265 5.511 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X113Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[49]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.299 11.014 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X113Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[49]/C clock pessimism 0.247 11.261 clock uncertainty -0.035 11.226 SLICE_X113Y442 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 11.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[49] ------------------------------------------------------------------- required time 11.133 arrival time -5.511 ------------------------------------------------------------------- slack 5.622 Slack (MET) : 5.622ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[50]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 2.405ns (logic 0.140ns (5.821%) route 2.265ns (94.179%)) Logic Levels: 0 Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 3.106ns Clock Pessimism Removal (CPR): 0.247ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.631ns (routing 1.082ns, distribution 1.549ns) Clock Net Delay (Destination): 2.299ns (routing 0.990ns, distribution 1.309ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.631 3.106 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X101Y436 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X101Y436 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 3.246 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.265 5.511 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X113Y442 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[50]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 2.299 11.014 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X113Y442 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[50]/C clock pessimism 0.247 11.261 clock uncertainty -0.035 11.226 SLICE_X113Y442 FDCE (Recov_AFF2_SLICEM_C_CLR) -0.093 11.133 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[50] ------------------------------------------------------------------- required time 11.133 arrival time -5.511 ------------------------------------------------------------------- slack 5.622 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.154ns (arrival time - required time) Source: SFP_GEN[13].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[13].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.245ns (logic 0.048ns (19.592%) route 0.197ns (80.408%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.332ns Source Clock Delay (SCD): 1.094ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 0.976ns (routing 0.459ns, distribution 0.517ns) Clock Net Delay (Destination): 1.167ns (routing 0.521ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.976 1.094 SFP_GEN[13].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y417 FDPE r SFP_GEN[13].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y417 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.142 f SFP_GEN[13].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.197 1.339 SFP_GEN[13].ngCCM_gbt/sync_m_reg[3][0] SLICE_X104Y417 FDCE f SFP_GEN[13].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.167 1.332 SFP_GEN[13].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y417 FDCE r SFP_GEN[13].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.152 1.180 SLICE_X104Y417 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.185 SFP_GEN[13].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.185 arrival time 1.339 ------------------------------------------------------------------- slack 0.154 Slack (MET) : 0.212ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.314ns (logic 0.049ns (15.605%) route 0.265ns (84.395%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.989ns (routing 0.459ns, distribution 0.530ns) Clock Net Delay (Destination): 1.194ns (routing 0.521ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.156 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.265 1.421 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X108Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.155 1.204 SLICE_X108Y436 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.209 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.209 arrival time 1.421 ------------------------------------------------------------------- slack 0.212 Slack (MET) : 0.212ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.314ns (logic 0.049ns (15.605%) route 0.265ns (84.395%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.989ns (routing 0.459ns, distribution 0.530ns) Clock Net Delay (Destination): 1.194ns (routing 0.521ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.156 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.265 1.421 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X108Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.155 1.204 SLICE_X108Y436 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.209 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.209 arrival time 1.421 ------------------------------------------------------------------- slack 0.212 Slack (MET) : 0.212ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.314ns (logic 0.049ns (15.605%) route 0.265ns (84.395%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.989ns (routing 0.459ns, distribution 0.530ns) Clock Net Delay (Destination): 1.194ns (routing 0.521ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.156 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.265 1.421 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X108Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.155 1.204 SLICE_X108Y436 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.209 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.209 arrival time 1.421 ------------------------------------------------------------------- slack 0.212 Slack (MET) : 0.212ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.314ns (logic 0.049ns (15.605%) route 0.265ns (84.395%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.989ns (routing 0.459ns, distribution 0.530ns) Clock Net Delay (Destination): 1.194ns (routing 0.521ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.156 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.265 1.421 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X108Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.155 1.204 SLICE_X108Y436 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.209 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.209 arrival time 1.421 ------------------------------------------------------------------- slack 0.212 Slack (MET) : 0.212ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.314ns (logic 0.049ns (15.605%) route 0.265ns (84.395%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.989ns (routing 0.459ns, distribution 0.530ns) Clock Net Delay (Destination): 1.194ns (routing 0.521ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.156 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.265 1.421 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X108Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.155 1.204 SLICE_X108Y436 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.209 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.209 arrival time 1.421 ------------------------------------------------------------------- slack 0.212 Slack (MET) : 0.212ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.314ns (logic 0.049ns (15.605%) route 0.265ns (84.395%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.989ns (routing 0.459ns, distribution 0.530ns) Clock Net Delay (Destination): 1.194ns (routing 0.521ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.156 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.265 1.421 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X108Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.155 1.204 SLICE_X108Y436 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 1.209 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.209 arrival time 1.421 ------------------------------------------------------------------- slack 0.212 Slack (MET) : 0.212ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.314ns (logic 0.049ns (15.605%) route 0.265ns (84.395%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.989ns (routing 0.459ns, distribution 0.530ns) Clock Net Delay (Destination): 1.194ns (routing 0.521ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.156 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.265 1.421 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X108Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.155 1.204 SLICE_X108Y436 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.209 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.209 arrival time 1.421 ------------------------------------------------------------------- slack 0.212 Slack (MET) : 0.212ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.314ns (logic 0.049ns (15.605%) route 0.265ns (84.395%)) Logic Levels: 0 Clock Path Skew: 0.097ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.989ns (routing 0.459ns, distribution 0.530ns) Clock Net Delay (Destination): 1.194ns (routing 0.521ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.156 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.265 1.421 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X108Y436 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X108Y436 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.155 1.204 SLICE_X108Y436 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.209 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -1.209 arrival time 1.421 ------------------------------------------------------------------- slack 0.212 Slack (MET) : 0.212ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns) Data Path Delay: 0.306ns (logic 0.049ns (16.013%) route 0.257ns (83.987%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.351ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 0.989ns (routing 0.459ns, distribution 0.530ns) Clock Net Delay (Destination): 1.186ns (routing 0.521ns, distribution 0.665ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y440 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X106Y440 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.156 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.257 1.413 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X107Y437 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y6 (CLOCK_ROOT) net (fo=674, routed) 1.186 1.351 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X107Y437 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.155 1.196 SLICE_X107Y437 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.201 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.201 arrival time 1.413 ------------------------------------------------------------------- slack 0.212 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_16 To Clock: gtwiz_userclk_rx_srcclk_out[0]_16 Setup : 0 Failing Endpoints, Worst Slack 4.574ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.151ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.574ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.611ns (logic 0.383ns (10.606%) route 3.228ns (89.394%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.004ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.731ns = ( 11.048 - 8.317 ) Source Clock Delay (SCD): 2.961ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.486ns (routing 0.732ns, distribution 1.754ns) Clock Net Delay (Destination): 2.333ns (routing 0.665ns, distribution 1.668ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.486 2.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y438 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.100 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.481 5.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y433 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.825 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.747 6.572 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X80Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 11.048 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/C clock pessimism 0.226 11.274 clock uncertainty -0.035 11.239 SLICE_X80Y434 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.146 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5] ------------------------------------------------------------------- required time 11.146 arrival time -6.572 ------------------------------------------------------------------- slack 4.574 Slack (MET) : 4.574ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.611ns (logic 0.383ns (10.606%) route 3.228ns (89.394%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.004ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.731ns = ( 11.048 - 8.317 ) Source Clock Delay (SCD): 2.961ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.486ns (routing 0.732ns, distribution 1.754ns) Clock Net Delay (Destination): 2.333ns (routing 0.665ns, distribution 1.668ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.486 2.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y438 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.100 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.481 5.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y433 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.825 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.747 6.572 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X80Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 11.048 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/C clock pessimism 0.226 11.274 clock uncertainty -0.035 11.239 SLICE_X80Y434 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.146 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6] ------------------------------------------------------------------- required time 11.146 arrival time -6.572 ------------------------------------------------------------------- slack 4.574 Slack (MET) : 4.574ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.611ns (logic 0.383ns (10.606%) route 3.228ns (89.394%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.004ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.731ns = ( 11.048 - 8.317 ) Source Clock Delay (SCD): 2.961ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.486ns (routing 0.732ns, distribution 1.754ns) Clock Net Delay (Destination): 2.333ns (routing 0.665ns, distribution 1.668ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.486 2.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y438 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.100 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.481 5.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y433 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.825 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.747 6.572 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X80Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.333 11.048 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/C clock pessimism 0.226 11.274 clock uncertainty -0.035 11.239 SLICE_X80Y434 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.146 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7] ------------------------------------------------------------------- required time 11.146 arrival time -6.572 ------------------------------------------------------------------- slack 4.574 Slack (MET) : 4.582ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.601ns (logic 0.383ns (10.636%) route 3.218ns (89.364%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.729ns = ( 11.046 - 8.317 ) Source Clock Delay (SCD): 2.961ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.486ns (routing 0.732ns, distribution 1.754ns) Clock Net Delay (Destination): 2.331ns (routing 0.665ns, distribution 1.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.486 2.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y438 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.100 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.481 5.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y433 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.825 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.737 6.562 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X80Y434 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.331 11.046 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y434 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/C clock pessimism 0.226 11.272 clock uncertainty -0.035 11.237 SLICE_X80Y434 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.144 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5] ------------------------------------------------------------------- required time 11.144 arrival time -6.562 ------------------------------------------------------------------- slack 4.582 Slack (MET) : 4.640ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.552ns (logic 0.383ns (10.783%) route 3.169ns (89.217%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.738ns = ( 11.055 - 8.317 ) Source Clock Delay (SCD): 2.961ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.486ns (routing 0.732ns, distribution 1.754ns) Clock Net Delay (Destination): 2.340ns (routing 0.665ns, distribution 1.675ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.486 2.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y438 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.100 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.481 5.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y433 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.825 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.688 6.513 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X80Y435 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.340 11.055 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/C clock pessimism 0.226 11.281 clock uncertainty -0.035 11.246 SLICE_X80Y435 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.153 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4] ------------------------------------------------------------------- required time 11.153 arrival time -6.513 ------------------------------------------------------------------- slack 4.640 Slack (MET) : 4.645ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.551ns (logic 0.383ns (10.786%) route 3.168ns (89.214%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.742ns = ( 11.059 - 8.317 ) Source Clock Delay (SCD): 2.961ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.486ns (routing 0.732ns, distribution 1.754ns) Clock Net Delay (Destination): 2.344ns (routing 0.665ns, distribution 1.679ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.486 2.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y438 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.100 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.481 5.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y433 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.825 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.687 6.512 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X79Y435 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.344 11.059 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/C clock pessimism 0.226 11.285 clock uncertainty -0.035 11.250 SLICE_X79Y435 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.157 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1] ------------------------------------------------------------------- required time 11.157 arrival time -6.512 ------------------------------------------------------------------- slack 4.645 Slack (MET) : 4.645ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.551ns (logic 0.383ns (10.786%) route 3.168ns (89.214%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.742ns = ( 11.059 - 8.317 ) Source Clock Delay (SCD): 2.961ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.486ns (routing 0.732ns, distribution 1.754ns) Clock Net Delay (Destination): 2.344ns (routing 0.665ns, distribution 1.679ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.486 2.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y438 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.100 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.481 5.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y433 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.825 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.687 6.512 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X79Y435 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.344 11.059 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/C clock pessimism 0.226 11.285 clock uncertainty -0.035 11.250 SLICE_X79Y435 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.157 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2] ------------------------------------------------------------------- required time 11.157 arrival time -6.512 ------------------------------------------------------------------- slack 4.645 Slack (MET) : 4.645ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.551ns (logic 0.383ns (10.786%) route 3.168ns (89.214%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.742ns = ( 11.059 - 8.317 ) Source Clock Delay (SCD): 2.961ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.486ns (routing 0.732ns, distribution 1.754ns) Clock Net Delay (Destination): 2.344ns (routing 0.665ns, distribution 1.679ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.486 2.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y438 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.100 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.481 5.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y433 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.825 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.687 6.512 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X79Y435 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.344 11.059 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/C clock pessimism 0.226 11.285 clock uncertainty -0.035 11.250 SLICE_X79Y435 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.157 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3] ------------------------------------------------------------------- required time 11.157 arrival time -6.512 ------------------------------------------------------------------- slack 4.645 Slack (MET) : 4.651ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.544ns (logic 0.383ns (10.807%) route 3.161ns (89.193%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.741ns = ( 11.058 - 8.317 ) Source Clock Delay (SCD): 2.961ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.486ns (routing 0.732ns, distribution 1.754ns) Clock Net Delay (Destination): 2.343ns (routing 0.665ns, distribution 1.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.486 2.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y438 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.100 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.481 5.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y433 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.825 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.680 6.505 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X79Y435 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.343 11.058 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C clock pessimism 0.226 11.284 clock uncertainty -0.035 11.249 SLICE_X79Y435 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.156 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2] ------------------------------------------------------------------- required time 11.156 arrival time -6.505 ------------------------------------------------------------------- slack 4.651 Slack (MET) : 4.651ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 3.544ns (logic 0.383ns (10.807%) route 3.161ns (89.193%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.741ns = ( 11.058 - 8.317 ) Source Clock Delay (SCD): 2.961ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.486ns (routing 0.732ns, distribution 1.754ns) Clock Net Delay (Destination): 2.343ns (routing 0.665ns, distribution 1.678ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.486 2.961 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X128Y438 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X128Y438 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.100 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.481 5.581 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y433 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.825 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/O net (fo=15, routed) 0.680 6.505 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X79Y435 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.343 11.058 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y435 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C clock pessimism 0.226 11.284 clock uncertainty -0.035 11.249 SLICE_X79Y435 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 11.156 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0] ------------------------------------------------------------------- required time 11.156 arrival time -6.505 ------------------------------------------------------------------- slack 4.651 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.151ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.049ns (21.212%) route 0.182ns (78.788%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.345ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.998ns (routing 0.320ns, distribution 0.678ns) Clock Net Delay (Destination): 1.180ns (routing 0.362ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X81Y433 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y433 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.165 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y434 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.180 1.345 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]/C clock pessimism -0.154 1.191 SLICE_X82Y434 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.196 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25] ------------------------------------------------------------------- required time -1.196 arrival time 1.347 ------------------------------------------------------------------- slack 0.151 Slack (MET) : 0.151ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[33]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.049ns (21.212%) route 0.182ns (78.788%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.345ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.998ns (routing 0.320ns, distribution 0.678ns) Clock Net Delay (Destination): 1.180ns (routing 0.362ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X81Y433 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y433 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.165 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y434 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[33]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.180 1.345 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[33]/C clock pessimism -0.154 1.191 SLICE_X82Y434 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.196 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[33] ------------------------------------------------------------------- required time -1.196 arrival time 1.347 ------------------------------------------------------------------- slack 0.151 Slack (MET) : 0.151ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[25]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.049ns (21.212%) route 0.182ns (78.788%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.345ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.998ns (routing 0.320ns, distribution 0.678ns) Clock Net Delay (Destination): 1.180ns (routing 0.362ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X81Y433 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y433 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.165 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y434 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.180 1.345 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[25]/C clock pessimism -0.154 1.191 SLICE_X82Y434 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.196 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[25] ------------------------------------------------------------------- required time -1.196 arrival time 1.347 ------------------------------------------------------------------- slack 0.151 Slack (MET) : 0.151ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[26]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.049ns (21.212%) route 0.182ns (78.788%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.345ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.998ns (routing 0.320ns, distribution 0.678ns) Clock Net Delay (Destination): 1.180ns (routing 0.362ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X81Y433 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y433 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.165 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y434 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.180 1.345 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[26]/C clock pessimism -0.154 1.191 SLICE_X82Y434 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.196 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[26] ------------------------------------------------------------------- required time -1.196 arrival time 1.347 ------------------------------------------------------------------- slack 0.151 Slack (MET) : 0.151ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[27]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.049ns (21.212%) route 0.182ns (78.788%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.345ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.998ns (routing 0.320ns, distribution 0.678ns) Clock Net Delay (Destination): 1.180ns (routing 0.362ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X81Y433 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y433 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.165 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y434 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.180 1.345 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[27]/C clock pessimism -0.154 1.191 SLICE_X82Y434 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.196 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[27] ------------------------------------------------------------------- required time -1.196 arrival time 1.347 ------------------------------------------------------------------- slack 0.151 Slack (MET) : 0.152ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.234ns (logic 0.049ns (20.940%) route 0.185ns (79.060%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.347ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.998ns (routing 0.320ns, distribution 0.678ns) Clock Net Delay (Destination): 1.182ns (routing 0.362ns, distribution 0.820ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X81Y433 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y433 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.165 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.185 1.350 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y434 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/C clock pessimism -0.154 1.193 SLICE_X82Y434 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.198 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24] ------------------------------------------------------------------- required time -1.198 arrival time 1.350 ------------------------------------------------------------------- slack 0.152 Slack (MET) : 0.152ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.234ns (logic 0.049ns (20.940%) route 0.185ns (79.060%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.347ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.998ns (routing 0.320ns, distribution 0.678ns) Clock Net Delay (Destination): 1.182ns (routing 0.362ns, distribution 0.820ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X81Y433 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y433 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.165 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.185 1.350 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y434 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]/C clock pessimism -0.154 1.193 SLICE_X82Y434 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.198 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26] ------------------------------------------------------------------- required time -1.198 arrival time 1.350 ------------------------------------------------------------------- slack 0.152 Slack (MET) : 0.152ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[27]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.234ns (logic 0.049ns (20.940%) route 0.185ns (79.060%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.347ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.998ns (routing 0.320ns, distribution 0.678ns) Clock Net Delay (Destination): 1.182ns (routing 0.362ns, distribution 0.820ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X81Y433 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y433 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.165 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.185 1.350 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y434 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[27]/C clock pessimism -0.154 1.193 SLICE_X82Y434 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.198 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[27] ------------------------------------------------------------------- required time -1.198 arrival time 1.350 ------------------------------------------------------------------- slack 0.152 Slack (MET) : 0.152ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[35]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.234ns (logic 0.049ns (20.940%) route 0.185ns (79.060%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.347ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.998ns (routing 0.320ns, distribution 0.678ns) Clock Net Delay (Destination): 1.182ns (routing 0.362ns, distribution 0.820ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X81Y433 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y433 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.165 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.185 1.350 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y434 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[35]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[35]/C clock pessimism -0.154 1.193 SLICE_X82Y434 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.198 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[35] ------------------------------------------------------------------- required time -1.198 arrival time 1.350 ------------------------------------------------------------------- slack 0.152 Slack (MET) : 0.152ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[33]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns) Data Path Delay: 0.234ns (logic 0.049ns (20.940%) route 0.185ns (79.060%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.347ns Source Clock Delay (SCD): 1.116ns Clock Pessimism Removal (CPR): 0.154ns Clock Net Delay (Source): 0.998ns (routing 0.320ns, distribution 0.678ns) Clock Net Delay (Destination): 1.182ns (routing 0.362ns, distribution 0.820ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.116 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X81Y433 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y433 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.165 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.185 1.350 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y434 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[33]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.182 1.347 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y434 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[33]/C clock pessimism -0.154 1.193 SLICE_X82Y434 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.198 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[33] ------------------------------------------------------------------- required time -1.198 arrival time 1.350 ------------------------------------------------------------------- slack 0.152 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_17 To Clock: gtwiz_userclk_rx_srcclk_out[0]_17 Setup : 0 Failing Endpoints, Worst Slack 4.263ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.171ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.263ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 3.540ns (logic 0.305ns (8.616%) route 3.235ns (91.384%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.386ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.331ns = ( 10.648 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.933ns (routing 0.664ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.514 5.586 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.752 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.721 6.473 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X102Y429 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.933 10.648 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 SLICE_X102Y429 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/C clock pessimism 0.216 10.865 clock uncertainty -0.035 10.829 SLICE_X102Y429 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.736 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1] ------------------------------------------------------------------- required time 10.736 arrival time -6.473 ------------------------------------------------------------------- slack 4.263 Slack (MET) : 4.263ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 3.540ns (logic 0.305ns (8.616%) route 3.235ns (91.384%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.386ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.331ns = ( 10.648 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.933ns (routing 0.664ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.514 5.586 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.752 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.721 6.473 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X102Y429 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.933 10.648 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 SLICE_X102Y429 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/C clock pessimism 0.216 10.865 clock uncertainty -0.035 10.829 SLICE_X102Y429 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.736 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2] ------------------------------------------------------------------- required time 10.736 arrival time -6.473 ------------------------------------------------------------------- slack 4.263 Slack (MET) : 4.263ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 3.540ns (logic 0.305ns (8.616%) route 3.235ns (91.384%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.386ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.331ns = ( 10.648 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.933ns (routing 0.664ns, distribution 1.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.514 5.586 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.752 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.721 6.473 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X102Y429 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.933 10.648 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 SLICE_X102Y429 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/C clock pessimism 0.216 10.865 clock uncertainty -0.035 10.829 SLICE_X102Y429 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.736 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4] ------------------------------------------------------------------- required time 10.736 arrival time -6.473 ------------------------------------------------------------------- slack 4.263 Slack (MET) : 4.271ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 3.530ns (logic 0.305ns (8.640%) route 3.225ns (91.360%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.388ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.329ns = ( 10.646 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.931ns (routing 0.664ns, distribution 1.267ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.514 5.586 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.752 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.711 6.463 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X102Y429 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.646 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 SLICE_X102Y429 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C clock pessimism 0.216 10.863 clock uncertainty -0.035 10.827 SLICE_X102Y429 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.734 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3] ------------------------------------------------------------------- required time 10.734 arrival time -6.463 ------------------------------------------------------------------- slack 4.271 Slack (MET) : 4.274ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 3.532ns (logic 0.305ns (8.635%) route 3.227ns (91.365%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.383ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.936ns (routing 0.664ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.514 5.586 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.752 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.713 6.465 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X101Y429 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 SLICE_X101Y429 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C clock pessimism 0.216 10.867 clock uncertainty -0.035 10.832 SLICE_X101Y429 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 10.739 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2] ------------------------------------------------------------------- required time 10.739 arrival time -6.465 ------------------------------------------------------------------- slack 4.274 Slack (MET) : 4.274ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 3.532ns (logic 0.305ns (8.635%) route 3.227ns (91.365%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.383ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.936ns (routing 0.664ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.514 5.586 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.752 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.713 6.465 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X101Y429 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 SLICE_X101Y429 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C clock pessimism 0.216 10.867 clock uncertainty -0.035 10.832 SLICE_X101Y429 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 10.739 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3] ------------------------------------------------------------------- required time 10.739 arrival time -6.465 ------------------------------------------------------------------- slack 4.274 Slack (MET) : 4.274ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 3.532ns (logic 0.305ns (8.635%) route 3.227ns (91.365%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.383ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.334ns = ( 10.651 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.936ns (routing 0.664ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.514 5.586 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.752 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.713 6.465 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X101Y429 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.651 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 SLICE_X101Y429 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C clock pessimism 0.216 10.867 clock uncertainty -0.035 10.832 SLICE_X101Y429 FDCE (Recov_FFF_SLICEM_C_CLR) -0.093 10.739 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5] ------------------------------------------------------------------- required time 10.739 arrival time -6.465 ------------------------------------------------------------------- slack 4.274 Slack (MET) : 4.367ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 3.440ns (logic 0.305ns (8.866%) route 3.135ns (91.134%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.382ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.335ns = ( 10.652 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.937ns (routing 0.664ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.514 5.586 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.752 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.621 6.373 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X101Y428 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.937 10.652 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 SLICE_X101Y428 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C clock pessimism 0.216 10.868 clock uncertainty -0.035 10.833 SLICE_X101Y428 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.740 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1] ------------------------------------------------------------------- required time 10.740 arrival time -6.373 ------------------------------------------------------------------- slack 4.367 Slack (MET) : 4.367ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 3.440ns (logic 0.305ns (8.866%) route 3.135ns (91.134%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.382ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.335ns = ( 10.652 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.937ns (routing 0.664ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.514 5.586 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.752 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.621 6.373 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X101Y428 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.937 10.652 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 SLICE_X101Y428 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C clock pessimism 0.216 10.868 clock uncertainty -0.035 10.833 SLICE_X101Y428 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.740 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4] ------------------------------------------------------------------- required time 10.740 arrival time -6.373 ------------------------------------------------------------------- slack 4.367 Slack (MET) : 4.367ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 3.440ns (logic 0.305ns (8.866%) route 3.135ns (91.134%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.382ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.335ns = ( 10.652 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.728ns, distribution 1.730ns) Clock Net Delay (Destination): 1.937ns (routing 0.664ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X131Y464 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X131Y464 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.072 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.514 5.586 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X102Y428 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.752 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/O net (fo=15, routed) 0.621 6.373 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X101Y428 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.937 10.652 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0 SLICE_X101Y428 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C clock pessimism 0.216 10.868 clock uncertainty -0.035 10.833 SLICE_X101Y428 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.740 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6] ------------------------------------------------------------------- required time 10.740 arrival time -6.373 ------------------------------------------------------------------- slack 4.367 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[85]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.264ns (logic 0.049ns (18.561%) route 0.215ns (81.439%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.822ns (routing 0.317ns, distribution 0.505ns) Clock Net Delay (Destination): 0.997ns (routing 0.360ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X102Y430 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y430 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.215 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X105Y430 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[85]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[85]/C clock pessimism -0.134 1.028 SLICE_X105Y430 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.033 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[85] ------------------------------------------------------------------- required time -1.033 arrival time 1.204 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[86]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.264ns (logic 0.049ns (18.561%) route 0.215ns (81.439%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.822ns (routing 0.317ns, distribution 0.505ns) Clock Net Delay (Destination): 0.997ns (routing 0.360ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X102Y430 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y430 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.215 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X105Y430 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[86]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[86]/C clock pessimism -0.134 1.028 SLICE_X105Y430 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.033 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[86] ------------------------------------------------------------------- required time -1.033 arrival time 1.204 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[87]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.264ns (logic 0.049ns (18.561%) route 0.215ns (81.439%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.822ns (routing 0.317ns, distribution 0.505ns) Clock Net Delay (Destination): 0.997ns (routing 0.360ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X102Y430 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y430 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.215 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X105Y430 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[87]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[87]/C clock pessimism -0.134 1.028 SLICE_X105Y430 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.033 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[87] ------------------------------------------------------------------- required time -1.033 arrival time 1.204 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[94]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.264ns (logic 0.049ns (18.561%) route 0.215ns (81.439%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.822ns (routing 0.317ns, distribution 0.505ns) Clock Net Delay (Destination): 0.997ns (routing 0.360ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X102Y430 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y430 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.215 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X105Y430 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[94]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[94]/C clock pessimism -0.134 1.028 SLICE_X105Y430 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.033 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[94] ------------------------------------------------------------------- required time -1.033 arrival time 1.204 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[85]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.264ns (logic 0.049ns (18.561%) route 0.215ns (81.439%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.822ns (routing 0.317ns, distribution 0.505ns) Clock Net Delay (Destination): 0.997ns (routing 0.360ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X102Y430 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y430 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.215 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X105Y430 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[85]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[85]/C clock pessimism -0.134 1.028 SLICE_X105Y430 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.033 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[85] ------------------------------------------------------------------- required time -1.033 arrival time 1.204 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.264ns (logic 0.049ns (18.561%) route 0.215ns (81.439%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.822ns (routing 0.317ns, distribution 0.505ns) Clock Net Delay (Destination): 0.997ns (routing 0.360ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X102Y430 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y430 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.215 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X105Y430 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]/C clock pessimism -0.134 1.028 SLICE_X105Y430 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.033 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86] ------------------------------------------------------------------- required time -1.033 arrival time 1.204 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[87]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.264ns (logic 0.049ns (18.561%) route 0.215ns (81.439%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.822ns (routing 0.317ns, distribution 0.505ns) Clock Net Delay (Destination): 0.997ns (routing 0.360ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X102Y430 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y430 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.215 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X105Y430 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[87]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[87]/C clock pessimism -0.134 1.028 SLICE_X105Y430 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.033 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[87] ------------------------------------------------------------------- required time -1.033 arrival time 1.204 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.171ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[94]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.264ns (logic 0.049ns (18.561%) route 0.215ns (81.439%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.162ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.822ns (routing 0.317ns, distribution 0.505ns) Clock Net Delay (Destination): 0.997ns (routing 0.360ns, distribution 0.637ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X102Y430 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y430 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.215 1.204 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X105Y430 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[94]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.162 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[94]/C clock pessimism -0.134 1.028 SLICE_X105Y430 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.033 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[94] ------------------------------------------------------------------- required time -1.033 arrival time 1.204 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.174ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.165ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.822ns (routing 0.317ns, distribution 0.505ns) Clock Net Delay (Destination): 1.000ns (routing 0.360ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X102Y430 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y430 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.210 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X105Y430 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[14]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.165 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[14]/C clock pessimism -0.134 1.031 SLICE_X105Y430 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.036 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[14] ------------------------------------------------------------------- required time -1.036 arrival time 1.210 ------------------------------------------------------------------- slack 0.174 Slack (MET) : 0.174ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.091ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.165ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.822ns (routing 0.317ns, distribution 0.505ns) Clock Net Delay (Destination): 1.000ns (routing 0.360ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.940 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X102Y430 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X102Y430 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.210 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X105Y430 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y7 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.165 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X105Y430 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[6]/C clock pessimism -0.134 1.031 SLICE_X105Y430 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.036 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[6] ------------------------------------------------------------------- required time -1.036 arrival time 1.210 ------------------------------------------------------------------- slack 0.174 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_18 To Clock: gtwiz_userclk_rx_srcclk_out[0]_18 Setup : 0 Failing Endpoints, Worst Slack 4.177ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.144ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.177ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.974ns (logic 0.362ns (9.109%) route 3.612ns (90.891%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.638ns = ( 10.955 - 8.317 ) Source Clock Delay (SCD): 2.902ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.427ns (routing 0.725ns, distribution 1.702ns) Clock Net Delay (Destination): 2.240ns (routing 0.657ns, distribution 1.583ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.427 2.902 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y490 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 5.656 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y484 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.879 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 0.997 6.876 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X93Y496 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.240 10.955 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X93Y496 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C clock pessimism 0.227 11.182 clock uncertainty -0.035 11.146 SLICE_X93Y496 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 11.053 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2] ------------------------------------------------------------------- required time 11.053 arrival time -6.876 ------------------------------------------------------------------- slack 4.177 Slack (MET) : 4.177ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.974ns (logic 0.362ns (9.109%) route 3.612ns (90.891%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.638ns = ( 10.955 - 8.317 ) Source Clock Delay (SCD): 2.902ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.427ns (routing 0.725ns, distribution 1.702ns) Clock Net Delay (Destination): 2.240ns (routing 0.657ns, distribution 1.583ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.427 2.902 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y490 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 5.656 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y484 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.879 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 0.997 6.876 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X93Y496 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.240 10.955 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X93Y496 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C clock pessimism 0.227 11.182 clock uncertainty -0.035 11.146 SLICE_X93Y496 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.053 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3] ------------------------------------------------------------------- required time 11.053 arrival time -6.876 ------------------------------------------------------------------- slack 4.177 Slack (MET) : 4.177ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.974ns (logic 0.362ns (9.109%) route 3.612ns (90.891%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.638ns = ( 10.955 - 8.317 ) Source Clock Delay (SCD): 2.902ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.427ns (routing 0.725ns, distribution 1.702ns) Clock Net Delay (Destination): 2.240ns (routing 0.657ns, distribution 1.583ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.427 2.902 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y490 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 5.656 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y484 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.879 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 0.997 6.876 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X93Y496 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.240 10.955 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X93Y496 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C clock pessimism 0.227 11.182 clock uncertainty -0.035 11.146 SLICE_X93Y496 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.053 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4] ------------------------------------------------------------------- required time 11.053 arrival time -6.876 ------------------------------------------------------------------- slack 4.177 Slack (MET) : 4.185ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.964ns (logic 0.362ns (9.132%) route 3.602ns (90.868%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.039ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.636ns = ( 10.953 - 8.317 ) Source Clock Delay (SCD): 2.902ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.427ns (routing 0.725ns, distribution 1.702ns) Clock Net Delay (Destination): 2.238ns (routing 0.657ns, distribution 1.581ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.427 2.902 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y490 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 5.656 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y484 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.879 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 0.987 6.866 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X93Y496 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.238 10.953 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X93Y496 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C clock pessimism 0.227 11.180 clock uncertainty -0.035 11.144 SLICE_X93Y496 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.051 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0] ------------------------------------------------------------------- required time 11.051 arrival time -6.866 ------------------------------------------------------------------- slack 4.185 Slack (MET) : 4.185ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.964ns (logic 0.362ns (9.132%) route 3.602ns (90.868%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.039ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.636ns = ( 10.953 - 8.317 ) Source Clock Delay (SCD): 2.902ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.427ns (routing 0.725ns, distribution 1.702ns) Clock Net Delay (Destination): 2.238ns (routing 0.657ns, distribution 1.581ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.427 2.902 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y490 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 5.656 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y484 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.879 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 0.987 6.866 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X93Y496 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.238 10.953 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X93Y496 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/C clock pessimism 0.227 11.180 clock uncertainty -0.035 11.144 SLICE_X93Y496 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.051 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5] ------------------------------------------------------------------- required time 11.051 arrival time -6.866 ------------------------------------------------------------------- slack 4.185 Slack (MET) : 4.255ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.870ns (logic 0.362ns (9.354%) route 3.508ns (90.646%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.063ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.612ns = ( 10.929 - 8.317 ) Source Clock Delay (SCD): 2.902ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.427ns (routing 0.725ns, distribution 1.702ns) Clock Net Delay (Destination): 2.214ns (routing 0.657ns, distribution 1.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.427 2.902 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y490 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 5.656 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y484 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.879 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 0.893 6.772 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X94Y496 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.214 10.929 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X94Y496 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C clock pessimism 0.227 11.156 clock uncertainty -0.035 11.120 SLICE_X94Y496 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.027 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5] ------------------------------------------------------------------- required time 11.027 arrival time -6.772 ------------------------------------------------------------------- slack 4.255 Slack (MET) : 4.255ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.870ns (logic 0.362ns (9.354%) route 3.508ns (90.646%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.063ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.612ns = ( 10.929 - 8.317 ) Source Clock Delay (SCD): 2.902ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.427ns (routing 0.725ns, distribution 1.702ns) Clock Net Delay (Destination): 2.214ns (routing 0.657ns, distribution 1.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.427 2.902 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y490 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 5.656 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y484 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.879 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 0.893 6.772 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X94Y496 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.214 10.929 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X94Y496 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C clock pessimism 0.227 11.156 clock uncertainty -0.035 11.120 SLICE_X94Y496 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.027 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6] ------------------------------------------------------------------- required time 11.027 arrival time -6.772 ------------------------------------------------------------------- slack 4.255 Slack (MET) : 4.255ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.870ns (logic 0.362ns (9.354%) route 3.508ns (90.646%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.063ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.612ns = ( 10.929 - 8.317 ) Source Clock Delay (SCD): 2.902ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.427ns (routing 0.725ns, distribution 1.702ns) Clock Net Delay (Destination): 2.214ns (routing 0.657ns, distribution 1.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.427 2.902 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y490 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 5.656 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y484 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.879 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 0.893 6.772 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X94Y496 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.214 10.929 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X94Y496 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/C clock pessimism 0.227 11.156 clock uncertainty -0.035 11.120 SLICE_X94Y496 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.027 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7] ------------------------------------------------------------------- required time 11.027 arrival time -6.772 ------------------------------------------------------------------- slack 4.255 Slack (MET) : 4.266ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.888ns (logic 0.362ns (9.311%) route 3.526ns (90.689%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.902ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.427ns (routing 0.725ns, distribution 1.702ns) Clock Net Delay (Destination): 2.243ns (routing 0.657ns, distribution 1.586ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.427 2.902 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y490 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 5.656 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y484 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.879 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 0.911 6.790 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X92Y497 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.243 10.958 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X92Y497 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/C clock pessimism 0.227 11.185 clock uncertainty -0.035 11.149 SLICE_X92Y497 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.056 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1] ------------------------------------------------------------------- required time 11.056 arrival time -6.790 ------------------------------------------------------------------- slack 4.266 Slack (MET) : 4.266ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 3.888ns (logic 0.362ns (9.311%) route 3.526ns (90.689%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.641ns = ( 10.958 - 8.317 ) Source Clock Delay (SCD): 2.902ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.427ns (routing 0.725ns, distribution 1.702ns) Clock Net Delay (Destination): 2.243ns (routing 0.657ns, distribution 1.586ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.427 2.902 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X134Y490 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X134Y490 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.041 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.615 5.656 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X94Y484 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.879 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/O net (fo=15, routed) 0.911 6.790 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X92Y497 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.243 10.958 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X92Y497 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/C clock pessimism 0.227 11.185 clock uncertainty -0.035 11.149 SLICE_X92Y497 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.056 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2] ------------------------------------------------------------------- required time 11.056 arrival time -6.790 ------------------------------------------------------------------- slack 4.266 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.144ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.048ns (20.168%) route 0.190ns (79.832%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.317ns Source Clock Delay (SCD): 1.075ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.957ns (routing 0.315ns, distribution 0.642ns) Clock Net Delay (Destination): 1.152ns (routing 0.355ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.075 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X90Y506 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.123 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.190 1.313 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X88Y506 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.152 1.317 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X88Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.153 1.164 SLICE_X88Y506 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.169 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.169 arrival time 1.313 ------------------------------------------------------------------- slack 0.144 Slack (MET) : 0.144ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.048ns (20.168%) route 0.190ns (79.832%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.317ns Source Clock Delay (SCD): 1.075ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.957ns (routing 0.315ns, distribution 0.642ns) Clock Net Delay (Destination): 1.152ns (routing 0.355ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.075 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X90Y506 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.123 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.190 1.313 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X88Y506 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.152 1.317 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X88Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.153 1.164 SLICE_X88Y506 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.169 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.169 arrival time 1.313 ------------------------------------------------------------------- slack 0.144 Slack (MET) : 0.144ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.048ns (20.168%) route 0.190ns (79.832%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.317ns Source Clock Delay (SCD): 1.075ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.957ns (routing 0.315ns, distribution 0.642ns) Clock Net Delay (Destination): 1.152ns (routing 0.355ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.075 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X90Y506 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.123 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.190 1.313 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X88Y506 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.152 1.317 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X88Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.153 1.164 SLICE_X88Y506 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.169 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -1.169 arrival time 1.313 ------------------------------------------------------------------- slack 0.144 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.248ns (logic 0.049ns (19.758%) route 0.199ns (80.242%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.300ns Source Clock Delay (SCD): 1.071ns Clock Pessimism Removal (CPR): 0.177ns Clock Net Delay (Source): 0.953ns (routing 0.315ns, distribution 0.638ns) Clock Net Delay (Destination): 1.135ns (routing 0.355ns, distribution 0.780ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.071 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X93Y495 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y495 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.120 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.199 1.319 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X92Y498 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.135 1.300 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X92Y498 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.177 1.123 SLICE_X92Y498 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.128 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.128 arrival time 1.319 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.193ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.048ns (17.582%) route 0.225ns (82.418%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.303ns Source Clock Delay (SCD): 1.075ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.957ns (routing 0.315ns, distribution 0.642ns) Clock Net Delay (Destination): 1.138ns (routing 0.355ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.075 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X90Y506 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.123 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.225 1.348 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X86Y506 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.138 1.303 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X86Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.153 1.150 SLICE_X86Y506 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.155 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.155 arrival time 1.348 ------------------------------------------------------------------- slack 0.193 Slack (MET) : 0.193ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.048ns (17.582%) route 0.225ns (82.418%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.303ns Source Clock Delay (SCD): 1.075ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.957ns (routing 0.315ns, distribution 0.642ns) Clock Net Delay (Destination): 1.138ns (routing 0.355ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.075 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X90Y506 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.123 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.225 1.348 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X86Y506 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.138 1.303 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X86Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.153 1.150 SLICE_X86Y506 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.155 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.155 arrival time 1.348 ------------------------------------------------------------------- slack 0.193 Slack (MET) : 0.193ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.048ns (17.582%) route 0.225ns (82.418%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.303ns Source Clock Delay (SCD): 1.075ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.957ns (routing 0.315ns, distribution 0.642ns) Clock Net Delay (Destination): 1.138ns (routing 0.355ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.075 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X90Y506 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.123 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.225 1.348 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X86Y506 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.138 1.303 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X86Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.153 1.150 SLICE_X86Y506 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.155 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.155 arrival time 1.348 ------------------------------------------------------------------- slack 0.193 Slack (MET) : 0.193ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.048ns (17.582%) route 0.225ns (82.418%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.303ns Source Clock Delay (SCD): 1.075ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.957ns (routing 0.315ns, distribution 0.642ns) Clock Net Delay (Destination): 1.138ns (routing 0.355ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.075 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X90Y506 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.123 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.225 1.348 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X86Y506 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.138 1.303 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X86Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C clock pessimism -0.153 1.150 SLICE_X86Y506 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.155 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -1.155 arrival time 1.348 ------------------------------------------------------------------- slack 0.193 Slack (MET) : 0.193ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.048ns (17.582%) route 0.225ns (82.418%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.303ns Source Clock Delay (SCD): 1.075ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.957ns (routing 0.315ns, distribution 0.642ns) Clock Net Delay (Destination): 1.138ns (routing 0.355ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.075 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X90Y506 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.123 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.225 1.348 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X86Y506 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.138 1.303 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X86Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.153 1.150 SLICE_X86Y506 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.155 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -1.155 arrival time 1.348 ------------------------------------------------------------------- slack 0.193 Slack (MET) : 0.193ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.048ns (17.582%) route 0.225ns (82.418%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.303ns Source Clock Delay (SCD): 1.075ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 0.957ns (routing 0.315ns, distribution 0.642ns) Clock Net Delay (Destination): 1.138ns (routing 0.355ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.075 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X90Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X90Y506 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.123 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.225 1.348 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X86Y506 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.138 1.303 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X86Y506 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.153 1.150 SLICE_X86Y506 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.155 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.155 arrival time 1.348 ------------------------------------------------------------------- slack 0.193 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_19 To Clock: gtwiz_userclk_rx_srcclk_out[0]_19 Setup : 0 Failing Endpoints, Worst Slack 4.404ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.162ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.404ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 3.804ns (logic 0.286ns (7.518%) route 3.518ns (92.482%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.019ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.707ns = ( 11.024 - 8.317 ) Source Clock Delay (SCD): 2.915ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.440ns (routing 0.723ns, distribution 1.717ns) Clock Net Delay (Destination): 2.309ns (routing 0.655ns, distribution 1.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.440 2.915 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y501 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.054 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.826 5.880 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X84Y491 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.027 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/O net (fo=15, routed) 0.692 6.719 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X83Y497 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.309 11.024 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C clock pessimism 0.227 11.252 clock uncertainty -0.035 11.216 SLICE_X83Y497 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.123 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1] ------------------------------------------------------------------- required time 11.123 arrival time -6.719 ------------------------------------------------------------------- slack 4.404 Slack (MET) : 4.404ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 3.804ns (logic 0.286ns (7.518%) route 3.518ns (92.482%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.019ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.707ns = ( 11.024 - 8.317 ) Source Clock Delay (SCD): 2.915ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.440ns (routing 0.723ns, distribution 1.717ns) Clock Net Delay (Destination): 2.309ns (routing 0.655ns, distribution 1.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.440 2.915 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y501 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.054 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.826 5.880 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X84Y491 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.027 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/O net (fo=15, routed) 0.692 6.719 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X83Y497 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.309 11.024 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C clock pessimism 0.227 11.252 clock uncertainty -0.035 11.216 SLICE_X83Y497 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 11.123 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2] ------------------------------------------------------------------- required time 11.123 arrival time -6.719 ------------------------------------------------------------------- slack 4.404 Slack (MET) : 4.404ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 3.804ns (logic 0.286ns (7.518%) route 3.518ns (92.482%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.019ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.707ns = ( 11.024 - 8.317 ) Source Clock Delay (SCD): 2.915ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.440ns (routing 0.723ns, distribution 1.717ns) Clock Net Delay (Destination): 2.309ns (routing 0.655ns, distribution 1.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.440 2.915 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y501 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.054 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.826 5.880 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X84Y491 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.027 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/O net (fo=15, routed) 0.692 6.719 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X83Y497 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.309 11.024 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C clock pessimism 0.227 11.252 clock uncertainty -0.035 11.216 SLICE_X83Y497 FDCE (Recov_AFF2_SLICEM_C_CLR) -0.093 11.123 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3] ------------------------------------------------------------------- required time 11.123 arrival time -6.719 ------------------------------------------------------------------- slack 4.404 Slack (MET) : 4.404ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 3.804ns (logic 0.286ns (7.518%) route 3.518ns (92.482%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.019ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.707ns = ( 11.024 - 8.317 ) Source Clock Delay (SCD): 2.915ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.440ns (routing 0.723ns, distribution 1.717ns) Clock Net Delay (Destination): 2.309ns (routing 0.655ns, distribution 1.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.440 2.915 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y501 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.054 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.826 5.880 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X84Y491 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.027 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/O net (fo=15, routed) 0.692 6.719 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X83Y497 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.309 11.024 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C clock pessimism 0.227 11.252 clock uncertainty -0.035 11.216 SLICE_X83Y497 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.123 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4] ------------------------------------------------------------------- required time 11.123 arrival time -6.719 ------------------------------------------------------------------- slack 4.404 Slack (MET) : 4.464ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 3.720ns (logic 0.286ns (7.688%) route 3.434ns (92.312%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.005ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.683ns = ( 11.000 - 8.317 ) Source Clock Delay (SCD): 2.915ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.440ns (routing 0.723ns, distribution 1.717ns) Clock Net Delay (Destination): 2.285ns (routing 0.655ns, distribution 1.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.440 2.915 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y501 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.054 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.826 5.880 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X84Y491 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.027 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/O net (fo=15, routed) 0.608 6.635 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X84Y496 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.285 11.000 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X84Y496 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/C clock pessimism 0.227 11.228 clock uncertainty -0.035 11.192 SLICE_X84Y496 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.099 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5] ------------------------------------------------------------------- required time 11.099 arrival time -6.635 ------------------------------------------------------------------- slack 4.464 Slack (MET) : 4.545ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 3.656ns (logic 0.286ns (7.823%) route 3.370ns (92.177%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.012ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.700ns = ( 11.017 - 8.317 ) Source Clock Delay (SCD): 2.915ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.440ns (routing 0.723ns, distribution 1.717ns) Clock Net Delay (Destination): 2.302ns (routing 0.655ns, distribution 1.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.440 2.915 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y501 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.054 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.826 5.880 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X84Y491 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.027 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/O net (fo=15, routed) 0.544 6.571 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X82Y493 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.302 11.017 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X82Y493 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/C clock pessimism 0.227 11.245 clock uncertainty -0.035 11.209 SLICE_X82Y493 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.116 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0] ------------------------------------------------------------------- required time 11.116 arrival time -6.571 ------------------------------------------------------------------- slack 4.545 Slack (MET) : 4.545ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 3.656ns (logic 0.286ns (7.823%) route 3.370ns (92.177%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.012ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.700ns = ( 11.017 - 8.317 ) Source Clock Delay (SCD): 2.915ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.440ns (routing 0.723ns, distribution 1.717ns) Clock Net Delay (Destination): 2.302ns (routing 0.655ns, distribution 1.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.440 2.915 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y501 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.054 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.826 5.880 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X84Y491 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.027 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/O net (fo=15, routed) 0.544 6.571 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X82Y493 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.302 11.017 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X82Y493 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/C clock pessimism 0.227 11.245 clock uncertainty -0.035 11.209 SLICE_X82Y493 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.116 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2] ------------------------------------------------------------------- required time 11.116 arrival time -6.571 ------------------------------------------------------------------- slack 4.545 Slack (MET) : 4.545ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 3.656ns (logic 0.286ns (7.823%) route 3.370ns (92.177%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.012ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.700ns = ( 11.017 - 8.317 ) Source Clock Delay (SCD): 2.915ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.440ns (routing 0.723ns, distribution 1.717ns) Clock Net Delay (Destination): 2.302ns (routing 0.655ns, distribution 1.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.440 2.915 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y501 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.054 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.826 5.880 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X84Y491 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.027 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/O net (fo=15, routed) 0.544 6.571 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X82Y493 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.302 11.017 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X82Y493 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C clock pessimism 0.227 11.245 clock uncertainty -0.035 11.209 SLICE_X82Y493 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.116 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3] ------------------------------------------------------------------- required time 11.116 arrival time -6.571 ------------------------------------------------------------------- slack 4.545 Slack (MET) : 4.550ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 3.649ns (logic 0.286ns (7.838%) route 3.363ns (92.162%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.698ns = ( 11.015 - 8.317 ) Source Clock Delay (SCD): 2.915ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.440ns (routing 0.723ns, distribution 1.717ns) Clock Net Delay (Destination): 2.300ns (routing 0.655ns, distribution 1.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.440 2.915 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y501 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.054 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.826 5.880 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X84Y491 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.027 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/O net (fo=15, routed) 0.537 6.564 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X82Y493 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.300 11.015 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X82Y493 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C clock pessimism 0.227 11.243 clock uncertainty -0.035 11.207 SLICE_X82Y493 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.114 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1] ------------------------------------------------------------------- required time 11.114 arrival time -6.564 ------------------------------------------------------------------- slack 4.550 Slack (MET) : 4.555ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 3.639ns (logic 0.286ns (7.859%) route 3.353ns (92.141%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.005ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.693ns = ( 11.010 - 8.317 ) Source Clock Delay (SCD): 2.915ns Clock Pessimism Removal (CPR): 0.227ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.440ns (routing 0.723ns, distribution 1.717ns) Clock Net Delay (Destination): 2.295ns (routing 0.655ns, distribution 1.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.440 2.915 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X136Y501 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X136Y501 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 3.054 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.826 5.880 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X84Y491 LUT3 (Prop_G6LUT_SLICEL_I0_O) 0.147 6.027 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0/O net (fo=15, routed) 0.527 6.554 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X82Y492 FDCE f g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.295 11.010 g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X82Y492 FDCE r g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/C clock pessimism 0.227 11.238 clock uncertainty -0.035 11.202 SLICE_X82Y492 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.109 g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4] ------------------------------------------------------------------- required time 11.109 arrival time -6.554 ------------------------------------------------------------------- slack 4.555 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.162ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.048ns (20.690%) route 0.184ns (79.310%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.003ns (routing 0.315ns, distribution 0.688ns) Clock Net Delay (Destination): 1.172ns (routing 0.355ns, distribution 0.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X83Y497 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.169 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.184 1.353 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X81Y497 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.337 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X81Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.151 1.186 SLICE_X81Y497 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.191 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.191 arrival time 1.353 ------------------------------------------------------------------- slack 0.162 Slack (MET) : 0.162ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.048ns (20.690%) route 0.184ns (79.310%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.003ns (routing 0.315ns, distribution 0.688ns) Clock Net Delay (Destination): 1.172ns (routing 0.355ns, distribution 0.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X83Y497 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.169 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.184 1.353 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X81Y497 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.337 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X81Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.151 1.186 SLICE_X81Y497 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.191 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.191 arrival time 1.353 ------------------------------------------------------------------- slack 0.162 Slack (MET) : 0.199ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.048ns (17.844%) route 0.221ns (82.156%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.003ns (routing 0.315ns, distribution 0.688ns) Clock Net Delay (Destination): 1.172ns (routing 0.355ns, distribution 0.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X83Y497 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.169 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.221 1.390 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X81Y496 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.337 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X81Y496 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.151 1.186 SLICE_X81Y496 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.191 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.191 arrival time 1.390 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.199ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.048ns (17.844%) route 0.221ns (82.156%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.003ns (routing 0.315ns, distribution 0.688ns) Clock Net Delay (Destination): 1.172ns (routing 0.355ns, distribution 0.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X83Y497 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.169 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.221 1.390 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X81Y496 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.337 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X81Y496 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.151 1.186 SLICE_X81Y496 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.191 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.191 arrival time 1.390 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.199ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.048ns (17.844%) route 0.221ns (82.156%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.003ns (routing 0.315ns, distribution 0.688ns) Clock Net Delay (Destination): 1.172ns (routing 0.355ns, distribution 0.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X83Y497 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.169 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.221 1.390 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X81Y496 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.337 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X81Y496 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.151 1.186 SLICE_X81Y496 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.191 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.191 arrival time 1.390 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.199ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.048ns (17.844%) route 0.221ns (82.156%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.003ns (routing 0.315ns, distribution 0.688ns) Clock Net Delay (Destination): 1.172ns (routing 0.355ns, distribution 0.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X83Y497 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.169 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.221 1.390 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X81Y496 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.337 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X81Y496 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.151 1.186 SLICE_X81Y496 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.191 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.191 arrival time 1.390 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.199ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.048ns (17.844%) route 0.221ns (82.156%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.003ns (routing 0.315ns, distribution 0.688ns) Clock Net Delay (Destination): 1.172ns (routing 0.355ns, distribution 0.817ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X83Y497 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.169 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.221 1.390 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X81Y496 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.337 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X81Y496 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.151 1.186 SLICE_X81Y496 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.191 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -1.191 arrival time 1.390 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.207ns (arrival time - required time) Source: SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[17].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.048ns (18.462%) route 0.212ns (81.538%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.356ns Source Clock Delay (SCD): 1.127ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.009ns (routing 0.315ns, distribution 0.694ns) Clock Net Delay (Destination): 1.191ns (routing 0.355ns, distribution 0.836ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.009 1.127 SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y482 FDPE r SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y482 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.175 f SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.212 1.387 SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] SLICE_X79Y481 FDCE f SFP_GEN[17].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.191 1.356 SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y481 FDCE r SFP_GEN[17].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.181 1.175 SLICE_X79Y481 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.180 SFP_GEN[17].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.180 arrival time 1.387 ------------------------------------------------------------------- slack 0.207 Slack (MET) : 0.218ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.310ns (logic 0.048ns (15.484%) route 0.262ns (84.516%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.003ns (routing 0.315ns, distribution 0.688ns) Clock Net Delay (Destination): 1.194ns (routing 0.355ns, distribution 0.839ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X83Y497 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.169 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.262 1.431 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X79Y497 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X79Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.151 1.208 SLICE_X79Y497 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.213 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.213 arrival time 1.431 ------------------------------------------------------------------- slack 0.218 Slack (MET) : 0.218ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns) Data Path Delay: 0.310ns (logic 0.048ns (15.484%) route 0.262ns (84.516%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.359ns Source Clock Delay (SCD): 1.121ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.003ns (routing 0.315ns, distribution 0.688ns) Clock Net Delay (Destination): 1.194ns (routing 0.355ns, distribution 0.839ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.003 1.121 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X83Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X83Y497 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.169 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.262 1.431 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X79Y497 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.194 1.359 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X79Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.151 1.208 SLICE_X79Y497 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.213 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.213 arrival time 1.431 ------------------------------------------------------------------- slack 0.218 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_2 To Clock: gtwiz_userclk_rx_srcclk_out[0]_2 Setup : 0 Failing Endpoints, Worst Slack 4.963ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.161ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.963ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.964ns (logic 0.364ns (12.281%) route 2.600ns (87.719%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.243ns = ( 10.560 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.845ns (routing 0.565ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.598 4.452 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X106Y235 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.677 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 1.002 5.679 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X106Y232 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.845 10.560 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X106Y232 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C clock pessimism 0.210 10.770 clock uncertainty -0.035 10.735 SLICE_X106Y232 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.642 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1] ------------------------------------------------------------------- required time 10.642 arrival time -5.679 ------------------------------------------------------------------- slack 4.963 Slack (MET) : 4.963ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.964ns (logic 0.364ns (12.281%) route 2.600ns (87.719%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.243ns = ( 10.560 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.845ns (routing 0.565ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.598 4.452 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X106Y235 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.677 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 1.002 5.679 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X106Y232 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.845 10.560 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X106Y232 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C clock pessimism 0.210 10.770 clock uncertainty -0.035 10.735 SLICE_X106Y232 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 10.642 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2] ------------------------------------------------------------------- required time 10.642 arrival time -5.679 ------------------------------------------------------------------- slack 4.963 Slack (MET) : 4.963ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.964ns (logic 0.364ns (12.281%) route 2.600ns (87.719%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.243ns = ( 10.560 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.845ns (routing 0.565ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.598 4.452 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X106Y235 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.677 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 1.002 5.679 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X106Y232 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.845 10.560 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X106Y232 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/C clock pessimism 0.210 10.770 clock uncertainty -0.035 10.735 SLICE_X106Y232 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.642 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3] ------------------------------------------------------------------- required time 10.642 arrival time -5.679 ------------------------------------------------------------------- slack 4.963 Slack (MET) : 4.963ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.964ns (logic 0.364ns (12.281%) route 2.600ns (87.719%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.243ns = ( 10.560 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.845ns (routing 0.565ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.598 4.452 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X106Y235 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.677 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 1.002 5.679 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X106Y232 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.845 10.560 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X106Y232 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/C clock pessimism 0.210 10.770 clock uncertainty -0.035 10.735 SLICE_X106Y232 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.642 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4] ------------------------------------------------------------------- required time 10.642 arrival time -5.679 ------------------------------------------------------------------- slack 4.963 Slack (MET) : 5.059ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.883ns (logic 0.286ns (9.920%) route 2.597ns (90.080%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.247ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.258ns = ( 10.575 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.860ns (routing 0.565ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.918 4.772 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X104Y236 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.147 4.919 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10/O net (fo=2, routed) 0.679 5.598 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X104Y236 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.860 10.575 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X104Y236 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.210 10.785 clock uncertainty -0.035 10.750 SLICE_X104Y236 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.657 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.657 arrival time -5.598 ------------------------------------------------------------------- slack 5.059 Slack (MET) : 5.059ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.883ns (logic 0.286ns (9.920%) route 2.597ns (90.080%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.247ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.258ns = ( 10.575 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.860ns (routing 0.565ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.918 4.772 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X104Y236 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.147 4.919 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10/O net (fo=2, routed) 0.679 5.598 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X104Y236 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.860 10.575 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X104Y236 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.210 10.785 clock uncertainty -0.035 10.750 SLICE_X104Y236 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.657 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.657 arrival time -5.598 ------------------------------------------------------------------- slack 5.059 Slack (MET) : 5.128ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.793ns (logic 0.364ns (13.033%) route 2.429ns (86.967%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.268ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.237ns = ( 10.554 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.839ns (routing 0.565ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.598 4.452 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X106Y235 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.677 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 0.831 5.508 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X105Y234 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.839 10.554 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X105Y234 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C clock pessimism 0.210 10.764 clock uncertainty -0.035 10.729 SLICE_X105Y234 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.636 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11] ------------------------------------------------------------------- required time 10.636 arrival time -5.508 ------------------------------------------------------------------- slack 5.128 Slack (MET) : 5.128ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.793ns (logic 0.364ns (13.033%) route 2.429ns (86.967%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.268ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.237ns = ( 10.554 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.839ns (routing 0.565ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.598 4.452 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X106Y235 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.677 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 0.831 5.508 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X105Y234 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.839 10.554 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X105Y234 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/C clock pessimism 0.210 10.764 clock uncertainty -0.035 10.729 SLICE_X105Y234 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.636 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0] ------------------------------------------------------------------- required time 10.636 arrival time -5.508 ------------------------------------------------------------------- slack 5.128 Slack (MET) : 5.128ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.793ns (logic 0.364ns (13.033%) route 2.429ns (86.967%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.268ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.237ns = ( 10.554 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.839ns (routing 0.565ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.598 4.452 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X106Y235 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.677 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 0.831 5.508 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X105Y234 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.839 10.554 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X105Y234 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/C clock pessimism 0.210 10.764 clock uncertainty -0.035 10.729 SLICE_X105Y234 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.636 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5] ------------------------------------------------------------------- required time 10.636 arrival time -5.508 ------------------------------------------------------------------- slack 5.128 Slack (MET) : 5.285ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 2.649ns (logic 0.364ns (13.741%) route 2.285ns (86.259%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.255ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.250ns = ( 10.567 - 8.317 ) Source Clock Delay (SCD): 2.715ns Clock Pessimism Removal (CPR): 0.210ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.240ns (routing 0.624ns, distribution 1.616ns) Clock Net Delay (Destination): 1.852ns (routing 0.565ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 2.240 2.715 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y236 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y236 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.854 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.598 4.452 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X106Y235 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.677 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/O net (fo=15, routed) 0.687 5.364 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X104Y234 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 1.852 10.567 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] SLICE_X104Y234 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C clock pessimism 0.210 10.777 clock uncertainty -0.035 10.742 SLICE_X104Y234 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.649 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0] ------------------------------------------------------------------- required time 10.649 arrival time -5.364 ------------------------------------------------------------------- slack 5.285 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.161ns (arrival time - required time) Source: SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.244ns (logic 0.048ns (19.672%) route 0.196ns (80.328%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.106ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.782ns (routing 0.265ns, distribution 0.517ns) Clock Net Delay (Destination): 0.941ns (routing 0.303ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y234 FDPE r SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y234 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.948 f SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.196 1.144 SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] SLICE_X109Y234 FDCE f SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.941 1.106 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y234 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.128 0.978 SLICE_X109Y234 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 0.983 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -0.983 arrival time 1.144 ------------------------------------------------------------------- slack 0.161 Slack (MET) : 0.161ns (arrival time - required time) Source: SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.244ns (logic 0.048ns (19.672%) route 0.196ns (80.328%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.106ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.782ns (routing 0.265ns, distribution 0.517ns) Clock Net Delay (Destination): 0.941ns (routing 0.303ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y234 FDPE r SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y234 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.948 f SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.196 1.144 SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] SLICE_X109Y234 FDCE f SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.941 1.106 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X109Y234 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism -0.128 0.978 SLICE_X109Y234 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 0.983 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time -0.983 arrival time 1.144 ------------------------------------------------------------------- slack 0.161 Slack (MET) : 0.172ns (arrival time - required time) Source: SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.271ns (logic 0.048ns (17.712%) route 0.223ns (82.288%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.122ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.782ns (routing 0.265ns, distribution 0.517ns) Clock Net Delay (Destination): 0.957ns (routing 0.303ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y234 FDPE r SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y234 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.948 f SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.223 1.171 SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] SLICE_X107Y236 FDCE f SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.122 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y236 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16]/C clock pessimism -0.128 0.994 SLICE_X107Y236 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 0.999 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[16] ------------------------------------------------------------------- required time -0.999 arrival time 1.171 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.271ns (logic 0.048ns (17.712%) route 0.223ns (82.288%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.122ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.782ns (routing 0.265ns, distribution 0.517ns) Clock Net Delay (Destination): 0.957ns (routing 0.303ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y234 FDPE r SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y234 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.948 f SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.223 1.171 SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] SLICE_X107Y236 FDCE f SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.122 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y236 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[17]/C clock pessimism -0.128 0.994 SLICE_X107Y236 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 0.999 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[17] ------------------------------------------------------------------- required time -0.999 arrival time 1.171 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.271ns (logic 0.048ns (17.712%) route 0.223ns (82.288%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.122ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.782ns (routing 0.265ns, distribution 0.517ns) Clock Net Delay (Destination): 0.957ns (routing 0.303ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y234 FDPE r SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y234 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.948 f SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.223 1.171 SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] SLICE_X107Y236 FDCE f SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.122 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y236 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.128 0.994 SLICE_X107Y236 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 0.999 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -0.999 arrival time 1.171 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.271ns (logic 0.048ns (17.712%) route 0.223ns (82.288%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.122ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.782ns (routing 0.265ns, distribution 0.517ns) Clock Net Delay (Destination): 0.957ns (routing 0.303ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y234 FDPE r SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y234 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.948 f SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.223 1.171 SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] SLICE_X107Y236 FDCE f SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.122 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y236 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[22]/C clock pessimism -0.128 0.994 SLICE_X107Y236 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 0.999 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[22] ------------------------------------------------------------------- required time -0.999 arrival time 1.171 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.271ns (logic 0.048ns (17.712%) route 0.223ns (82.288%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.122ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.782ns (routing 0.265ns, distribution 0.517ns) Clock Net Delay (Destination): 0.957ns (routing 0.303ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y234 FDPE r SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y234 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.948 f SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.223 1.171 SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] SLICE_X107Y236 FDCE f SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.122 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y236 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[24]/C clock pessimism -0.128 0.994 SLICE_X107Y236 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 0.999 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[24] ------------------------------------------------------------------- required time -0.999 arrival time 1.171 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.271ns (logic 0.048ns (17.712%) route 0.223ns (82.288%)) Logic Levels: 0 Clock Path Skew: 0.094ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.122ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.782ns (routing 0.265ns, distribution 0.517ns) Clock Net Delay (Destination): 0.957ns (routing 0.303ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y234 FDPE r SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y234 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.948 f SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.223 1.171 SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] SLICE_X107Y236 FDCE f SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.957 1.122 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X107Y236 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[31]/C clock pessimism -0.128 0.994 SLICE_X107Y236 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 0.999 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[31] ------------------------------------------------------------------- required time -0.999 arrival time 1.171 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.223ns (logic 0.048ns (21.525%) route 0.175ns (78.475%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.106ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.782ns (routing 0.265ns, distribution 0.517ns) Clock Net Delay (Destination): 0.941ns (routing 0.303ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y234 FDPE r SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y234 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.948 f SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.175 1.123 SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] SLICE_X106Y236 FDCE f SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.941 1.106 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y236 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism -0.160 0.946 SLICE_X106Y236 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 0.951 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time -0.951 arrival time 1.123 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns) Data Path Delay: 0.223ns (logic 0.048ns (21.525%) route 0.175ns (78.475%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.106ns Source Clock Delay (SCD): 0.900ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.782ns (routing 0.265ns, distribution 0.517ns) Clock Net Delay (Destination): 0.941ns (routing 0.303ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.782 0.900 SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y234 FDPE r SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y234 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.948 f SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.175 1.123 SFP_GEN[11].ngCCM_gbt/sync_m_reg[3][0] SLICE_X106Y236 FDCE f SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y3 (CLOCK_ROOT) net (fo=674, routed) 0.941 1.106 SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X106Y236 FDCE r SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[19]/C clock pessimism -0.160 0.946 SLICE_X106Y236 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 0.951 SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[19] ------------------------------------------------------------------- required time -0.951 arrival time 1.123 ------------------------------------------------------------------- slack 0.172 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_20 To Clock: gtwiz_userclk_rx_srcclk_out[0]_20 Setup : 0 Failing Endpoints, Worst Slack 5.139ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.143ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.139ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/headerFlag_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 2.852ns (logic 0.139ns (4.874%) route 2.713ns (95.126%)) Logic Levels: 0 Clock Path Skew: -0.198ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.609ns = ( 10.926 - 8.317 ) Source Clock Delay (SCD): 3.064ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.589ns (routing 0.728ns, distribution 1.861ns) Clock Net Delay (Destination): 2.211ns (routing 0.660ns, distribution 1.551ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.589 3.064 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.203 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.713 5.916 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X95Y498 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/headerFlag_s_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.211 10.926 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X95Y498 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/headerFlag_s_reg/C clock pessimism 0.257 11.183 clock uncertainty -0.035 11.148 SLICE_X95Y498 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.055 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/headerFlag_s_reg ------------------------------------------------------------------- required time 11.055 arrival time -5.916 ------------------------------------------------------------------- slack 5.139 Slack (MET) : 5.239ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/RX_HEADER_LOCKED_O_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 2.758ns (logic 0.139ns (5.040%) route 2.619ns (94.960%)) Logic Levels: 0 Clock Path Skew: -0.192ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.615ns = ( 10.932 - 8.317 ) Source Clock Delay (SCD): 3.064ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.589ns (routing 0.728ns, distribution 1.861ns) Clock Net Delay (Destination): 2.217ns (routing 0.660ns, distribution 1.557ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.589 3.064 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.203 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.619 5.822 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X94Y497 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/RX_HEADER_LOCKED_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.217 10.932 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X94Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/RX_HEADER_LOCKED_O_reg/C clock pessimism 0.257 11.189 clock uncertainty -0.035 11.154 SLICE_X94Y497 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.061 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/RX_HEADER_LOCKED_O_reg ------------------------------------------------------------------- required time 11.061 arrival time -5.822 ------------------------------------------------------------------- slack 5.239 Slack (MET) : 5.302ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 2.697ns (logic 0.139ns (5.154%) route 2.558ns (94.846%)) Logic Levels: 0 Clock Path Skew: -0.190ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.618ns = ( 10.935 - 8.317 ) Source Clock Delay (SCD): 3.064ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.589ns (routing 0.728ns, distribution 1.861ns) Clock Net Delay (Destination): 2.220ns (routing 0.660ns, distribution 1.560ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.589 3.064 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.203 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.558 5.761 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X95Y497 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.220 10.935 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X95Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.257 11.192 clock uncertainty -0.035 11.156 SLICE_X95Y497 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.063 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 11.063 arrival time -5.761 ------------------------------------------------------------------- slack 5.302 Slack (MET) : 5.302ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 2.697ns (logic 0.139ns (5.154%) route 2.558ns (94.846%)) Logic Levels: 0 Clock Path Skew: -0.190ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.618ns = ( 10.935 - 8.317 ) Source Clock Delay (SCD): 3.064ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.589ns (routing 0.728ns, distribution 1.861ns) Clock Net Delay (Destination): 2.220ns (routing 0.660ns, distribution 1.560ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.589 3.064 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.203 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.558 5.761 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X95Y497 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.220 10.935 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X95Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.257 11.192 clock uncertainty -0.035 11.156 SLICE_X95Y497 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.063 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 11.063 arrival time -5.761 ------------------------------------------------------------------- slack 5.302 Slack (MET) : 5.307ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 2.690ns (logic 0.139ns (5.167%) route 2.551ns (94.833%)) Logic Levels: 0 Clock Path Skew: -0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.616ns = ( 10.933 - 8.317 ) Source Clock Delay (SCD): 3.064ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.589ns (routing 0.728ns, distribution 1.861ns) Clock Net Delay (Destination): 2.218ns (routing 0.660ns, distribution 1.558ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.589 3.064 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.203 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.551 5.754 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X95Y497 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.218 10.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X95Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[0]/C clock pessimism 0.257 11.190 clock uncertainty -0.035 11.154 SLICE_X95Y497 FDCE (Recov_GFF2_SLICEM_C_CLR) -0.093 11.061 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[0] ------------------------------------------------------------------- required time 11.061 arrival time -5.754 ------------------------------------------------------------------- slack 5.307 Slack (MET) : 5.307ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 2.690ns (logic 0.139ns (5.167%) route 2.551ns (94.833%)) Logic Levels: 0 Clock Path Skew: -0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.616ns = ( 10.933 - 8.317 ) Source Clock Delay (SCD): 3.064ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.589ns (routing 0.728ns, distribution 1.861ns) Clock Net Delay (Destination): 2.218ns (routing 0.660ns, distribution 1.558ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.589 3.064 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.203 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.551 5.754 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X95Y497 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.218 10.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X95Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[1]/C clock pessimism 0.257 11.190 clock uncertainty -0.035 11.154 SLICE_X95Y497 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.061 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[1] ------------------------------------------------------------------- required time 11.061 arrival time -5.754 ------------------------------------------------------------------- slack 5.307 Slack (MET) : 5.307ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 2.690ns (logic 0.139ns (5.167%) route 2.551ns (94.833%)) Logic Levels: 0 Clock Path Skew: -0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.616ns = ( 10.933 - 8.317 ) Source Clock Delay (SCD): 3.064ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.589ns (routing 0.728ns, distribution 1.861ns) Clock Net Delay (Destination): 2.218ns (routing 0.660ns, distribution 1.558ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.589 3.064 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.203 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.551 5.754 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X95Y497 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.218 10.933 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X95Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[2]/C clock pessimism 0.257 11.190 clock uncertainty -0.035 11.154 SLICE_X95Y497 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 11.061 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/psAddress_reg[2] ------------------------------------------------------------------- required time 11.061 arrival time -5.754 ------------------------------------------------------------------- slack 5.307 Slack (MET) : 5.478ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 2.204ns (logic 0.139ns (6.307%) route 2.065ns (93.693%)) Logic Levels: 0 Clock Path Skew: -0.507ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.326ns = ( 10.643 - 8.317 ) Source Clock Delay (SCD): 3.064ns Clock Pessimism Removal (CPR): 0.231ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.589ns (routing 0.728ns, distribution 1.861ns) Clock Net Delay (Destination): 1.928ns (routing 0.660ns, distribution 1.268ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.589 3.064 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.203 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.065 5.268 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/AS[0] SLICE_X99Y498 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.928 10.643 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/CLK SLICE_X99Y498 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C clock pessimism 0.231 10.874 clock uncertainty -0.035 10.839 SLICE_X99Y498 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.746 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg ------------------------------------------------------------------- required time 10.746 arrival time -5.268 ------------------------------------------------------------------- slack 5.478 Slack (MET) : 5.565ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 2.110ns (logic 0.139ns (6.588%) route 1.971ns (93.412%)) Logic Levels: 0 Clock Path Skew: -0.514ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.319ns = ( 10.636 - 8.317 ) Source Clock Delay (SCD): 3.064ns Clock Pessimism Removal (CPR): 0.231ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.589ns (routing 0.728ns, distribution 1.861ns) Clock Net Delay (Destination): 1.921ns (routing 0.660ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.589 3.064 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.203 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.971 5.174 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X97Y497 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.921 10.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X97Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/C clock pessimism 0.231 10.867 clock uncertainty -0.035 10.832 SLICE_X97Y497 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.739 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0] ------------------------------------------------------------------- required time 10.739 arrival time -5.174 ------------------------------------------------------------------- slack 5.565 Slack (MET) : 5.565ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 2.110ns (logic 0.139ns (6.588%) route 1.971ns (93.412%)) Logic Levels: 0 Clock Path Skew: -0.514ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.319ns = ( 10.636 - 8.317 ) Source Clock Delay (SCD): 3.064ns Clock Pessimism Removal (CPR): 0.231ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.589ns (routing 0.728ns, distribution 1.861ns) Clock Net Delay (Destination): 1.921ns (routing 0.660ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.589 3.064 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y486 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y486 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.203 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.971 5.174 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X97Y497 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.921 10.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X97Y497 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/C clock pessimism 0.231 10.867 clock uncertainty -0.035 10.832 SLICE_X97Y497 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 10.739 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1] ------------------------------------------------------------------- required time 10.739 arrival time -5.174 ------------------------------------------------------------------- slack 5.565 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.143ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.217ns (logic 0.049ns (22.581%) route 0.168ns (77.419%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.832ns (routing 0.314ns, distribution 0.518ns) Clock Net Delay (Destination): 0.986ns (routing 0.355ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.832 0.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X97Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X97Y485 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.999 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.168 1.167 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X96Y485 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.132 1.019 SLICE_X96Y485 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.024 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.024 arrival time 1.167 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.143ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.217ns (logic 0.049ns (22.581%) route 0.168ns (77.419%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.832ns (routing 0.314ns, distribution 0.518ns) Clock Net Delay (Destination): 0.986ns (routing 0.355ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.832 0.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X97Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X97Y485 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.999 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.168 1.167 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X96Y485 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.132 1.019 SLICE_X96Y485 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.024 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.024 arrival time 1.167 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.143ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.217ns (logic 0.049ns (22.581%) route 0.168ns (77.419%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.832ns (routing 0.314ns, distribution 0.518ns) Clock Net Delay (Destination): 0.986ns (routing 0.355ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.832 0.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X97Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X97Y485 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.999 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.168 1.167 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X96Y485 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.132 1.019 SLICE_X96Y485 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.024 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.024 arrival time 1.167 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.143ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.217ns (logic 0.049ns (22.581%) route 0.168ns (77.419%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.832ns (routing 0.314ns, distribution 0.518ns) Clock Net Delay (Destination): 0.986ns (routing 0.355ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.832 0.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X97Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X97Y485 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.999 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.168 1.167 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X96Y485 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.132 1.019 SLICE_X96Y485 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.024 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.024 arrival time 1.167 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.143ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.217ns (logic 0.049ns (22.581%) route 0.168ns (77.419%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.832ns (routing 0.314ns, distribution 0.518ns) Clock Net Delay (Destination): 0.986ns (routing 0.355ns, distribution 0.631ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.832 0.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X97Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X97Y485 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.999 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.168 1.167 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X96Y485 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.986 1.151 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.132 1.019 SLICE_X96Y485 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.024 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.024 arrival time 1.167 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.186ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.278ns (logic 0.049ns (17.626%) route 0.229ns (82.374%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.941ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.823ns (routing 0.314ns, distribution 0.509ns) Clock Net Delay (Destination): 0.995ns (routing 0.355ns, distribution 0.640ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.823 0.941 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X96Y481 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y481 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.990 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.229 1.219 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X97Y485 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.995 1.160 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X97Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C clock pessimism -0.132 1.028 SLICE_X97Y485 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.033 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg ------------------------------------------------------------------- required time -1.033 arrival time 1.219 ------------------------------------------------------------------- slack 0.186 Slack (MET) : 0.190ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.061ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.143ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.832ns (routing 0.314ns, distribution 0.518ns) Clock Net Delay (Destination): 0.978ns (routing 0.355ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.832 0.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X97Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X97Y485 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.999 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.207 1.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X96Y484 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.143 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.132 1.011 SLICE_X96Y484 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.016 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.016 arrival time 1.206 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.190ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.061ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.143ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.832ns (routing 0.314ns, distribution 0.518ns) Clock Net Delay (Destination): 0.978ns (routing 0.355ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.832 0.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X97Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X97Y485 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.999 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.207 1.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X96Y484 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.143 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.132 1.011 SLICE_X96Y484 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.016 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.016 arrival time 1.206 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.190ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.061ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.143ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.832ns (routing 0.314ns, distribution 0.518ns) Clock Net Delay (Destination): 0.978ns (routing 0.355ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.832 0.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X97Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X97Y485 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.999 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.207 1.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X96Y484 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.143 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.132 1.011 SLICE_X96Y484 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.016 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.016 arrival time 1.206 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.190ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.061ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.143ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 0.832ns (routing 0.314ns, distribution 0.518ns) Clock Net Delay (Destination): 0.978ns (routing 0.355ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.832 0.950 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X97Y485 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X97Y485 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 0.999 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.207 1.206 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X96Y484 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.143 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X96Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.132 1.011 SLICE_X96Y484 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.016 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.016 arrival time 1.206 ------------------------------------------------------------------- slack 0.190 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_21 To Clock: gtwiz_userclk_rx_srcclk_out[0]_21 Setup : 0 Failing Endpoints, Worst Slack 5.343ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.186ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.343ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.298ns (logic 0.139ns (6.049%) route 2.159ns (93.951%)) Logic Levels: 0 Clock Path Skew: -0.548ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.226ns = ( 10.543 - 8.317 ) Source Clock Delay (SCD): 2.994ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.519ns (routing 0.624ns, distribution 1.895ns) Clock Net Delay (Destination): 1.828ns (routing 0.565ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.519 2.994 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.133 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.159 5.292 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/AS[0] SLICE_X112Y492 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.828 10.543 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/CLK SLICE_X112Y492 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C clock pessimism 0.220 10.763 clock uncertainty -0.035 10.728 SLICE_X112Y492 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.635 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/RX_BITSLIPCMD_o_reg ------------------------------------------------------------------- required time 10.635 arrival time -5.292 ------------------------------------------------------------------- slack 5.343 Slack (MET) : 5.378ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.264ns (logic 0.139ns (6.140%) route 2.125ns (93.860%)) Logic Levels: 0 Clock Path Skew: -0.547ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.227ns = ( 10.544 - 8.317 ) Source Clock Delay (SCD): 2.994ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.519ns (routing 0.624ns, distribution 1.895ns) Clock Net Delay (Destination): 1.829ns (routing 0.565ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.519 2.994 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.133 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.125 5.258 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitslip_reset_7 SLICE_X111Y493 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.829 10.544 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK SLICE_X111Y493 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[0]/C clock pessimism 0.220 10.764 clock uncertainty -0.035 10.729 SLICE_X111Y493 FDCE (Recov_GFF2_SLICEL_C_CLR) -0.093 10.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[0] ------------------------------------------------------------------- required time 10.636 arrival time -5.258 ------------------------------------------------------------------- slack 5.378 Slack (MET) : 5.378ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.264ns (logic 0.139ns (6.140%) route 2.125ns (93.860%)) Logic Levels: 0 Clock Path Skew: -0.547ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.227ns = ( 10.544 - 8.317 ) Source Clock Delay (SCD): 2.994ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.519ns (routing 0.624ns, distribution 1.895ns) Clock Net Delay (Destination): 1.829ns (routing 0.565ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.519 2.994 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.133 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.125 5.258 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitslip_reset_7 SLICE_X111Y493 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.829 10.544 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK SLICE_X111Y493 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[1]/C clock pessimism 0.220 10.764 clock uncertainty -0.035 10.729 SLICE_X111Y493 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[1] ------------------------------------------------------------------- required time 10.636 arrival time -5.258 ------------------------------------------------------------------- slack 5.378 Slack (MET) : 5.378ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.264ns (logic 0.139ns (6.140%) route 2.125ns (93.860%)) Logic Levels: 0 Clock Path Skew: -0.547ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.227ns = ( 10.544 - 8.317 ) Source Clock Delay (SCD): 2.994ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.519ns (routing 0.624ns, distribution 1.895ns) Clock Net Delay (Destination): 1.829ns (routing 0.565ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.519 2.994 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.133 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.125 5.258 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitslip_reset_7 SLICE_X111Y493 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.829 10.544 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK SLICE_X111Y493 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]/C clock pessimism 0.220 10.764 clock uncertainty -0.035 10.729 SLICE_X111Y493 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.636 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2] ------------------------------------------------------------------- required time 10.636 arrival time -5.258 ------------------------------------------------------------------- slack 5.378 Slack (MET) : 5.421ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.261ns (logic 0.286ns (12.649%) route 1.975ns (87.351%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.507ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.268ns = ( 10.585 - 8.317 ) Source Clock Delay (SCD): 2.994ns Clock Pessimism Removal (CPR): 0.219ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.519ns (routing 0.624ns, distribution 1.895ns) Clock Net Delay (Destination): 1.870ns (routing 0.565ns, distribution 1.305ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.519 2.994 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.133 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.252 4.385 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X104Y480 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.147 4.532 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__18/O net (fo=2, routed) 0.723 5.255 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X104Y480 FDCE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.870 10.585 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X104Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.219 10.805 clock uncertainty -0.035 10.769 SLICE_X104Y480 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.676 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.676 arrival time -5.255 ------------------------------------------------------------------- slack 5.421 Slack (MET) : 5.421ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.261ns (logic 0.286ns (12.649%) route 1.975ns (87.351%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.507ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.268ns = ( 10.585 - 8.317 ) Source Clock Delay (SCD): 2.994ns Clock Pessimism Removal (CPR): 0.219ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.519ns (routing 0.624ns, distribution 1.895ns) Clock Net Delay (Destination): 1.870ns (routing 0.565ns, distribution 1.305ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.519 2.994 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.133 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.252 4.385 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X104Y480 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.147 4.532 f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__18/O net (fo=2, routed) 0.723 5.255 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X104Y480 FDCE f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.870 10.585 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X104Y480 FDCE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.219 10.805 clock uncertainty -0.035 10.769 SLICE_X104Y480 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.676 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.676 arrival time -5.255 ------------------------------------------------------------------- slack 5.421 Slack (MET) : 5.429ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv/PRE (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.223ns (logic 0.139ns (6.253%) route 2.084ns (93.747%)) Logic Levels: 0 Clock Path Skew: -0.537ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.237ns = ( 10.554 - 8.317 ) Source Clock Delay (SCD): 2.994ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.519ns (routing 0.624ns, distribution 1.895ns) Clock Net Delay (Destination): 1.839ns (routing 0.565ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.519 2.994 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.133 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.084 5.217 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitslip_reset_7 SLICE_X110Y492 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.839 10.554 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK SLICE_X110Y492 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv/C clock pessimism 0.220 10.774 clock uncertainty -0.035 10.739 SLICE_X110Y492 FDPE (Recov_DFF_SLICEM_C_PRE) -0.093 10.646 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/shiftPsAddr_reg_inv ------------------------------------------------------------------- required time 10.646 arrival time -5.217 ------------------------------------------------------------------- slack 5.429 Slack (MET) : 5.434ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.216ns (logic 0.139ns (6.273%) route 2.077ns (93.727%)) Logic Levels: 0 Clock Path Skew: -0.539ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.235ns = ( 10.552 - 8.317 ) Source Clock Delay (SCD): 2.994ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.519ns (routing 0.624ns, distribution 1.895ns) Clock Net Delay (Destination): 1.837ns (routing 0.565ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.519 2.994 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.133 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.077 5.210 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitslip_reset_7 SLICE_X110Y492 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.837 10.552 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK SLICE_X110Y492 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/C clock pessimism 0.220 10.772 clock uncertainty -0.035 10.737 SLICE_X110Y492 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 10.644 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2] ------------------------------------------------------------------- required time 10.644 arrival time -5.210 ------------------------------------------------------------------- slack 5.434 Slack (MET) : 5.515ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.146ns (logic 0.139ns (6.477%) route 2.007ns (93.523%)) Logic Levels: 0 Clock Path Skew: -0.528ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.246ns = ( 10.563 - 8.317 ) Source Clock Delay (SCD): 2.994ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.519ns (routing 0.624ns, distribution 1.895ns) Clock Net Delay (Destination): 1.848ns (routing 0.565ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.519 2.994 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.133 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.007 5.140 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitslip_reset_7 SLICE_X111Y491 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.848 10.563 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/CLK SLICE_X111Y491 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/C clock pessimism 0.220 10.783 clock uncertainty -0.035 10.748 SLICE_X111Y491 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.655 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg ------------------------------------------------------------------- required time 10.655 arrival time -5.140 ------------------------------------------------------------------- slack 5.515 Slack (MET) : 5.515ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 2.146ns (logic 0.139ns (6.477%) route 2.007ns (93.523%)) Logic Levels: 0 Clock Path Skew: -0.528ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.246ns = ( 10.563 - 8.317 ) Source Clock Delay (SCD): 2.994ns Clock Pessimism Removal (CPR): 0.220ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.519ns (routing 0.624ns, distribution 1.895ns) Clock Net Delay (Destination): 1.848ns (routing 0.565ns, distribution 1.283ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 2.519 2.994 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X93Y484 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X93Y484 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.133 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.007 5.140 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/AS[0] SLICE_X111Y491 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 1.848 10.563 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/CLK SLICE_X111Y491 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/C clock pessimism 0.220 10.783 clock uncertainty -0.035 10.748 SLICE_X111Y491 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.655 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time 10.655 arrival time -5.140 ------------------------------------------------------------------- slack 5.515 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.186ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.049ns (18.992%) route 0.209ns (81.008%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.100ns Source Clock Delay (SCD): 0.905ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.787ns (routing 0.265ns, distribution 0.522ns) Clock Net Delay (Destination): 0.935ns (routing 0.303ns, distribution 0.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.787 0.905 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X105Y480 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X105Y480 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.954 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.209 1.163 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X106Y482 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.935 1.100 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X106Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C clock pessimism -0.128 0.972 SLICE_X106Y482 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 0.977 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] ------------------------------------------------------------------- required time -0.977 arrival time 1.163 ------------------------------------------------------------------- slack 0.186 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.049ns (18.216%) route 0.220ns (81.784%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.107ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.788ns (routing 0.265ns, distribution 0.523ns) Clock Net Delay (Destination): 0.942ns (routing 0.303ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y482 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.955 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.220 1.175 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X106Y483 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.942 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X106Y483 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C clock pessimism -0.128 0.979 SLICE_X106Y483 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 0.984 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -0.984 arrival time 1.175 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.049ns (18.216%) route 0.220ns (81.784%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.107ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.788ns (routing 0.265ns, distribution 0.523ns) Clock Net Delay (Destination): 0.942ns (routing 0.303ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y482 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.955 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.220 1.175 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X106Y483 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.942 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X106Y483 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.128 0.979 SLICE_X106Y483 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 0.984 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -0.984 arrival time 1.175 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.049ns (18.216%) route 0.220ns (81.784%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.107ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.788ns (routing 0.265ns, distribution 0.523ns) Clock Net Delay (Destination): 0.942ns (routing 0.303ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y482 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.955 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.220 1.175 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X106Y483 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.942 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X106Y483 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.128 0.979 SLICE_X106Y483 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 0.984 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -0.984 arrival time 1.175 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.049ns (18.216%) route 0.220ns (81.784%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.107ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.788ns (routing 0.265ns, distribution 0.523ns) Clock Net Delay (Destination): 0.942ns (routing 0.303ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y482 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.955 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.220 1.175 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X106Y483 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.942 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X106Y483 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.128 0.979 SLICE_X106Y483 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 0.984 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -0.984 arrival time 1.175 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.049ns (18.216%) route 0.220ns (81.784%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.107ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.788ns (routing 0.265ns, distribution 0.523ns) Clock Net Delay (Destination): 0.942ns (routing 0.303ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y482 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.955 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.220 1.175 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X106Y483 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.942 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X106Y483 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.128 0.979 SLICE_X106Y483 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 0.984 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -0.984 arrival time 1.175 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.049ns (18.216%) route 0.220ns (81.784%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.107ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.788ns (routing 0.265ns, distribution 0.523ns) Clock Net Delay (Destination): 0.942ns (routing 0.303ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y482 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.955 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.220 1.175 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X106Y483 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.942 1.107 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X106Y483 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.128 0.979 SLICE_X106Y483 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 0.984 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -0.984 arrival time 1.175 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.207ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.293ns (logic 0.049ns (16.724%) route 0.244ns (83.276%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.115ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.788ns (routing 0.265ns, distribution 0.523ns) Clock Net Delay (Destination): 0.950ns (routing 0.303ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y482 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.955 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.244 1.199 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X111Y487 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.950 1.115 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X111Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.128 0.987 SLICE_X111Y487 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.992 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -0.992 arrival time 1.199 ------------------------------------------------------------------- slack 0.207 Slack (MET) : 0.207ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.293ns (logic 0.049ns (16.724%) route 0.244ns (83.276%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.115ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.788ns (routing 0.265ns, distribution 0.523ns) Clock Net Delay (Destination): 0.950ns (routing 0.303ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y482 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X107Y482 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 0.955 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.244 1.199 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X111Y487 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.950 1.115 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X111Y487 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.128 0.987 SLICE_X111Y487 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 0.992 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -0.992 arrival time 1.199 ------------------------------------------------------------------- slack 0.207 Slack (MET) : 0.210ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns) Data Path Delay: 0.282ns (logic 0.049ns (17.376%) route 0.233ns (82.624%)) Logic Levels: 0 Clock Path Skew: 0.067ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.100ns Source Clock Delay (SCD): 0.905ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.787ns (routing 0.265ns, distribution 0.522ns) Clock Net Delay (Destination): 0.935ns (routing 0.303ns, distribution 0.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.787 0.905 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X105Y480 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X105Y480 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.954 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.233 1.187 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X106Y481 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y8 (CLOCK_ROOT) net (fo=674, routed) 0.935 1.100 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X106Y481 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.128 0.972 SLICE_X106Y481 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 0.977 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.977 arrival time 1.187 ------------------------------------------------------------------- slack 0.210 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_22 To Clock: gtwiz_userclk_rx_srcclk_out[0]_22 Setup : 0 Failing Endpoints, Worst Slack 5.109ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.209ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.109ns (required time - arrival time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.561ns (logic 0.139ns (5.428%) route 2.422ns (94.572%)) Logic Levels: 0 Clock Path Skew: -0.519ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.198ns = ( 10.515 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.612ns, distribution 1.846ns) Clock Net Delay (Destination): 1.800ns (routing 0.555ns, distribution 1.245ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y543 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.072 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.422 5.494 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X116Y544 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.800 10.515 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y544 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[60]/C clock pessimism 0.216 10.731 clock uncertainty -0.035 10.696 SLICE_X116Y544 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.603 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[60] ------------------------------------------------------------------- required time 10.603 arrival time -5.494 ------------------------------------------------------------------- slack 5.109 Slack (MET) : 5.109ns (required time - arrival time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.561ns (logic 0.139ns (5.428%) route 2.422ns (94.572%)) Logic Levels: 0 Clock Path Skew: -0.519ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.198ns = ( 10.515 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.612ns, distribution 1.846ns) Clock Net Delay (Destination): 1.800ns (routing 0.555ns, distribution 1.245ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y543 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.072 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.422 5.494 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X116Y544 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.800 10.515 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y544 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[62]/C clock pessimism 0.216 10.731 clock uncertainty -0.035 10.696 SLICE_X116Y544 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.603 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[62] ------------------------------------------------------------------- required time 10.603 arrival time -5.494 ------------------------------------------------------------------- slack 5.109 Slack (MET) : 5.109ns (required time - arrival time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.561ns (logic 0.139ns (5.428%) route 2.422ns (94.572%)) Logic Levels: 0 Clock Path Skew: -0.519ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.198ns = ( 10.515 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.612ns, distribution 1.846ns) Clock Net Delay (Destination): 1.800ns (routing 0.555ns, distribution 1.245ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y543 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.072 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.422 5.494 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X116Y544 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.800 10.515 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y544 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[64]/C clock pessimism 0.216 10.731 clock uncertainty -0.035 10.696 SLICE_X116Y544 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.603 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[64] ------------------------------------------------------------------- required time 10.603 arrival time -5.494 ------------------------------------------------------------------- slack 5.109 Slack (MET) : 5.109ns (required time - arrival time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.561ns (logic 0.139ns (5.428%) route 2.422ns (94.572%)) Logic Levels: 0 Clock Path Skew: -0.519ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.198ns = ( 10.515 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.612ns, distribution 1.846ns) Clock Net Delay (Destination): 1.800ns (routing 0.555ns, distribution 1.245ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y543 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.072 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.422 5.494 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X116Y544 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.800 10.515 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X116Y544 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]/C clock pessimism 0.216 10.731 clock uncertainty -0.035 10.696 SLICE_X116Y544 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.603 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66] ------------------------------------------------------------------- required time 10.603 arrival time -5.494 ------------------------------------------------------------------- slack 5.109 Slack (MET) : 5.291ns (required time - arrival time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.414ns (logic 0.139ns (5.758%) route 2.275ns (94.242%)) Logic Levels: 0 Clock Path Skew: -0.484ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.233ns = ( 10.550 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.612ns, distribution 1.846ns) Clock Net Delay (Destination): 1.835ns (routing 0.555ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y543 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.072 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.275 5.347 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X104Y541 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.835 10.550 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y541 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[17]/C clock pessimism 0.216 10.766 clock uncertainty -0.035 10.731 SLICE_X104Y541 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.638 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[17] ------------------------------------------------------------------- required time 10.638 arrival time -5.347 ------------------------------------------------------------------- slack 5.291 Slack (MET) : 5.291ns (required time - arrival time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.414ns (logic 0.139ns (5.758%) route 2.275ns (94.242%)) Logic Levels: 0 Clock Path Skew: -0.484ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.233ns = ( 10.550 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.612ns, distribution 1.846ns) Clock Net Delay (Destination): 1.835ns (routing 0.555ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y543 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.072 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.275 5.347 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X104Y541 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.835 10.550 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y541 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism 0.216 10.766 clock uncertainty -0.035 10.731 SLICE_X104Y541 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 10.638 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time 10.638 arrival time -5.347 ------------------------------------------------------------------- slack 5.291 Slack (MET) : 5.291ns (required time - arrival time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.414ns (logic 0.139ns (5.758%) route 2.275ns (94.242%)) Logic Levels: 0 Clock Path Skew: -0.484ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.233ns = ( 10.550 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.612ns, distribution 1.846ns) Clock Net Delay (Destination): 1.835ns (routing 0.555ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y543 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.072 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.275 5.347 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X104Y541 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.835 10.550 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y541 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]/C clock pessimism 0.216 10.766 clock uncertainty -0.035 10.731 SLICE_X104Y541 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.638 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24] ------------------------------------------------------------------- required time 10.638 arrival time -5.347 ------------------------------------------------------------------- slack 5.291 Slack (MET) : 5.291ns (required time - arrival time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.414ns (logic 0.139ns (5.758%) route 2.275ns (94.242%)) Logic Levels: 0 Clock Path Skew: -0.484ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.233ns = ( 10.550 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.612ns, distribution 1.846ns) Clock Net Delay (Destination): 1.835ns (routing 0.555ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y543 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.072 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.275 5.347 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X104Y541 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.835 10.550 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y541 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[25]/C clock pessimism 0.216 10.766 clock uncertainty -0.035 10.731 SLICE_X104Y541 FDCE (Recov_BFF2_SLICEL_C_CLR) -0.093 10.638 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[25] ------------------------------------------------------------------- required time 10.638 arrival time -5.347 ------------------------------------------------------------------- slack 5.291 Slack (MET) : 5.291ns (required time - arrival time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.414ns (logic 0.139ns (5.758%) route 2.275ns (94.242%)) Logic Levels: 0 Clock Path Skew: -0.484ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.233ns = ( 10.550 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.612ns, distribution 1.846ns) Clock Net Delay (Destination): 1.835ns (routing 0.555ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y543 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.072 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.275 5.347 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X104Y541 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.835 10.550 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y541 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]/C clock pessimism 0.216 10.766 clock uncertainty -0.035 10.731 SLICE_X104Y541 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.638 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26] ------------------------------------------------------------------- required time 10.638 arrival time -5.347 ------------------------------------------------------------------- slack 5.291 Slack (MET) : 5.291ns (required time - arrival time) Source: SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 2.414ns (logic 0.139ns (5.758%) route 2.275ns (94.242%)) Logic Levels: 0 Clock Path Skew: -0.484ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.233ns = ( 10.550 - 8.317 ) Source Clock Delay (SCD): 2.933ns Clock Pessimism Removal (CPR): 0.216ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.458ns (routing 0.612ns, distribution 1.846ns) Clock Net Delay (Destination): 1.835ns (routing 0.555ns, distribution 1.280ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.458 2.933 SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X94Y543 FDPE r SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X94Y543 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.072 f SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.275 5.347 SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] SLICE_X104Y541 FDCE f SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.835 10.550 SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X104Y541 FDCE r SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]/C clock pessimism 0.216 10.766 clock uncertainty -0.035 10.731 SLICE_X104Y541 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.638 SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27] ------------------------------------------------------------------- required time 10.638 arrival time -5.347 ------------------------------------------------------------------- slack 5.291 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.209ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.243ns (logic 0.049ns (20.165%) route 0.194ns (79.835%)) Logic Levels: 0 Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.109ns Source Clock Delay (SCD): 0.906ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.788ns (routing 0.262ns, distribution 0.526ns) Clock Net Delay (Destination): 0.944ns (routing 0.300ns, distribution 0.644ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.788 0.906 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X104Y542 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X104Y542 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 0.955 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.194 1.149 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X104Y542 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.944 1.109 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X104Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.174 0.935 SLICE_X104Y542 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.940 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.940 arrival time 1.149 ------------------------------------------------------------------- slack 0.209 Slack (MET) : 0.227ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.310ns (logic 0.049ns (15.806%) route 0.261ns (84.194%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.106ns Source Clock Delay (SCD): 0.901ns Clock Pessimism Removal (CPR): 0.127ns Clock Net Delay (Source): 0.783ns (routing 0.262ns, distribution 0.521ns) Clock Net Delay (Destination): 0.941ns (routing 0.300ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.783 0.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X108Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y545 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.950 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.261 1.211 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X111Y546 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.941 1.106 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/CLK SLICE_X111Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.127 0.979 SLICE_X111Y546 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.984 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -0.984 arrival time 1.211 ------------------------------------------------------------------- slack 0.227 Slack (MET) : 0.227ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.310ns (logic 0.049ns (15.806%) route 0.261ns (84.194%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.106ns Source Clock Delay (SCD): 0.901ns Clock Pessimism Removal (CPR): 0.127ns Clock Net Delay (Source): 0.783ns (routing 0.262ns, distribution 0.521ns) Clock Net Delay (Destination): 0.941ns (routing 0.300ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.783 0.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X108Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y545 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.950 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.261 1.211 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X111Y546 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.941 1.106 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/CLK SLICE_X111Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.127 0.979 SLICE_X111Y546 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 0.984 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -0.984 arrival time 1.211 ------------------------------------------------------------------- slack 0.227 Slack (MET) : 0.227ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.310ns (logic 0.049ns (15.806%) route 0.261ns (84.194%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.106ns Source Clock Delay (SCD): 0.901ns Clock Pessimism Removal (CPR): 0.127ns Clock Net Delay (Source): 0.783ns (routing 0.262ns, distribution 0.521ns) Clock Net Delay (Destination): 0.941ns (routing 0.300ns, distribution 0.641ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.783 0.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X108Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y545 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.950 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.261 1.211 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X111Y546 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.941 1.106 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X111Y546 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.127 0.979 SLICE_X111Y546 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 0.984 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -0.984 arrival time 1.211 ------------------------------------------------------------------- slack 0.227 Slack (MET) : 0.268ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.326ns (logic 0.049ns (15.031%) route 0.277ns (84.969%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.111ns Source Clock Delay (SCD): 0.901ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 0.783ns (routing 0.262ns, distribution 0.521ns) Clock Net Delay (Destination): 0.946ns (routing 0.300ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.783 0.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X108Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y545 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.950 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.277 1.227 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X107Y541 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.946 1.111 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X107Y541 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.157 0.954 SLICE_X107Y541 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.959 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -0.959 arrival time 1.227 ------------------------------------------------------------------- slack 0.268 Slack (MET) : 0.268ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.326ns (logic 0.049ns (15.031%) route 0.277ns (84.969%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.111ns Source Clock Delay (SCD): 0.901ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 0.783ns (routing 0.262ns, distribution 0.521ns) Clock Net Delay (Destination): 0.946ns (routing 0.300ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.783 0.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X108Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y545 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.950 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.277 1.227 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X107Y541 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.946 1.111 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X107Y541 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.157 0.954 SLICE_X107Y541 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 0.959 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -0.959 arrival time 1.227 ------------------------------------------------------------------- slack 0.268 Slack (MET) : 0.272ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.331ns (logic 0.049ns (14.804%) route 0.282ns (85.196%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.112ns Source Clock Delay (SCD): 0.901ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 0.783ns (routing 0.262ns, distribution 0.521ns) Clock Net Delay (Destination): 0.947ns (routing 0.300ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.783 0.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X108Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y545 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.950 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.282 1.232 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X108Y541 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.947 1.112 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y541 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.157 0.955 SLICE_X108Y541 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 0.960 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -0.960 arrival time 1.232 ------------------------------------------------------------------- slack 0.272 Slack (MET) : 0.272ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.331ns (logic 0.049ns (14.804%) route 0.282ns (85.196%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.112ns Source Clock Delay (SCD): 0.901ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 0.783ns (routing 0.262ns, distribution 0.521ns) Clock Net Delay (Destination): 0.947ns (routing 0.300ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.783 0.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X108Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y545 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.950 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.282 1.232 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X108Y541 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.947 1.112 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X108Y541 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.157 0.955 SLICE_X108Y541 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 0.960 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -0.960 arrival time 1.232 ------------------------------------------------------------------- slack 0.272 Slack (MET) : 0.295ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.369ns (logic 0.049ns (13.279%) route 0.320ns (86.721%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.901ns Clock Pessimism Removal (CPR): 0.127ns Clock Net Delay (Source): 0.783ns (routing 0.262ns, distribution 0.521ns) Clock Net Delay (Destination): 0.932ns (routing 0.300ns, distribution 0.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.783 0.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X108Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y545 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.950 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.320 1.270 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X106Y541 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X106Y541 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.127 0.970 SLICE_X106Y541 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.975 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -0.975 arrival time 1.270 ------------------------------------------------------------------- slack 0.295 Slack (MET) : 0.295ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns) Data Path Delay: 0.369ns (logic 0.049ns (13.279%) route 0.320ns (86.721%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.097ns Source Clock Delay (SCD): 0.901ns Clock Pessimism Removal (CPR): 0.127ns Clock Net Delay (Source): 0.783ns (routing 0.262ns, distribution 0.521ns) Clock Net Delay (Destination): 0.932ns (routing 0.300ns, distribution 0.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.783 0.901 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X108Y545 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X108Y545 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 0.950 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.320 1.270 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X106Y541 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.932 1.097 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X106Y541 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.127 0.970 SLICE_X106Y541 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 0.975 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -0.975 arrival time 1.270 ------------------------------------------------------------------- slack 0.295 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_23 To Clock: gtwiz_userclk_rx_srcclk_out[0]_23 Setup : 0 Failing Endpoints, Worst Slack 6.165ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.138ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 6.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 2.040ns (logic 0.140ns (6.863%) route 1.900ns (93.137%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.525ns = ( 10.842 - 8.317 ) Source Clock Delay (SCD): 2.723ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.721ns, distribution 1.527ns) Clock Net Delay (Destination): 2.127ns (routing 0.657ns, distribution 1.470ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.723 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X113Y540 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y540 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.863 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.900 4.763 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X128Y549 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.127 10.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X128Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]/C clock pessimism 0.214 11.056 clock uncertainty -0.035 11.021 SLICE_X128Y549 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83] ------------------------------------------------------------------- required time 10.928 arrival time -4.763 ------------------------------------------------------------------- slack 6.165 Slack (MET) : 6.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[88]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 2.040ns (logic 0.140ns (6.863%) route 1.900ns (93.137%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.525ns = ( 10.842 - 8.317 ) Source Clock Delay (SCD): 2.723ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.721ns, distribution 1.527ns) Clock Net Delay (Destination): 2.127ns (routing 0.657ns, distribution 1.470ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.723 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X113Y540 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y540 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.863 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.900 4.763 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X128Y549 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[88]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.127 10.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X128Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[88]/C clock pessimism 0.214 11.056 clock uncertainty -0.035 11.021 SLICE_X128Y549 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[88] ------------------------------------------------------------------- required time 10.928 arrival time -4.763 ------------------------------------------------------------------- slack 6.165 Slack (MET) : 6.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[91]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 2.040ns (logic 0.140ns (6.863%) route 1.900ns (93.137%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.525ns = ( 10.842 - 8.317 ) Source Clock Delay (SCD): 2.723ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.721ns, distribution 1.527ns) Clock Net Delay (Destination): 2.127ns (routing 0.657ns, distribution 1.470ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.723 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X113Y540 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y540 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.863 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.900 4.763 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X128Y549 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[91]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.127 10.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X128Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[91]/C clock pessimism 0.214 11.056 clock uncertainty -0.035 11.021 SLICE_X128Y549 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[91] ------------------------------------------------------------------- required time 10.928 arrival time -4.763 ------------------------------------------------------------------- slack 6.165 Slack (MET) : 6.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[99]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 2.040ns (logic 0.140ns (6.863%) route 1.900ns (93.137%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.525ns = ( 10.842 - 8.317 ) Source Clock Delay (SCD): 2.723ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.721ns, distribution 1.527ns) Clock Net Delay (Destination): 2.127ns (routing 0.657ns, distribution 1.470ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.723 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X113Y540 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y540 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.863 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.900 4.763 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X128Y549 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[99]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.127 10.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X128Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[99]/C clock pessimism 0.214 11.056 clock uncertainty -0.035 11.021 SLICE_X128Y549 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[99] ------------------------------------------------------------------- required time 10.928 arrival time -4.763 ------------------------------------------------------------------- slack 6.165 Slack (MET) : 6.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[83]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 2.040ns (logic 0.140ns (6.863%) route 1.900ns (93.137%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.525ns = ( 10.842 - 8.317 ) Source Clock Delay (SCD): 2.723ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.721ns, distribution 1.527ns) Clock Net Delay (Destination): 2.127ns (routing 0.657ns, distribution 1.470ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.723 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X113Y540 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y540 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.863 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.900 4.763 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X128Y549 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.127 10.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X128Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[83]/C clock pessimism 0.214 11.056 clock uncertainty -0.035 11.021 SLICE_X128Y549 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[83] ------------------------------------------------------------------- required time 10.928 arrival time -4.763 ------------------------------------------------------------------- slack 6.165 Slack (MET) : 6.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[88]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 2.040ns (logic 0.140ns (6.863%) route 1.900ns (93.137%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.525ns = ( 10.842 - 8.317 ) Source Clock Delay (SCD): 2.723ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.721ns, distribution 1.527ns) Clock Net Delay (Destination): 2.127ns (routing 0.657ns, distribution 1.470ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.723 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X113Y540 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y540 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.863 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.900 4.763 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X128Y549 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[88]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.127 10.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X128Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[88]/C clock pessimism 0.214 11.056 clock uncertainty -0.035 11.021 SLICE_X128Y549 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[88] ------------------------------------------------------------------- required time 10.928 arrival time -4.763 ------------------------------------------------------------------- slack 6.165 Slack (MET) : 6.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[91]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 2.040ns (logic 0.140ns (6.863%) route 1.900ns (93.137%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.525ns = ( 10.842 - 8.317 ) Source Clock Delay (SCD): 2.723ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.721ns, distribution 1.527ns) Clock Net Delay (Destination): 2.127ns (routing 0.657ns, distribution 1.470ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.723 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X113Y540 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y540 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.863 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.900 4.763 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X128Y549 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[91]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.127 10.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X128Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[91]/C clock pessimism 0.214 11.056 clock uncertainty -0.035 11.021 SLICE_X128Y549 FDCE (Recov_BFF2_SLICEL_C_CLR) -0.093 10.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[91] ------------------------------------------------------------------- required time 10.928 arrival time -4.763 ------------------------------------------------------------------- slack 6.165 Slack (MET) : 6.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[99]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 2.040ns (logic 0.140ns (6.863%) route 1.900ns (93.137%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.525ns = ( 10.842 - 8.317 ) Source Clock Delay (SCD): 2.723ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.721ns, distribution 1.527ns) Clock Net Delay (Destination): 2.127ns (routing 0.657ns, distribution 1.470ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.723 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X113Y540 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y540 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.863 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.900 4.763 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X128Y549 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[99]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.127 10.842 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X128Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[99]/C clock pessimism 0.214 11.056 clock uncertainty -0.035 11.021 SLICE_X128Y549 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 10.928 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[99] ------------------------------------------------------------------- required time 10.928 arrival time -4.763 ------------------------------------------------------------------- slack 6.165 Slack (MET) : 6.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[80]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 2.027ns (logic 0.140ns (6.907%) route 1.887ns (93.093%)) Logic Levels: 0 Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.512ns = ( 10.829 - 8.317 ) Source Clock Delay (SCD): 2.723ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.721ns, distribution 1.527ns) Clock Net Delay (Destination): 2.114ns (routing 0.657ns, distribution 1.457ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.723 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X113Y540 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y540 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.863 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.887 4.750 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X127Y549 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[80]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.114 10.829 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X127Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[80]/C clock pessimism 0.214 11.043 clock uncertainty -0.035 11.008 SLICE_X127Y549 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.915 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[80] ------------------------------------------------------------------- required time 10.915 arrival time -4.750 ------------------------------------------------------------------- slack 6.165 Slack (MET) : 6.165ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 2.027ns (logic 0.140ns (6.907%) route 1.887ns (93.093%)) Logic Levels: 0 Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.512ns = ( 10.829 - 8.317 ) Source Clock Delay (SCD): 2.723ns Clock Pessimism Removal (CPR): 0.214ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.248ns (routing 0.721ns, distribution 1.527ns) Clock Net Delay (Destination): 2.114ns (routing 0.657ns, distribution 1.457ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.248 2.723 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X113Y540 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y540 FDPE (Prop_AFF_SLICEM_C_Q) 0.140 2.863 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.887 4.750 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X127Y549 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 2.114 10.829 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X127Y549 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]/C clock pessimism 0.214 11.043 clock uncertainty -0.035 11.008 SLICE_X127Y549 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.915 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82] ------------------------------------------------------------------- required time 10.915 arrival time -4.750 ------------------------------------------------------------------- slack 6.165 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.227ns Source Clock Delay (SCD): 1.010ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.892ns (routing 0.316ns, distribution 0.576ns) Clock Net Delay (Destination): 1.062ns (routing 0.357ns, distribution 0.705ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.010 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X123Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y543 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.059 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.231 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X121Y542 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.062 1.227 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X121Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.139 1.088 SLICE_X121Y542 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.093 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.093 arrival time 1.231 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.227ns Source Clock Delay (SCD): 1.010ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.892ns (routing 0.316ns, distribution 0.576ns) Clock Net Delay (Destination): 1.062ns (routing 0.357ns, distribution 0.705ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.010 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X123Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y543 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.059 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.231 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X121Y542 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.062 1.227 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X121Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.139 1.088 SLICE_X121Y542 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.093 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.093 arrival time 1.231 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.227ns Source Clock Delay (SCD): 1.010ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.892ns (routing 0.316ns, distribution 0.576ns) Clock Net Delay (Destination): 1.062ns (routing 0.357ns, distribution 0.705ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.010 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X123Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y543 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.059 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.231 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X121Y542 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.062 1.227 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X121Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.139 1.088 SLICE_X121Y542 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.093 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.093 arrival time 1.231 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.227ns Source Clock Delay (SCD): 1.010ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.892ns (routing 0.316ns, distribution 0.576ns) Clock Net Delay (Destination): 1.062ns (routing 0.357ns, distribution 0.705ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.010 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X123Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y543 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.059 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.231 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X121Y542 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.062 1.227 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X121Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.139 1.088 SLICE_X121Y542 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.093 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.093 arrival time 1.231 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.227ns Source Clock Delay (SCD): 1.010ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.892ns (routing 0.316ns, distribution 0.576ns) Clock Net Delay (Destination): 1.062ns (routing 0.357ns, distribution 0.705ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.010 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X123Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y543 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.059 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.231 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X121Y542 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.062 1.227 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X121Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.139 1.088 SLICE_X121Y542 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.093 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.093 arrival time 1.231 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.049ns (22.172%) route 0.172ns (77.828%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.227ns Source Clock Delay (SCD): 1.010ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.892ns (routing 0.316ns, distribution 0.576ns) Clock Net Delay (Destination): 1.062ns (routing 0.357ns, distribution 0.705ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.010 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X123Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y543 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.059 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.231 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X121Y542 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.062 1.227 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X121Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.139 1.088 SLICE_X121Y542 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.093 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.093 arrival time 1.231 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.226ns (logic 0.049ns (21.681%) route 0.177ns (78.319%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.229ns Source Clock Delay (SCD): 1.010ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.892ns (routing 0.316ns, distribution 0.576ns) Clock Net Delay (Destination): 1.064ns (routing 0.357ns, distribution 0.707ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.010 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X123Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y543 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.059 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.177 1.236 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X121Y542 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.064 1.229 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X121Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.139 1.090 SLICE_X121Y542 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.095 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.095 arrival time 1.236 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.226ns (logic 0.049ns (21.681%) route 0.177ns (78.319%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.229ns Source Clock Delay (SCD): 1.010ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.892ns (routing 0.316ns, distribution 0.576ns) Clock Net Delay (Destination): 1.064ns (routing 0.357ns, distribution 0.707ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.010 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X123Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y543 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.059 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.177 1.236 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X121Y542 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.064 1.229 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X121Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.139 1.090 SLICE_X121Y542 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.095 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.095 arrival time 1.236 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.226ns (logic 0.049ns (21.681%) route 0.177ns (78.319%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.229ns Source Clock Delay (SCD): 1.010ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.892ns (routing 0.316ns, distribution 0.576ns) Clock Net Delay (Destination): 1.064ns (routing 0.357ns, distribution 0.707ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.010 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X123Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y543 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.059 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.177 1.236 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X121Y542 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.064 1.229 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X121Y542 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.139 1.090 SLICE_X121Y542 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.095 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.095 arrival time 1.236 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.158ns (arrival time - required time) Source: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns) Data Path Delay: 0.241ns (logic 0.049ns (20.332%) route 0.192ns (79.668%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.227ns Source Clock Delay (SCD): 1.010ns Clock Pessimism Removal (CPR): 0.139ns Clock Net Delay (Source): 0.892ns (routing 0.316ns, distribution 0.576ns) Clock Net Delay (Destination): 1.062ns (routing 0.357ns, distribution 0.705ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 0.892 1.010 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X123Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X123Y543 FDCE (Prop_DFF2_SLICEL_C_Q) 0.049 1.059 r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.192 1.251 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X119Y543 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y9 (CLOCK_ROOT) net (fo=674, routed) 1.062 1.227 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X119Y543 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.139 1.088 SLICE_X119Y543 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.093 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.093 arrival time 1.251 ------------------------------------------------------------------- slack 0.158 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_24 To Clock: gtwiz_userclk_rx_srcclk_out[0]_24 Setup : 0 Failing Endpoints, Worst Slack 4.096ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.134ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.096ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.082ns (logic 0.228ns (5.585%) route 3.854ns (94.415%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.570ns = ( 10.887 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.194ns (routing 0.646ns, distribution 1.548ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.440 6.361 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y154 LUT2 (Prop_C6LUT_SLICEL_I0_O) 0.088 6.449 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__23/O net (fo=2, routed) 0.414 6.863 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 SLICE_X52Y154 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.194 10.887 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X52Y154 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.200 11.087 clock uncertainty -0.035 11.052 SLICE_X52Y154 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.959 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.959 arrival time -6.863 ------------------------------------------------------------------- slack 4.096 Slack (MET) : 4.096ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.082ns (logic 0.228ns (5.585%) route 3.854ns (94.415%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.570ns = ( 10.887 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.194ns (routing 0.646ns, distribution 1.548ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.440 6.361 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y154 LUT2 (Prop_C6LUT_SLICEL_I0_O) 0.088 6.449 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__23/O net (fo=2, routed) 0.414 6.863 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 SLICE_X52Y154 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.194 10.887 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X52Y154 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.200 11.087 clock uncertainty -0.035 11.052 SLICE_X52Y154 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 10.959 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.959 arrival time -6.863 ------------------------------------------------------------------- slack 4.096 Slack (MET) : 4.132ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.052ns (logic 0.232ns (5.726%) route 3.820ns (94.274%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.005ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.576ns = ( 10.893 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.200ns (routing 0.646ns, distribution 1.554ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.288 6.209 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y153 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.301 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.532 6.833 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X53Y150 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.200 10.893 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y150 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/C clock pessimism 0.200 11.093 clock uncertainty -0.035 11.058 SLICE_X53Y150 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.965 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3] ------------------------------------------------------------------- required time 10.965 arrival time -6.833 ------------------------------------------------------------------- slack 4.132 Slack (MET) : 4.132ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.052ns (logic 0.232ns (5.726%) route 3.820ns (94.274%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.005ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.576ns = ( 10.893 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.200ns (routing 0.646ns, distribution 1.554ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.288 6.209 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y153 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.301 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.532 6.833 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X53Y150 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.200 10.893 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y150 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/C clock pessimism 0.200 11.093 clock uncertainty -0.035 11.058 SLICE_X53Y150 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.965 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6] ------------------------------------------------------------------- required time 10.965 arrival time -6.833 ------------------------------------------------------------------- slack 4.132 Slack (MET) : 4.138ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.045ns (logic 0.232ns (5.735%) route 3.813ns (94.265%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.575ns = ( 10.892 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.199ns (routing 0.646ns, distribution 1.553ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.288 6.209 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y153 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.301 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.525 6.826 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X53Y150 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.199 10.892 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y150 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/C clock pessimism 0.200 11.092 clock uncertainty -0.035 11.057 SLICE_X53Y150 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.964 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2] ------------------------------------------------------------------- required time 10.964 arrival time -6.826 ------------------------------------------------------------------- slack 4.138 Slack (MET) : 4.152ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.041ns (logic 0.232ns (5.741%) route 3.809ns (94.259%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.004ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.585ns = ( 10.902 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.209ns (routing 0.646ns, distribution 1.563ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.288 6.209 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y153 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.301 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.521 6.822 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X53Y151 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.209 10.902 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y151 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C clock pessimism 0.200 11.102 clock uncertainty -0.035 11.067 SLICE_X53Y151 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.974 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0] ------------------------------------------------------------------- required time 10.974 arrival time -6.822 ------------------------------------------------------------------- slack 4.152 Slack (MET) : 4.152ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.041ns (logic 0.232ns (5.741%) route 3.809ns (94.259%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.004ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.585ns = ( 10.902 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.209ns (routing 0.646ns, distribution 1.563ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.288 6.209 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y153 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.301 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.521 6.822 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X53Y151 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.209 10.902 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y151 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/C clock pessimism 0.200 11.102 clock uncertainty -0.035 11.067 SLICE_X53Y151 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 10.974 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0] ------------------------------------------------------------------- required time 10.974 arrival time -6.822 ------------------------------------------------------------------- slack 4.152 Slack (MET) : 4.152ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.041ns (logic 0.232ns (5.741%) route 3.809ns (94.259%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.004ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.585ns = ( 10.902 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.209ns (routing 0.646ns, distribution 1.563ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.288 6.209 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y153 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.301 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.521 6.822 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X53Y151 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.209 10.902 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y151 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/C clock pessimism 0.200 11.102 clock uncertainty -0.035 11.067 SLICE_X53Y151 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.974 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0] ------------------------------------------------------------------- required time 10.974 arrival time -6.822 ------------------------------------------------------------------- slack 4.152 Slack (MET) : 4.158ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.034ns (logic 0.232ns (5.751%) route 3.802ns (94.249%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.584ns = ( 10.901 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.208ns (routing 0.646ns, distribution 1.562ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.288 6.209 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y153 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.301 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.514 6.815 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X53Y151 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.208 10.901 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y151 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/C clock pessimism 0.200 11.101 clock uncertainty -0.035 11.066 SLICE_X53Y151 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.973 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1] ------------------------------------------------------------------- required time 10.973 arrival time -6.815 ------------------------------------------------------------------- slack 4.158 Slack (MET) : 4.158ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 4.034ns (logic 0.232ns (5.751%) route 3.802ns (94.249%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.584ns = ( 10.901 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.200ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.714ns, distribution 1.642ns) Clock Net Delay (Destination): 2.208ns (routing 0.646ns, distribution 1.562ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y130 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y130 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.921 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.288 6.209 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y153 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.301 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/O net (fo=15, routed) 0.514 6.815 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X53Y151 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.208 10.901 g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X53Y151 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C clock pessimism 0.200 11.101 clock uncertainty -0.035 11.066 SLICE_X53Y151 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 10.973 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5] ------------------------------------------------------------------- required time 10.973 arrival time -6.815 ------------------------------------------------------------------- slack 4.158 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.134ns (arrival time - required time) Source: SFP_GEN[24].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[24].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.219ns (logic 0.048ns (21.918%) route 0.171ns (78.082%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.108ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.992ns (routing 0.327ns, distribution 0.665ns) Clock Net Delay (Destination): 1.185ns (routing 0.379ns, distribution 0.806ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.992 1.108 SFP_GEN[24].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X62Y176 FDPE r SFP_GEN[24].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y176 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.156 f SFP_GEN[24].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.171 1.327 SFP_GEN[24].ngCCM_gbt/sync_m_reg[3][0] SLICE_X64Y176 FDCE f SFP_GEN[24].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.337 SFP_GEN[24].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X64Y176 FDCE r SFP_GEN[24].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.149 1.188 SLICE_X64Y176 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.193 SFP_GEN[24].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.193 arrival time 1.327 ------------------------------------------------------------------- slack 0.134 Slack (MET) : 0.172ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns Source Clock Delay (SCD): 1.077ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.961ns (routing 0.327ns, distribution 0.634ns) Clock Net Delay (Destination): 1.162ns (routing 0.379ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.961 1.077 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X58Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y153 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.125 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.342 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X59Y154 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.314 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X59Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.149 1.165 SLICE_X59Y154 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.170 arrival time 1.342 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns Source Clock Delay (SCD): 1.077ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.961ns (routing 0.327ns, distribution 0.634ns) Clock Net Delay (Destination): 1.162ns (routing 0.379ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.961 1.077 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X58Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y153 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.125 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.342 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X59Y154 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.314 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X59Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.149 1.165 SLICE_X59Y154 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.170 arrival time 1.342 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns Source Clock Delay (SCD): 1.077ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.961ns (routing 0.327ns, distribution 0.634ns) Clock Net Delay (Destination): 1.162ns (routing 0.379ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.961 1.077 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X58Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y153 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.125 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.342 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X59Y154 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.314 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X59Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.149 1.165 SLICE_X59Y154 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.170 arrival time 1.342 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns Source Clock Delay (SCD): 1.077ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.961ns (routing 0.327ns, distribution 0.634ns) Clock Net Delay (Destination): 1.162ns (routing 0.379ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.961 1.077 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X58Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y153 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.125 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.342 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X59Y154 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.314 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X59Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.149 1.165 SLICE_X59Y154 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -1.170 arrival time 1.342 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns Source Clock Delay (SCD): 1.077ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.961ns (routing 0.327ns, distribution 0.634ns) Clock Net Delay (Destination): 1.162ns (routing 0.379ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.961 1.077 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X58Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y153 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.125 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.342 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X59Y154 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.314 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X59Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.149 1.165 SLICE_X59Y154 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.170 arrival time 1.342 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.048ns (17.778%) route 0.222ns (82.222%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.315ns Source Clock Delay (SCD): 1.077ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.961ns (routing 0.327ns, distribution 0.634ns) Clock Net Delay (Destination): 1.163ns (routing 0.379ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.961 1.077 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X58Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y153 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.125 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.222 1.347 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X60Y154 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.163 1.315 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X60Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.149 1.166 SLICE_X60Y154 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.171 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.171 arrival time 1.347 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.048ns (17.778%) route 0.222ns (82.222%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.315ns Source Clock Delay (SCD): 1.077ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.961ns (routing 0.327ns, distribution 0.634ns) Clock Net Delay (Destination): 1.163ns (routing 0.379ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.961 1.077 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X58Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y153 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.125 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.222 1.347 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X60Y154 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.163 1.315 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C clock pessimism -0.149 1.166 SLICE_X60Y154 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.171 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -1.171 arrival time 1.347 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.048ns (17.778%) route 0.222ns (82.222%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.315ns Source Clock Delay (SCD): 1.077ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.961ns (routing 0.327ns, distribution 0.634ns) Clock Net Delay (Destination): 1.163ns (routing 0.379ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.961 1.077 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X58Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y153 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.125 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.222 1.347 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X60Y154 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.163 1.315 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.149 1.166 SLICE_X60Y154 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.171 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.171 arrival time 1.347 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.048ns (17.778%) route 0.222ns (82.222%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.315ns Source Clock Delay (SCD): 1.077ns Clock Pessimism Removal (CPR): 0.149ns Clock Net Delay (Source): 0.961ns (routing 0.327ns, distribution 0.634ns) Clock Net Delay (Destination): 1.163ns (routing 0.379ns, distribution 0.784ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.961 1.077 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X58Y153 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X58Y153 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.125 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.222 1.347 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X60Y154 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.163 1.315 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X60Y154 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.149 1.166 SLICE_X60Y154 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.171 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.171 arrival time 1.347 ------------------------------------------------------------------- slack 0.176 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_25 To Clock: gtwiz_userclk_rx_srcclk_out[0]_25 Setup : 0 Failing Endpoints, Worst Slack 4.220ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.138ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.220ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.011ns (logic 0.306ns (7.629%) route 3.705ns (92.371%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.578ns = ( 10.895 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.202ns (routing 0.591ns, distribution 1.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.884 5.754 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X52Y270 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.921 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.821 6.742 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X57Y266 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.202 10.895 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X57Y266 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C clock pessimism 0.195 11.090 clock uncertainty -0.035 11.055 SLICE_X57Y266 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.962 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10] ------------------------------------------------------------------- required time 10.962 arrival time -6.742 ------------------------------------------------------------------- slack 4.220 Slack (MET) : 4.220ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 4.011ns (logic 0.306ns (7.629%) route 3.705ns (92.371%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.042ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.578ns = ( 10.895 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.202ns (routing 0.591ns, distribution 1.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.884 5.754 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X52Y270 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.921 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.821 6.742 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X57Y266 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.202 10.895 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X57Y266 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]/C clock pessimism 0.195 11.090 clock uncertainty -0.035 11.055 SLICE_X57Y266 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.962 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5] ------------------------------------------------------------------- required time 10.962 arrival time -6.742 ------------------------------------------------------------------- slack 4.220 Slack (MET) : 4.274ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 3.960ns (logic 0.306ns (7.727%) route 3.654ns (92.273%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.045ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.581ns = ( 10.898 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.205ns (routing 0.591ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.884 5.754 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X52Y270 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.921 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.770 6.691 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X57Y271 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.205 10.898 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X57Y271 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C clock pessimism 0.195 11.093 clock uncertainty -0.035 11.058 SLICE_X57Y271 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.965 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1] ------------------------------------------------------------------- required time 10.965 arrival time -6.691 ------------------------------------------------------------------- slack 4.274 Slack (MET) : 4.274ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 3.960ns (logic 0.306ns (7.727%) route 3.654ns (92.273%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.045ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.581ns = ( 10.898 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.205ns (routing 0.591ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.884 5.754 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X52Y270 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.921 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.770 6.691 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X57Y271 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.205 10.898 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X57Y271 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C clock pessimism 0.195 11.093 clock uncertainty -0.035 11.058 SLICE_X57Y271 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.965 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3] ------------------------------------------------------------------- required time 10.965 arrival time -6.691 ------------------------------------------------------------------- slack 4.274 Slack (MET) : 4.274ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 3.960ns (logic 0.306ns (7.727%) route 3.654ns (92.273%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.045ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.581ns = ( 10.898 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.205ns (routing 0.591ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.884 5.754 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X52Y270 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.921 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.770 6.691 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X57Y271 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.205 10.898 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X57Y271 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C clock pessimism 0.195 11.093 clock uncertainty -0.035 11.058 SLICE_X57Y271 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.965 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5] ------------------------------------------------------------------- required time 10.965 arrival time -6.691 ------------------------------------------------------------------- slack 4.274 Slack (MET) : 4.282ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 3.950ns (logic 0.306ns (7.747%) route 3.644ns (92.253%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.203ns (routing 0.591ns, distribution 1.612ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.884 5.754 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X52Y270 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.921 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.760 6.681 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X57Y271 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X57Y271 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C clock pessimism 0.195 11.091 clock uncertainty -0.035 11.056 SLICE_X57Y271 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.963 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2] ------------------------------------------------------------------- required time 10.963 arrival time -6.681 ------------------------------------------------------------------- slack 4.282 Slack (MET) : 4.414ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 3.818ns (logic 0.306ns (8.015%) route 3.512ns (91.985%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.203ns (routing 0.591ns, distribution 1.612ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.884 5.754 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X52Y270 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.921 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.628 6.549 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X57Y270 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X57Y270 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/C clock pessimism 0.195 11.091 clock uncertainty -0.035 11.056 SLICE_X57Y270 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.963 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0] ------------------------------------------------------------------- required time 10.963 arrival time -6.549 ------------------------------------------------------------------- slack 4.414 Slack (MET) : 4.414ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 3.818ns (logic 0.306ns (8.015%) route 3.512ns (91.985%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.203ns (routing 0.591ns, distribution 1.612ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.884 5.754 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X52Y270 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.921 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.628 6.549 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X57Y270 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X57Y270 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C clock pessimism 0.195 11.091 clock uncertainty -0.035 11.056 SLICE_X57Y270 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.963 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1] ------------------------------------------------------------------- required time 10.963 arrival time -6.549 ------------------------------------------------------------------- slack 4.414 Slack (MET) : 4.414ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 3.818ns (logic 0.306ns (8.015%) route 3.512ns (91.985%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.203ns (routing 0.591ns, distribution 1.612ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.884 5.754 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X52Y270 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.921 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.628 6.549 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X57Y270 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X57Y270 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C clock pessimism 0.195 11.091 clock uncertainty -0.035 11.056 SLICE_X57Y270 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.963 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2] ------------------------------------------------------------------- required time 10.963 arrival time -6.549 ------------------------------------------------------------------- slack 4.414 Slack (MET) : 4.414ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 3.818ns (logic 0.306ns (8.015%) route 3.512ns (91.985%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.731ns Clock Pessimism Removal (CPR): 0.195ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.306ns (routing 0.655ns, distribution 1.651ns) Clock Net Delay (Destination): 2.203ns (routing 0.591ns, distribution 1.612ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.306 2.731 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y276 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y276 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.870 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.884 5.754 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X52Y270 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.921 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/O net (fo=15, routed) 0.628 6.549 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X57Y270 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] SLICE_X57Y270 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C clock pessimism 0.195 11.091 clock uncertainty -0.035 11.056 SLICE_X57Y270 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 10.963 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3] ------------------------------------------------------------------- required time 10.963 arrival time -6.549 ------------------------------------------------------------------- slack 4.414 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.048ns (21.818%) route 0.172ns (78.182%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.155ns (routing 0.343ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X56Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y283 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.136 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.308 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X57Y283 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.155 1.307 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.142 1.165 SLICE_X57Y283 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -1.170 arrival time 1.308 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.048ns (21.818%) route 0.172ns (78.182%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.155ns (routing 0.343ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X56Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y283 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.136 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.308 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X57Y283 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.155 1.307 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.142 1.165 SLICE_X57Y283 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.170 arrival time 1.308 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.048ns (21.818%) route 0.172ns (78.182%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.155ns (routing 0.343ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X56Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y283 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.136 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.308 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X57Y283 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.155 1.307 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.142 1.165 SLICE_X57Y283 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.170 arrival time 1.308 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.048ns (21.818%) route 0.172ns (78.182%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.155ns (routing 0.343ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X56Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y283 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.136 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.308 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X57Y283 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.155 1.307 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.142 1.165 SLICE_X57Y283 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.170 arrival time 1.308 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.048ns (21.818%) route 0.172ns (78.182%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.155ns (routing 0.343ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X56Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y283 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.136 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.308 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X57Y283 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.155 1.307 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.142 1.165 SLICE_X57Y283 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.170 arrival time 1.308 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.048ns (21.818%) route 0.172ns (78.182%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.155ns (routing 0.343ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X56Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y283 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.136 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.308 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X57Y283 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.155 1.307 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.142 1.165 SLICE_X57Y283 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.170 arrival time 1.308 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.048ns (21.818%) route 0.172ns (78.182%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.155ns (routing 0.343ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X56Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y283 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.136 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.308 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X57Y283 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.155 1.307 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.142 1.165 SLICE_X57Y283 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.170 arrival time 1.308 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.048ns (21.818%) route 0.172ns (78.182%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.307ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.155ns (routing 0.343ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X56Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y283 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.136 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.172 1.308 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X57Y283 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.155 1.307 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X57Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.142 1.165 SLICE_X57Y283 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.170 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.170 arrival time 1.308 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.173ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.048ns (18.251%) route 0.215ns (81.749%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.315ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.163ns (routing 0.343ns, distribution 0.820ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X56Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y283 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.136 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.215 1.351 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X53Y281 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.163 1.315 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK SLICE_X53Y281 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.142 1.173 SLICE_X53Y281 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.178 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.178 arrival time 1.351 ------------------------------------------------------------------- slack 0.173 Slack (MET) : 0.173ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.048ns (18.750%) route 0.208ns (81.250%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.308ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.972ns (routing 0.297ns, distribution 0.675ns) Clock Net Delay (Destination): 1.156ns (routing 0.343ns, distribution 0.813ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK SLICE_X56Y283 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y283 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.136 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.208 1.344 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X57Y284 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y18 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y99 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.308 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X57Y284 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.142 1.166 SLICE_X57Y284 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.171 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.171 arrival time 1.344 ------------------------------------------------------------------- slack 0.173 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_26 To Clock: gtwiz_userclk_rx_srcclk_out[0]_26 Setup : 0 Failing Endpoints, Worst Slack 5.217ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.148ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.217ns (required time - arrival time) Source: SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 2.842ns (logic 0.139ns (4.891%) route 2.703ns (95.109%)) Logic Levels: 0 Clock Path Skew: -0.130ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.570ns = ( 10.887 - 8.317 ) Source Clock Delay (SCD): 2.921ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.496ns (routing 0.702ns, distribution 1.794ns) Clock Net Delay (Destination): 2.194ns (routing 0.634ns, distribution 1.560ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.496 2.921 SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y270 FDPE r SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y270 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.060 f SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.703 5.763 SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y276 FDCE f SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.194 10.887 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y276 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[30]/C clock pessimism 0.221 11.108 clock uncertainty -0.035 11.073 SLICE_X48Y276 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.980 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[30] ------------------------------------------------------------------- required time 10.980 arrival time -5.763 ------------------------------------------------------------------- slack 5.217 Slack (MET) : 5.217ns (required time - arrival time) Source: SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[82]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 2.842ns (logic 0.139ns (4.891%) route 2.703ns (95.109%)) Logic Levels: 0 Clock Path Skew: -0.130ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.570ns = ( 10.887 - 8.317 ) Source Clock Delay (SCD): 2.921ns Clock Pessimism Removal (CPR): 0.221ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.496ns (routing 0.702ns, distribution 1.794ns) Clock Net Delay (Destination): 2.194ns (routing 0.634ns, distribution 1.560ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.496 2.921 SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y270 FDPE r SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y270 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.060 f SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.703 5.763 SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y276 FDCE f SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[82]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.194 10.887 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y276 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[82]/C clock pessimism 0.221 11.108 clock uncertainty -0.035 11.073 SLICE_X48Y276 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 10.980 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[82] ------------------------------------------------------------------- required time 10.980 arrival time -5.763 ------------------------------------------------------------------- slack 5.217 Slack (MET) : 5.410ns (required time - arrival time) Source: SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 2.347ns (logic 0.139ns (5.922%) route 2.208ns (94.078%)) Logic Levels: 0 Clock Path Skew: -0.432ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.285ns = ( 10.602 - 8.317 ) Source Clock Delay (SCD): 2.921ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.496ns (routing 0.702ns, distribution 1.794ns) Clock Net Delay (Destination): 1.909ns (routing 0.634ns, distribution 1.275ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.496 2.921 SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y270 FDPE r SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y270 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.060 f SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.208 5.268 SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y282 FDCE f SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.909 10.602 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y282 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[56]/C clock pessimism 0.204 10.806 clock uncertainty -0.035 10.771 SLICE_X41Y282 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.678 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[56] ------------------------------------------------------------------- required time 10.678 arrival time -5.268 ------------------------------------------------------------------- slack 5.410 Slack (MET) : 5.410ns (required time - arrival time) Source: SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 2.347ns (logic 0.139ns (5.922%) route 2.208ns (94.078%)) Logic Levels: 0 Clock Path Skew: -0.432ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.285ns = ( 10.602 - 8.317 ) Source Clock Delay (SCD): 2.921ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.496ns (routing 0.702ns, distribution 1.794ns) Clock Net Delay (Destination): 1.909ns (routing 0.634ns, distribution 1.275ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.496 2.921 SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y270 FDPE r SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y270 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.060 f SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.208 5.268 SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y282 FDCE f SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.909 10.602 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y282 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[58]/C clock pessimism 0.204 10.806 clock uncertainty -0.035 10.771 SLICE_X41Y282 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.678 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[58] ------------------------------------------------------------------- required time 10.678 arrival time -5.268 ------------------------------------------------------------------- slack 5.410 Slack (MET) : 5.474ns (required time - arrival time) Source: SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 2.279ns (logic 0.139ns (6.099%) route 2.140ns (93.901%)) Logic Levels: 0 Clock Path Skew: -0.436ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.281ns = ( 10.598 - 8.317 ) Source Clock Delay (SCD): 2.921ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.496ns (routing 0.702ns, distribution 1.794ns) Clock Net Delay (Destination): 1.905ns (routing 0.634ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.496 2.921 SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y270 FDPE r SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y270 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.060 f SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.140 5.200 SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y277 FDCE f SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.905 10.598 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y277 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism 0.204 10.802 clock uncertainty -0.035 10.767 SLICE_X41Y277 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.674 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time 10.674 arrival time -5.200 ------------------------------------------------------------------- slack 5.474 Slack (MET) : 5.474ns (required time - arrival time) Source: SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 2.279ns (logic 0.139ns (6.099%) route 2.140ns (93.901%)) Logic Levels: 0 Clock Path Skew: -0.436ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.281ns = ( 10.598 - 8.317 ) Source Clock Delay (SCD): 2.921ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.496ns (routing 0.702ns, distribution 1.794ns) Clock Net Delay (Destination): 1.905ns (routing 0.634ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.496 2.921 SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y270 FDPE r SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y270 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.060 f SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.140 5.200 SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y277 FDCE f SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.905 10.598 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y277 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[54]/C clock pessimism 0.204 10.802 clock uncertainty -0.035 10.767 SLICE_X41Y277 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.674 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[54] ------------------------------------------------------------------- required time 10.674 arrival time -5.200 ------------------------------------------------------------------- slack 5.474 Slack (MET) : 5.474ns (required time - arrival time) Source: SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 2.279ns (logic 0.139ns (6.099%) route 2.140ns (93.901%)) Logic Levels: 0 Clock Path Skew: -0.436ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.281ns = ( 10.598 - 8.317 ) Source Clock Delay (SCD): 2.921ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.496ns (routing 0.702ns, distribution 1.794ns) Clock Net Delay (Destination): 1.905ns (routing 0.634ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.496 2.921 SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y270 FDPE r SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y270 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.060 f SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.140 5.200 SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y277 FDCE f SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.905 10.598 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y277 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[60]/C clock pessimism 0.204 10.802 clock uncertainty -0.035 10.767 SLICE_X41Y277 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.674 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[60] ------------------------------------------------------------------- required time 10.674 arrival time -5.200 ------------------------------------------------------------------- slack 5.474 Slack (MET) : 5.474ns (required time - arrival time) Source: SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 2.279ns (logic 0.139ns (6.099%) route 2.140ns (93.901%)) Logic Levels: 0 Clock Path Skew: -0.436ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.281ns = ( 10.598 - 8.317 ) Source Clock Delay (SCD): 2.921ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.496ns (routing 0.702ns, distribution 1.794ns) Clock Net Delay (Destination): 1.905ns (routing 0.634ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.496 2.921 SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y270 FDPE r SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y270 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.060 f SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.140 5.200 SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y277 FDCE f SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.905 10.598 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y277 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[62]/C clock pessimism 0.204 10.802 clock uncertainty -0.035 10.767 SLICE_X41Y277 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 10.674 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[62] ------------------------------------------------------------------- required time 10.674 arrival time -5.200 ------------------------------------------------------------------- slack 5.474 Slack (MET) : 5.474ns (required time - arrival time) Source: SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 2.279ns (logic 0.139ns (6.099%) route 2.140ns (93.901%)) Logic Levels: 0 Clock Path Skew: -0.436ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.281ns = ( 10.598 - 8.317 ) Source Clock Delay (SCD): 2.921ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.496ns (routing 0.702ns, distribution 1.794ns) Clock Net Delay (Destination): 1.905ns (routing 0.634ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.496 2.921 SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y270 FDPE r SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y270 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.060 f SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.140 5.200 SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y277 FDCE f SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.905 10.598 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y277 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[68]/C clock pessimism 0.204 10.802 clock uncertainty -0.035 10.767 SLICE_X41Y277 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.674 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[68] ------------------------------------------------------------------- required time 10.674 arrival time -5.200 ------------------------------------------------------------------- slack 5.474 Slack (MET) : 5.474ns (required time - arrival time) Source: SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 2.279ns (logic 0.139ns (6.099%) route 2.140ns (93.901%)) Logic Levels: 0 Clock Path Skew: -0.436ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.281ns = ( 10.598 - 8.317 ) Source Clock Delay (SCD): 2.921ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.496ns (routing 0.702ns, distribution 1.794ns) Clock Net Delay (Destination): 1.905ns (routing 0.634ns, distribution 1.271ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.496 2.921 SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y270 FDPE r SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y270 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.060 f SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.140 5.200 SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] SLICE_X41Y277 FDCE f SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.905 10.598 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y277 FDCE r SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[70]/C clock pessimism 0.204 10.802 clock uncertainty -0.035 10.767 SLICE_X41Y277 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 10.674 SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[70] ------------------------------------------------------------------- required time 10.674 arrival time -5.200 ------------------------------------------------------------------- slack 5.474 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.148ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.164ns Source Clock Delay (SCD): 0.966ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.850ns (routing 0.323ns, distribution 0.527ns) Clock Net Delay (Destination): 1.012ns (routing 0.374ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.850 0.966 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X45Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y288 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.173 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X46Y288 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.164 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/CLK SLICE_X46Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.130 1.034 SLICE_X46Y288 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.039 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -1.039 arrival time 1.187 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.164ns Source Clock Delay (SCD): 0.966ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.850ns (routing 0.323ns, distribution 0.527ns) Clock Net Delay (Destination): 1.012ns (routing 0.374ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.850 0.966 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X45Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y288 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.173 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X46Y288 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.164 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X46Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.130 1.034 SLICE_X46Y288 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.039 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.039 arrival time 1.187 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.164ns Source Clock Delay (SCD): 0.966ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.850ns (routing 0.323ns, distribution 0.527ns) Clock Net Delay (Destination): 1.012ns (routing 0.374ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.850 0.966 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X45Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y288 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.173 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X46Y288 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.164 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X46Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.130 1.034 SLICE_X46Y288 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.039 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.039 arrival time 1.187 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.164ns Source Clock Delay (SCD): 0.966ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.850ns (routing 0.323ns, distribution 0.527ns) Clock Net Delay (Destination): 1.012ns (routing 0.374ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.850 0.966 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X45Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y288 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.173 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X46Y288 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.164 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X46Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.130 1.034 SLICE_X46Y288 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.039 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.039 arrival time 1.187 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.164ns Source Clock Delay (SCD): 0.966ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.850ns (routing 0.323ns, distribution 0.527ns) Clock Net Delay (Destination): 1.012ns (routing 0.374ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.850 0.966 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X45Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y288 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.173 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X46Y288 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.164 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X46Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.130 1.034 SLICE_X46Y288 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.039 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -1.039 arrival time 1.187 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.164ns Source Clock Delay (SCD): 0.966ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.850ns (routing 0.323ns, distribution 0.527ns) Clock Net Delay (Destination): 1.012ns (routing 0.374ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.850 0.966 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X45Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y288 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.014 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.173 1.187 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X46Y288 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.012 1.164 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X46Y288 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.130 1.034 SLICE_X46Y288 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.039 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.039 arrival time 1.187 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.149ns (arrival time - required time) Source: SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[35].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.048ns (21.818%) route 0.172ns (78.182%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.279ns Source Clock Delay (SCD): 1.065ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 0.949ns (routing 0.323ns, distribution 0.626ns) Clock Net Delay (Destination): 1.127ns (routing 0.374ns, distribution 0.753ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.949 1.065 SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y270 FDPE r SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y270 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.113 f SFP_GEN[35].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.172 1.285 SFP_GEN[35].ngCCM_gbt/sync_m_reg[3][0] SLICE_X52Y270 FDCE f SFP_GEN[35].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.127 1.279 SFP_GEN[35].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X52Y270 FDCE r SFP_GEN[35].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.148 1.131 SLICE_X52Y270 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.136 SFP_GEN[35].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.136 arrival time 1.285 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.960ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.844ns (routing 0.323ns, distribution 0.521ns) Clock Net Delay (Destination): 1.017ns (routing 0.374ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.844 0.960 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X45Y284 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y284 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.009 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.211 1.220 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y286 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X42Y286 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[18]/C clock pessimism -0.130 1.039 SLICE_X42Y286 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.044 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[18] ------------------------------------------------------------------- required time -1.044 arrival time 1.220 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.960ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.844ns (routing 0.323ns, distribution 0.521ns) Clock Net Delay (Destination): 1.017ns (routing 0.374ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.844 0.960 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X45Y284 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y284 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.009 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.211 1.220 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y286 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X42Y286 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[19]/C clock pessimism -0.130 1.039 SLICE_X42Y286 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.044 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[19] ------------------------------------------------------------------- required time -1.044 arrival time 1.220 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.049ns (18.846%) route 0.211ns (81.154%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.960ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.844ns (routing 0.323ns, distribution 0.521ns) Clock Net Delay (Destination): 1.017ns (routing 0.374ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.844 0.960 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X45Y284 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X45Y284 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.009 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.211 1.220 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y286 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y19 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y105 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X42Y286 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[1]/C clock pessimism -0.130 1.039 SLICE_X42Y286 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.044 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[1] ------------------------------------------------------------------- required time -1.044 arrival time 1.220 ------------------------------------------------------------------- slack 0.176 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_27 To Clock: gtwiz_userclk_rx_srcclk_out[0]_27 Setup : 0 Failing Endpoints, Worst Slack 4.443ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.133ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.443ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.486ns (logic 0.364ns (10.442%) route 3.122ns (89.558%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.294ns = ( 10.611 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 1.918ns (routing 0.603ns, distribution 1.315ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.574 5.453 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X44Y167 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.225 5.678 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24/O net (fo=2, routed) 0.548 6.226 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X44Y164 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.918 10.611 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X44Y164 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.186 10.798 clock uncertainty -0.035 10.762 SLICE_X44Y164 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.669 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.669 arrival time -6.226 ------------------------------------------------------------------- slack 4.443 Slack (MET) : 4.443ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.486ns (logic 0.364ns (10.442%) route 3.122ns (89.558%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.294ns = ( 10.611 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 1.918ns (routing 0.603ns, distribution 1.315ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.574 5.453 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X44Y167 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.225 5.678 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24/O net (fo=2, routed) 0.548 6.226 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X44Y164 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.918 10.611 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X44Y164 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.186 10.798 clock uncertainty -0.035 10.762 SLICE_X44Y164 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 10.669 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.669 arrival time -6.226 ------------------------------------------------------------------- slack 4.443 Slack (MET) : 4.632ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.310ns (logic 0.364ns (10.997%) route 2.946ns (89.003%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.247ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 1.931ns (routing 0.603ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.412 5.291 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y165 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.516 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.534 6.050 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X45Y168 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.624 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X45Y168 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C clock pessimism 0.186 10.811 clock uncertainty -0.035 10.775 SLICE_X45Y168 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.682 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2] ------------------------------------------------------------------- required time 10.682 arrival time -6.050 ------------------------------------------------------------------- slack 4.632 Slack (MET) : 4.632ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.310ns (logic 0.364ns (10.997%) route 2.946ns (89.003%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.247ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 1.931ns (routing 0.603ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.412 5.291 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y165 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.516 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.534 6.050 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X45Y168 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.624 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X45Y168 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C clock pessimism 0.186 10.811 clock uncertainty -0.035 10.775 SLICE_X45Y168 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.682 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6] ------------------------------------------------------------------- required time 10.682 arrival time -6.050 ------------------------------------------------------------------- slack 4.632 Slack (MET) : 4.632ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.310ns (logic 0.364ns (10.997%) route 2.946ns (89.003%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.247ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 1.931ns (routing 0.603ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.412 5.291 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y165 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.516 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.534 6.050 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X45Y168 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.624 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X45Y168 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C clock pessimism 0.186 10.811 clock uncertainty -0.035 10.775 SLICE_X45Y168 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.682 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7] ------------------------------------------------------------------- required time 10.682 arrival time -6.050 ------------------------------------------------------------------- slack 4.632 Slack (MET) : 4.640ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.300ns (logic 0.364ns (11.030%) route 2.936ns (88.970%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.249ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.305ns = ( 10.622 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 1.929ns (routing 0.603ns, distribution 1.326ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.412 5.291 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y165 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.516 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.524 6.040 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X45Y168 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.929 10.622 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X45Y168 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C clock pessimism 0.186 10.809 clock uncertainty -0.035 10.773 SLICE_X45Y168 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.680 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3] ------------------------------------------------------------------- required time 10.680 arrival time -6.040 ------------------------------------------------------------------- slack 4.640 Slack (MET) : 4.640ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.300ns (logic 0.364ns (11.030%) route 2.936ns (88.970%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.249ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.305ns = ( 10.622 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 1.929ns (routing 0.603ns, distribution 1.326ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.412 5.291 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y165 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.516 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.524 6.040 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X45Y168 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.929 10.622 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X45Y168 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C clock pessimism 0.186 10.809 clock uncertainty -0.035 10.773 SLICE_X45Y168 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 10.680 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4] ------------------------------------------------------------------- required time 10.680 arrival time -6.040 ------------------------------------------------------------------- slack 4.640 Slack (MET) : 4.709ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.241ns (logic 0.364ns (11.231%) route 2.877ns (88.769%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.239ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.315ns = ( 10.632 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 1.939ns (routing 0.603ns, distribution 1.336ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.412 5.291 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y165 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.516 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.465 5.981 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X45Y167 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.939 10.632 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X45Y167 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C clock pessimism 0.186 10.819 clock uncertainty -0.035 10.783 SLICE_X45Y167 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.690 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5] ------------------------------------------------------------------- required time 10.690 arrival time -5.981 ------------------------------------------------------------------- slack 4.709 Slack (MET) : 4.714ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.233ns (logic 0.364ns (11.259%) route 2.869ns (88.741%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.242ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.312ns = ( 10.629 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 1.936ns (routing 0.603ns, distribution 1.333ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.412 5.291 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y165 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.516 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.457 5.973 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X44Y167 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.936 10.629 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X44Y167 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C clock pessimism 0.186 10.816 clock uncertainty -0.035 10.780 SLICE_X44Y167 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.687 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1] ------------------------------------------------------------------- required time 10.687 arrival time -5.973 ------------------------------------------------------------------- slack 4.714 Slack (MET) : 4.717ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 3.231ns (logic 0.364ns (11.266%) route 2.867ns (88.734%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.241ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.313ns = ( 10.630 - 8.317 ) Source Clock Delay (SCD): 2.740ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.315ns (routing 0.667ns, distribution 1.648ns) Clock Net Delay (Destination): 1.937ns (routing 0.603ns, distribution 1.334ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.315 2.740 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y158 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y158 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.879 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.412 5.291 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X44Y165 LUT3 (Prop_B6LUT_SLICEM_I0_O) 0.225 5.516 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/O net (fo=15, routed) 0.455 5.971 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X45Y167 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.937 10.630 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X45Y167 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C clock pessimism 0.186 10.817 clock uncertainty -0.035 10.781 SLICE_X45Y167 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.688 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0] ------------------------------------------------------------------- required time 10.688 arrival time -5.971 ------------------------------------------------------------------- slack 4.717 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.133ns (arrival time - required time) Source: SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.048ns (21.333%) route 0.177ns (78.667%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.087ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.971ns (routing 0.301ns, distribution 0.670ns) Clock Net Delay (Destination): 1.166ns (routing 0.348ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.971 1.087 SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y176 FDPE r SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y176 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.135 f SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.177 1.312 SFP_GEN[25].ngCCM_gbt/sync_m_reg[3][0] SLICE_X54Y176 FDCE f SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.318 SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y176 FDCE r SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.144 1.174 SLICE_X54Y176 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.179 SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.179 arrival time 1.312 ------------------------------------------------------------------- slack 0.133 Slack (MET) : 0.133ns (arrival time - required time) Source: SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.048ns (21.333%) route 0.177ns (78.667%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.087ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.971ns (routing 0.301ns, distribution 0.670ns) Clock Net Delay (Destination): 1.166ns (routing 0.348ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.971 1.087 SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y176 FDPE r SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y176 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.135 f SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.177 1.312 SFP_GEN[25].ngCCM_gbt/sync_m_reg[3][0] SLICE_X54Y176 FDCE f SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.318 SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y176 FDCE r SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.144 1.174 SLICE_X54Y176 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.179 SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -1.179 arrival time 1.312 ------------------------------------------------------------------- slack 0.133 Slack (MET) : 0.133ns (arrival time - required time) Source: SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.048ns (21.333%) route 0.177ns (78.667%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.318ns Source Clock Delay (SCD): 1.087ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.971ns (routing 0.301ns, distribution 0.670ns) Clock Net Delay (Destination): 1.166ns (routing 0.348ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.971 1.087 SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y176 FDPE r SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y176 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.135 f SFP_GEN[25].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.177 1.312 SFP_GEN[25].ngCCM_gbt/sync_m_reg[3][0] SLICE_X54Y176 FDCE f SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.166 1.318 SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X54Y176 FDCE r SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.144 1.174 SLICE_X54Y176 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.179 SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.179 arrival time 1.312 ------------------------------------------------------------------- slack 0.133 Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[71]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.848ns (routing 0.301ns, distribution 0.547ns) Clock Net Delay (Destination): 1.014ns (routing 0.348ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X41Y163 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y163 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[71]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X42Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[71]/C clock pessimism -0.125 1.041 SLICE_X42Y161 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.046 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[71] ------------------------------------------------------------------- required time -1.046 arrival time 1.234 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[77]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.848ns (routing 0.301ns, distribution 0.547ns) Clock Net Delay (Destination): 1.014ns (routing 0.348ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X41Y163 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y163 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[77]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X42Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[77]/C clock pessimism -0.125 1.041 SLICE_X42Y161 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.046 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[77] ------------------------------------------------------------------- required time -1.046 arrival time 1.234 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[79]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.848ns (routing 0.301ns, distribution 0.547ns) Clock Net Delay (Destination): 1.014ns (routing 0.348ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X41Y163 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y163 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[79]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X42Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[79]/C clock pessimism -0.125 1.041 SLICE_X42Y161 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.046 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[79] ------------------------------------------------------------------- required time -1.046 arrival time 1.234 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.848ns (routing 0.301ns, distribution 0.547ns) Clock Net Delay (Destination): 1.014ns (routing 0.348ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X41Y163 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y163 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X42Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]/C clock pessimism -0.125 1.041 SLICE_X42Y161 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.046 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23] ------------------------------------------------------------------- required time -1.046 arrival time 1.234 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[71]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.848ns (routing 0.301ns, distribution 0.547ns) Clock Net Delay (Destination): 1.014ns (routing 0.348ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X41Y163 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y163 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[71]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X42Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[71]/C clock pessimism -0.125 1.041 SLICE_X42Y161 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.046 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[71] ------------------------------------------------------------------- required time -1.046 arrival time 1.234 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[77]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.848ns (routing 0.301ns, distribution 0.547ns) Clock Net Delay (Destination): 1.014ns (routing 0.348ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X41Y163 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y163 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[77]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X42Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[77]/C clock pessimism -0.125 1.041 SLICE_X42Y161 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.046 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[77] ------------------------------------------------------------------- required time -1.046 arrival time 1.234 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[79]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.848ns (routing 0.301ns, distribution 0.547ns) Clock Net Delay (Destination): 1.014ns (routing 0.348ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK SLICE_X41Y163 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y163 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y161 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[79]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X42Y161 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[79]/C clock pessimism -0.125 1.041 SLICE_X42Y161 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.046 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[79] ------------------------------------------------------------------- required time -1.046 arrival time 1.234 ------------------------------------------------------------------- slack 0.188 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_28 To Clock: gtwiz_userclk_rx_srcclk_out[0]_28 Setup : 0 Failing Endpoints, Worst Slack 5.210ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.201ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.210ns (required time - arrival time) Source: SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 2.504ns (logic 0.139ns (5.551%) route 2.365ns (94.449%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.554ns (routing 0.699ns, distribution 1.855ns) Clock Net Delay (Destination): 1.930ns (routing 0.636ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.554 2.979 SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y177 FDPE r SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y177 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.118 f SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.365 5.483 SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] SLICE_X44Y139 FDCE f SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y139 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism 0.198 10.821 clock uncertainty -0.035 10.786 SLICE_X44Y139 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.693 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time 10.693 arrival time -5.483 ------------------------------------------------------------------- slack 5.210 Slack (MET) : 5.210ns (required time - arrival time) Source: SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 2.504ns (logic 0.139ns (5.551%) route 2.365ns (94.449%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.554ns (routing 0.699ns, distribution 1.855ns) Clock Net Delay (Destination): 1.930ns (routing 0.636ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.554 2.979 SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y177 FDPE r SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y177 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.118 f SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.365 5.483 SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] SLICE_X44Y139 FDCE f SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y139 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism 0.198 10.821 clock uncertainty -0.035 10.786 SLICE_X44Y139 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.693 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time 10.693 arrival time -5.483 ------------------------------------------------------------------- slack 5.210 Slack (MET) : 5.210ns (required time - arrival time) Source: SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 2.504ns (logic 0.139ns (5.551%) route 2.365ns (94.449%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.554ns (routing 0.699ns, distribution 1.855ns) Clock Net Delay (Destination): 1.930ns (routing 0.636ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.554 2.979 SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y177 FDPE r SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y177 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.118 f SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.365 5.483 SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] SLICE_X44Y139 FDCE f SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y139 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism 0.198 10.821 clock uncertainty -0.035 10.786 SLICE_X44Y139 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.693 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time 10.693 arrival time -5.483 ------------------------------------------------------------------- slack 5.210 Slack (MET) : 5.210ns (required time - arrival time) Source: SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 2.504ns (logic 0.139ns (5.551%) route 2.365ns (94.449%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.554ns (routing 0.699ns, distribution 1.855ns) Clock Net Delay (Destination): 1.930ns (routing 0.636ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.554 2.979 SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y177 FDPE r SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y177 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.118 f SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.365 5.483 SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] SLICE_X44Y139 FDCE f SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y139 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism 0.198 10.821 clock uncertainty -0.035 10.786 SLICE_X44Y139 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 10.693 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time 10.693 arrival time -5.483 ------------------------------------------------------------------- slack 5.210 Slack (MET) : 5.210ns (required time - arrival time) Source: SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 2.504ns (logic 0.139ns (5.551%) route 2.365ns (94.449%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.554ns (routing 0.699ns, distribution 1.855ns) Clock Net Delay (Destination): 1.930ns (routing 0.636ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.554 2.979 SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y177 FDPE r SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y177 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.118 f SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.365 5.483 SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] SLICE_X44Y139 FDCE f SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y139 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism 0.198 10.821 clock uncertainty -0.035 10.786 SLICE_X44Y139 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.693 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time 10.693 arrival time -5.483 ------------------------------------------------------------------- slack 5.210 Slack (MET) : 5.210ns (required time - arrival time) Source: SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 2.504ns (logic 0.139ns (5.551%) route 2.365ns (94.449%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.554ns (routing 0.699ns, distribution 1.855ns) Clock Net Delay (Destination): 1.930ns (routing 0.636ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.554 2.979 SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y177 FDPE r SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y177 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.118 f SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.365 5.483 SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] SLICE_X44Y139 FDCE f SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y139 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism 0.198 10.821 clock uncertainty -0.035 10.786 SLICE_X44Y139 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 10.693 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time 10.693 arrival time -5.483 ------------------------------------------------------------------- slack 5.210 Slack (MET) : 5.210ns (required time - arrival time) Source: SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 2.504ns (logic 0.139ns (5.551%) route 2.365ns (94.449%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.554ns (routing 0.699ns, distribution 1.855ns) Clock Net Delay (Destination): 1.930ns (routing 0.636ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.554 2.979 SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y177 FDPE r SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y177 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.118 f SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.365 5.483 SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] SLICE_X44Y139 FDCE f SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y139 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[4]/C clock pessimism 0.198 10.821 clock uncertainty -0.035 10.786 SLICE_X44Y139 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.693 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[4] ------------------------------------------------------------------- required time 10.693 arrival time -5.483 ------------------------------------------------------------------- slack 5.210 Slack (MET) : 5.210ns (required time - arrival time) Source: SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 2.504ns (logic 0.139ns (5.551%) route 2.365ns (94.449%)) Logic Levels: 0 Clock Path Skew: -0.475ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.198ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.554ns (routing 0.699ns, distribution 1.855ns) Clock Net Delay (Destination): 1.930ns (routing 0.636ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.554 2.979 SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y177 FDPE r SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y177 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.118 f SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.365 5.483 SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] SLICE_X44Y139 FDCE f SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y139 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[6]/C clock pessimism 0.198 10.821 clock uncertainty -0.035 10.786 SLICE_X44Y139 FDCE (Recov_AFF2_SLICEM_C_CLR) -0.093 10.693 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[6] ------------------------------------------------------------------- required time 10.693 arrival time -5.483 ------------------------------------------------------------------- slack 5.210 Slack (MET) : 5.241ns (required time - arrival time) Source: SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 2.488ns (logic 0.139ns (5.587%) route 2.349ns (94.413%)) Logic Levels: 0 Clock Path Skew: -0.460ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.322ns = ( 10.639 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.554ns (routing 0.699ns, distribution 1.855ns) Clock Net Delay (Destination): 1.946ns (routing 0.636ns, distribution 1.310ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.554 2.979 SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y177 FDPE r SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y177 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.118 f SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.349 5.467 SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] SLICE_X45Y140 FDCE f SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.946 10.639 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X45Y140 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[17]/C clock pessimism 0.197 10.837 clock uncertainty -0.035 10.801 SLICE_X45Y140 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.708 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[17] ------------------------------------------------------------------- required time 10.708 arrival time -5.467 ------------------------------------------------------------------- slack 5.241 Slack (MET) : 5.241ns (required time - arrival time) Source: SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 2.488ns (logic 0.139ns (5.587%) route 2.349ns (94.413%)) Logic Levels: 0 Clock Path Skew: -0.460ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.322ns = ( 10.639 - 8.317 ) Source Clock Delay (SCD): 2.979ns Clock Pessimism Removal (CPR): 0.197ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.554ns (routing 0.699ns, distribution 1.855ns) Clock Net Delay (Destination): 1.946ns (routing 0.636ns, distribution 1.310ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.554 2.979 SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y177 FDPE r SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y177 FDPE (Prop_CFF2_SLICEM_C_Q) 0.139 3.118 f SFP_GEN[26].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.349 5.467 SFP_GEN[26].ngCCM_gbt/sync_m_reg[3][0] SLICE_X45Y140 FDCE f SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.946 10.639 SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X45Y140 FDCE r SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism 0.197 10.837 clock uncertainty -0.035 10.801 SLICE_X45Y140 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 10.708 SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time 10.708 arrival time -5.467 ------------------------------------------------------------------- slack 5.241 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.201ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.283ns (logic 0.048ns (16.961%) route 0.235ns (83.039%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.168ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.845ns (routing 0.319ns, distribution 0.526ns) Clock Net Delay (Destination): 1.016ns (routing 0.369ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X42Y147 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y147 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.009 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.235 1.244 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X44Y142 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X44Y142 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.130 1.038 SLICE_X44Y142 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.043 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.043 arrival time 1.244 ------------------------------------------------------------------- slack 0.201 Slack (MET) : 0.201ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.283ns (logic 0.048ns (16.961%) route 0.235ns (83.039%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.168ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.845ns (routing 0.319ns, distribution 0.526ns) Clock Net Delay (Destination): 1.016ns (routing 0.369ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X42Y147 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y147 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.009 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.235 1.244 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X44Y142 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X44Y142 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.130 1.038 SLICE_X44Y142 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.043 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.043 arrival time 1.244 ------------------------------------------------------------------- slack 0.201 Slack (MET) : 0.203ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.240ns (logic 0.048ns (20.000%) route 0.192ns (80.000%)) Logic Levels: 0 Clock Path Skew: 0.032ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.157ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 0.845ns (routing 0.319ns, distribution 0.526ns) Clock Net Delay (Destination): 1.005ns (routing 0.369ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X42Y147 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y147 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.009 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.192 1.201 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X42Y143 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.005 1.157 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X42Y143 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.164 0.993 SLICE_X42Y143 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 0.998 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -0.998 arrival time 1.201 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.206ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.048ns (16.609%) route 0.241ns (83.391%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.845ns (routing 0.319ns, distribution 0.526ns) Clock Net Delay (Destination): 1.017ns (routing 0.369ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X42Y147 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y147 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.009 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.241 1.250 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X44Y141 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X44Y141 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.130 1.039 SLICE_X44Y141 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.044 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.044 arrival time 1.250 ------------------------------------------------------------------- slack 0.206 Slack (MET) : 0.206ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.048ns (16.609%) route 0.241ns (83.391%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.845ns (routing 0.319ns, distribution 0.526ns) Clock Net Delay (Destination): 1.017ns (routing 0.369ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X42Y147 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y147 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.009 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.241 1.250 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X44Y141 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X44Y141 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.130 1.039 SLICE_X44Y141 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.044 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.044 arrival time 1.250 ------------------------------------------------------------------- slack 0.206 Slack (MET) : 0.206ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.048ns (16.609%) route 0.241ns (83.391%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.845ns (routing 0.319ns, distribution 0.526ns) Clock Net Delay (Destination): 1.017ns (routing 0.369ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X42Y147 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X42Y147 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.009 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.241 1.250 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X44Y141 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X44Y141 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.130 1.039 SLICE_X44Y141 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.044 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.044 arrival time 1.250 ------------------------------------------------------------------- slack 0.206 Slack (MET) : 0.206ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[40]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.285ns (logic 0.049ns (17.193%) route 0.236ns (82.807%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.144ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.824ns (routing 0.319ns, distribution 0.505ns) Clock Net Delay (Destination): 0.992ns (routing 0.369ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.940 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X36Y154 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y154 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.236 1.225 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X36Y148 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[40]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.992 1.144 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X36Y148 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[40]/C clock pessimism -0.130 1.014 SLICE_X36Y148 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.019 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[40] ------------------------------------------------------------------- required time -1.019 arrival time 1.225 ------------------------------------------------------------------- slack 0.206 Slack (MET) : 0.206ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[57]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.285ns (logic 0.049ns (17.193%) route 0.236ns (82.807%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.144ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.824ns (routing 0.319ns, distribution 0.505ns) Clock Net Delay (Destination): 0.992ns (routing 0.369ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.940 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X36Y154 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y154 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.236 1.225 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X36Y148 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[57]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.992 1.144 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X36Y148 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[57]/C clock pessimism -0.130 1.014 SLICE_X36Y148 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.019 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[57] ------------------------------------------------------------------- required time -1.019 arrival time 1.225 ------------------------------------------------------------------- slack 0.206 Slack (MET) : 0.206ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[58]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.285ns (logic 0.049ns (17.193%) route 0.236ns (82.807%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.144ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.824ns (routing 0.319ns, distribution 0.505ns) Clock Net Delay (Destination): 0.992ns (routing 0.369ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.940 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X36Y154 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y154 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.236 1.225 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X36Y148 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[58]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.992 1.144 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X36Y148 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[58]/C clock pessimism -0.130 1.014 SLICE_X36Y148 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.019 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[58] ------------------------------------------------------------------- required time -1.019 arrival time 1.225 ------------------------------------------------------------------- slack 0.206 Slack (MET) : 0.206ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[59]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns) Data Path Delay: 0.285ns (logic 0.049ns (17.193%) route 0.236ns (82.807%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.144ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.824ns (routing 0.319ns, distribution 0.505ns) Clock Net Delay (Destination): 0.992ns (routing 0.369ns, distribution 0.623ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.824 0.940 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X36Y154 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X36Y154 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 0.989 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.236 1.225 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X36Y148 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[59]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.992 1.144 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X36Y148 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[59]/C clock pessimism -0.130 1.014 SLICE_X36Y148 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.019 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[59] ------------------------------------------------------------------- required time -1.019 arrival time 1.225 ------------------------------------------------------------------- slack 0.206 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_29 To Clock: gtwiz_userclk_rx_srcclk_out[0]_29 Setup : 0 Failing Endpoints, Worst Slack 5.335ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.102ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.335ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 2.565ns (logic 0.364ns (14.191%) route 2.201ns (85.809%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.413ns = ( 10.730 - 8.317 ) Source Clock Delay (SCD): 2.906ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.481ns (routing 0.804ns, distribution 1.677ns) Clock Net Delay (Destination): 2.037ns (routing 0.721ns, distribution 1.316ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.481 2.906 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.045 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.256 4.301 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X28Y173 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.526 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.945 5.471 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X27Y172 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.037 10.730 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y172 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/C clock pessimism 0.204 10.934 clock uncertainty -0.035 10.899 SLICE_X27Y172 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.806 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1] ------------------------------------------------------------------- required time 10.806 arrival time -5.471 ------------------------------------------------------------------- slack 5.335 Slack (MET) : 5.335ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 2.565ns (logic 0.364ns (14.191%) route 2.201ns (85.809%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.413ns = ( 10.730 - 8.317 ) Source Clock Delay (SCD): 2.906ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.481ns (routing 0.804ns, distribution 1.677ns) Clock Net Delay (Destination): 2.037ns (routing 0.721ns, distribution 1.316ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.481 2.906 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.045 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.256 4.301 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X28Y173 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.526 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.945 5.471 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X27Y172 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.037 10.730 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y172 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/C clock pessimism 0.204 10.934 clock uncertainty -0.035 10.899 SLICE_X27Y172 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.806 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2] ------------------------------------------------------------------- required time 10.806 arrival time -5.471 ------------------------------------------------------------------- slack 5.335 Slack (MET) : 5.335ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 2.565ns (logic 0.364ns (14.191%) route 2.201ns (85.809%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.413ns = ( 10.730 - 8.317 ) Source Clock Delay (SCD): 2.906ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.481ns (routing 0.804ns, distribution 1.677ns) Clock Net Delay (Destination): 2.037ns (routing 0.721ns, distribution 1.316ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.481 2.906 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.045 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.256 4.301 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X28Y173 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.526 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.945 5.471 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X27Y172 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.037 10.730 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y172 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C clock pessimism 0.204 10.934 clock uncertainty -0.035 10.899 SLICE_X27Y172 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.806 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3] ------------------------------------------------------------------- required time 10.806 arrival time -5.471 ------------------------------------------------------------------- slack 5.335 Slack (MET) : 5.335ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 2.565ns (logic 0.364ns (14.191%) route 2.201ns (85.809%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.413ns = ( 10.730 - 8.317 ) Source Clock Delay (SCD): 2.906ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.481ns (routing 0.804ns, distribution 1.677ns) Clock Net Delay (Destination): 2.037ns (routing 0.721ns, distribution 1.316ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.481 2.906 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.045 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.256 4.301 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X28Y173 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.526 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.945 5.471 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X27Y172 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.037 10.730 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y172 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/C clock pessimism 0.204 10.934 clock uncertainty -0.035 10.899 SLICE_X27Y172 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.806 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4] ------------------------------------------------------------------- required time 10.806 arrival time -5.471 ------------------------------------------------------------------- slack 5.335 Slack (MET) : 5.335ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 2.565ns (logic 0.364ns (14.191%) route 2.201ns (85.809%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.413ns = ( 10.730 - 8.317 ) Source Clock Delay (SCD): 2.906ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.481ns (routing 0.804ns, distribution 1.677ns) Clock Net Delay (Destination): 2.037ns (routing 0.721ns, distribution 1.316ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.481 2.906 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.045 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.256 4.301 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X28Y173 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.526 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.945 5.471 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X27Y172 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.037 10.730 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y172 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/C clock pessimism 0.204 10.934 clock uncertainty -0.035 10.899 SLICE_X27Y172 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.806 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5] ------------------------------------------------------------------- required time 10.806 arrival time -5.471 ------------------------------------------------------------------- slack 5.335 Slack (MET) : 5.353ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 2.537ns (logic 0.364ns (14.348%) route 2.173ns (85.652%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.299ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.403ns = ( 10.720 - 8.317 ) Source Clock Delay (SCD): 2.906ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.481ns (routing 0.804ns, distribution 1.677ns) Clock Net Delay (Destination): 2.027ns (routing 0.721ns, distribution 1.306ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.481 2.906 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.045 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.256 4.301 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X28Y173 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.526 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.917 5.443 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X27Y173 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.027 10.720 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y173 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C clock pessimism 0.204 10.924 clock uncertainty -0.035 10.889 SLICE_X27Y173 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.796 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3] ------------------------------------------------------------------- required time 10.796 arrival time -5.443 ------------------------------------------------------------------- slack 5.353 Slack (MET) : 5.353ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 2.537ns (logic 0.364ns (14.348%) route 2.173ns (85.652%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.299ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.403ns = ( 10.720 - 8.317 ) Source Clock Delay (SCD): 2.906ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.481ns (routing 0.804ns, distribution 1.677ns) Clock Net Delay (Destination): 2.027ns (routing 0.721ns, distribution 1.306ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.481 2.906 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.045 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.256 4.301 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X28Y173 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.526 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.917 5.443 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X27Y173 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.027 10.720 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y173 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/C clock pessimism 0.204 10.924 clock uncertainty -0.035 10.889 SLICE_X27Y173 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.796 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0] ------------------------------------------------------------------- required time 10.796 arrival time -5.443 ------------------------------------------------------------------- slack 5.353 Slack (MET) : 5.470ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 2.431ns (logic 0.364ns (14.973%) route 2.067ns (85.027%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.288ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.414ns = ( 10.731 - 8.317 ) Source Clock Delay (SCD): 2.906ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.481ns (routing 0.804ns, distribution 1.677ns) Clock Net Delay (Destination): 2.038ns (routing 0.721ns, distribution 1.317ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.481 2.906 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.045 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.256 4.301 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X28Y173 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.526 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.811 5.337 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X27Y174 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.038 10.731 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y174 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C clock pessimism 0.204 10.935 clock uncertainty -0.035 10.900 SLICE_X27Y174 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.807 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2] ------------------------------------------------------------------- required time 10.807 arrival time -5.337 ------------------------------------------------------------------- slack 5.470 Slack (MET) : 5.470ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 2.431ns (logic 0.364ns (14.973%) route 2.067ns (85.027%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.288ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.414ns = ( 10.731 - 8.317 ) Source Clock Delay (SCD): 2.906ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.481ns (routing 0.804ns, distribution 1.677ns) Clock Net Delay (Destination): 2.038ns (routing 0.721ns, distribution 1.317ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.481 2.906 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.045 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.256 4.301 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X28Y173 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.526 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.811 5.337 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X27Y174 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.038 10.731 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y174 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C clock pessimism 0.204 10.935 clock uncertainty -0.035 10.900 SLICE_X27Y174 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.807 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6] ------------------------------------------------------------------- required time 10.807 arrival time -5.337 ------------------------------------------------------------------- slack 5.470 Slack (MET) : 5.470ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 2.431ns (logic 0.364ns (14.973%) route 2.067ns (85.027%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.288ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.414ns = ( 10.731 - 8.317 ) Source Clock Delay (SCD): 2.906ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.481ns (routing 0.804ns, distribution 1.677ns) Clock Net Delay (Destination): 2.038ns (routing 0.721ns, distribution 1.317ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.481 2.906 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y171 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.045 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.256 4.301 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X28Y173 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.526 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/O net (fo=15, routed) 0.811 5.337 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X27Y174 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.038 10.731 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X27Y174 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C clock pessimism 0.204 10.935 clock uncertainty -0.035 10.900 SLICE_X27Y174 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.807 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7] ------------------------------------------------------------------- required time 10.807 arrival time -5.337 ------------------------------------------------------------------- slack 5.470 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.102ns (arrival time - required time) Source: SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[27].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.196ns (logic 0.048ns (24.490%) route 0.148ns (75.510%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.257ns Source Clock Delay (SCD): 1.025ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.909ns (routing 0.382ns, distribution 0.527ns) Clock Net Delay (Destination): 1.105ns (routing 0.446ns, distribution 0.659ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.909 1.025 SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X37Y173 FDPE r SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y173 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.073 f SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.148 1.221 SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] SLICE_X35Y173 FDCE f SFP_GEN[27].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.105 1.257 SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y173 FDCE r SFP_GEN[27].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.143 1.114 SLICE_X35Y173 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.119 SFP_GEN[27].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.119 arrival time 1.221 ------------------------------------------------------------------- slack 0.102 Slack (MET) : 0.165ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.049ns (21.586%) route 0.178ns (78.414%)) Logic Levels: 0 Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.268ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.953ns (routing 0.382ns, distribution 0.571ns) Clock Net Delay (Destination): 1.116ns (routing 0.446ns, distribution 0.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.069 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X22Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X22Y171 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.118 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.178 1.296 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X23Y171 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.116 1.268 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X23Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.142 1.126 SLICE_X23Y171 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.131 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.131 arrival time 1.296 ------------------------------------------------------------------- slack 0.165 Slack (MET) : 0.165ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.049ns (21.586%) route 0.178ns (78.414%)) Logic Levels: 0 Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.268ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.953ns (routing 0.382ns, distribution 0.571ns) Clock Net Delay (Destination): 1.116ns (routing 0.446ns, distribution 0.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.069 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X22Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X22Y171 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.118 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.178 1.296 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X23Y171 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.116 1.268 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X23Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.142 1.126 SLICE_X23Y171 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.131 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.131 arrival time 1.296 ------------------------------------------------------------------- slack 0.165 Slack (MET) : 0.165ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.049ns (21.586%) route 0.178ns (78.414%)) Logic Levels: 0 Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.268ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.953ns (routing 0.382ns, distribution 0.571ns) Clock Net Delay (Destination): 1.116ns (routing 0.446ns, distribution 0.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.069 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X22Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X22Y171 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.118 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.178 1.296 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X23Y171 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.116 1.268 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X23Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.142 1.126 SLICE_X23Y171 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.131 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -1.131 arrival time 1.296 ------------------------------------------------------------------- slack 0.165 Slack (MET) : 0.165ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.049ns (21.586%) route 0.178ns (78.414%)) Logic Levels: 0 Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.268ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.953ns (routing 0.382ns, distribution 0.571ns) Clock Net Delay (Destination): 1.116ns (routing 0.446ns, distribution 0.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.069 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X22Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X22Y171 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.118 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.178 1.296 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X23Y171 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.116 1.268 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X23Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.142 1.126 SLICE_X23Y171 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.131 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.131 arrival time 1.296 ------------------------------------------------------------------- slack 0.165 Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.266ns (logic 0.049ns (18.421%) route 0.217ns (81.579%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.284ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.953ns (routing 0.382ns, distribution 0.571ns) Clock Net Delay (Destination): 1.132ns (routing 0.446ns, distribution 0.686ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.069 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X22Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X22Y171 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.118 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.335 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X23Y170 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.132 1.284 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X23Y170 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.142 1.142 SLICE_X23Y170 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.147 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.147 arrival time 1.335 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.266ns (logic 0.049ns (18.421%) route 0.217ns (81.579%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.284ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.953ns (routing 0.382ns, distribution 0.571ns) Clock Net Delay (Destination): 1.132ns (routing 0.446ns, distribution 0.686ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.069 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X22Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X22Y171 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.118 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.335 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X23Y170 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.132 1.284 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X23Y170 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.142 1.142 SLICE_X23Y170 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.147 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.147 arrival time 1.335 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.188ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.266ns (logic 0.049ns (18.421%) route 0.217ns (81.579%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.284ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.953ns (routing 0.382ns, distribution 0.571ns) Clock Net Delay (Destination): 1.132ns (routing 0.446ns, distribution 0.686ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.069 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X22Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X22Y171 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.118 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.217 1.335 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X23Y170 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.132 1.284 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X23Y170 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.142 1.142 SLICE_X23Y170 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.147 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.147 arrival time 1.335 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.275ns (logic 0.049ns (17.818%) route 0.226ns (82.182%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.285ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.953ns (routing 0.382ns, distribution 0.571ns) Clock Net Delay (Destination): 1.133ns (routing 0.446ns, distribution 0.687ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.069 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X22Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X22Y171 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.118 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.226 1.344 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X24Y169 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.133 1.285 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X24Y169 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.142 1.143 SLICE_X24Y169 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.148 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.148 arrival time 1.344 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns) Data Path Delay: 0.275ns (logic 0.049ns (17.818%) route 0.226ns (82.182%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.285ns Source Clock Delay (SCD): 1.069ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.953ns (routing 0.382ns, distribution 0.571ns) Clock Net Delay (Destination): 1.133ns (routing 0.446ns, distribution 0.687ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 0.953 1.069 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X22Y171 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X22Y171 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.118 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.226 1.344 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X24Y169 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.133 1.285 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X24Y169 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.142 1.143 SLICE_X24Y169 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.148 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.148 arrival time 1.344 ------------------------------------------------------------------- slack 0.196 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_3 To Clock: gtwiz_userclk_rx_srcclk_out[0]_3 Setup : 0 Failing Endpoints, Worst Slack 4.028ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.102ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.028ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.508ns (logic 0.374ns (10.661%) route 3.134ns (89.339%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.653ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.782ns = ( 11.099 - 8.317 ) Source Clock Delay (SCD): 3.707ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.232ns (routing 1.234ns, distribution 1.998ns) Clock Net Delay (Destination): 2.384ns (routing 1.125ns, distribution 1.259ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.232 3.707 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y79 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.846 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.391 6.237 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y80 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.472 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 0.743 7.215 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X80Y80 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.384 11.099 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X80Y80 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/C clock pessimism 0.272 11.371 clock uncertainty -0.035 11.336 SLICE_X80Y80 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.243 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1] ------------------------------------------------------------------- required time 11.243 arrival time -7.215 ------------------------------------------------------------------- slack 4.028 Slack (MET) : 4.028ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.508ns (logic 0.374ns (10.661%) route 3.134ns (89.339%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.653ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.782ns = ( 11.099 - 8.317 ) Source Clock Delay (SCD): 3.707ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.232ns (routing 1.234ns, distribution 1.998ns) Clock Net Delay (Destination): 2.384ns (routing 1.125ns, distribution 1.259ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.232 3.707 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y79 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.846 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.391 6.237 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y80 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.472 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 0.743 7.215 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X80Y80 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.384 11.099 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X80Y80 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/C clock pessimism 0.272 11.371 clock uncertainty -0.035 11.336 SLICE_X80Y80 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 11.243 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2] ------------------------------------------------------------------- required time 11.243 arrival time -7.215 ------------------------------------------------------------------- slack 4.028 Slack (MET) : 4.028ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.508ns (logic 0.374ns (10.661%) route 3.134ns (89.339%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.653ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.782ns = ( 11.099 - 8.317 ) Source Clock Delay (SCD): 3.707ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.232ns (routing 1.234ns, distribution 1.998ns) Clock Net Delay (Destination): 2.384ns (routing 1.125ns, distribution 1.259ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.232 3.707 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y79 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.846 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.391 6.237 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y80 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.472 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 0.743 7.215 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X80Y80 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.384 11.099 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X80Y80 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C clock pessimism 0.272 11.371 clock uncertainty -0.035 11.336 SLICE_X80Y80 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.243 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3] ------------------------------------------------------------------- required time 11.243 arrival time -7.215 ------------------------------------------------------------------- slack 4.028 Slack (MET) : 4.028ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.508ns (logic 0.374ns (10.661%) route 3.134ns (89.339%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.653ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.782ns = ( 11.099 - 8.317 ) Source Clock Delay (SCD): 3.707ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.232ns (routing 1.234ns, distribution 1.998ns) Clock Net Delay (Destination): 2.384ns (routing 1.125ns, distribution 1.259ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.232 3.707 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y79 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.846 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.391 6.237 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y80 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.472 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 0.743 7.215 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X80Y80 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.384 11.099 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X80Y80 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/C clock pessimism 0.272 11.371 clock uncertainty -0.035 11.336 SLICE_X80Y80 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.243 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4] ------------------------------------------------------------------- required time 11.243 arrival time -7.215 ------------------------------------------------------------------- slack 4.028 Slack (MET) : 4.078ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.449ns (logic 0.374ns (10.844%) route 3.075ns (89.156%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.662ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.773ns = ( 11.090 - 8.317 ) Source Clock Delay (SCD): 3.707ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.232ns (routing 1.234ns, distribution 1.998ns) Clock Net Delay (Destination): 2.375ns (routing 1.125ns, distribution 1.250ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.232 3.707 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y79 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.846 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.391 6.237 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y80 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.472 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 0.684 7.156 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X80Y81 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.375 11.090 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X80Y81 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C clock pessimism 0.272 11.362 clock uncertainty -0.035 11.327 SLICE_X80Y81 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.234 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1] ------------------------------------------------------------------- required time 11.234 arrival time -7.156 ------------------------------------------------------------------- slack 4.078 Slack (MET) : 4.086ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.439ns (logic 0.374ns (10.875%) route 3.065ns (89.125%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.664ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.771ns = ( 11.088 - 8.317 ) Source Clock Delay (SCD): 3.707ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.232ns (routing 1.234ns, distribution 1.998ns) Clock Net Delay (Destination): 2.373ns (routing 1.125ns, distribution 1.248ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.232 3.707 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y79 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.846 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.391 6.237 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y80 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.472 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 0.674 7.146 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X80Y81 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.373 11.088 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X80Y81 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C clock pessimism 0.272 11.360 clock uncertainty -0.035 11.325 SLICE_X80Y81 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 11.232 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0] ------------------------------------------------------------------- required time 11.232 arrival time -7.146 ------------------------------------------------------------------- slack 4.086 Slack (MET) : 4.086ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.439ns (logic 0.374ns (10.875%) route 3.065ns (89.125%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.664ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.771ns = ( 11.088 - 8.317 ) Source Clock Delay (SCD): 3.707ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.232ns (routing 1.234ns, distribution 1.998ns) Clock Net Delay (Destination): 2.373ns (routing 1.125ns, distribution 1.248ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.232 3.707 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y79 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.846 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.391 6.237 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y80 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.472 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 0.674 7.146 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X80Y81 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.373 11.088 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X80Y81 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/C clock pessimism 0.272 11.360 clock uncertainty -0.035 11.325 SLICE_X80Y81 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.232 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] ------------------------------------------------------------------- required time 11.232 arrival time -7.146 ------------------------------------------------------------------- slack 4.086 Slack (MET) : 4.161ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.365ns (logic 0.374ns (11.114%) route 2.991ns (88.886%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.663ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.772ns = ( 11.089 - 8.317 ) Source Clock Delay (SCD): 3.707ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.232ns (routing 1.234ns, distribution 1.998ns) Clock Net Delay (Destination): 2.374ns (routing 1.125ns, distribution 1.249ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.232 3.707 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y79 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.846 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.391 6.237 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y80 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.472 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 0.600 7.072 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y81 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.374 11.089 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X81Y81 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C clock pessimism 0.272 11.361 clock uncertainty -0.035 11.326 SLICE_X81Y81 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.233 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5] ------------------------------------------------------------------- required time 11.233 arrival time -7.072 ------------------------------------------------------------------- slack 4.161 Slack (MET) : 4.169ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.355ns (logic 0.374ns (11.148%) route 2.981ns (88.852%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.665ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.770ns = ( 11.087 - 8.317 ) Source Clock Delay (SCD): 3.707ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.232ns (routing 1.234ns, distribution 1.998ns) Clock Net Delay (Destination): 2.372ns (routing 1.125ns, distribution 1.247ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.232 3.707 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y79 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.846 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.391 6.237 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y80 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.472 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 0.590 7.062 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y81 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.372 11.087 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X81Y81 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C clock pessimism 0.272 11.359 clock uncertainty -0.035 11.324 SLICE_X81Y81 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.231 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6] ------------------------------------------------------------------- required time 11.231 arrival time -7.062 ------------------------------------------------------------------- slack 4.169 Slack (MET) : 4.169ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 3.355ns (logic 0.374ns (11.148%) route 2.981ns (88.852%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.665ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.770ns = ( 11.087 - 8.317 ) Source Clock Delay (SCD): 3.707ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.232ns (routing 1.234ns, distribution 1.998ns) Clock Net Delay (Destination): 2.372ns (routing 1.125ns, distribution 1.247ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.232 3.707 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y79 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.846 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.391 6.237 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y80 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 6.472 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/O net (fo=15, routed) 0.590 7.062 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X81Y81 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.372 11.087 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] SLICE_X81Y81 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C clock pessimism 0.272 11.359 clock uncertainty -0.035 11.324 SLICE_X81Y81 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.231 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7] ------------------------------------------------------------------- required time 11.231 arrival time -7.062 ------------------------------------------------------------------- slack 4.169 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.102ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.194ns (logic 0.049ns (25.258%) route 0.145ns (74.742%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.402ns Source Clock Delay (SCD): 1.158ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.040ns (routing 0.538ns, distribution 0.502ns) Clock Net Delay (Destination): 1.237ns (routing 0.604ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X81Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y75 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.207 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.145 1.352 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X82Y75 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.237 1.402 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X82Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.157 1.245 SLICE_X82Y75 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.250 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.250 arrival time 1.352 ------------------------------------------------------------------- slack 0.102 Slack (MET) : 0.102ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.194ns (logic 0.049ns (25.258%) route 0.145ns (74.742%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.402ns Source Clock Delay (SCD): 1.158ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.040ns (routing 0.538ns, distribution 0.502ns) Clock Net Delay (Destination): 1.237ns (routing 0.604ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X81Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y75 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.207 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.145 1.352 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X82Y75 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.237 1.402 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X82Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.157 1.245 SLICE_X82Y75 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.250 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.250 arrival time 1.352 ------------------------------------------------------------------- slack 0.102 Slack (MET) : 0.102ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.194ns (logic 0.049ns (25.258%) route 0.145ns (74.742%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.402ns Source Clock Delay (SCD): 1.158ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.040ns (routing 0.538ns, distribution 0.502ns) Clock Net Delay (Destination): 1.237ns (routing 0.604ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X81Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y75 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.207 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.145 1.352 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X82Y75 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.237 1.402 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X82Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.157 1.245 SLICE_X82Y75 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.250 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.250 arrival time 1.352 ------------------------------------------------------------------- slack 0.102 Slack (MET) : 0.102ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.194ns (logic 0.049ns (25.258%) route 0.145ns (74.742%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.402ns Source Clock Delay (SCD): 1.158ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.040ns (routing 0.538ns, distribution 0.502ns) Clock Net Delay (Destination): 1.237ns (routing 0.604ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X81Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y75 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.207 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.145 1.352 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X82Y75 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.237 1.402 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X82Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.157 1.245 SLICE_X82Y75 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.250 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.250 arrival time 1.352 ------------------------------------------------------------------- slack 0.102 Slack (MET) : 0.102ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.194ns (logic 0.049ns (25.258%) route 0.145ns (74.742%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.402ns Source Clock Delay (SCD): 1.158ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.040ns (routing 0.538ns, distribution 0.502ns) Clock Net Delay (Destination): 1.237ns (routing 0.604ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X81Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y75 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.207 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.145 1.352 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X82Y75 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.237 1.402 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X82Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.157 1.245 SLICE_X82Y75 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.250 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -1.250 arrival time 1.352 ------------------------------------------------------------------- slack 0.102 Slack (MET) : 0.145ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.049ns (20.588%) route 0.189ns (79.412%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.403ns Source Clock Delay (SCD): 1.158ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.040ns (routing 0.538ns, distribution 0.502ns) Clock Net Delay (Destination): 1.238ns (routing 0.604ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X81Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y75 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.207 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.189 1.396 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X83Y75 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.238 1.403 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X83Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.157 1.246 SLICE_X83Y75 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.251 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.251 arrival time 1.396 ------------------------------------------------------------------- slack 0.145 Slack (MET) : 0.145ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.049ns (20.588%) route 0.189ns (79.412%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.403ns Source Clock Delay (SCD): 1.158ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.040ns (routing 0.538ns, distribution 0.502ns) Clock Net Delay (Destination): 1.238ns (routing 0.604ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X81Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y75 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.207 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.189 1.396 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X83Y75 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.238 1.403 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X83Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.157 1.246 SLICE_X83Y75 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.251 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.251 arrival time 1.396 ------------------------------------------------------------------- slack 0.145 Slack (MET) : 0.145ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.049ns (20.588%) route 0.189ns (79.412%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.403ns Source Clock Delay (SCD): 1.158ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.040ns (routing 0.538ns, distribution 0.502ns) Clock Net Delay (Destination): 1.238ns (routing 0.604ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X81Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y75 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.207 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.189 1.396 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X83Y75 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.238 1.403 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X83Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.157 1.246 SLICE_X83Y75 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.251 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.251 arrival time 1.396 ------------------------------------------------------------------- slack 0.145 Slack (MET) : 0.145ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.049ns (20.588%) route 0.189ns (79.412%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.403ns Source Clock Delay (SCD): 1.158ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.040ns (routing 0.538ns, distribution 0.502ns) Clock Net Delay (Destination): 1.238ns (routing 0.604ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X81Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y75 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.207 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.189 1.396 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X83Y75 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.238 1.403 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X83Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.157 1.246 SLICE_X83Y75 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.251 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.251 arrival time 1.396 ------------------------------------------------------------------- slack 0.145 Slack (MET) : 0.145ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.049ns (20.588%) route 0.189ns (79.412%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.403ns Source Clock Delay (SCD): 1.158ns Clock Pessimism Removal (CPR): 0.157ns Clock Net Delay (Source): 1.040ns (routing 0.538ns, distribution 0.502ns) Clock Net Delay (Destination): 1.238ns (routing 0.604ns, distribution 0.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.040 1.158 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X81Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y75 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.207 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.189 1.396 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X83Y75 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y5 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y33 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.238 1.403 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X83Y75 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.157 1.246 SLICE_X83Y75 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.251 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.251 arrival time 1.396 ------------------------------------------------------------------- slack 0.145 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_30 To Clock: gtwiz_userclk_rx_srcclk_out[0]_30 Setup : 0 Failing Endpoints, Worst Slack 4.894ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.174ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.894ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 2.999ns (logic 0.231ns (7.703%) route 2.768ns (92.297%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.296ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.710ns = ( 11.027 - 8.317 ) Source Clock Delay (SCD): 3.229ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.804ns (routing 1.111ns, distribution 1.693ns) Clock Net Delay (Destination): 2.334ns (routing 1.016ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.804 3.229 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y187 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y187 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.368 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.759 5.127 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y194 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.219 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 1.009 6.228 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X40Y189 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.334 11.027 g_gbt_bank[2].gbtbank/CLK SLICE_X40Y189 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/C clock pessimism 0.223 11.250 clock uncertainty -0.035 11.215 SLICE_X40Y189 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.122 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1] ------------------------------------------------------------------- required time 11.122 arrival time -6.228 ------------------------------------------------------------------- slack 4.894 Slack (MET) : 4.894ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 2.999ns (logic 0.231ns (7.703%) route 2.768ns (92.297%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.296ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.710ns = ( 11.027 - 8.317 ) Source Clock Delay (SCD): 3.229ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.804ns (routing 1.111ns, distribution 1.693ns) Clock Net Delay (Destination): 2.334ns (routing 1.016ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.804 3.229 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y187 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y187 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.368 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.759 5.127 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y194 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.219 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 1.009 6.228 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X40Y189 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.334 11.027 g_gbt_bank[2].gbtbank/CLK SLICE_X40Y189 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/C clock pessimism 0.223 11.250 clock uncertainty -0.035 11.215 SLICE_X40Y189 FDCE (Recov_BFF2_SLICEL_C_CLR) -0.093 11.122 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2] ------------------------------------------------------------------- required time 11.122 arrival time -6.228 ------------------------------------------------------------------- slack 4.894 Slack (MET) : 5.001ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 2.901ns (logic 0.231ns (7.963%) route 2.670ns (92.037%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.287ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.719ns = ( 11.036 - 8.317 ) Source Clock Delay (SCD): 3.229ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.804ns (routing 1.111ns, distribution 1.693ns) Clock Net Delay (Destination): 2.343ns (routing 1.016ns, distribution 1.327ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.804 3.229 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y187 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y187 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.368 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.759 5.127 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y194 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.219 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.911 6.130 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X41Y189 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.343 11.036 g_gbt_bank[2].gbtbank/CLK SLICE_X41Y189 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/C clock pessimism 0.223 11.259 clock uncertainty -0.035 11.224 SLICE_X41Y189 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.131 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3] ------------------------------------------------------------------- required time 11.131 arrival time -6.130 ------------------------------------------------------------------- slack 5.001 Slack (MET) : 5.001ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 2.901ns (logic 0.231ns (7.963%) route 2.670ns (92.037%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.287ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.719ns = ( 11.036 - 8.317 ) Source Clock Delay (SCD): 3.229ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.804ns (routing 1.111ns, distribution 1.693ns) Clock Net Delay (Destination): 2.343ns (routing 1.016ns, distribution 1.327ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.804 3.229 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y187 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y187 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.368 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.759 5.127 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y194 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.219 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.911 6.130 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X41Y189 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.343 11.036 g_gbt_bank[2].gbtbank/CLK SLICE_X41Y189 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/C clock pessimism 0.223 11.259 clock uncertainty -0.035 11.224 SLICE_X41Y189 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.131 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4] ------------------------------------------------------------------- required time 11.131 arrival time -6.130 ------------------------------------------------------------------- slack 5.001 Slack (MET) : 5.228ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 2.661ns (logic 0.364ns (13.679%) route 2.297ns (86.321%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.300ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.706ns = ( 11.023 - 8.317 ) Source Clock Delay (SCD): 3.229ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.804ns (routing 1.111ns, distribution 1.693ns) Clock Net Delay (Destination): 2.330ns (routing 1.016ns, distribution 1.314ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.804 3.229 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y187 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y187 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.368 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.597 4.965 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X41Y194 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.225 5.190 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__27/O net (fo=2, routed) 0.700 5.890 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X40Y194 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.330 11.023 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X40Y194 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.223 11.246 clock uncertainty -0.035 11.211 SLICE_X40Y194 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.118 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.118 arrival time -5.890 ------------------------------------------------------------------- slack 5.228 Slack (MET) : 5.228ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 2.661ns (logic 0.364ns (13.679%) route 2.297ns (86.321%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.300ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.706ns = ( 11.023 - 8.317 ) Source Clock Delay (SCD): 3.229ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.804ns (routing 1.111ns, distribution 1.693ns) Clock Net Delay (Destination): 2.330ns (routing 1.016ns, distribution 1.314ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.804 3.229 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y187 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y187 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.368 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.597 4.965 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X41Y194 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.225 5.190 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__27/O net (fo=2, routed) 0.700 5.890 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X40Y194 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.330 11.023 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X40Y194 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.223 11.246 clock uncertainty -0.035 11.211 SLICE_X40Y194 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.118 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 11.118 arrival time -5.890 ------------------------------------------------------------------- slack 5.228 Slack (MET) : 5.263ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 2.636ns (logic 0.231ns (8.763%) route 2.405ns (91.237%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.716ns = ( 11.033 - 8.317 ) Source Clock Delay (SCD): 3.229ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.804ns (routing 1.111ns, distribution 1.693ns) Clock Net Delay (Destination): 2.340ns (routing 1.016ns, distribution 1.324ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.804 3.229 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y187 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y187 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.368 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.759 5.127 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y194 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.219 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.646 5.865 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X41Y195 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.340 11.033 g_gbt_bank[2].gbtbank/CLK SLICE_X41Y195 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C clock pessimism 0.223 11.256 clock uncertainty -0.035 11.221 SLICE_X41Y195 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.128 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6] ------------------------------------------------------------------- required time 11.128 arrival time -5.865 ------------------------------------------------------------------- slack 5.263 Slack (MET) : 5.263ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 2.636ns (logic 0.231ns (8.763%) route 2.405ns (91.237%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.716ns = ( 11.033 - 8.317 ) Source Clock Delay (SCD): 3.229ns Clock Pessimism Removal (CPR): 0.223ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.804ns (routing 1.111ns, distribution 1.693ns) Clock Net Delay (Destination): 2.340ns (routing 1.016ns, distribution 1.324ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.804 3.229 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X3Y187 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X3Y187 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.368 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.759 5.127 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X42Y194 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 5.219 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/O net (fo=15, routed) 0.646 5.865 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X41Y195 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.340 11.033 g_gbt_bank[2].gbtbank/CLK SLICE_X41Y195 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/C clock pessimism 0.223 11.256 clock uncertainty -0.035 11.221 SLICE_X41Y195 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.128 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7] ------------------------------------------------------------------- required time 11.128 arrival time -5.865 ------------------------------------------------------------------- slack 5.263 Slack (MET) : 5.263ns (required time - arrival time) Source: SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 2.362ns (logic 0.139ns (5.885%) route 2.223ns (94.115%)) Logic Levels: 0 Clock Path Skew: -0.564ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 3.398ns Clock Pessimism Removal (CPR): 0.144ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.973ns (routing 1.111ns, distribution 1.862ns) Clock Net Delay (Destination): 2.314ns (routing 1.016ns, distribution 1.298ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.973 3.398 SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y187 FDPE r SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y187 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.537 f SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.223 5.760 SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] SLICE_X35Y179 FDCE f SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.314 11.007 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y179 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism 0.144 11.151 clock uncertainty -0.035 11.116 SLICE_X35Y179 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.023 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time 11.023 arrival time -5.760 ------------------------------------------------------------------- slack 5.263 Slack (MET) : 5.263ns (required time - arrival time) Source: SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 2.362ns (logic 0.139ns (5.885%) route 2.223ns (94.115%)) Logic Levels: 0 Clock Path Skew: -0.564ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.690ns = ( 11.007 - 8.317 ) Source Clock Delay (SCD): 3.398ns Clock Pessimism Removal (CPR): 0.144ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.973ns (routing 1.111ns, distribution 1.862ns) Clock Net Delay (Destination): 2.314ns (routing 1.016ns, distribution 1.298ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.973 3.398 SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y187 FDPE r SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y187 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 3.537 f SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 2.223 5.760 SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] SLICE_X35Y179 FDCE f SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 2.314 11.007 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y179 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[54]/C clock pessimism 0.144 11.151 clock uncertainty -0.035 11.116 SLICE_X35Y179 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.023 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[54] ------------------------------------------------------------------- required time 11.023 arrival time -5.760 ------------------------------------------------------------------- slack 5.263 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.174ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.252ns (logic 0.049ns (19.444%) route 0.203ns (80.556%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.370ns Source Clock Delay (SCD): 1.146ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.030ns (routing 0.483ns, distribution 0.547ns) Clock Net Delay (Destination): 1.218ns (routing 0.551ns, distribution 0.667ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.030 1.146 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X40Y192 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X40Y192 FDPE (Prop_AFF_SLICEL_C_Q) 0.049 1.195 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.203 1.398 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X41Y190 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.218 1.370 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y190 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.151 1.219 SLICE_X41Y190 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.224 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.224 arrival time 1.398 ------------------------------------------------------------------- slack 0.174 Slack (MET) : 0.185ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.272ns (logic 0.048ns (17.647%) route 0.224ns (82.353%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.386ns Source Clock Delay (SCD): 1.153ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.037ns (routing 0.483ns, distribution 0.554ns) Clock Net Delay (Destination): 1.234ns (routing 0.551ns, distribution 0.683ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.037 1.153 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y186 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y186 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.201 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.224 1.425 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X37Y185 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.234 1.386 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/CLK SLICE_X37Y185 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.151 1.235 SLICE_X37Y185 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.240 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.240 arrival time 1.425 ------------------------------------------------------------------- slack 0.185 Slack (MET) : 0.205ns (arrival time - required time) Source: SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.048ns (18.605%) route 0.210ns (81.395%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.514ns Source Clock Delay (SCD): 1.266ns Clock Pessimism Removal (CPR): 0.200ns Clock Net Delay (Source): 1.150ns (routing 0.483ns, distribution 0.667ns) Clock Net Delay (Destination): 1.362ns (routing 0.551ns, distribution 0.811ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.150 1.266 SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y187 FDPE r SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y187 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.314 f SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.210 1.524 SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y189 FDCE f SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.362 1.514 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y189 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[20]/C clock pessimism -0.200 1.314 SLICE_X48Y189 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.319 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[20] ------------------------------------------------------------------- required time -1.319 arrival time 1.524 ------------------------------------------------------------------- slack 0.205 Slack (MET) : 0.205ns (arrival time - required time) Source: SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.048ns (18.605%) route 0.210ns (81.395%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.514ns Source Clock Delay (SCD): 1.266ns Clock Pessimism Removal (CPR): 0.200ns Clock Net Delay (Source): 1.150ns (routing 0.483ns, distribution 0.667ns) Clock Net Delay (Destination): 1.362ns (routing 0.551ns, distribution 0.811ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.150 1.266 SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y187 FDPE r SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y187 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.314 f SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.210 1.524 SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y189 FDCE f SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.362 1.514 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y189 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.200 1.314 SLICE_X48Y189 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.319 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -1.319 arrival time 1.524 ------------------------------------------------------------------- slack 0.205 Slack (MET) : 0.205ns (arrival time - required time) Source: SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.048ns (18.605%) route 0.210ns (81.395%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.514ns Source Clock Delay (SCD): 1.266ns Clock Pessimism Removal (CPR): 0.200ns Clock Net Delay (Source): 1.150ns (routing 0.483ns, distribution 0.667ns) Clock Net Delay (Destination): 1.362ns (routing 0.551ns, distribution 0.811ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.150 1.266 SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y187 FDPE r SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y187 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.314 f SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.210 1.524 SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y189 FDCE f SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.362 1.514 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y189 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[22]/C clock pessimism -0.200 1.314 SLICE_X48Y189 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.319 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[22] ------------------------------------------------------------------- required time -1.319 arrival time 1.524 ------------------------------------------------------------------- slack 0.205 Slack (MET) : 0.205ns (arrival time - required time) Source: SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.048ns (18.605%) route 0.210ns (81.395%)) Logic Levels: 0 Clock Path Skew: 0.048ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.514ns Source Clock Delay (SCD): 1.266ns Clock Pessimism Removal (CPR): 0.200ns Clock Net Delay (Source): 1.150ns (routing 0.483ns, distribution 0.667ns) Clock Net Delay (Destination): 1.362ns (routing 0.551ns, distribution 0.811ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.150 1.266 SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y187 FDPE r SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y187 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.314 f SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.210 1.524 SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y189 FDCE f SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.362 1.514 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y189 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.200 1.314 SLICE_X48Y189 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.319 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -1.319 arrival time 1.524 ------------------------------------------------------------------- slack 0.205 Slack (MET) : 0.225ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.048ns (15.534%) route 0.261ns (84.466%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.383ns Source Clock Delay (SCD): 1.153ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 1.037ns (routing 0.483ns, distribution 0.554ns) Clock Net Delay (Destination): 1.231ns (routing 0.551ns, distribution 0.680ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.037 1.153 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y186 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y186 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 1.201 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.261 1.462 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X36Y185 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.231 1.383 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/CLK SLICE_X36Y185 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.151 1.232 SLICE_X36Y185 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.237 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -1.237 arrival time 1.462 ------------------------------------------------------------------- slack 0.225 Slack (MET) : 0.241ns (arrival time - required time) Source: SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.293ns (logic 0.048ns (16.382%) route 0.245ns (83.618%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.513ns Source Clock Delay (SCD): 1.266ns Clock Pessimism Removal (CPR): 0.200ns Clock Net Delay (Source): 1.150ns (routing 0.483ns, distribution 0.667ns) Clock Net Delay (Destination): 1.361ns (routing 0.551ns, distribution 0.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.150 1.266 SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y187 FDPE r SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y187 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.314 f SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.245 1.559 SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y190 FDCE f SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.361 1.513 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y190 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[16]/C clock pessimism -0.200 1.313 SLICE_X48Y190 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.318 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[16] ------------------------------------------------------------------- required time -1.318 arrival time 1.559 ------------------------------------------------------------------- slack 0.241 Slack (MET) : 0.241ns (arrival time - required time) Source: SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.293ns (logic 0.048ns (16.382%) route 0.245ns (83.618%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.513ns Source Clock Delay (SCD): 1.266ns Clock Pessimism Removal (CPR): 0.200ns Clock Net Delay (Source): 1.150ns (routing 0.483ns, distribution 0.667ns) Clock Net Delay (Destination): 1.361ns (routing 0.551ns, distribution 0.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.150 1.266 SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y187 FDPE r SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y187 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.314 f SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.245 1.559 SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y190 FDCE f SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.361 1.513 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y190 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[17]/C clock pessimism -0.200 1.313 SLICE_X48Y190 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.318 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[17] ------------------------------------------------------------------- required time -1.318 arrival time 1.559 ------------------------------------------------------------------- slack 0.241 Slack (MET) : 0.241ns (arrival time - required time) Source: SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns) Data Path Delay: 0.293ns (logic 0.048ns (16.382%) route 0.245ns (83.618%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.513ns Source Clock Delay (SCD): 1.266ns Clock Pessimism Removal (CPR): 0.200ns Clock Net Delay (Source): 1.150ns (routing 0.483ns, distribution 0.667ns) Clock Net Delay (Destination): 1.361ns (routing 0.551ns, distribution 0.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.150 1.266 SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y187 FDPE r SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y187 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.314 f SFP_GEN[28].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.245 1.559 SFP_GEN[28].ngCCM_gbt/sync_m_reg[3][0] SLICE_X48Y190 FDCE f SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y12 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y78 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y2 (CLOCK_ROOT) net (fo=674, routed) 1.361 1.513 SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X48Y190 FDCE r SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[19]/C clock pessimism -0.200 1.313 SLICE_X48Y190 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.318 SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[19] ------------------------------------------------------------------- required time -1.318 arrival time 1.559 ------------------------------------------------------------------- slack 0.241 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_31 To Clock: gtwiz_userclk_rx_srcclk_out[0]_31 Setup : 0 Failing Endpoints, Worst Slack 4.963ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.130ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.963ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 2.954ns (logic 0.305ns (10.325%) route 2.649ns (89.675%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.271ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.394ns = ( 10.711 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.804ns, distribution 1.641ns) Clock Net Delay (Destination): 2.018ns (routing 0.721ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y210 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y210 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.971 4.981 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X36Y226 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.146 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.678 5.824 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X37Y224 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.018 10.711 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X37Y224 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C clock pessimism 0.205 10.916 clock uncertainty -0.035 10.880 SLICE_X37Y224 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.787 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1] ------------------------------------------------------------------- required time 10.787 arrival time -5.824 ------------------------------------------------------------------- slack 4.963 Slack (MET) : 4.963ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 2.954ns (logic 0.305ns (10.325%) route 2.649ns (89.675%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.271ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.394ns = ( 10.711 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.804ns, distribution 1.641ns) Clock Net Delay (Destination): 2.018ns (routing 0.721ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y210 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y210 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.971 4.981 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X36Y226 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.146 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.678 5.824 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X37Y224 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.018 10.711 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X37Y224 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/C clock pessimism 0.205 10.916 clock uncertainty -0.035 10.880 SLICE_X37Y224 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 10.787 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2] ------------------------------------------------------------------- required time 10.787 arrival time -5.824 ------------------------------------------------------------------- slack 4.963 Slack (MET) : 5.030ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 2.880ns (logic 0.305ns (10.590%) route 2.575ns (89.410%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.386ns = ( 10.703 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.804ns, distribution 1.641ns) Clock Net Delay (Destination): 2.010ns (routing 0.721ns, distribution 1.289ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y210 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y210 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.971 4.981 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X36Y226 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.146 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.604 5.750 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X37Y225 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.010 10.703 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X37Y225 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/C clock pessimism 0.205 10.908 clock uncertainty -0.035 10.873 SLICE_X37Y225 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.780 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6] ------------------------------------------------------------------- required time 10.780 arrival time -5.750 ------------------------------------------------------------------- slack 5.030 Slack (MET) : 5.030ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 2.880ns (logic 0.305ns (10.590%) route 2.575ns (89.410%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.386ns = ( 10.703 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.804ns, distribution 1.641ns) Clock Net Delay (Destination): 2.010ns (routing 0.721ns, distribution 1.289ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y210 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y210 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.971 4.981 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X36Y226 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.146 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.604 5.750 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X37Y225 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.010 10.703 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X37Y225 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/C clock pessimism 0.205 10.908 clock uncertainty -0.035 10.873 SLICE_X37Y225 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.780 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7] ------------------------------------------------------------------- required time 10.780 arrival time -5.750 ------------------------------------------------------------------- slack 5.030 Slack (MET) : 5.035ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 2.873ns (logic 0.305ns (10.616%) route 2.568ns (89.384%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.281ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.384ns = ( 10.701 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.804ns, distribution 1.641ns) Clock Net Delay (Destination): 2.008ns (routing 0.721ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y210 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y210 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.971 4.981 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X36Y226 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.146 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.597 5.743 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X37Y225 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.008 10.701 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X37Y225 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C clock pessimism 0.205 10.906 clock uncertainty -0.035 10.871 SLICE_X37Y225 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.778 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3] ------------------------------------------------------------------- required time 10.778 arrival time -5.743 ------------------------------------------------------------------- slack 5.035 Slack (MET) : 5.035ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 2.873ns (logic 0.305ns (10.616%) route 2.568ns (89.384%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.281ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.384ns = ( 10.701 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.804ns, distribution 1.641ns) Clock Net Delay (Destination): 2.008ns (routing 0.721ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y210 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y210 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.971 4.981 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X36Y226 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.146 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.597 5.743 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X37Y225 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.008 10.701 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X37Y225 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/C clock pessimism 0.205 10.906 clock uncertainty -0.035 10.871 SLICE_X37Y225 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 10.778 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4] ------------------------------------------------------------------- required time 10.778 arrival time -5.743 ------------------------------------------------------------------- slack 5.035 Slack (MET) : 5.035ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 2.873ns (logic 0.305ns (10.616%) route 2.568ns (89.384%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.281ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.384ns = ( 10.701 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.804ns, distribution 1.641ns) Clock Net Delay (Destination): 2.008ns (routing 0.721ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y210 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y210 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.971 4.981 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X36Y226 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.146 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.597 5.743 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X37Y225 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.008 10.701 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X37Y225 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/C clock pessimism 0.205 10.906 clock uncertainty -0.035 10.871 SLICE_X37Y225 FDCE (Recov_FFF_SLICEM_C_CLR) -0.093 10.778 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5] ------------------------------------------------------------------- required time 10.778 arrival time -5.743 ------------------------------------------------------------------- slack 5.035 Slack (MET) : 5.039ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 2.867ns (logic 0.306ns (10.673%) route 2.561ns (89.327%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.382ns = ( 10.699 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.804ns, distribution 1.641ns) Clock Net Delay (Destination): 2.006ns (routing 0.721ns, distribution 1.285ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y210 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y210 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.984 4.994 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X36Y226 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.166 5.160 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28/O net (fo=2, routed) 0.577 5.737 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X36Y227 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.006 10.699 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X36Y227 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.205 10.904 clock uncertainty -0.035 10.869 SLICE_X36Y227 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.776 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.776 arrival time -5.737 ------------------------------------------------------------------- slack 5.039 Slack (MET) : 5.039ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 2.867ns (logic 0.306ns (10.673%) route 2.561ns (89.327%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.382ns = ( 10.699 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.804ns, distribution 1.641ns) Clock Net Delay (Destination): 2.006ns (routing 0.721ns, distribution 1.285ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y210 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y210 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.984 4.994 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X36Y226 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.166 5.160 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28/O net (fo=2, routed) 0.577 5.737 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X36Y227 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.006 10.699 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X36Y227 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.205 10.904 clock uncertainty -0.035 10.869 SLICE_X36Y227 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.776 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.776 arrival time -5.737 ------------------------------------------------------------------- slack 5.039 Slack (MET) : 5.114ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 2.801ns (logic 0.305ns (10.889%) route 2.496ns (89.111%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.274ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.391ns = ( 10.708 - 8.317 ) Source Clock Delay (SCD): 2.870ns Clock Pessimism Removal (CPR): 0.205ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.445ns (routing 0.804ns, distribution 1.641ns) Clock Net Delay (Destination): 2.015ns (routing 0.721ns, distribution 1.294ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.445 2.870 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y210 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y210 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.010 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.971 4.981 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X36Y226 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.146 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/O net (fo=15, routed) 0.525 5.671 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X36Y225 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.015 10.708 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X36Y225 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/C clock pessimism 0.205 10.913 clock uncertainty -0.035 10.878 SLICE_X36Y225 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.785 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5] ------------------------------------------------------------------- required time 10.785 arrival time -5.671 ------------------------------------------------------------------- slack 5.114 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.130ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.049ns (21.586%) route 0.178ns (78.414%)) Logic Levels: 0 Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.263ns Source Clock Delay (SCD): 1.028ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.912ns (routing 0.382ns, distribution 0.530ns) Clock Net Delay (Destination): 1.111ns (routing 0.446ns, distribution 0.665ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.912 1.028 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X33Y224 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X33Y224 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.077 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.178 1.255 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X35Y224 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.111 1.263 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X35Y224 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.143 1.120 SLICE_X35Y224 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.125 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.125 arrival time 1.255 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.049ns (22.273%) route 0.171ns (77.727%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.245ns Source Clock Delay (SCD): 1.025ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.909ns (routing 0.382ns, distribution 0.527ns) Clock Net Delay (Destination): 1.093ns (routing 0.446ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.909 1.025 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X35Y219 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y219 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.074 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.171 1.245 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X34Y219 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.093 1.245 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X34Y219 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C clock pessimism -0.143 1.102 SLICE_X34Y219 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.107 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12] ------------------------------------------------------------------- required time -1.107 arrival time 1.245 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.138ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.049ns (22.273%) route 0.171ns (77.727%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.245ns Source Clock Delay (SCD): 1.025ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.909ns (routing 0.382ns, distribution 0.527ns) Clock Net Delay (Destination): 1.093ns (routing 0.446ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.909 1.025 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X35Y219 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y219 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.074 r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.171 1.245 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X34Y219 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.093 1.245 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X34Y219 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.143 1.102 SLICE_X34Y219 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.107 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.107 arrival time 1.245 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.149ns (arrival time - required time) Source: SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.048ns (20.690%) route 0.184ns (79.310%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.245ns Source Clock Delay (SCD): 1.024ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.908ns (routing 0.382ns, distribution 0.526ns) Clock Net Delay (Destination): 1.093ns (routing 0.446ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.908 1.024 SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y224 FDPE r SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y224 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.072 f SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.184 1.256 SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] SLICE_X38Y223 FDCE f SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.093 1.245 SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X38Y223 FDCE r SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[16]/C clock pessimism -0.143 1.102 SLICE_X38Y223 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.107 SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[16] ------------------------------------------------------------------- required time -1.107 arrival time 1.256 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.048ns (20.690%) route 0.184ns (79.310%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.245ns Source Clock Delay (SCD): 1.024ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.908ns (routing 0.382ns, distribution 0.526ns) Clock Net Delay (Destination): 1.093ns (routing 0.446ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.908 1.024 SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y224 FDPE r SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y224 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.072 f SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.184 1.256 SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] SLICE_X38Y223 FDCE f SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.093 1.245 SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X38Y223 FDCE r SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[25]/C clock pessimism -0.143 1.102 SLICE_X38Y223 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 1.107 SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[25] ------------------------------------------------------------------- required time -1.107 arrival time 1.256 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.048ns (20.690%) route 0.184ns (79.310%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.245ns Source Clock Delay (SCD): 1.024ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.908ns (routing 0.382ns, distribution 0.526ns) Clock Net Delay (Destination): 1.093ns (routing 0.446ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.908 1.024 SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y224 FDPE r SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y224 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.072 f SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.184 1.256 SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] SLICE_X38Y223 FDCE f SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.093 1.245 SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X38Y223 FDCE r SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.143 1.102 SLICE_X38Y223 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.107 SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.107 arrival time 1.256 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[29].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.048ns (20.690%) route 0.184ns (79.310%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.245ns Source Clock Delay (SCD): 1.024ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.908ns (routing 0.382ns, distribution 0.526ns) Clock Net Delay (Destination): 1.093ns (routing 0.446ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.908 1.024 SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y224 FDPE r SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y224 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.072 f SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.184 1.256 SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] SLICE_X38Y223 FDCE f SFP_GEN[29].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.093 1.245 SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X38Y223 FDCE r SFP_GEN[29].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.143 1.102 SLICE_X38Y223 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.107 SFP_GEN[29].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.107 arrival time 1.256 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.159ns (arrival time - required time) Source: SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.048ns (20.870%) route 0.182ns (79.130%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.233ns Source Clock Delay (SCD): 1.024ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.908ns (routing 0.382ns, distribution 0.526ns) Clock Net Delay (Destination): 1.081ns (routing 0.446ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.908 1.024 SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y224 FDPE r SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y224 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.072 f SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.182 1.254 SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] SLICE_X38Y222 FDCE f SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.081 1.233 SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X38Y222 FDCE r SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[27]/C clock pessimism -0.143 1.090 SLICE_X38Y222 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.095 SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[27] ------------------------------------------------------------------- required time -1.095 arrival time 1.254 ------------------------------------------------------------------- slack 0.159 Slack (MET) : 0.161ns (arrival time - required time) Source: SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.048ns (21.429%) route 0.176ns (78.571%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.257ns Source Clock Delay (SCD): 1.024ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 0.908ns (routing 0.382ns, distribution 0.526ns) Clock Net Delay (Destination): 1.105ns (routing 0.446ns, distribution 0.659ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.908 1.024 SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y224 FDPE r SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y224 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.072 f SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.176 1.248 SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y222 FDCE f SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.105 1.257 SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y222 FDCE r SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[17]/C clock pessimism -0.175 1.082 SLICE_X39Y222 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.087 SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[17] ------------------------------------------------------------------- required time -1.087 arrival time 1.248 ------------------------------------------------------------------- slack 0.161 Slack (MET) : 0.161ns (arrival time - required time) Source: SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.048ns (21.429%) route 0.176ns (78.571%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.257ns Source Clock Delay (SCD): 1.024ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 0.908ns (routing 0.382ns, distribution 0.526ns) Clock Net Delay (Destination): 1.105ns (routing 0.446ns, distribution 0.659ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.908 1.024 SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y224 FDPE r SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y224 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.072 f SFP_GEN[29].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.176 1.248 SFP_GEN[29].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y222 FDCE f SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y13 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y95 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.105 1.257 SFP_GEN[29].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y222 FDCE r SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism -0.175 1.082 SLICE_X39Y222 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.087 SFP_GEN[29].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time -1.087 arrival time 1.248 ------------------------------------------------------------------- slack 0.161 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_32 To Clock: gtwiz_userclk_rx_srcclk_out[0]_32 Setup : 0 Failing Endpoints, Worst Slack 5.263ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.131ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.263ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.675ns (logic 0.227ns (8.486%) route 2.448ns (91.514%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.251ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.299ns = ( 10.616 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 1.923ns (routing 0.603ns, distribution 1.320ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.763 4.638 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.726 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.685 5.411 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X46Y213 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.923 10.616 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y213 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/C clock pessimism 0.186 10.803 clock uncertainty -0.035 10.767 SLICE_X46Y213 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.674 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1] ------------------------------------------------------------------- required time 10.674 arrival time -5.411 ------------------------------------------------------------------- slack 5.263 Slack (MET) : 5.263ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.675ns (logic 0.227ns (8.486%) route 2.448ns (91.514%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.251ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.299ns = ( 10.616 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 1.923ns (routing 0.603ns, distribution 1.320ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.763 4.638 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.726 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.685 5.411 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X46Y213 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.923 10.616 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y213 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/C clock pessimism 0.186 10.803 clock uncertainty -0.035 10.767 SLICE_X46Y213 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.674 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2] ------------------------------------------------------------------- required time 10.674 arrival time -5.411 ------------------------------------------------------------------- slack 5.263 Slack (MET) : 5.263ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.675ns (logic 0.227ns (8.486%) route 2.448ns (91.514%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.251ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.299ns = ( 10.616 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 1.923ns (routing 0.603ns, distribution 1.320ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.763 4.638 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.726 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.685 5.411 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X46Y213 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.923 10.616 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y213 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C clock pessimism 0.186 10.803 clock uncertainty -0.035 10.767 SLICE_X46Y213 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.674 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3] ------------------------------------------------------------------- required time 10.674 arrival time -5.411 ------------------------------------------------------------------- slack 5.263 Slack (MET) : 5.263ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.675ns (logic 0.227ns (8.486%) route 2.448ns (91.514%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.251ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.299ns = ( 10.616 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 1.923ns (routing 0.603ns, distribution 1.320ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.763 4.638 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.726 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.685 5.411 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X46Y213 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.923 10.616 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y213 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/C clock pessimism 0.186 10.803 clock uncertainty -0.035 10.767 SLICE_X46Y213 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.674 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4] ------------------------------------------------------------------- required time 10.674 arrival time -5.411 ------------------------------------------------------------------- slack 5.263 Slack (MET) : 5.317ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.619ns (logic 0.228ns (8.706%) route 2.391ns (91.294%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.253ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.297ns = ( 10.614 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 1.921ns (routing 0.603ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.783 4.658 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.089 4.747 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__29/O net (fo=2, routed) 0.608 5.355 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X43Y217 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.921 10.614 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X43Y217 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.186 10.801 clock uncertainty -0.035 10.765 SLICE_X43Y217 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.672 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.672 arrival time -5.355 ------------------------------------------------------------------- slack 5.317 Slack (MET) : 5.317ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.619ns (logic 0.228ns (8.706%) route 2.391ns (91.294%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.253ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.297ns = ( 10.614 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 1.921ns (routing 0.603ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.783 4.658 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.089 4.747 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__29/O net (fo=2, routed) 0.608 5.355 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X43Y217 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.921 10.614 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X43Y217 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.186 10.801 clock uncertainty -0.035 10.765 SLICE_X43Y217 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.672 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.672 arrival time -5.355 ------------------------------------------------------------------- slack 5.317 Slack (MET) : 5.336ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.605ns (logic 0.227ns (8.714%) route 2.378ns (91.286%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.248ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.302ns = ( 10.619 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 1.926ns (routing 0.603ns, distribution 1.323ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.763 4.638 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.726 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.615 5.341 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X46Y215 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.619 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y215 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C clock pessimism 0.186 10.806 clock uncertainty -0.035 10.770 SLICE_X46Y215 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.677 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6] ------------------------------------------------------------------- required time 10.677 arrival time -5.341 ------------------------------------------------------------------- slack 5.336 Slack (MET) : 5.344ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.595ns (logic 0.227ns (8.748%) route 2.368ns (91.252%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.250ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.300ns = ( 10.617 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 1.924ns (routing 0.603ns, distribution 1.321ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.763 4.638 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.726 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.605 5.331 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X46Y215 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.924 10.617 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y215 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/C clock pessimism 0.186 10.804 clock uncertainty -0.035 10.768 SLICE_X46Y215 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.675 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7] ------------------------------------------------------------------- required time 10.675 arrival time -5.331 ------------------------------------------------------------------- slack 5.344 Slack (MET) : 5.344ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.595ns (logic 0.227ns (8.748%) route 2.368ns (91.252%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.250ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.300ns = ( 10.617 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 1.924ns (routing 0.603ns, distribution 1.321ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.763 4.638 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.726 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.605 5.331 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X46Y215 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.924 10.617 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y215 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/C clock pessimism 0.186 10.804 clock uncertainty -0.035 10.768 SLICE_X46Y215 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.675 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0] ------------------------------------------------------------------- required time 10.675 arrival time -5.331 ------------------------------------------------------------------- slack 5.344 Slack (MET) : 5.344ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 2.595ns (logic 0.227ns (8.748%) route 2.368ns (91.252%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.250ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.300ns = ( 10.617 - 8.317 ) Source Clock Delay (SCD): 2.736ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.311ns (routing 0.667ns, distribution 1.644ns) Clock Net Delay (Destination): 1.924ns (routing 0.603ns, distribution 1.321ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.311 2.736 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y222 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y222 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.875 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.763 4.638 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X46Y218 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.088 4.726 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/O net (fo=15, routed) 0.605 5.331 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X46Y215 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.924 10.617 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X46Y215 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/C clock pessimism 0.186 10.804 clock uncertainty -0.035 10.768 SLICE_X46Y215 FDCE (Recov_GFF2_SLICEL_C_CLR) -0.093 10.675 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5] ------------------------------------------------------------------- required time 10.675 arrival time -5.331 ------------------------------------------------------------------- slack 5.344 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.131ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.099ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.126ns Clock Net Delay (Source): 0.828ns (routing 0.301ns, distribution 0.527ns) Clock Net Delay (Destination): 1.017ns (routing 0.348ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.944 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X41Y209 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y209 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.993 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y209 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[13]/C clock pessimism -0.126 1.043 SLICE_X42Y209 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.048 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[13] ------------------------------------------------------------------- required time -1.048 arrival time 1.179 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.099ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.126ns Clock Net Delay (Source): 0.828ns (routing 0.301ns, distribution 0.527ns) Clock Net Delay (Destination): 1.017ns (routing 0.348ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.944 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X41Y209 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y209 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.993 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y209 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[14]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[14]/C clock pessimism -0.126 1.043 SLICE_X42Y209 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.048 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[14] ------------------------------------------------------------------- required time -1.048 arrival time 1.179 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.099ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.126ns Clock Net Delay (Source): 0.828ns (routing 0.301ns, distribution 0.527ns) Clock Net Delay (Destination): 1.017ns (routing 0.348ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.944 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X41Y209 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y209 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.993 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y209 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[15]/C clock pessimism -0.126 1.043 SLICE_X42Y209 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.048 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[15] ------------------------------------------------------------------- required time -1.048 arrival time 1.179 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.099ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.126ns Clock Net Delay (Source): 0.828ns (routing 0.301ns, distribution 0.527ns) Clock Net Delay (Destination): 1.017ns (routing 0.348ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.944 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X41Y209 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y209 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.993 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y209 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[4]/C clock pessimism -0.126 1.043 SLICE_X42Y209 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.048 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[4] ------------------------------------------------------------------- required time -1.048 arrival time 1.179 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.099ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.126ns Clock Net Delay (Source): 0.828ns (routing 0.301ns, distribution 0.527ns) Clock Net Delay (Destination): 1.017ns (routing 0.348ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.944 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X41Y209 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y209 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.993 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y209 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[13]/C clock pessimism -0.126 1.043 SLICE_X42Y209 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.048 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[13] ------------------------------------------------------------------- required time -1.048 arrival time 1.179 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.099ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.126ns Clock Net Delay (Source): 0.828ns (routing 0.301ns, distribution 0.527ns) Clock Net Delay (Destination): 1.017ns (routing 0.348ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.944 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X41Y209 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y209 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.993 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y209 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[14]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[14]/C clock pessimism -0.126 1.043 SLICE_X42Y209 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.048 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[14] ------------------------------------------------------------------- required time -1.048 arrival time 1.179 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.099ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.126ns Clock Net Delay (Source): 0.828ns (routing 0.301ns, distribution 0.527ns) Clock Net Delay (Destination): 1.017ns (routing 0.348ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.944 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X41Y209 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y209 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.993 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y209 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[15]/C clock pessimism -0.126 1.043 SLICE_X42Y209 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.048 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[15] ------------------------------------------------------------------- required time -1.048 arrival time 1.179 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.049ns (20.851%) route 0.186ns (79.149%)) Logic Levels: 0 Clock Path Skew: 0.099ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.169ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.126ns Clock Net Delay (Source): 0.828ns (routing 0.301ns, distribution 0.527ns) Clock Net Delay (Destination): 1.017ns (routing 0.348ns, distribution 0.669ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.944 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X41Y209 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y209 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.993 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.186 1.179 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y209 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.017 1.169 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[4]/C clock pessimism -0.126 1.043 SLICE_X42Y209 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.048 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[4] ------------------------------------------------------------------- required time -1.048 arrival time 1.179 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.132ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.049ns (20.588%) route 0.189ns (79.412%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.171ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.126ns Clock Net Delay (Source): 0.828ns (routing 0.301ns, distribution 0.527ns) Clock Net Delay (Destination): 1.019ns (routing 0.348ns, distribution 0.671ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.944 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X41Y209 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y209 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.993 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.189 1.182 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y209 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.171 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]/C clock pessimism -0.126 1.045 SLICE_X42Y209 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.050 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44] ------------------------------------------------------------------- required time -1.050 arrival time 1.182 ------------------------------------------------------------------- slack 0.132 Slack (MET) : 0.132ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[53]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.049ns (20.588%) route 0.189ns (79.412%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.171ns Source Clock Delay (SCD): 0.944ns Clock Pessimism Removal (CPR): 0.126ns Clock Net Delay (Source): 0.828ns (routing 0.301ns, distribution 0.527ns) Clock Net Delay (Destination): 1.019ns (routing 0.348ns, distribution 0.671ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.828 0.944 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X41Y209 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y209 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.993 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.189 1.182 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X42Y209 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[53]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y14 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y75 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.019 1.171 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y209 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[53]/C clock pessimism -0.126 1.045 SLICE_X42Y209 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.050 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[53] ------------------------------------------------------------------- required time -1.050 arrival time 1.182 ------------------------------------------------------------------- slack 0.132 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_33 To Clock: gtwiz_userclk_rx_srcclk_out[0]_33 Setup : 0 Failing Endpoints, Worst Slack 4.837ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.176ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.837ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.062ns (logic 0.383ns (12.508%) route 2.679ns (87.492%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.785ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.360ns (routing 0.699ns, distribution 1.661ns) Clock Net Delay (Destination): 1.931ns (routing 0.636ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.360 2.785 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y235 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y235 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.924 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.897 4.821 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X41Y241 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.065 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.782 5.847 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X41Y230 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.624 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X41Y230 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C clock pessimism 0.188 10.812 clock uncertainty -0.035 10.777 SLICE_X41Y230 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.684 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1] ------------------------------------------------------------------- required time 10.684 arrival time -5.847 ------------------------------------------------------------------- slack 4.837 Slack (MET) : 4.837ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.062ns (logic 0.383ns (12.508%) route 2.679ns (87.492%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.785ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.360ns (routing 0.699ns, distribution 1.661ns) Clock Net Delay (Destination): 1.931ns (routing 0.636ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.360 2.785 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y235 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y235 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.924 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.897 4.821 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X41Y241 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.065 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.782 5.847 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X41Y230 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.624 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X41Y230 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/C clock pessimism 0.188 10.812 clock uncertainty -0.035 10.777 SLICE_X41Y230 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 10.684 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2] ------------------------------------------------------------------- required time 10.684 arrival time -5.847 ------------------------------------------------------------------- slack 4.837 Slack (MET) : 4.837ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.062ns (logic 0.383ns (12.508%) route 2.679ns (87.492%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.785ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.360ns (routing 0.699ns, distribution 1.661ns) Clock Net Delay (Destination): 1.931ns (routing 0.636ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.360 2.785 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y235 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y235 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.924 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.897 4.821 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X41Y241 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.065 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.782 5.847 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X41Y230 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.624 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X41Y230 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C clock pessimism 0.188 10.812 clock uncertainty -0.035 10.777 SLICE_X41Y230 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.684 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3] ------------------------------------------------------------------- required time 10.684 arrival time -5.847 ------------------------------------------------------------------- slack 4.837 Slack (MET) : 4.837ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.062ns (logic 0.383ns (12.508%) route 2.679ns (87.492%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.785ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.360ns (routing 0.699ns, distribution 1.661ns) Clock Net Delay (Destination): 1.931ns (routing 0.636ns, distribution 1.295ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.360 2.785 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y235 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y235 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.924 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.897 4.821 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X41Y241 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.065 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.782 5.847 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X41Y230 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.624 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X41Y230 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/C clock pessimism 0.188 10.812 clock uncertainty -0.035 10.777 SLICE_X41Y230 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.684 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4] ------------------------------------------------------------------- required time 10.684 arrival time -5.847 ------------------------------------------------------------------- slack 4.837 Slack (MET) : 4.892ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.015ns (logic 0.383ns (12.703%) route 2.632ns (87.297%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.785ns Clock Pessimism Removal (CPR): 0.187ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.360ns (routing 0.699ns, distribution 1.661ns) Clock Net Delay (Destination): 1.940ns (routing 0.636ns, distribution 1.304ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.360 2.785 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y235 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y235 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.924 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.897 4.821 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X41Y241 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.065 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.735 5.800 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X40Y231 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.940 10.633 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y231 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/C clock pessimism 0.187 10.821 clock uncertainty -0.035 10.785 SLICE_X40Y231 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.692 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2] ------------------------------------------------------------------- required time 10.692 arrival time -5.800 ------------------------------------------------------------------- slack 4.892 Slack (MET) : 4.892ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.015ns (logic 0.383ns (12.703%) route 2.632ns (87.297%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.785ns Clock Pessimism Removal (CPR): 0.187ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.360ns (routing 0.699ns, distribution 1.661ns) Clock Net Delay (Destination): 1.940ns (routing 0.636ns, distribution 1.304ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.360 2.785 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y235 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y235 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.924 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.897 4.821 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X41Y241 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.065 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.735 5.800 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X40Y231 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.940 10.633 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y231 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C clock pessimism 0.187 10.821 clock uncertainty -0.035 10.785 SLICE_X40Y231 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.692 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3] ------------------------------------------------------------------- required time 10.692 arrival time -5.800 ------------------------------------------------------------------- slack 4.892 Slack (MET) : 4.892ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.014ns (logic 0.383ns (12.707%) route 2.631ns (87.293%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.315ns = ( 10.632 - 8.317 ) Source Clock Delay (SCD): 2.785ns Clock Pessimism Removal (CPR): 0.187ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.360ns (routing 0.699ns, distribution 1.661ns) Clock Net Delay (Destination): 1.939ns (routing 0.636ns, distribution 1.303ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.360 2.785 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y235 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y235 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.924 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.897 4.821 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X41Y241 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.065 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.734 5.799 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X39Y231 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.939 10.632 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X39Y231 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/C clock pessimism 0.187 10.820 clock uncertainty -0.035 10.784 SLICE_X39Y231 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.691 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7] ------------------------------------------------------------------- required time 10.691 arrival time -5.799 ------------------------------------------------------------------- slack 4.892 Slack (MET) : 4.900ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 3.005ns (logic 0.383ns (12.745%) route 2.622ns (87.255%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.314ns = ( 10.631 - 8.317 ) Source Clock Delay (SCD): 2.785ns Clock Pessimism Removal (CPR): 0.187ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.360ns (routing 0.699ns, distribution 1.661ns) Clock Net Delay (Destination): 1.938ns (routing 0.636ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.360 2.785 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y235 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y235 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.924 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.897 4.821 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X41Y241 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.065 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.725 5.790 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X40Y231 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.938 10.631 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y231 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/C clock pessimism 0.187 10.819 clock uncertainty -0.035 10.783 SLICE_X40Y231 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.690 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5] ------------------------------------------------------------------- required time 10.690 arrival time -5.790 ------------------------------------------------------------------- slack 4.900 Slack (MET) : 4.912ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 2.995ns (logic 0.383ns (12.788%) route 2.612ns (87.212%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.785ns Clock Pessimism Removal (CPR): 0.187ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.360ns (routing 0.699ns, distribution 1.661ns) Clock Net Delay (Destination): 1.940ns (routing 0.636ns, distribution 1.304ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.360 2.785 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y235 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y235 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.924 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.897 4.821 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X41Y241 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.065 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.715 5.780 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X40Y230 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.940 10.633 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y230 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C clock pessimism 0.187 10.821 clock uncertainty -0.035 10.785 SLICE_X40Y230 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.692 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1] ------------------------------------------------------------------- required time 10.692 arrival time -5.780 ------------------------------------------------------------------- slack 4.912 Slack (MET) : 4.912ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 2.995ns (logic 0.383ns (12.788%) route 2.612ns (87.212%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.785ns Clock Pessimism Removal (CPR): 0.187ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.360ns (routing 0.699ns, distribution 1.661ns) Clock Net Delay (Destination): 1.940ns (routing 0.636ns, distribution 1.304ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 2.360 2.785 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y235 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y235 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.924 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.897 4.821 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X41Y241 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 5.065 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/O net (fo=15, routed) 0.715 5.780 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X40Y230 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.940 10.633 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] SLICE_X40Y230 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C clock pessimism 0.187 10.821 clock uncertainty -0.035 10.785 SLICE_X40Y230 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.692 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6] ------------------------------------------------------------------- required time 10.692 arrival time -5.780 ------------------------------------------------------------------- slack 4.912 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.176ns (arrival time - required time) Source: SFP_GEN[31].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[31].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.048ns (18.321%) route 0.214ns (81.679%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns Source Clock Delay (SCD): 1.085ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 0.969ns (routing 0.319ns, distribution 0.650ns) Clock Net Delay (Destination): 1.162ns (routing 0.369ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.969 1.085 SFP_GEN[31].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X51Y237 FDPE r SFP_GEN[31].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y237 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.133 f SFP_GEN[31].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.214 1.347 SFP_GEN[31].ngCCM_gbt/sync_m_reg[3][0] SLICE_X52Y238 FDCE f SFP_GEN[31].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.314 SFP_GEN[31].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X52Y238 FDCE r SFP_GEN[31].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.148 1.166 SLICE_X52Y238 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.171 SFP_GEN[31].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.171 arrival time 1.347 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.190ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.267ns (logic 0.049ns (18.352%) route 0.218ns (81.648%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.848ns (routing 0.319ns, distribution 0.529ns) Clock Net Delay (Destination): 1.014ns (routing 0.369ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X41Y232 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y232 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.218 1.231 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X39Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[18]/C clock pessimism -0.130 1.036 SLICE_X39Y229 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.041 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[18] ------------------------------------------------------------------- required time -1.041 arrival time 1.231 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.190ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.267ns (logic 0.049ns (18.352%) route 0.218ns (81.648%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.848ns (routing 0.319ns, distribution 0.529ns) Clock Net Delay (Destination): 1.014ns (routing 0.369ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X41Y232 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y232 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.218 1.231 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X39Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[19]/C clock pessimism -0.130 1.036 SLICE_X39Y229 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.041 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[19] ------------------------------------------------------------------- required time -1.041 arrival time 1.231 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.190ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.267ns (logic 0.049ns (18.352%) route 0.218ns (81.648%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.848ns (routing 0.319ns, distribution 0.529ns) Clock Net Delay (Destination): 1.014ns (routing 0.369ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X41Y232 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y232 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.218 1.231 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X39Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[8]/C clock pessimism -0.130 1.036 SLICE_X39Y229 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.041 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[8] ------------------------------------------------------------------- required time -1.041 arrival time 1.231 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.190ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.267ns (logic 0.049ns (18.352%) route 0.218ns (81.648%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.848ns (routing 0.319ns, distribution 0.529ns) Clock Net Delay (Destination): 1.014ns (routing 0.369ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X41Y232 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y232 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.218 1.231 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X39Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[18]/C clock pessimism -0.130 1.036 SLICE_X39Y229 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.041 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[18] ------------------------------------------------------------------- required time -1.041 arrival time 1.231 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.190ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.267ns (logic 0.049ns (18.352%) route 0.218ns (81.648%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.848ns (routing 0.319ns, distribution 0.529ns) Clock Net Delay (Destination): 1.014ns (routing 0.369ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X41Y232 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y232 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.218 1.231 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X39Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[19]/C clock pessimism -0.130 1.036 SLICE_X39Y229 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.041 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[19] ------------------------------------------------------------------- required time -1.041 arrival time 1.231 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.190ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.267ns (logic 0.049ns (18.352%) route 0.218ns (81.648%)) Logic Levels: 0 Clock Path Skew: 0.072ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.848ns (routing 0.319ns, distribution 0.529ns) Clock Net Delay (Destination): 1.014ns (routing 0.369ns, distribution 0.645ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X41Y232 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y232 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.218 1.231 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X39Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[8]/C clock pessimism -0.130 1.036 SLICE_X39Y229 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.041 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[8] ------------------------------------------------------------------- required time -1.041 arrival time 1.231 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[42]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.168ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.848ns (routing 0.319ns, distribution 0.529ns) Clock Net Delay (Destination): 1.016ns (routing 0.369ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X41Y232 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y232 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X39Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[42]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[42]/C clock pessimism -0.130 1.038 SLICE_X39Y229 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.043 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[42] ------------------------------------------------------------------- required time -1.043 arrival time 1.234 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[48]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.168ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.848ns (routing 0.319ns, distribution 0.529ns) Clock Net Delay (Destination): 1.016ns (routing 0.369ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X41Y232 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y232 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X39Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[48]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[48]/C clock pessimism -0.130 1.038 SLICE_X39Y229 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.043 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[48] ------------------------------------------------------------------- required time -1.043 arrival time 1.234 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.191ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[50]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.049ns (18.148%) route 0.221ns (81.852%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.168ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.848ns (routing 0.319ns, distribution 0.529ns) Clock Net Delay (Destination): 1.016ns (routing 0.369ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 0.848 0.964 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X41Y232 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y232 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.013 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.221 1.234 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X39Y229 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[50]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y15 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y77 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y3 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y229 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[50]/C clock pessimism -0.130 1.038 SLICE_X39Y229 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.043 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[50] ------------------------------------------------------------------- required time -1.043 arrival time 1.234 ------------------------------------------------------------------- slack 0.191 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_34 To Clock: gtwiz_userclk_rx_srcclk_out[0]_34 Setup : 0 Failing Endpoints, Worst Slack 4.041ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.144ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.041ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.151ns (logic 0.306ns (7.372%) route 3.845ns (92.628%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.588ns = ( 10.905 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.686ns, distribution 1.670ns) Clock Net Delay (Destination): 2.212ns (routing 0.623ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y249 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.920 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.210 6.130 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X52Y254 LUT2 (Prop_C6LUT_SLICEM_I0_O) 0.167 6.297 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31/O net (fo=2, routed) 0.635 6.932 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X50Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.905 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X50Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.196 11.101 clock uncertainty -0.035 11.066 SLICE_X50Y253 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.973 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.973 arrival time -6.932 ------------------------------------------------------------------- slack 4.041 Slack (MET) : 4.041ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 4.151ns (logic 0.306ns (7.372%) route 3.845ns (92.628%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.588ns = ( 10.905 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.686ns, distribution 1.670ns) Clock Net Delay (Destination): 2.212ns (routing 0.623ns, distribution 1.589ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y249 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.920 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.210 6.130 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X52Y254 LUT2 (Prop_C6LUT_SLICEM_I0_O) 0.167 6.297 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31/O net (fo=2, routed) 0.635 6.932 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X50Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.905 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X50Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.196 11.101 clock uncertainty -0.035 11.066 SLICE_X50Y253 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.973 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.973 arrival time -6.932 ------------------------------------------------------------------- slack 4.041 Slack (MET) : 4.248ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.651ns (logic 0.139ns (3.807%) route 3.512ns (96.193%)) Logic Levels: 0 Clock Path Skew: -0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.302ns = ( 10.619 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.686ns, distribution 1.670ns) Clock Net Delay (Destination): 1.926ns (routing 0.623ns, distribution 1.303ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y249 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.920 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.512 6.432 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/AS[0] SLICE_X47Y251 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.926 10.619 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK SLICE_X47Y251 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C clock pessimism 0.189 10.808 clock uncertainty -0.035 10.773 SLICE_X47Y251 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.680 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg ------------------------------------------------------------------- required time 10.680 arrival time -6.432 ------------------------------------------------------------------- slack 4.248 Slack (MET) : 4.606ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.592ns (logic 0.285ns (7.934%) route 3.307ns (92.066%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.594ns = ( 10.911 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.686ns, distribution 1.670ns) Clock Net Delay (Destination): 2.218ns (routing 0.623ns, distribution 1.595ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y249 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.920 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.753 5.673 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X50Y252 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.819 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.554 6.373 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X49Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.218 10.911 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X49Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/C clock pessimism 0.196 11.107 clock uncertainty -0.035 11.072 SLICE_X49Y253 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.979 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1] ------------------------------------------------------------------- required time 10.979 arrival time -6.373 ------------------------------------------------------------------- slack 4.606 Slack (MET) : 4.606ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.592ns (logic 0.285ns (7.934%) route 3.307ns (92.066%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.009ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.594ns = ( 10.911 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.686ns, distribution 1.670ns) Clock Net Delay (Destination): 2.218ns (routing 0.623ns, distribution 1.595ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y249 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.920 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.753 5.673 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X50Y252 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.819 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.554 6.373 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X49Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.218 10.911 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X49Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/C clock pessimism 0.196 11.107 clock uncertainty -0.035 11.072 SLICE_X49Y253 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 10.979 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2] ------------------------------------------------------------------- required time 10.979 arrival time -6.373 ------------------------------------------------------------------- slack 4.606 Slack (MET) : 4.612ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.585ns (logic 0.285ns (7.950%) route 3.300ns (92.050%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.008ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.593ns = ( 10.910 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.686ns, distribution 1.670ns) Clock Net Delay (Destination): 2.217ns (routing 0.623ns, distribution 1.594ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y249 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.920 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.753 5.673 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X50Y252 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.819 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.547 6.366 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X49Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.217 10.910 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X49Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/C clock pessimism 0.196 11.106 clock uncertainty -0.035 11.071 SLICE_X49Y253 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.978 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5] ------------------------------------------------------------------- required time 10.978 arrival time -6.366 ------------------------------------------------------------------- slack 4.612 Slack (MET) : 4.627ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.575ns (logic 0.285ns (7.972%) route 3.290ns (92.028%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.598ns = ( 10.915 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.686ns, distribution 1.670ns) Clock Net Delay (Destination): 2.222ns (routing 0.623ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y249 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.920 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.753 5.673 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X50Y252 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.819 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.537 6.356 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X48Y254 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.222 10.915 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X48Y254 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C clock pessimism 0.196 11.111 clock uncertainty -0.035 11.076 SLICE_X48Y254 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.983 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5] ------------------------------------------------------------------- required time 10.983 arrival time -6.356 ------------------------------------------------------------------- slack 4.627 Slack (MET) : 4.627ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.575ns (logic 0.285ns (7.972%) route 3.290ns (92.028%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.598ns = ( 10.915 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.686ns, distribution 1.670ns) Clock Net Delay (Destination): 2.222ns (routing 0.623ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y249 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.920 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.753 5.673 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X50Y252 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.819 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.537 6.356 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X48Y254 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.222 10.915 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X48Y254 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/C clock pessimism 0.196 11.111 clock uncertainty -0.035 11.076 SLICE_X48Y254 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.983 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7] ------------------------------------------------------------------- required time 10.983 arrival time -6.356 ------------------------------------------------------------------- slack 4.627 Slack (MET) : 4.633ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.569ns (logic 0.285ns (7.985%) route 3.284ns (92.015%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.598ns = ( 10.915 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.686ns, distribution 1.670ns) Clock Net Delay (Destination): 2.222ns (routing 0.623ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y249 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.920 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.753 5.673 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X50Y252 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.819 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.531 6.350 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X48Y253 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.222 10.915 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X48Y253 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/C clock pessimism 0.196 11.111 clock uncertainty -0.035 11.076 SLICE_X48Y253 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.983 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8] ------------------------------------------------------------------- required time 10.983 arrival time -6.350 ------------------------------------------------------------------- slack 4.633 Slack (MET) : 4.635ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 3.565ns (logic 0.285ns (7.994%) route 3.280ns (92.006%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.596ns = ( 10.913 - 8.317 ) Source Clock Delay (SCD): 2.781ns Clock Pessimism Removal (CPR): 0.196ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.356ns (routing 0.686ns, distribution 1.670ns) Clock Net Delay (Destination): 2.220ns (routing 0.623ns, distribution 1.597ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.356 2.781 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X4Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X4Y249 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.920 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.753 5.673 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X50Y252 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.146 5.819 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/O net (fo=15, routed) 0.527 6.346 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X48Y254 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.220 10.913 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 SLICE_X48Y254 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/C clock pessimism 0.196 11.109 clock uncertainty -0.035 11.074 SLICE_X48Y254 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.981 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6] ------------------------------------------------------------------- required time 10.981 arrival time -6.346 ------------------------------------------------------------------- slack 4.635 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.144ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.049ns (26.486%) route 0.136ns (73.514%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.314ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.188ns Clock Net Delay (Source): 0.974ns (routing 0.315ns, distribution 0.659ns) Clock Net Delay (Destination): 1.162ns (routing 0.364ns, distribution 0.798ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X48Y250 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X48Y250 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.139 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.136 1.275 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X48Y250 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.314 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X48Y250 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.188 1.126 SLICE_X48Y250 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.131 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.131 arrival time 1.275 ------------------------------------------------------------------- slack 0.144 Slack (MET) : 0.151ns (arrival time - required time) Source: SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.048ns (20.690%) route 0.184ns (79.310%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.094ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.978ns (routing 0.315ns, distribution 0.663ns) Clock Net Delay (Destination): 1.164ns (routing 0.364ns, distribution 0.800ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.094 SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y243 FDPE r SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y243 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.142 f SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.184 1.326 SFP_GEN[32].ngCCM_gbt/sync_m_reg[3][0] SLICE_X58Y245 FDCE f SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.164 1.316 SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y245 FDCE r SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.146 1.170 SLICE_X58Y245 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.175 SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.175 arrival time 1.326 ------------------------------------------------------------------- slack 0.151 Slack (MET) : 0.151ns (arrival time - required time) Source: SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.232ns (logic 0.048ns (20.690%) route 0.184ns (79.310%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.316ns Source Clock Delay (SCD): 1.094ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.978ns (routing 0.315ns, distribution 0.663ns) Clock Net Delay (Destination): 1.164ns (routing 0.364ns, distribution 0.800ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.978 1.094 SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X59Y243 FDPE r SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X59Y243 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.142 f SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.184 1.326 SFP_GEN[32].ngCCM_gbt/sync_m_reg[3][0] SLICE_X58Y245 FDCE f SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.164 1.316 SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y245 FDCE r SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.146 1.170 SLICE_X58Y245 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.175 SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -1.175 arrival time 1.326 ------------------------------------------------------------------- slack 0.151 Slack (MET) : 0.155ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[80]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.301ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.974ns (routing 0.315ns, distribution 0.659ns) Clock Net Delay (Destination): 1.149ns (routing 0.364ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X48Y250 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X48Y250 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.139 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.176 1.315 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X49Y249 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[80]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.149 1.301 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X49Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[80]/C clock pessimism -0.146 1.155 SLICE_X49Y249 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.160 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[80] ------------------------------------------------------------------- required time -1.160 arrival time 1.315 ------------------------------------------------------------------- slack 0.155 Slack (MET) : 0.155ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[80]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.301ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.974ns (routing 0.315ns, distribution 0.659ns) Clock Net Delay (Destination): 1.149ns (routing 0.364ns, distribution 0.785ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X48Y250 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X48Y250 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.139 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.176 1.315 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X49Y249 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[80]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.149 1.301 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X49Y249 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[80]/C clock pessimism -0.146 1.155 SLICE_X49Y249 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.160 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[80] ------------------------------------------------------------------- required time -1.160 arrival time 1.315 ------------------------------------------------------------------- slack 0.155 Slack (MET) : 0.164ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.974ns (routing 0.315ns, distribution 0.659ns) Clock Net Delay (Destination): 1.157ns (routing 0.364ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X48Y250 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X48Y250 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.139 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.193 1.332 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X50Y248 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X50Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]/C clock pessimism -0.146 1.163 SLICE_X50Y248 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81] ------------------------------------------------------------------- required time -1.168 arrival time 1.332 ------------------------------------------------------------------- slack 0.164 Slack (MET) : 0.164ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[82]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.974ns (routing 0.315ns, distribution 0.659ns) Clock Net Delay (Destination): 1.157ns (routing 0.364ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X48Y250 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X48Y250 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.139 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.193 1.332 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X50Y248 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[82]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X50Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[82]/C clock pessimism -0.146 1.163 SLICE_X50Y248 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[82] ------------------------------------------------------------------- required time -1.168 arrival time 1.332 ------------------------------------------------------------------- slack 0.164 Slack (MET) : 0.164ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.974ns (routing 0.315ns, distribution 0.659ns) Clock Net Delay (Destination): 1.157ns (routing 0.364ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X48Y250 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X48Y250 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.139 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.193 1.332 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X50Y248 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X50Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]/C clock pessimism -0.146 1.163 SLICE_X50Y248 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83] ------------------------------------------------------------------- required time -1.168 arrival time 1.332 ------------------------------------------------------------------- slack 0.164 Slack (MET) : 0.164ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.974ns (routing 0.315ns, distribution 0.659ns) Clock Net Delay (Destination): 1.157ns (routing 0.364ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X48Y250 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X48Y250 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.139 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.193 1.332 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X50Y248 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X50Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]/C clock pessimism -0.146 1.163 SLICE_X50Y248 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81] ------------------------------------------------------------------- required time -1.168 arrival time 1.332 ------------------------------------------------------------------- slack 0.164 Slack (MET) : 0.164ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[82]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.974ns (routing 0.315ns, distribution 0.659ns) Clock Net Delay (Destination): 1.157ns (routing 0.364ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X48Y250 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X48Y250 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.139 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.193 1.332 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X50Y248 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[82]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y16 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y101 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X50Y248 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[82]/C clock pessimism -0.146 1.163 SLICE_X50Y248 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.168 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[82] ------------------------------------------------------------------- required time -1.168 arrival time 1.332 ------------------------------------------------------------------- slack 0.164 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_35 To Clock: gtwiz_userclk_rx_srcclk_out[0]_35 Setup : 0 Failing Endpoints, Worst Slack 5.239ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.146ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.239ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 2.663ns (logic 0.374ns (14.044%) route 2.289ns (85.956%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.287ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.291ns = ( 10.608 - 8.317 ) Source Clock Delay (SCD): 2.767ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.342ns (routing 0.686ns, distribution 1.656ns) Clock Net Delay (Destination): 1.915ns (routing 0.623ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.342 2.767 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y260 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.906 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.773 4.679 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y265 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 4.914 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.516 5.430 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X41Y264 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.915 10.608 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X41Y264 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/C clock pessimism 0.189 10.797 clock uncertainty -0.035 10.762 SLICE_X41Y264 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.669 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1] ------------------------------------------------------------------- required time 10.669 arrival time -5.430 ------------------------------------------------------------------- slack 5.239 Slack (MET) : 5.239ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 2.663ns (logic 0.374ns (14.044%) route 2.289ns (85.956%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.287ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.291ns = ( 10.608 - 8.317 ) Source Clock Delay (SCD): 2.767ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.342ns (routing 0.686ns, distribution 1.656ns) Clock Net Delay (Destination): 1.915ns (routing 0.623ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.342 2.767 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y260 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.906 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.773 4.679 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y265 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 4.914 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.516 5.430 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X41Y264 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.915 10.608 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X41Y264 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/C clock pessimism 0.189 10.797 clock uncertainty -0.035 10.762 SLICE_X41Y264 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.669 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2] ------------------------------------------------------------------- required time 10.669 arrival time -5.430 ------------------------------------------------------------------- slack 5.239 Slack (MET) : 5.239ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 2.663ns (logic 0.374ns (14.044%) route 2.289ns (85.956%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.287ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.291ns = ( 10.608 - 8.317 ) Source Clock Delay (SCD): 2.767ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.342ns (routing 0.686ns, distribution 1.656ns) Clock Net Delay (Destination): 1.915ns (routing 0.623ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.342 2.767 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y260 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.906 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.773 4.679 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y265 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 4.914 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.516 5.430 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X41Y264 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.915 10.608 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X41Y264 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/C clock pessimism 0.189 10.797 clock uncertainty -0.035 10.762 SLICE_X41Y264 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.669 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4] ------------------------------------------------------------------- required time 10.669 arrival time -5.430 ------------------------------------------------------------------- slack 5.239 Slack (MET) : 5.244ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 2.656ns (logic 0.374ns (14.081%) route 2.282ns (85.919%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.289ns = ( 10.606 - 8.317 ) Source Clock Delay (SCD): 2.767ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.342ns (routing 0.686ns, distribution 1.656ns) Clock Net Delay (Destination): 1.913ns (routing 0.623ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.342 2.767 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y260 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.906 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.773 4.679 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y265 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 4.914 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.509 5.423 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X41Y264 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.913 10.606 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X41Y264 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C clock pessimism 0.189 10.795 clock uncertainty -0.035 10.760 SLICE_X41Y264 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.667 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3] ------------------------------------------------------------------- required time 10.667 arrival time -5.423 ------------------------------------------------------------------- slack 5.244 Slack (MET) : 5.244ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 2.656ns (logic 0.374ns (14.081%) route 2.282ns (85.919%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.289ns = ( 10.606 - 8.317 ) Source Clock Delay (SCD): 2.767ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.342ns (routing 0.686ns, distribution 1.656ns) Clock Net Delay (Destination): 1.913ns (routing 0.623ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.342 2.767 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y260 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.906 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.773 4.679 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y265 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 4.914 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.509 5.423 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X41Y264 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.913 10.606 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X41Y264 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/C clock pessimism 0.189 10.795 clock uncertainty -0.035 10.760 SLICE_X41Y264 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 10.667 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5] ------------------------------------------------------------------- required time 10.667 arrival time -5.423 ------------------------------------------------------------------- slack 5.244 Slack (MET) : 5.293ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 2.624ns (logic 0.286ns (10.899%) route 2.338ns (89.101%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.272ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.767ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.342ns (routing 0.686ns, distribution 1.656ns) Clock Net Delay (Destination): 1.930ns (routing 0.623ns, distribution 1.307ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.342 2.767 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y260 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.906 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.761 4.667 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y263 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.147 4.814 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32/O net (fo=2, routed) 0.577 5.391 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X40Y263 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X40Y263 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.189 10.812 clock uncertainty -0.035 10.777 SLICE_X40Y263 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.684 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.684 arrival time -5.391 ------------------------------------------------------------------- slack 5.293 Slack (MET) : 5.293ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 2.624ns (logic 0.286ns (10.899%) route 2.338ns (89.101%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.272ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.767ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.342ns (routing 0.686ns, distribution 1.656ns) Clock Net Delay (Destination): 1.930ns (routing 0.623ns, distribution 1.307ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.342 2.767 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y260 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.906 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.761 4.667 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y263 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.147 4.814 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32/O net (fo=2, routed) 0.577 5.391 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X40Y263 FDCE f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X40Y263 FDCE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.189 10.812 clock uncertainty -0.035 10.777 SLICE_X40Y263 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.684 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.684 arrival time -5.391 ------------------------------------------------------------------- slack 5.293 Slack (MET) : 5.313ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 2.588ns (logic 0.374ns (14.451%) route 2.214ns (85.549%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.288ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.290ns = ( 10.607 - 8.317 ) Source Clock Delay (SCD): 2.767ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.342ns (routing 0.686ns, distribution 1.656ns) Clock Net Delay (Destination): 1.914ns (routing 0.623ns, distribution 1.291ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.342 2.767 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y260 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.906 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.773 4.679 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y265 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 4.914 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.441 5.355 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X41Y265 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.914 10.607 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X41Y265 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C clock pessimism 0.189 10.796 clock uncertainty -0.035 10.761 SLICE_X41Y265 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.668 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1] ------------------------------------------------------------------- required time 10.668 arrival time -5.355 ------------------------------------------------------------------- slack 5.313 Slack (MET) : 5.313ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 2.588ns (logic 0.374ns (14.451%) route 2.214ns (85.549%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.288ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.290ns = ( 10.607 - 8.317 ) Source Clock Delay (SCD): 2.767ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.342ns (routing 0.686ns, distribution 1.656ns) Clock Net Delay (Destination): 1.914ns (routing 0.623ns, distribution 1.291ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.342 2.767 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y260 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.906 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.773 4.679 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y265 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 4.914 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.441 5.355 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X41Y265 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.914 10.607 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X41Y265 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/C clock pessimism 0.189 10.796 clock uncertainty -0.035 10.761 SLICE_X41Y265 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 10.668 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2] ------------------------------------------------------------------- required time 10.668 arrival time -5.355 ------------------------------------------------------------------- slack 5.313 Slack (MET) : 5.313ns (required time - arrival time) Source: g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 2.588ns (logic 0.374ns (14.451%) route 2.214ns (85.549%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.288ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.290ns = ( 10.607 - 8.317 ) Source Clock Delay (SCD): 2.767ns Clock Pessimism Removal (CPR): 0.189ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.342ns (routing 0.686ns, distribution 1.656ns) Clock Net Delay (Destination): 1.914ns (routing 0.623ns, distribution 1.291ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 2.342 2.767 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y260 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y260 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.906 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.773 4.679 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y265 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.235 4.914 f g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/O net (fo=15, routed) 0.441 5.355 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9]0 SLICE_X41Y265 FDCE f g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.914 10.607 g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X41Y265 FDCE r g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/C clock pessimism 0.189 10.796 clock uncertainty -0.035 10.761 SLICE_X41Y265 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.668 g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3] ------------------------------------------------------------------- required time 10.668 arrival time -5.355 ------------------------------------------------------------------- slack 5.313 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.146ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.048ns (26.229%) route 0.135ns (73.770%)) Logic Levels: 0 Clock Path Skew: 0.032ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.172ns Clock Net Delay (Source): 0.853ns (routing 0.315ns, distribution 0.538ns) Clock Net Delay (Destination): 1.021ns (routing 0.364ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y253 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y253 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.017 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.135 1.152 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X40Y253 FDCE f SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.173 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X40Y253 FDCE r SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.172 1.001 SLICE_X40Y253 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.006 SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.006 arrival time 1.152 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.177ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.168ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.853ns (routing 0.315ns, distribution 0.538ns) Clock Net Delay (Destination): 1.016ns (routing 0.364ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y253 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y253 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.017 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.173 1.190 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y251 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.168 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y251 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.160 1.008 SLICE_X39Y251 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.013 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.013 arrival time 1.190 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.177ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.168ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.853ns (routing 0.315ns, distribution 0.538ns) Clock Net Delay (Destination): 1.016ns (routing 0.364ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y253 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y253 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.017 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.173 1.190 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y251 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.168 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y251 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.160 1.008 SLICE_X39Y251 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.013 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -1.013 arrival time 1.190 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.177ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.168ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.853ns (routing 0.315ns, distribution 0.538ns) Clock Net Delay (Destination): 1.016ns (routing 0.364ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y253 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y253 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.017 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.173 1.190 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y251 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.168 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y251 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.160 1.008 SLICE_X39Y251 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.013 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -1.013 arrival time 1.190 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.177ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.048ns (21.719%) route 0.173ns (78.281%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.168ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.853ns (routing 0.315ns, distribution 0.538ns) Clock Net Delay (Destination): 1.016ns (routing 0.364ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y253 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y253 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.017 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.173 1.190 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y251 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.168 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y251 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism -0.160 1.008 SLICE_X39Y251 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.013 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time -1.013 arrival time 1.190 ------------------------------------------------------------------- slack 0.177 Slack (MET) : 0.183ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.226ns (logic 0.048ns (21.239%) route 0.178ns (78.761%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.167ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.853ns (routing 0.315ns, distribution 0.538ns) Clock Net Delay (Destination): 1.015ns (routing 0.364ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y253 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y253 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.017 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.178 1.195 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X40Y255 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.015 1.167 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X40Y255 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[25]/C clock pessimism -0.160 1.007 SLICE_X40Y255 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.012 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[25] ------------------------------------------------------------------- required time -1.012 arrival time 1.195 ------------------------------------------------------------------- slack 0.183 Slack (MET) : 0.191ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.272ns (logic 0.048ns (17.647%) route 0.224ns (82.353%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.853ns (routing 0.315ns, distribution 0.538ns) Clock Net Delay (Destination): 1.021ns (routing 0.364ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y253 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y253 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.017 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.224 1.241 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X35Y251 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.173 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y251 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[4]/C clock pessimism -0.128 1.045 SLICE_X35Y251 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.050 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[4] ------------------------------------------------------------------- required time -1.050 arrival time 1.241 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.191ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.272ns (logic 0.048ns (17.647%) route 0.224ns (82.353%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.173ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.128ns Clock Net Delay (Source): 0.853ns (routing 0.315ns, distribution 0.538ns) Clock Net Delay (Destination): 1.021ns (routing 0.364ns, distribution 0.657ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y253 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y253 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.017 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.224 1.241 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X35Y251 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.021 1.173 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y251 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[6]/C clock pessimism -0.128 1.045 SLICE_X35Y251 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.050 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[6] ------------------------------------------------------------------- required time -1.050 arrival time 1.241 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.207ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.182ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.853ns (routing 0.315ns, distribution 0.538ns) Clock Net Delay (Destination): 1.030ns (routing 0.364ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y253 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y253 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.017 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.217 1.234 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y257 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.030 1.182 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y257 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.160 1.022 SLICE_X39Y257 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.027 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.027 arrival time 1.234 ------------------------------------------------------------------- slack 0.207 Slack (MET) : 0.207ns (arrival time - required time) Source: SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.182ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.853ns (routing 0.315ns, distribution 0.538ns) Clock Net Delay (Destination): 1.030ns (routing 0.364ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y253 FDPE r SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y253 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.017 f SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.217 1.234 SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y257 FDCE f SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y17 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y102 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y4 (CLOCK_ROOT) net (fo=674, routed) 1.030 1.182 SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y257 FDCE r SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.160 1.022 SLICE_X39Y257 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.027 SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.027 arrival time 1.234 ------------------------------------------------------------------- slack 0.207 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_36 To Clock: gtwiz_userclk_rx_srcclk_out[0]_36 Setup : 0 Failing Endpoints, Worst Slack 4.943ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.112ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.943ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 2.947ns (logic 0.376ns (12.759%) route 2.571ns (87.241%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.299ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.789ns = ( 11.106 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.413ns (routing 1.095ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.571 5.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X38Y416 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.237 5.272 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 1.000 6.272 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X41Y424 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.413 11.106 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y424 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/C clock pessimism 0.237 11.344 clock uncertainty -0.035 11.308 SLICE_X41Y424 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.215 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1] ------------------------------------------------------------------- required time 11.215 arrival time -6.272 ------------------------------------------------------------------- slack 4.943 Slack (MET) : 4.943ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 2.947ns (logic 0.376ns (12.759%) route 2.571ns (87.241%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.299ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.789ns = ( 11.106 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.413ns (routing 1.095ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.571 5.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X38Y416 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.237 5.272 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 1.000 6.272 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X41Y424 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.413 11.106 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y424 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/C clock pessimism 0.237 11.344 clock uncertainty -0.035 11.308 SLICE_X41Y424 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.215 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2] ------------------------------------------------------------------- required time 11.215 arrival time -6.272 ------------------------------------------------------------------- slack 4.943 Slack (MET) : 4.943ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 2.947ns (logic 0.376ns (12.759%) route 2.571ns (87.241%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.299ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.789ns = ( 11.106 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.413ns (routing 1.095ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.571 5.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X38Y416 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.237 5.272 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 1.000 6.272 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X41Y424 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.413 11.106 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y424 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/C clock pessimism 0.237 11.344 clock uncertainty -0.035 11.308 SLICE_X41Y424 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.215 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3] ------------------------------------------------------------------- required time 11.215 arrival time -6.272 ------------------------------------------------------------------- slack 4.943 Slack (MET) : 4.943ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 2.947ns (logic 0.376ns (12.759%) route 2.571ns (87.241%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.299ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.789ns = ( 11.106 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.413ns (routing 1.095ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.571 5.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X38Y416 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.237 5.272 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 1.000 6.272 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X41Y424 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.413 11.106 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X41Y424 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/C clock pessimism 0.237 11.344 clock uncertainty -0.035 11.308 SLICE_X41Y424 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.215 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4] ------------------------------------------------------------------- required time 11.215 arrival time -6.272 ------------------------------------------------------------------- slack 4.943 Slack (MET) : 4.981ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 2.892ns (logic 0.376ns (13.001%) route 2.516ns (86.999%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.316ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.771ns = ( 11.088 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.238ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.395ns (routing 1.095ns, distribution 1.300ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.571 5.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X38Y416 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.237 5.272 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.945 6.217 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X44Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.395 11.088 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X44Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C clock pessimism 0.238 11.326 clock uncertainty -0.035 11.291 SLICE_X44Y421 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.198 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0] ------------------------------------------------------------------- required time 11.198 arrival time -6.217 ------------------------------------------------------------------- slack 4.981 Slack (MET) : 5.095ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 2.796ns (logic 0.376ns (13.448%) route 2.420ns (86.552%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.298ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.790ns = ( 11.107 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.414ns (routing 1.095ns, distribution 1.319ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.571 5.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X38Y416 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.237 5.272 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.849 6.121 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X42Y423 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.414 11.107 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y423 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/C clock pessimism 0.237 11.345 clock uncertainty -0.035 11.309 SLICE_X42Y423 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.216 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4] ------------------------------------------------------------------- required time 11.216 arrival time -6.121 ------------------------------------------------------------------- slack 5.095 Slack (MET) : 5.095ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 2.796ns (logic 0.376ns (13.448%) route 2.420ns (86.552%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.298ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.790ns = ( 11.107 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.414ns (routing 1.095ns, distribution 1.319ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.571 5.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X38Y416 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.237 5.272 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.849 6.121 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X42Y423 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.414 11.107 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y423 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/C clock pessimism 0.237 11.345 clock uncertainty -0.035 11.309 SLICE_X42Y423 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.216 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5] ------------------------------------------------------------------- required time 11.216 arrival time -6.121 ------------------------------------------------------------------- slack 5.095 Slack (MET) : 5.095ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 2.796ns (logic 0.376ns (13.448%) route 2.420ns (86.552%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.298ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.790ns = ( 11.107 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.414ns (routing 1.095ns, distribution 1.319ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.571 5.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X38Y416 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.237 5.272 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.849 6.121 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X42Y423 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.414 11.107 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y423 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/C clock pessimism 0.237 11.345 clock uncertainty -0.035 11.309 SLICE_X42Y423 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.216 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6] ------------------------------------------------------------------- required time 11.216 arrival time -6.121 ------------------------------------------------------------------- slack 5.095 Slack (MET) : 5.095ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 2.796ns (logic 0.376ns (13.448%) route 2.420ns (86.552%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.298ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.790ns = ( 11.107 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.414ns (routing 1.095ns, distribution 1.319ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.571 5.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X38Y416 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.237 5.272 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.849 6.121 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X42Y423 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.414 11.107 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y423 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/C clock pessimism 0.237 11.345 clock uncertainty -0.035 11.309 SLICE_X42Y423 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.216 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7] ------------------------------------------------------------------- required time 11.216 arrival time -6.121 ------------------------------------------------------------------- slack 5.095 Slack (MET) : 5.148ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 2.729ns (logic 0.376ns (13.778%) route 2.353ns (86.222%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.775ns = ( 11.092 - 8.317 ) Source Clock Delay (SCD): 3.325ns Clock Pessimism Removal (CPR): 0.238ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.900ns (routing 1.208ns, distribution 1.692ns) Clock Net Delay (Destination): 2.399ns (routing 1.095ns, distribution 1.304ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.900 3.325 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y423 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y423 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.464 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.571 5.035 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X38Y416 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.237 5.272 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/O net (fo=15, routed) 0.782 6.054 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0]0 SLICE_X42Y421 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.399 11.092 g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] SLICE_X42Y421 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/C clock pessimism 0.238 11.330 clock uncertainty -0.035 11.295 SLICE_X42Y421 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.202 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0] ------------------------------------------------------------------- required time 11.202 arrival time -6.054 ------------------------------------------------------------------- slack 5.148 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.112ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.451ns Source Clock Delay (SCD): 1.216ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 1.100ns (routing 0.544ns, distribution 0.556ns) Clock Net Delay (Destination): 1.299ns (routing 0.626ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.100 1.216 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X38Y422 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X38Y422 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.265 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.139 1.404 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X39Y422 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.299 1.451 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X39Y422 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.164 1.287 SLICE_X39Y422 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.292 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.292 arrival time 1.404 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.049ns (26.064%) route 0.139ns (73.936%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.451ns Source Clock Delay (SCD): 1.216ns Clock Pessimism Removal (CPR): 0.164ns Clock Net Delay (Source): 1.100ns (routing 0.544ns, distribution 0.556ns) Clock Net Delay (Destination): 1.299ns (routing 0.626ns, distribution 0.673ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.100 1.216 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X38Y422 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X38Y422 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.265 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.139 1.404 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X39Y422 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.299 1.451 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X39Y422 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.164 1.287 SLICE_X39Y422 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.292 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.292 arrival time 1.404 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[105]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.240ns (logic 0.049ns (20.417%) route 0.191ns (79.583%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.442ns Source Clock Delay (SCD): 1.195ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 1.079ns (routing 0.544ns, distribution 0.535ns) Clock Net Delay (Destination): 1.290ns (routing 0.626ns, distribution 0.664ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.079 1.195 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X34Y418 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y418 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.244 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.191 1.435 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X35Y418 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[105]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.290 1.442 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X35Y418 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[105]/C clock pessimism -0.161 1.281 SLICE_X35Y418 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.286 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[105] ------------------------------------------------------------------- required time -1.286 arrival time 1.435 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[75]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.049ns (20.763%) route 0.187ns (79.237%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.438ns Source Clock Delay (SCD): 1.195ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 1.079ns (routing 0.544ns, distribution 0.535ns) Clock Net Delay (Destination): 1.286ns (routing 0.626ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.079 1.195 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X34Y418 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y418 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.244 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.187 1.431 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X36Y418 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[75]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.286 1.438 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X36Y418 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[75]/C clock pessimism -0.161 1.277 SLICE_X36Y418 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.282 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[75] ------------------------------------------------------------------- required time -1.282 arrival time 1.431 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[106]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.049ns (20.763%) route 0.187ns (79.237%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.438ns Source Clock Delay (SCD): 1.195ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 1.079ns (routing 0.544ns, distribution 0.535ns) Clock Net Delay (Destination): 1.286ns (routing 0.626ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.079 1.195 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X34Y418 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y418 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.244 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.187 1.431 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X36Y418 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[106]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.286 1.438 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X36Y418 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[106]/C clock pessimism -0.161 1.277 SLICE_X36Y418 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.282 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[106] ------------------------------------------------------------------- required time -1.282 arrival time 1.431 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[114]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.049ns (20.763%) route 0.187ns (79.237%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.438ns Source Clock Delay (SCD): 1.195ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 1.079ns (routing 0.544ns, distribution 0.535ns) Clock Net Delay (Destination): 1.286ns (routing 0.626ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.079 1.195 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X34Y418 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y418 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.244 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.187 1.431 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X36Y418 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[114]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.286 1.438 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X36Y418 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[114]/C clock pessimism -0.161 1.277 SLICE_X36Y418 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.282 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[114] ------------------------------------------------------------------- required time -1.282 arrival time 1.431 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[115]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.049ns (20.763%) route 0.187ns (79.237%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.438ns Source Clock Delay (SCD): 1.195ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 1.079ns (routing 0.544ns, distribution 0.535ns) Clock Net Delay (Destination): 1.286ns (routing 0.626ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.079 1.195 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X34Y418 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y418 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.244 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.187 1.431 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X36Y418 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[115]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.286 1.438 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X36Y418 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[115]/C clock pessimism -0.161 1.277 SLICE_X36Y418 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.282 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[115] ------------------------------------------------------------------- required time -1.282 arrival time 1.431 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.149ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[75]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.049ns (20.763%) route 0.187ns (79.237%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.438ns Source Clock Delay (SCD): 1.195ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 1.079ns (routing 0.544ns, distribution 0.535ns) Clock Net Delay (Destination): 1.286ns (routing 0.626ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.079 1.195 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X34Y418 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y418 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.244 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.187 1.431 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X36Y418 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[75]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.286 1.438 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X36Y418 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[75]/C clock pessimism -0.161 1.277 SLICE_X36Y418 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.282 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[75] ------------------------------------------------------------------- required time -1.282 arrival time 1.431 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.152ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[67]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.441ns Source Clock Delay (SCD): 1.195ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 1.079ns (routing 0.544ns, distribution 0.535ns) Clock Net Delay (Destination): 1.289ns (routing 0.626ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.079 1.195 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X34Y418 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y418 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.244 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.193 1.437 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X36Y418 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[67]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.289 1.441 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X36Y418 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[67]/C clock pessimism -0.161 1.280 SLICE_X36Y418 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.285 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[67] ------------------------------------------------------------------- required time -1.285 arrival time 1.437 ------------------------------------------------------------------- slack 0.152 Slack (MET) : 0.152ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[73]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.049ns (20.248%) route 0.193ns (79.752%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.441ns Source Clock Delay (SCD): 1.195ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 1.079ns (routing 0.544ns, distribution 0.535ns) Clock Net Delay (Destination): 1.289ns (routing 0.626ns, distribution 0.663ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.079 1.195 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK SLICE_X34Y418 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X34Y418 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.244 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.193 1.437 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X36Y418 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[73]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y28 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y191 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.289 1.441 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK SLICE_X36Y418 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[73]/C clock pessimism -0.161 1.280 SLICE_X36Y418 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.285 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[73] ------------------------------------------------------------------- required time -1.285 arrival time 1.437 ------------------------------------------------------------------- slack 0.152 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_37 To Clock: gtwiz_userclk_rx_srcclk_out[0]_37 Setup : 0 Failing Endpoints, Worst Slack 3.774ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.210ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.774ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 4.476ns (logic 0.383ns (8.557%) route 4.093ns (91.443%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.614ns = ( 10.931 - 8.317 ) Source Clock Delay (SCD): 2.746ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.697ns, distribution 1.624ns) Clock Net Delay (Destination): 2.238ns (routing 0.634ns, distribution 1.604ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y577 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y577 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.885 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.423 6.308 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X65Y559 LUT2 (Prop_C6LUT_SLICEM_I0_O) 0.244 6.552 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__45/O net (fo=2, routed) 0.670 7.222 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X68Y556 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.238 10.931 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK SLICE_X68Y556 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.193 11.124 clock uncertainty -0.035 11.089 SLICE_X68Y556 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.996 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.996 arrival time -7.222 ------------------------------------------------------------------- slack 3.774 Slack (MET) : 3.774ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 4.476ns (logic 0.383ns (8.557%) route 4.093ns (91.443%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.614ns = ( 10.931 - 8.317 ) Source Clock Delay (SCD): 2.746ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.697ns, distribution 1.624ns) Clock Net Delay (Destination): 2.238ns (routing 0.634ns, distribution 1.604ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y577 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y577 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.885 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.423 6.308 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X65Y559 LUT2 (Prop_C6LUT_SLICEM_I0_O) 0.244 6.552 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__45/O net (fo=2, routed) 0.670 7.222 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X68Y556 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.238 10.931 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK SLICE_X68Y556 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.193 11.124 clock uncertainty -0.035 11.089 SLICE_X68Y556 FDCE (Recov_AFF2_SLICEL_C_CLR) -0.093 10.996 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.996 arrival time -7.222 ------------------------------------------------------------------- slack 3.774 Slack (MET) : 3.815ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 4.434ns (logic 0.288ns (6.495%) route 4.146ns (93.505%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.613ns = ( 10.930 - 8.317 ) Source Clock Delay (SCD): 2.746ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.697ns, distribution 1.624ns) Clock Net Delay (Destination): 2.237ns (routing 0.634ns, distribution 1.603ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y577 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y577 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.885 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.406 6.291 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y559 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.440 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 0.740 7.180 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X70Y554 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.237 10.930 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X70Y554 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/C clock pessimism 0.193 11.123 clock uncertainty -0.035 11.088 SLICE_X70Y554 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.995 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0] ------------------------------------------------------------------- required time 10.995 arrival time -7.180 ------------------------------------------------------------------- slack 3.815 Slack (MET) : 3.815ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 4.434ns (logic 0.288ns (6.495%) route 4.146ns (93.505%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.613ns = ( 10.930 - 8.317 ) Source Clock Delay (SCD): 2.746ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.697ns, distribution 1.624ns) Clock Net Delay (Destination): 2.237ns (routing 0.634ns, distribution 1.603ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y577 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y577 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.885 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.406 6.291 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y559 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.440 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 0.740 7.180 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X70Y554 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.237 10.930 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X70Y554 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C clock pessimism 0.193 11.123 clock uncertainty -0.035 11.088 SLICE_X70Y554 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.995 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4] ------------------------------------------------------------------- required time 10.995 arrival time -7.180 ------------------------------------------------------------------- slack 3.815 Slack (MET) : 3.984ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 4.268ns (logic 0.288ns (6.748%) route 3.980ns (93.252%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.063ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.616ns = ( 10.933 - 8.317 ) Source Clock Delay (SCD): 2.746ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.697ns, distribution 1.624ns) Clock Net Delay (Destination): 2.240ns (routing 0.634ns, distribution 1.606ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y577 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y577 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.885 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.406 6.291 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y559 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.440 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 0.574 7.014 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X68Y554 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.240 10.933 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X68Y554 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C clock pessimism 0.193 11.126 clock uncertainty -0.035 11.091 SLICE_X68Y554 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.998 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3] ------------------------------------------------------------------- required time 10.998 arrival time -7.014 ------------------------------------------------------------------- slack 3.984 Slack (MET) : 3.984ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 4.268ns (logic 0.288ns (6.748%) route 3.980ns (93.252%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.063ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.616ns = ( 10.933 - 8.317 ) Source Clock Delay (SCD): 2.746ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.697ns, distribution 1.624ns) Clock Net Delay (Destination): 2.240ns (routing 0.634ns, distribution 1.606ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y577 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y577 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.885 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.406 6.291 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y559 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.440 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 0.574 7.014 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X68Y554 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.240 10.933 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X68Y554 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C clock pessimism 0.193 11.126 clock uncertainty -0.035 11.091 SLICE_X68Y554 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.998 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5] ------------------------------------------------------------------- required time 10.998 arrival time -7.014 ------------------------------------------------------------------- slack 3.984 Slack (MET) : 3.984ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 4.268ns (logic 0.288ns (6.748%) route 3.980ns (93.252%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.063ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.616ns = ( 10.933 - 8.317 ) Source Clock Delay (SCD): 2.746ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.697ns, distribution 1.624ns) Clock Net Delay (Destination): 2.240ns (routing 0.634ns, distribution 1.606ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y577 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y577 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.885 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.406 6.291 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y559 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.440 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 0.574 7.014 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X68Y554 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.240 10.933 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X68Y554 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C clock pessimism 0.193 11.126 clock uncertainty -0.035 11.091 SLICE_X68Y554 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.998 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7] ------------------------------------------------------------------- required time 10.998 arrival time -7.014 ------------------------------------------------------------------- slack 3.984 Slack (MET) : 3.992ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 4.258ns (logic 0.288ns (6.764%) route 3.970ns (93.236%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.614ns = ( 10.931 - 8.317 ) Source Clock Delay (SCD): 2.746ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.697ns, distribution 1.624ns) Clock Net Delay (Destination): 2.238ns (routing 0.634ns, distribution 1.604ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y577 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y577 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.885 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.406 6.291 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y559 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.440 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 0.564 7.004 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X68Y554 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.238 10.931 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X68Y554 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C clock pessimism 0.193 11.124 clock uncertainty -0.035 11.089 SLICE_X68Y554 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.996 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1] ------------------------------------------------------------------- required time 10.996 arrival time -7.004 ------------------------------------------------------------------- slack 3.992 Slack (MET) : 3.992ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 4.258ns (logic 0.288ns (6.764%) route 3.970ns (93.236%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.614ns = ( 10.931 - 8.317 ) Source Clock Delay (SCD): 2.746ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.697ns, distribution 1.624ns) Clock Net Delay (Destination): 2.238ns (routing 0.634ns, distribution 1.604ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y577 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y577 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.885 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.406 6.291 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y559 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.440 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 0.564 7.004 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X68Y554 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.238 10.931 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X68Y554 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C clock pessimism 0.193 11.124 clock uncertainty -0.035 11.089 SLICE_X68Y554 FDCE (Recov_GFF2_SLICEL_C_CLR) -0.093 10.996 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2] ------------------------------------------------------------------- required time 10.996 arrival time -7.004 ------------------------------------------------------------------- slack 3.992 Slack (MET) : 3.992ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 4.258ns (logic 0.288ns (6.764%) route 3.970ns (93.236%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.614ns = ( 10.931 - 8.317 ) Source Clock Delay (SCD): 2.746ns Clock Pessimism Removal (CPR): 0.193ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.697ns, distribution 1.624ns) Clock Net Delay (Destination): 2.238ns (routing 0.634ns, distribution 1.604ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y577 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y577 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.885 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.406 6.291 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X65Y559 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 6.440 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/O net (fo=15, routed) 0.564 7.004 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 SLICE_X68Y554 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.238 10.931 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] SLICE_X68Y554 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C clock pessimism 0.193 11.124 clock uncertainty -0.035 11.089 SLICE_X68Y554 FDCE (Recov_FFF_SLICEL_C_CLR) -0.093 10.996 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6] ------------------------------------------------------------------- required time 10.996 arrival time -7.004 ------------------------------------------------------------------- slack 3.992 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.210ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.281ns (logic 0.049ns (17.438%) route 0.232ns (82.562%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.303ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.974ns (routing 0.318ns, distribution 0.656ns) Clock Net Delay (Destination): 1.151ns (routing 0.368ns, distribution 0.783ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y571 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.232 1.371 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X68Y569 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.151 1.303 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK SLICE_X68Y569 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.147 1.156 SLICE_X68Y569 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.161 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.161 arrival time 1.371 ------------------------------------------------------------------- slack 0.210 Slack (MET) : 0.214ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.288ns (logic 0.049ns (17.014%) route 0.239ns (82.986%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.306ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.974ns (routing 0.318ns, distribution 0.656ns) Clock Net Delay (Destination): 1.154ns (routing 0.368ns, distribution 0.786ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y571 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.239 1.378 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X64Y568 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.154 1.306 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X64Y568 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.147 1.159 SLICE_X64Y568 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.164 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -1.164 arrival time 1.378 ------------------------------------------------------------------- slack 0.214 Slack (MET) : 0.214ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.288ns (logic 0.049ns (17.014%) route 0.239ns (82.986%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.306ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.974ns (routing 0.318ns, distribution 0.656ns) Clock Net Delay (Destination): 1.154ns (routing 0.368ns, distribution 0.786ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y571 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.239 1.378 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X64Y568 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.154 1.306 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X64Y568 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.147 1.159 SLICE_X64Y568 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.164 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.164 arrival time 1.378 ------------------------------------------------------------------- slack 0.214 Slack (MET) : 0.214ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.288ns (logic 0.049ns (17.014%) route 0.239ns (82.986%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.306ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.974ns (routing 0.318ns, distribution 0.656ns) Clock Net Delay (Destination): 1.154ns (routing 0.368ns, distribution 0.786ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y571 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.239 1.378 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X64Y568 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.154 1.306 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X64Y568 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.147 1.159 SLICE_X64Y568 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.164 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.164 arrival time 1.378 ------------------------------------------------------------------- slack 0.214 Slack (MET) : 0.214ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.288ns (logic 0.049ns (17.014%) route 0.239ns (82.986%)) Logic Levels: 0 Clock Path Skew: 0.069ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.306ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.974ns (routing 0.318ns, distribution 0.656ns) Clock Net Delay (Destination): 1.154ns (routing 0.368ns, distribution 0.786ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y571 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.239 1.378 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X64Y568 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.154 1.306 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X64Y568 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.147 1.159 SLICE_X64Y568 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.164 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.164 arrival time 1.378 ------------------------------------------------------------------- slack 0.214 Slack (MET) : 0.216ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.292ns (logic 0.049ns (16.781%) route 0.243ns (83.219%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.308ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.974ns (routing 0.318ns, distribution 0.656ns) Clock Net Delay (Destination): 1.156ns (routing 0.368ns, distribution 0.788ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y571 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.243 1.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X64Y567 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.308 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X64Y567 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.147 1.161 SLICE_X64Y567 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.166 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.166 arrival time 1.382 ------------------------------------------------------------------- slack 0.216 Slack (MET) : 0.216ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.292ns (logic 0.049ns (16.781%) route 0.243ns (83.219%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.308ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.974ns (routing 0.318ns, distribution 0.656ns) Clock Net Delay (Destination): 1.156ns (routing 0.368ns, distribution 0.788ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y571 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.243 1.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X64Y567 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.308 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X64Y567 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.147 1.161 SLICE_X64Y567 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.166 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.166 arrival time 1.382 ------------------------------------------------------------------- slack 0.216 Slack (MET) : 0.216ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.292ns (logic 0.049ns (16.781%) route 0.243ns (83.219%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.308ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.974ns (routing 0.318ns, distribution 0.656ns) Clock Net Delay (Destination): 1.156ns (routing 0.368ns, distribution 0.788ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y571 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.243 1.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X64Y567 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.308 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X64Y567 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.147 1.161 SLICE_X64Y567 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.166 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.166 arrival time 1.382 ------------------------------------------------------------------- slack 0.216 Slack (MET) : 0.216ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.292ns (logic 0.049ns (16.781%) route 0.243ns (83.219%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.308ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.974ns (routing 0.318ns, distribution 0.656ns) Clock Net Delay (Destination): 1.156ns (routing 0.368ns, distribution 0.788ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y571 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.243 1.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X64Y567 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.308 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X64Y567 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.147 1.161 SLICE_X64Y567 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.166 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.166 arrival time 1.382 ------------------------------------------------------------------- slack 0.216 Slack (MET) : 0.216ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns) Data Path Delay: 0.292ns (logic 0.049ns (16.781%) route 0.243ns (83.219%)) Logic Levels: 0 Clock Path Skew: 0.071ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.308ns Source Clock Delay (SCD): 1.090ns Clock Pessimism Removal (CPR): 0.147ns Clock Net Delay (Source): 0.974ns (routing 0.318ns, distribution 0.656ns) Clock Net Delay (Destination): 1.156ns (routing 0.368ns, distribution 0.788ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.974 1.090 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y571 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X65Y571 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.139 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.243 1.382 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X64Y567 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y38 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y221 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.156 1.308 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X64Y567 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.147 1.161 SLICE_X64Y567 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.166 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.166 arrival time 1.382 ------------------------------------------------------------------- slack 0.216 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_38 To Clock: gtwiz_userclk_rx_srcclk_out[0]_38 Setup : 0 Failing Endpoints, Worst Slack 3.630ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.175ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.630ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.659ns (logic 0.365ns (7.834%) route 4.294ns (92.166%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.100ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.191ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.288ns (routing 0.691ns, distribution 1.597ns) Clock Net Delay (Destination): 2.246ns (routing 0.628ns, distribution 1.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.288 2.713 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y597 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y597 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.853 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.463 6.316 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y587 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.541 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 0.831 7.372 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X65Y589 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] SLICE_X65Y589 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/C clock pessimism 0.191 11.131 clock uncertainty -0.035 11.095 SLICE_X65Y589 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.002 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0] ------------------------------------------------------------------- required time 11.002 arrival time -7.372 ------------------------------------------------------------------- slack 3.630 Slack (MET) : 3.653ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.626ns (logic 0.365ns (7.890%) route 4.261ns (92.110%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.612ns = ( 10.929 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.191ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.288ns (routing 0.691ns, distribution 1.597ns) Clock Net Delay (Destination): 2.236ns (routing 0.628ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.288 2.713 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y597 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y597 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.853 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.463 6.316 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y587 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.541 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 0.798 7.339 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X68Y590 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.236 10.929 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] SLICE_X68Y590 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/C clock pessimism 0.191 11.121 clock uncertainty -0.035 11.085 SLICE_X68Y590 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.992 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1] ------------------------------------------------------------------- required time 10.992 arrival time -7.339 ------------------------------------------------------------------- slack 3.653 Slack (MET) : 3.653ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.626ns (logic 0.365ns (7.890%) route 4.261ns (92.110%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.090ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.612ns = ( 10.929 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.191ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.288ns (routing 0.691ns, distribution 1.597ns) Clock Net Delay (Destination): 2.236ns (routing 0.628ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.288 2.713 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y597 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y597 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.853 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.463 6.316 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y587 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.541 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 0.798 7.339 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X68Y590 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.236 10.929 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] SLICE_X68Y590 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C clock pessimism 0.191 11.121 clock uncertainty -0.035 11.085 SLICE_X68Y590 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.992 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7] ------------------------------------------------------------------- required time 10.992 arrival time -7.339 ------------------------------------------------------------------- slack 3.653 Slack (MET) : 3.661ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.616ns (logic 0.365ns (7.907%) route 4.251ns (92.093%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.088ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.610ns = ( 10.927 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.191ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.288ns (routing 0.691ns, distribution 1.597ns) Clock Net Delay (Destination): 2.234ns (routing 0.628ns, distribution 1.606ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.288 2.713 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y597 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y597 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.853 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.463 6.316 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y587 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.541 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 0.788 7.329 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X68Y590 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.234 10.927 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] SLICE_X68Y590 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C clock pessimism 0.191 11.119 clock uncertainty -0.035 11.083 SLICE_X68Y590 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 10.990 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0] ------------------------------------------------------------------- required time 10.990 arrival time -7.329 ------------------------------------------------------------------- slack 3.661 Slack (MET) : 3.661ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.616ns (logic 0.365ns (7.907%) route 4.251ns (92.093%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.088ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.610ns = ( 10.927 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.191ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.288ns (routing 0.691ns, distribution 1.597ns) Clock Net Delay (Destination): 2.234ns (routing 0.628ns, distribution 1.606ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.288 2.713 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y597 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y597 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.853 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.463 6.316 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y587 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.541 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 0.788 7.329 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X68Y590 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.234 10.927 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] SLICE_X68Y590 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C clock pessimism 0.191 11.119 clock uncertainty -0.035 11.083 SLICE_X68Y590 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.990 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6] ------------------------------------------------------------------- required time 10.990 arrival time -7.329 ------------------------------------------------------------------- slack 3.661 Slack (MET) : 3.661ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.616ns (logic 0.365ns (7.907%) route 4.251ns (92.093%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.088ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.610ns = ( 10.927 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.191ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.288ns (routing 0.691ns, distribution 1.597ns) Clock Net Delay (Destination): 2.234ns (routing 0.628ns, distribution 1.606ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.288 2.713 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y597 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y597 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.853 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.463 6.316 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y587 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.541 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 0.788 7.329 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X68Y590 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.234 10.927 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] SLICE_X68Y590 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]/C clock pessimism 0.191 11.119 clock uncertainty -0.035 11.083 SLICE_X68Y590 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.990 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5] ------------------------------------------------------------------- required time 10.990 arrival time -7.329 ------------------------------------------------------------------- slack 3.661 Slack (MET) : 3.693ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.596ns (logic 0.365ns (7.942%) route 4.231ns (92.058%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.100ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.191ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.288ns (routing 0.691ns, distribution 1.597ns) Clock Net Delay (Destination): 2.246ns (routing 0.628ns, distribution 1.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.288 2.713 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y597 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y597 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.853 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.463 6.316 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y587 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.541 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 0.768 7.309 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X65Y590 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] SLICE_X65Y590 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/C clock pessimism 0.191 11.131 clock uncertainty -0.035 11.095 SLICE_X65Y590 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.002 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2] ------------------------------------------------------------------- required time 11.002 arrival time -7.309 ------------------------------------------------------------------- slack 3.693 Slack (MET) : 3.693ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.596ns (logic 0.365ns (7.942%) route 4.231ns (92.058%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.100ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.191ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.288ns (routing 0.691ns, distribution 1.597ns) Clock Net Delay (Destination): 2.246ns (routing 0.628ns, distribution 1.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.288 2.713 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y597 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y597 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.853 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.463 6.316 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y587 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.541 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 0.768 7.309 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X65Y590 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] SLICE_X65Y590 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C clock pessimism 0.191 11.131 clock uncertainty -0.035 11.095 SLICE_X65Y590 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.002 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3] ------------------------------------------------------------------- required time 11.002 arrival time -7.309 ------------------------------------------------------------------- slack 3.693 Slack (MET) : 3.693ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.596ns (logic 0.365ns (7.942%) route 4.231ns (92.058%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.100ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.191ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.288ns (routing 0.691ns, distribution 1.597ns) Clock Net Delay (Destination): 2.246ns (routing 0.628ns, distribution 1.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.288 2.713 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y597 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y597 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.853 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.463 6.316 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y587 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.541 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 0.768 7.309 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X65Y590 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] SLICE_X65Y590 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C clock pessimism 0.191 11.131 clock uncertainty -0.035 11.095 SLICE_X65Y590 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.002 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4] ------------------------------------------------------------------- required time 11.002 arrival time -7.309 ------------------------------------------------------------------- slack 3.693 Slack (MET) : 3.693ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 4.596ns (logic 0.365ns (7.942%) route 4.231ns (92.058%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.100ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.622ns = ( 10.939 - 8.317 ) Source Clock Delay (SCD): 2.713ns Clock Pessimism Removal (CPR): 0.191ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.288ns (routing 0.691ns, distribution 1.597ns) Clock Net Delay (Destination): 2.246ns (routing 0.628ns, distribution 1.618ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.288 2.713 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X10Y597 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X10Y597 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.853 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.463 6.316 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y587 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.225 6.541 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/O net (fo=15, routed) 0.768 7.309 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 SLICE_X65Y590 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.246 10.939 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_9[0] SLICE_X65Y590 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C clock pessimism 0.191 11.131 clock uncertainty -0.035 11.095 SLICE_X65Y590 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.002 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5] ------------------------------------------------------------------- required time 11.002 arrival time -7.309 ------------------------------------------------------------------- slack 3.693 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.175ns (arrival time - required time) Source: SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.250ns (logic 0.048ns (19.200%) route 0.202ns (80.800%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.991ns (routing 0.317ns, distribution 0.674ns) Clock Net Delay (Destination): 1.170ns (routing 0.366ns, distribution 0.804ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.107 SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y587 FDPE r SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y587 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.155 f SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.202 1.357 SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] SLICE_X61Y587 FDCE f SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.170 1.322 SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y587 FDCE r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[20]/C clock pessimism -0.145 1.177 SLICE_X61Y587 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[20] ------------------------------------------------------------------- required time -1.182 arrival time 1.357 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.175ns (arrival time - required time) Source: SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.250ns (logic 0.048ns (19.200%) route 0.202ns (80.800%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.991ns (routing 0.317ns, distribution 0.674ns) Clock Net Delay (Destination): 1.170ns (routing 0.366ns, distribution 0.804ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.107 SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y587 FDPE r SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y587 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.155 f SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.202 1.357 SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] SLICE_X61Y587 FDCE f SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.170 1.322 SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y587 FDCE r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.145 1.177 SLICE_X61Y587 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -1.182 arrival time 1.357 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.175ns (arrival time - required time) Source: SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.250ns (logic 0.048ns (19.200%) route 0.202ns (80.800%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.991ns (routing 0.317ns, distribution 0.674ns) Clock Net Delay (Destination): 1.170ns (routing 0.366ns, distribution 0.804ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.107 SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y587 FDPE r SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y587 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.155 f SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.202 1.357 SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] SLICE_X61Y587 FDCE f SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.170 1.322 SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y587 FDCE r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[22]/C clock pessimism -0.145 1.177 SLICE_X61Y587 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[22] ------------------------------------------------------------------- required time -1.182 arrival time 1.357 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.175ns (arrival time - required time) Source: SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.250ns (logic 0.048ns (19.200%) route 0.202ns (80.800%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.991ns (routing 0.317ns, distribution 0.674ns) Clock Net Delay (Destination): 1.170ns (routing 0.366ns, distribution 0.804ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.107 SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y587 FDPE r SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y587 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.155 f SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.202 1.357 SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] SLICE_X61Y587 FDCE f SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.170 1.322 SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y587 FDCE r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[25]/C clock pessimism -0.145 1.177 SLICE_X61Y587 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[25] ------------------------------------------------------------------- required time -1.182 arrival time 1.357 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.175ns (arrival time - required time) Source: SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.250ns (logic 0.048ns (19.200%) route 0.202ns (80.800%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.991ns (routing 0.317ns, distribution 0.674ns) Clock Net Delay (Destination): 1.170ns (routing 0.366ns, distribution 0.804ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.107 SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y587 FDPE r SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y587 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.155 f SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.202 1.357 SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] SLICE_X61Y587 FDCE f SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.170 1.322 SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y587 FDCE r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[26]/C clock pessimism -0.145 1.177 SLICE_X61Y587 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[26] ------------------------------------------------------------------- required time -1.182 arrival time 1.357 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.175ns (arrival time - required time) Source: SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.250ns (logic 0.048ns (19.200%) route 0.202ns (80.800%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.991ns (routing 0.317ns, distribution 0.674ns) Clock Net Delay (Destination): 1.170ns (routing 0.366ns, distribution 0.804ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.107 SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y587 FDPE r SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y587 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.155 f SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.202 1.357 SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] SLICE_X61Y587 FDCE f SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.170 1.322 SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y587 FDCE r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[31]/C clock pessimism -0.145 1.177 SLICE_X61Y587 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[31] ------------------------------------------------------------------- required time -1.182 arrival time 1.357 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.175ns (arrival time - required time) Source: SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.250ns (logic 0.048ns (19.200%) route 0.202ns (80.800%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.991ns (routing 0.317ns, distribution 0.674ns) Clock Net Delay (Destination): 1.170ns (routing 0.366ns, distribution 0.804ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.991 1.107 SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X65Y587 FDPE r SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y587 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.155 f SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.202 1.357 SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] SLICE_X61Y587 FDCE f SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.170 1.322 SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X61Y587 FDCE r SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[81]/C clock pessimism -0.145 1.177 SLICE_X61Y587 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[81] ------------------------------------------------------------------- required time -1.182 arrival time 1.357 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.175ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.049ns (22.072%) route 0.173ns (77.928%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.330ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.178ns Clock Net Delay (Source): 0.994ns (routing 0.317ns, distribution 0.677ns) Clock Net Delay (Destination): 1.178ns (routing 0.366ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X66Y591 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X66Y591 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.159 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.173 1.332 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X66Y593 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.330 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X66Y593 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24]/C clock pessimism -0.178 1.152 SLICE_X66Y593 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.157 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[24] ------------------------------------------------------------------- required time -1.157 arrival time 1.332 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.185ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.049ns (18.491%) route 0.216ns (81.509%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.330ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.994ns (routing 0.317ns, distribution 0.677ns) Clock Net Delay (Destination): 1.178ns (routing 0.366ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X66Y591 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X66Y591 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.159 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.216 1.375 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X68Y594 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.330 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X68Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[81]/C clock pessimism -0.145 1.185 SLICE_X68Y594 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.190 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[81] ------------------------------------------------------------------- required time -1.190 arrival time 1.375 ------------------------------------------------------------------- slack 0.185 Slack (MET) : 0.185ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.049ns (18.491%) route 0.216ns (81.509%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.330ns Source Clock Delay (SCD): 1.110ns Clock Pessimism Removal (CPR): 0.145ns Clock Net Delay (Source): 0.994ns (routing 0.317ns, distribution 0.677ns) Clock Net Delay (Destination): 1.178ns (routing 0.366ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.994 1.110 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK SLICE_X66Y591 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X66Y591 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.159 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.216 1.375 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X68Y594 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y220 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.330 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK SLICE_X68Y594 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[81]/C clock pessimism -0.145 1.185 SLICE_X68Y594 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.190 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[81] ------------------------------------------------------------------- required time -1.190 arrival time 1.375 ------------------------------------------------------------------- slack 0.185 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_39 To Clock: gtwiz_userclk_rx_srcclk_out[0]_39 Setup : 0 Failing Endpoints, Worst Slack 4.460ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.215ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.460ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.422ns (logic 0.229ns (6.692%) route 3.193ns (93.308%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.680ns = ( 10.997 - 8.317 ) Source Clock Delay (SCD): 3.209ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.784ns (routing 1.110ns, distribution 1.674ns) Clock Net Delay (Destination): 2.304ns (routing 1.013ns, distribution 1.291ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.784 3.209 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y428 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y428 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.349 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.123 5.472 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X33Y421 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.089 5.561 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 1.070 6.631 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X27Y431 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.304 10.997 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X27Y431 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C clock pessimism 0.222 11.219 clock uncertainty -0.035 11.184 SLICE_X27Y431 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.091 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1] ------------------------------------------------------------------- required time 11.091 arrival time -6.631 ------------------------------------------------------------------- slack 4.460 Slack (MET) : 4.489ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.399ns (logic 0.229ns (6.737%) route 3.170ns (93.263%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.301ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.686ns = ( 11.003 - 8.317 ) Source Clock Delay (SCD): 3.209ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.784ns (routing 1.110ns, distribution 1.674ns) Clock Net Delay (Destination): 2.310ns (routing 1.013ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.784 3.209 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y428 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y428 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.349 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.123 5.472 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X33Y421 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.089 5.561 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 1.047 6.608 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X28Y435 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.310 11.003 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X28Y435 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/C clock pessimism 0.222 11.225 clock uncertainty -0.035 11.190 SLICE_X28Y435 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.097 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1] ------------------------------------------------------------------- required time 11.097 arrival time -6.608 ------------------------------------------------------------------- slack 4.489 Slack (MET) : 4.489ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.399ns (logic 0.229ns (6.737%) route 3.170ns (93.263%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.301ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.686ns = ( 11.003 - 8.317 ) Source Clock Delay (SCD): 3.209ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.784ns (routing 1.110ns, distribution 1.674ns) Clock Net Delay (Destination): 2.310ns (routing 1.013ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.784 3.209 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y428 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y428 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.349 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.123 5.472 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X33Y421 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.089 5.561 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 1.047 6.608 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X28Y435 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.310 11.003 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X28Y435 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/C clock pessimism 0.222 11.225 clock uncertainty -0.035 11.190 SLICE_X28Y435 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.097 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2] ------------------------------------------------------------------- required time 11.097 arrival time -6.608 ------------------------------------------------------------------- slack 4.489 Slack (MET) : 4.489ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.399ns (logic 0.229ns (6.737%) route 3.170ns (93.263%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.301ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.686ns = ( 11.003 - 8.317 ) Source Clock Delay (SCD): 3.209ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.784ns (routing 1.110ns, distribution 1.674ns) Clock Net Delay (Destination): 2.310ns (routing 1.013ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.784 3.209 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y428 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y428 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.349 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.123 5.472 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X33Y421 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.089 5.561 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 1.047 6.608 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X28Y435 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.310 11.003 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X28Y435 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C clock pessimism 0.222 11.225 clock uncertainty -0.035 11.190 SLICE_X28Y435 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.097 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3] ------------------------------------------------------------------- required time 11.097 arrival time -6.608 ------------------------------------------------------------------- slack 4.489 Slack (MET) : 4.489ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.399ns (logic 0.229ns (6.737%) route 3.170ns (93.263%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.301ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.686ns = ( 11.003 - 8.317 ) Source Clock Delay (SCD): 3.209ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.784ns (routing 1.110ns, distribution 1.674ns) Clock Net Delay (Destination): 2.310ns (routing 1.013ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.784 3.209 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y428 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y428 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.349 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.123 5.472 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X33Y421 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.089 5.561 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 1.047 6.608 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X28Y435 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.310 11.003 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X28Y435 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/C clock pessimism 0.222 11.225 clock uncertainty -0.035 11.190 SLICE_X28Y435 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.097 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4] ------------------------------------------------------------------- required time 11.097 arrival time -6.608 ------------------------------------------------------------------- slack 4.489 Slack (MET) : 4.534ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.356ns (logic 0.229ns (6.824%) route 3.127ns (93.176%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.299ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.688ns = ( 11.005 - 8.317 ) Source Clock Delay (SCD): 3.209ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.784ns (routing 1.110ns, distribution 1.674ns) Clock Net Delay (Destination): 2.312ns (routing 1.013ns, distribution 1.299ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.784 3.209 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y428 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y428 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.349 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.123 5.472 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X33Y421 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.089 5.561 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 1.004 6.565 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X28Y431 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.312 11.005 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X28Y431 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C clock pessimism 0.222 11.227 clock uncertainty -0.035 11.192 SLICE_X28Y431 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.099 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1] ------------------------------------------------------------------- required time 11.099 arrival time -6.565 ------------------------------------------------------------------- slack 4.534 Slack (MET) : 4.534ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.356ns (logic 0.229ns (6.824%) route 3.127ns (93.176%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.299ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.688ns = ( 11.005 - 8.317 ) Source Clock Delay (SCD): 3.209ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.784ns (routing 1.110ns, distribution 1.674ns) Clock Net Delay (Destination): 2.312ns (routing 1.013ns, distribution 1.299ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.784 3.209 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y428 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y428 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.349 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.123 5.472 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X33Y421 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.089 5.561 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 1.004 6.565 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X28Y431 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.312 11.005 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X28Y431 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C clock pessimism 0.222 11.227 clock uncertainty -0.035 11.192 SLICE_X28Y431 FDCE (Recov_BFF2_SLICEM_C_CLR) -0.093 11.099 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2] ------------------------------------------------------------------- required time 11.099 arrival time -6.565 ------------------------------------------------------------------- slack 4.534 Slack (MET) : 4.534ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.356ns (logic 0.229ns (6.824%) route 3.127ns (93.176%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.299ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.688ns = ( 11.005 - 8.317 ) Source Clock Delay (SCD): 3.209ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.784ns (routing 1.110ns, distribution 1.674ns) Clock Net Delay (Destination): 2.312ns (routing 1.013ns, distribution 1.299ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.784 3.209 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y428 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y428 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.349 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.123 5.472 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X33Y421 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.089 5.561 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 1.004 6.565 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X28Y431 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.312 11.005 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X28Y431 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C clock pessimism 0.222 11.227 clock uncertainty -0.035 11.192 SLICE_X28Y431 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.099 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3] ------------------------------------------------------------------- required time 11.099 arrival time -6.565 ------------------------------------------------------------------- slack 4.534 Slack (MET) : 4.539ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.349ns (logic 0.229ns (6.838%) route 3.120ns (93.162%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.301ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.686ns = ( 11.003 - 8.317 ) Source Clock Delay (SCD): 3.209ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.784ns (routing 1.110ns, distribution 1.674ns) Clock Net Delay (Destination): 2.310ns (routing 1.013ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.784 3.209 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y428 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y428 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.349 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.123 5.472 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X33Y421 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.089 5.561 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 0.997 6.558 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X28Y431 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.310 11.003 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X28Y431 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C clock pessimism 0.222 11.225 clock uncertainty -0.035 11.190 SLICE_X28Y431 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.097 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0] ------------------------------------------------------------------- required time 11.097 arrival time -6.558 ------------------------------------------------------------------- slack 4.539 Slack (MET) : 4.539ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 3.349ns (logic 0.229ns (6.838%) route 3.120ns (93.162%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.301ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.686ns = ( 11.003 - 8.317 ) Source Clock Delay (SCD): 3.209ns Clock Pessimism Removal (CPR): 0.222ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.784ns (routing 1.110ns, distribution 1.674ns) Clock Net Delay (Destination): 2.310ns (routing 1.013ns, distribution 1.297ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.784 3.209 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X7Y428 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X7Y428 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 3.349 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.123 5.472 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X33Y421 LUT3 (Prop_B6LUT_SLICEL_I0_O) 0.089 5.561 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/O net (fo=15, routed) 0.997 6.558 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1]0 SLICE_X28Y431 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 2.310 11.003 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] SLICE_X28Y431 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C clock pessimism 0.222 11.225 clock uncertainty -0.035 11.190 SLICE_X28Y431 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.097 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4] ------------------------------------------------------------------- required time 11.097 arrival time -6.558 ------------------------------------------------------------------- slack 4.539 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.215ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.048ns (18.605%) route 0.210ns (81.395%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.023ns (routing 0.483ns, distribution 0.540ns) Clock Net Delay (Destination): 1.206ns (routing 0.550ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y430 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y430 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.187 f SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.210 1.397 SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] SLICE_X31Y434 FDCE f SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.206 1.358 SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X31Y434 FDCE r SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[16]/C clock pessimism -0.181 1.177 SLICE_X31Y434 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[16] ------------------------------------------------------------------- required time -1.182 arrival time 1.397 ------------------------------------------------------------------- slack 0.215 Slack (MET) : 0.215ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.048ns (18.605%) route 0.210ns (81.395%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.023ns (routing 0.483ns, distribution 0.540ns) Clock Net Delay (Destination): 1.206ns (routing 0.550ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y430 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y430 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.187 f SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.210 1.397 SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] SLICE_X31Y434 FDCE f SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.206 1.358 SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X31Y434 FDCE r SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism -0.181 1.177 SLICE_X31Y434 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time -1.182 arrival time 1.397 ------------------------------------------------------------------- slack 0.215 Slack (MET) : 0.215ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.048ns (18.605%) route 0.210ns (81.395%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.023ns (routing 0.483ns, distribution 0.540ns) Clock Net Delay (Destination): 1.206ns (routing 0.550ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y430 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y430 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.187 f SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.210 1.397 SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] SLICE_X31Y434 FDCE f SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.206 1.358 SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X31Y434 FDCE r SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[24]/C clock pessimism -0.181 1.177 SLICE_X31Y434 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[24] ------------------------------------------------------------------- required time -1.182 arrival time 1.397 ------------------------------------------------------------------- slack 0.215 Slack (MET) : 0.215ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.258ns (logic 0.048ns (18.605%) route 0.210ns (81.395%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.358ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.181ns Clock Net Delay (Source): 1.023ns (routing 0.483ns, distribution 0.540ns) Clock Net Delay (Destination): 1.206ns (routing 0.550ns, distribution 0.656ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y430 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y430 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.187 f SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.210 1.397 SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] SLICE_X31Y434 FDCE f SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.206 1.358 SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X31Y434 FDCE r SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[30]/C clock pessimism -0.181 1.177 SLICE_X31Y434 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.182 SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[30] ------------------------------------------------------------------- required time -1.182 arrival time 1.397 ------------------------------------------------------------------- slack 0.215 Slack (MET) : 0.228ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.349ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.023ns (routing 0.483ns, distribution 0.540ns) Clock Net Delay (Destination): 1.197ns (routing 0.550ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y430 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y430 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.187 f SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.247 1.434 SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] SLICE_X28Y436 FDCE f SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.197 1.349 SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X28Y436 FDCE r SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.148 1.201 SLICE_X28Y436 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.206 SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.206 arrival time 1.434 ------------------------------------------------------------------- slack 0.228 Slack (MET) : 0.228ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.349ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.023ns (routing 0.483ns, distribution 0.540ns) Clock Net Delay (Destination): 1.197ns (routing 0.550ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y430 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y430 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.187 f SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.247 1.434 SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] SLICE_X28Y436 FDCE f SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.197 1.349 SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X28Y436 FDCE r SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.148 1.201 SLICE_X28Y436 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.206 SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -1.206 arrival time 1.434 ------------------------------------------------------------------- slack 0.228 Slack (MET) : 0.228ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.349ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.023ns (routing 0.483ns, distribution 0.540ns) Clock Net Delay (Destination): 1.197ns (routing 0.550ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y430 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y430 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.187 f SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.247 1.434 SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] SLICE_X28Y436 FDCE f SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.197 1.349 SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X28Y436 FDCE r SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[4]/C clock pessimism -0.148 1.201 SLICE_X28Y436 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.206 SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[4] ------------------------------------------------------------------- required time -1.206 arrival time 1.434 ------------------------------------------------------------------- slack 0.228 Slack (MET) : 0.228ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.349ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.023ns (routing 0.483ns, distribution 0.540ns) Clock Net Delay (Destination): 1.197ns (routing 0.550ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y430 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y430 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.187 f SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.247 1.434 SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] SLICE_X28Y436 FDCE f SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.197 1.349 SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X28Y436 FDCE r SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[6]/C clock pessimism -0.148 1.201 SLICE_X28Y436 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 1.206 SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[6] ------------------------------------------------------------------- required time -1.206 arrival time 1.434 ------------------------------------------------------------------- slack 0.228 Slack (MET) : 0.228ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.349ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.023ns (routing 0.483ns, distribution 0.540ns) Clock Net Delay (Destination): 1.197ns (routing 0.550ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y430 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y430 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.187 f SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.247 1.434 SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] SLICE_X28Y436 FDCE f SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.197 1.349 SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X28Y436 FDCE r SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]/C clock pessimism -0.148 1.201 SLICE_X28Y436 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.206 SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82] ------------------------------------------------------------------- required time -1.206 arrival time 1.434 ------------------------------------------------------------------- slack 0.228 Slack (MET) : 0.228ns (arrival time - required time) Source: SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns) Data Path Delay: 0.295ns (logic 0.048ns (16.271%) route 0.247ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.349ns Source Clock Delay (SCD): 1.139ns Clock Pessimism Removal (CPR): 0.148ns Clock Net Delay (Source): 1.023ns (routing 0.483ns, distribution 0.540ns) Clock Net Delay (Destination): 1.197ns (routing 0.550ns, distribution 0.647ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.023 1.139 SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y430 FDPE r SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y430 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.187 f SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.247 1.434 SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] SLICE_X28Y436 FDCE f SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y29 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y172 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y6 (CLOCK_ROOT) net (fo=674, routed) 1.197 1.349 SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X28Y436 FDCE r SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[83]/C clock pessimism -0.148 1.201 SLICE_X28Y436 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.206 SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[83] ------------------------------------------------------------------- required time -1.206 arrival time 1.434 ------------------------------------------------------------------- slack 0.228 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_4 To Clock: gtwiz_userclk_rx_srcclk_out[0]_4 Setup : 0 Failing Endpoints, Worst Slack 3.966ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.112ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.966ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.582ns (logic 0.231ns (6.449%) route 3.351ns (93.551%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.641ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.687ns = ( 11.004 - 8.317 ) Source Clock Delay (SCD): 3.585ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.110ns (routing 1.094ns, distribution 2.016ns) Clock Net Delay (Destination): 2.289ns (routing 0.997ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.110 3.585 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y90 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y90 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.724 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.742 6.466 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y92 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.558 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.609 7.167 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y95 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.289 11.004 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y95 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/C clock pessimism 0.257 11.261 clock uncertainty -0.035 11.226 SLICE_X81Y95 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 11.133 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2] ------------------------------------------------------------------- required time 11.133 arrival time -7.167 ------------------------------------------------------------------- slack 3.966 Slack (MET) : 3.966ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.582ns (logic 0.231ns (6.449%) route 3.351ns (93.551%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.641ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.687ns = ( 11.004 - 8.317 ) Source Clock Delay (SCD): 3.585ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.110ns (routing 1.094ns, distribution 2.016ns) Clock Net Delay (Destination): 2.289ns (routing 0.997ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.110 3.585 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y90 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y90 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.724 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.742 6.466 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y92 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.558 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.609 7.167 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y95 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.289 11.004 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y95 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/C clock pessimism 0.257 11.261 clock uncertainty -0.035 11.226 SLICE_X81Y95 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.133 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6] ------------------------------------------------------------------- required time 11.133 arrival time -7.167 ------------------------------------------------------------------- slack 3.966 Slack (MET) : 3.966ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.582ns (logic 0.231ns (6.449%) route 3.351ns (93.551%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.641ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.687ns = ( 11.004 - 8.317 ) Source Clock Delay (SCD): 3.585ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.110ns (routing 1.094ns, distribution 2.016ns) Clock Net Delay (Destination): 2.289ns (routing 0.997ns, distribution 1.292ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.110 3.585 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y90 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y90 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.724 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.742 6.466 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y92 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.558 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.609 7.167 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y95 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.289 11.004 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y95 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/C clock pessimism 0.257 11.261 clock uncertainty -0.035 11.226 SLICE_X81Y95 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.133 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7] ------------------------------------------------------------------- required time 11.133 arrival time -7.167 ------------------------------------------------------------------- slack 3.966 Slack (MET) : 3.974ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.572ns (logic 0.231ns (6.467%) route 3.341ns (93.533%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.643ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.685ns = ( 11.002 - 8.317 ) Source Clock Delay (SCD): 3.585ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.110ns (routing 1.094ns, distribution 2.016ns) Clock Net Delay (Destination): 2.287ns (routing 0.997ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.110 3.585 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y90 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y90 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.724 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.742 6.466 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y92 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.558 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.599 7.157 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y95 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.287 11.002 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y95 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/C clock pessimism 0.257 11.259 clock uncertainty -0.035 11.224 SLICE_X81Y95 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3] ------------------------------------------------------------------- required time 11.131 arrival time -7.157 ------------------------------------------------------------------- slack 3.974 Slack (MET) : 3.974ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.572ns (logic 0.231ns (6.467%) route 3.341ns (93.533%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.643ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.685ns = ( 11.002 - 8.317 ) Source Clock Delay (SCD): 3.585ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.110ns (routing 1.094ns, distribution 2.016ns) Clock Net Delay (Destination): 2.287ns (routing 0.997ns, distribution 1.290ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.110 3.585 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y90 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y90 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.724 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.742 6.466 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y92 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.558 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.599 7.157 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y95 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.287 11.002 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y95 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/C clock pessimism 0.257 11.259 clock uncertainty -0.035 11.224 SLICE_X81Y95 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.131 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5] ------------------------------------------------------------------- required time 11.131 arrival time -7.157 ------------------------------------------------------------------- slack 3.974 Slack (MET) : 3.981ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.564ns (logic 0.231ns (6.481%) route 3.333ns (93.519%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.644ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.684ns = ( 11.001 - 8.317 ) Source Clock Delay (SCD): 3.585ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.110ns (routing 1.094ns, distribution 2.016ns) Clock Net Delay (Destination): 2.286ns (routing 0.997ns, distribution 1.289ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.110 3.585 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y90 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y90 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.724 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.742 6.466 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y92 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.558 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.591 7.149 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y93 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.286 11.001 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y93 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C clock pessimism 0.257 11.258 clock uncertainty -0.035 11.223 SLICE_X81Y93 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.130 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2] ------------------------------------------------------------------- required time 11.130 arrival time -7.149 ------------------------------------------------------------------- slack 3.981 Slack (MET) : 3.981ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.564ns (logic 0.231ns (6.481%) route 3.333ns (93.519%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.644ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.684ns = ( 11.001 - 8.317 ) Source Clock Delay (SCD): 3.585ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.110ns (routing 1.094ns, distribution 2.016ns) Clock Net Delay (Destination): 2.286ns (routing 0.997ns, distribution 1.289ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.110 3.585 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y90 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y90 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.724 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.742 6.466 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y92 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.558 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.591 7.149 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y93 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.286 11.001 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y93 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C clock pessimism 0.257 11.258 clock uncertainty -0.035 11.223 SLICE_X81Y93 FDCE (Recov_BFF2_SLICEL_C_CLR) -0.093 11.130 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0] ------------------------------------------------------------------- required time 11.130 arrival time -7.149 ------------------------------------------------------------------- slack 3.981 Slack (MET) : 3.981ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.564ns (logic 0.231ns (6.481%) route 3.333ns (93.519%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.644ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.684ns = ( 11.001 - 8.317 ) Source Clock Delay (SCD): 3.585ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.110ns (routing 1.094ns, distribution 2.016ns) Clock Net Delay (Destination): 2.286ns (routing 0.997ns, distribution 1.289ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.110 3.585 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y90 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y90 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.724 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.742 6.466 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y92 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.558 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.591 7.149 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y93 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.286 11.001 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y93 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/C clock pessimism 0.257 11.258 clock uncertainty -0.035 11.223 SLICE_X81Y93 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.130 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5] ------------------------------------------------------------------- required time 11.130 arrival time -7.149 ------------------------------------------------------------------- slack 3.981 Slack (MET) : 3.989ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.554ns (logic 0.231ns (6.500%) route 3.323ns (93.500%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.646ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.682ns = ( 10.999 - 8.317 ) Source Clock Delay (SCD): 3.585ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.110ns (routing 1.094ns, distribution 2.016ns) Clock Net Delay (Destination): 2.284ns (routing 0.997ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.110 3.585 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y90 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y90 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.724 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.742 6.466 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y92 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.558 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.581 7.139 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y93 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.284 10.999 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y93 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/C clock pessimism 0.257 11.256 clock uncertainty -0.035 11.221 SLICE_X81Y93 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.128 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1] ------------------------------------------------------------------- required time 11.128 arrival time -7.139 ------------------------------------------------------------------- slack 3.989 Slack (MET) : 3.989ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 3.554ns (logic 0.231ns (6.500%) route 3.323ns (93.500%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.646ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.682ns = ( 10.999 - 8.317 ) Source Clock Delay (SCD): 3.585ns Clock Pessimism Removal (CPR): 0.257ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.110ns (routing 1.094ns, distribution 2.016ns) Clock Net Delay (Destination): 2.284ns (routing 0.997ns, distribution 1.287ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.110 3.585 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X132Y90 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X132Y90 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.724 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.742 6.466 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X82Y92 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.092 6.558 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/O net (fo=15, routed) 0.581 7.139 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X81Y93 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.284 10.999 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] SLICE_X81Y93 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/C clock pessimism 0.257 11.256 clock uncertainty -0.035 11.221 SLICE_X81Y93 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.128 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4] ------------------------------------------------------------------- required time 11.128 arrival time -7.139 ------------------------------------------------------------------- slack 3.989 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.112ns (arrival time - required time) Source: SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.196ns (logic 0.048ns (24.490%) route 0.148ns (75.510%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.344ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.997ns (routing 0.466ns, distribution 0.531ns) Clock Net Delay (Destination): 1.179ns (routing 0.526ns, distribution 0.653ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y93 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y93 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.148 1.311 SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y93 FDCE f SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.179 1.344 SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y93 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[83]/C clock pessimism -0.150 1.194 SLICE_X76Y93 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.199 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[83] ------------------------------------------------------------------- required time -1.199 arrival time 1.311 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.148ns (arrival time - required time) Source: SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.997ns (routing 0.466ns, distribution 0.531ns) Clock Net Delay (Destination): 1.178ns (routing 0.526ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y93 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y93 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.183 1.346 SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y92 FDCE f SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.343 SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y92 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]/C clock pessimism -0.150 1.193 SLICE_X76Y92 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.198 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19] ------------------------------------------------------------------- required time -1.198 arrival time 1.346 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.997ns (routing 0.466ns, distribution 0.531ns) Clock Net Delay (Destination): 1.178ns (routing 0.526ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y93 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y93 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.183 1.346 SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y92 FDCE f SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.343 SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y92 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.150 1.193 SLICE_X76Y92 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.198 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -1.198 arrival time 1.346 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.997ns (routing 0.466ns, distribution 0.531ns) Clock Net Delay (Destination): 1.178ns (routing 0.526ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y93 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y93 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.183 1.346 SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y92 FDCE f SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.343 SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y92 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.150 1.193 SLICE_X76Y92 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.198 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -1.198 arrival time 1.346 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.997ns (routing 0.466ns, distribution 0.531ns) Clock Net Delay (Destination): 1.178ns (routing 0.526ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y93 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y93 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.183 1.346 SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y92 FDCE f SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.343 SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y92 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]/C clock pessimism -0.150 1.193 SLICE_X76Y92 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.198 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25] ------------------------------------------------------------------- required time -1.198 arrival time 1.346 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.997ns (routing 0.466ns, distribution 0.531ns) Clock Net Delay (Destination): 1.178ns (routing 0.526ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y93 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y93 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.183 1.346 SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y92 FDCE f SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.343 SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y92 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]/C clock pessimism -0.150 1.193 SLICE_X76Y92 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.198 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27] ------------------------------------------------------------------- required time -1.198 arrival time 1.346 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.997ns (routing 0.466ns, distribution 0.531ns) Clock Net Delay (Destination): 1.178ns (routing 0.526ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y93 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y93 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.183 1.346 SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y92 FDCE f SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.343 SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y92 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.150 1.193 SLICE_X76Y92 FDCE (Remov_CFF2_SLICEM_C_CLR) 0.005 1.198 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -1.198 arrival time 1.346 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.997ns (routing 0.466ns, distribution 0.531ns) Clock Net Delay (Destination): 1.178ns (routing 0.526ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y93 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y93 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.183 1.346 SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y92 FDCE f SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.343 SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y92 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[29]/C clock pessimism -0.150 1.193 SLICE_X76Y92 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.198 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[29] ------------------------------------------------------------------- required time -1.198 arrival time 1.346 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.048ns (20.779%) route 0.183ns (79.221%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.343ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.997ns (routing 0.466ns, distribution 0.531ns) Clock Net Delay (Destination): 1.178ns (routing 0.526ns, distribution 0.652ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y93 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y93 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.183 1.346 SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y92 FDCE f SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.178 1.343 SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y92 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[31]/C clock pessimism -0.150 1.193 SLICE_X76Y92 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.198 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[31] ------------------------------------------------------------------- required time -1.198 arrival time 1.346 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.153ns (arrival time - required time) Source: SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.048ns (20.426%) route 0.187ns (79.574%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.115ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 0.997ns (routing 0.466ns, distribution 0.531ns) Clock Net Delay (Destination): 1.177ns (routing 0.526ns, distribution 0.651ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 0.997 1.115 SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X75Y93 FDPE r SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y93 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.163 f SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.187 1.350 SFP_GEN[2].ngCCM_gbt/sync_m_reg[3][0] SLICE_X77Y93 FDCE f SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y6 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y47 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.177 1.342 SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y93 FDCE r SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism -0.150 1.192 SLICE_X77Y93 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.197 SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time -1.197 arrival time 1.350 ------------------------------------------------------------------- slack 0.153 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_40 To Clock: gtwiz_userclk_rx_srcclk_out[0]_40 Setup : 0 Failing Endpoints, Worst Slack 4.733ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.201ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.733ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.167ns (logic 0.288ns (9.094%) route 2.879ns (90.906%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.286ns = ( 10.603 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.910ns (routing 0.636ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.817 4.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X34Y445 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 4.868 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/O net (fo=15, routed) 1.062 5.930 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X33Y458 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.910 10.603 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X33Y458 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C clock pessimism 0.188 10.791 clock uncertainty -0.035 10.756 SLICE_X33Y458 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.663 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1] ------------------------------------------------------------------- required time 10.663 arrival time -5.930 ------------------------------------------------------------------- slack 4.733 Slack (MET) : 4.733ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.167ns (logic 0.288ns (9.094%) route 2.879ns (90.906%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.286ns = ( 10.603 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.910ns (routing 0.636ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.817 4.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X34Y445 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 4.868 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/O net (fo=15, routed) 1.062 5.930 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X33Y458 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.910 10.603 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X33Y458 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/C clock pessimism 0.188 10.791 clock uncertainty -0.035 10.756 SLICE_X33Y458 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.663 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2] ------------------------------------------------------------------- required time 10.663 arrival time -5.930 ------------------------------------------------------------------- slack 4.733 Slack (MET) : 4.733ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.167ns (logic 0.288ns (9.094%) route 2.879ns (90.906%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.286ns = ( 10.603 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.910ns (routing 0.636ns, distribution 1.274ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.817 4.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X34Y445 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 4.868 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/O net (fo=15, routed) 1.062 5.930 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X33Y458 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.910 10.603 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X33Y458 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C clock pessimism 0.188 10.791 clock uncertainty -0.035 10.756 SLICE_X33Y458 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.663 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4] ------------------------------------------------------------------- required time 10.663 arrival time -5.930 ------------------------------------------------------------------- slack 4.733 Slack (MET) : 4.741ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.157ns (logic 0.288ns (9.123%) route 2.869ns (90.877%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.291ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.284ns = ( 10.601 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.908ns (routing 0.636ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.817 4.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X34Y445 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 4.868 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/O net (fo=15, routed) 1.052 5.920 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X33Y458 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.908 10.601 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X33Y458 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/C clock pessimism 0.188 10.789 clock uncertainty -0.035 10.754 SLICE_X33Y458 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.661 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1] ------------------------------------------------------------------- required time 10.661 arrival time -5.920 ------------------------------------------------------------------- slack 4.741 Slack (MET) : 4.741ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.157ns (logic 0.288ns (9.123%) route 2.869ns (90.877%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.291ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.284ns = ( 10.601 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.908ns (routing 0.636ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.817 4.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X34Y445 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 4.868 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/O net (fo=15, routed) 1.052 5.920 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X33Y458 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.908 10.601 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X33Y458 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/C clock pessimism 0.188 10.789 clock uncertainty -0.035 10.754 SLICE_X33Y458 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 10.661 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4] ------------------------------------------------------------------- required time 10.661 arrival time -5.920 ------------------------------------------------------------------- slack 4.741 Slack (MET) : 4.741ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.157ns (logic 0.288ns (9.123%) route 2.869ns (90.877%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.291ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.284ns = ( 10.601 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.908ns (routing 0.636ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.817 4.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X34Y445 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 4.868 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/O net (fo=15, routed) 1.052 5.920 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X33Y458 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.908 10.601 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X33Y458 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/C clock pessimism 0.188 10.789 clock uncertainty -0.035 10.754 SLICE_X33Y458 FDCE (Recov_FFF_SLICEL_C_CLR) -0.093 10.661 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5] ------------------------------------------------------------------- required time 10.661 arrival time -5.920 ------------------------------------------------------------------- slack 4.741 Slack (MET) : 4.741ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.157ns (logic 0.288ns (9.123%) route 2.869ns (90.877%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.291ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.284ns = ( 10.601 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.908ns (routing 0.636ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.817 4.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X34Y445 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 4.868 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/O net (fo=15, routed) 1.052 5.920 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X33Y458 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.908 10.601 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X33Y458 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C clock pessimism 0.188 10.789 clock uncertainty -0.035 10.754 SLICE_X33Y458 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.661 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] ------------------------------------------------------------------- required time 10.661 arrival time -5.920 ------------------------------------------------------------------- slack 4.741 Slack (MET) : 4.741ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.157ns (logic 0.288ns (9.123%) route 2.869ns (90.877%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.291ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.284ns = ( 10.601 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.908ns (routing 0.636ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.817 4.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X34Y445 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 4.868 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/O net (fo=15, routed) 1.052 5.920 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X33Y458 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.908 10.601 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X33Y458 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C clock pessimism 0.188 10.789 clock uncertainty -0.035 10.754 SLICE_X33Y458 FDCE (Recov_GFF2_SLICEL_C_CLR) -0.093 10.661 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3] ------------------------------------------------------------------- required time 10.661 arrival time -5.920 ------------------------------------------------------------------- slack 4.741 Slack (MET) : 4.741ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.157ns (logic 0.288ns (9.123%) route 2.869ns (90.877%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.291ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.284ns = ( 10.601 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.908ns (routing 0.636ns, distribution 1.272ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.817 4.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X34Y445 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 4.868 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/O net (fo=15, routed) 1.052 5.920 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X33Y458 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.908 10.601 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X33Y458 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/C clock pessimism 0.188 10.789 clock uncertainty -0.035 10.754 SLICE_X33Y458 FDCE (Recov_FFF2_SLICEL_C_CLR) -0.093 10.661 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5] ------------------------------------------------------------------- required time 10.661 arrival time -5.920 ------------------------------------------------------------------- slack 4.741 Slack (MET) : 4.807ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 3.092ns (logic 0.288ns (9.314%) route 2.804ns (90.686%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.285ns = ( 10.602 - 8.317 ) Source Clock Delay (SCD): 2.763ns Clock Pessimism Removal (CPR): 0.188ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.338ns (routing 0.699ns, distribution 1.639ns) Clock Net Delay (Destination): 1.909ns (routing 0.636ns, distribution 1.273ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.338 2.763 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X5Y434 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X5Y434 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.902 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.817 4.719 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X34Y445 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.149 4.868 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2/O net (fo=15, routed) 0.987 5.855 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2]0 SLICE_X33Y457 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.909 10.602 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] SLICE_X33Y457 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/C clock pessimism 0.188 10.790 clock uncertainty -0.035 10.755 SLICE_X33Y457 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.662 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3] ------------------------------------------------------------------- required time 10.662 arrival time -5.855 ------------------------------------------------------------------- slack 4.807 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.201ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.259ns (logic 0.049ns (18.919%) route 0.210ns (81.081%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.151ns Source Clock Delay (SCD): 0.938ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.822ns (routing 0.319ns, distribution 0.503ns) Clock Net Delay (Destination): 0.999ns (routing 0.369ns, distribution 0.630ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.822 0.938 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK SLICE_X31Y460 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y460 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.987 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.210 1.197 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X32Y461 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.999 1.151 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X32Y461 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.160 0.991 SLICE_X32Y461 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 0.996 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.996 arrival time 1.197 ------------------------------------------------------------------- slack 0.201 Slack (MET) : 0.209ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.048ns (16.327%) route 0.246ns (83.673%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.834ns (routing 0.319ns, distribution 0.515ns) Clock Net Delay (Destination): 1.008ns (routing 0.369ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.834 0.950 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X31Y466 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y466 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 0.998 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.246 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X33Y467 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.160 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X33Y467 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.130 1.030 SLICE_X33Y467 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.035 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -1.035 arrival time 1.244 ------------------------------------------------------------------- slack 0.209 Slack (MET) : 0.209ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.048ns (16.327%) route 0.246ns (83.673%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.834ns (routing 0.319ns, distribution 0.515ns) Clock Net Delay (Destination): 1.008ns (routing 0.369ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.834 0.950 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X31Y466 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y466 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 0.998 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.246 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X33Y467 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.160 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X33Y467 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.130 1.030 SLICE_X33Y467 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.035 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -1.035 arrival time 1.244 ------------------------------------------------------------------- slack 0.209 Slack (MET) : 0.209ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.048ns (16.327%) route 0.246ns (83.673%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.834ns (routing 0.319ns, distribution 0.515ns) Clock Net Delay (Destination): 1.008ns (routing 0.369ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.834 0.950 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X31Y466 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y466 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 0.998 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.246 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X33Y467 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.160 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X33Y467 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.130 1.030 SLICE_X33Y467 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.035 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.035 arrival time 1.244 ------------------------------------------------------------------- slack 0.209 Slack (MET) : 0.209ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.048ns (16.327%) route 0.246ns (83.673%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.834ns (routing 0.319ns, distribution 0.515ns) Clock Net Delay (Destination): 1.008ns (routing 0.369ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.834 0.950 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X31Y466 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y466 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 0.998 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.246 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X33Y467 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.160 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X33Y467 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.130 1.030 SLICE_X33Y467 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.035 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.035 arrival time 1.244 ------------------------------------------------------------------- slack 0.209 Slack (MET) : 0.209ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.048ns (16.327%) route 0.246ns (83.673%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.834ns (routing 0.319ns, distribution 0.515ns) Clock Net Delay (Destination): 1.008ns (routing 0.369ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.834 0.950 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X31Y466 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y466 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 0.998 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.246 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X33Y467 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.160 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X33Y467 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.130 1.030 SLICE_X33Y467 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.035 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -1.035 arrival time 1.244 ------------------------------------------------------------------- slack 0.209 Slack (MET) : 0.209ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.048ns (16.327%) route 0.246ns (83.673%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.834ns (routing 0.319ns, distribution 0.515ns) Clock Net Delay (Destination): 1.008ns (routing 0.369ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.834 0.950 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X31Y466 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y466 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 0.998 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.246 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X33Y467 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.160 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X33Y467 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.130 1.030 SLICE_X33Y467 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 1.035 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.035 arrival time 1.244 ------------------------------------------------------------------- slack 0.209 Slack (MET) : 0.209ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.048ns (16.327%) route 0.246ns (83.673%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.160ns Source Clock Delay (SCD): 0.950ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.834ns (routing 0.319ns, distribution 0.515ns) Clock Net Delay (Destination): 1.008ns (routing 0.369ns, distribution 0.639ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.834 0.950 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X31Y466 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y466 FDCE (Prop_HFF2_SLICEM_C_Q) 0.048 0.998 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.246 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X33Y467 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.008 1.160 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X33Y467 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.130 1.030 SLICE_X33Y467 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.035 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.035 arrival time 1.244 ------------------------------------------------------------------- slack 0.209 Slack (MET) : 0.221ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.300ns (logic 0.048ns (16.000%) route 0.252ns (84.000%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.159ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.839ns (routing 0.319ns, distribution 0.520ns) Clock Net Delay (Destination): 1.007ns (routing 0.369ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.839 0.955 SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y470 FDPE r SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y470 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.003 f SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.252 1.255 SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] SLICE_X32Y468 FDCE f SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.159 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y468 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.130 1.029 SLICE_X32Y468 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.034 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.034 arrival time 1.255 ------------------------------------------------------------------- slack 0.221 Slack (MET) : 0.221ns (arrival time - required time) Source: SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns) Data Path Delay: 0.300ns (logic 0.048ns (16.000%) route 0.252ns (84.000%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.159ns Source Clock Delay (SCD): 0.955ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.839ns (routing 0.319ns, distribution 0.520ns) Clock Net Delay (Destination): 1.007ns (routing 0.369ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.839 0.955 SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X34Y470 FDPE r SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y470 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.003 f SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.252 1.255 SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] SLICE_X32Y468 FDCE f SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y30 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y173 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.159 SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X32Y468 FDCE r SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.130 1.029 SLICE_X32Y468 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.034 SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -1.034 arrival time 1.255 ------------------------------------------------------------------- slack 0.221 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_41 To Clock: gtwiz_userclk_rx_srcclk_out[0]_41 Setup : 0 Failing Endpoints, Worst Slack 3.911ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.158ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.911ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.018ns (logic 0.286ns (7.118%) route 3.732ns (92.882%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.297ns = ( 10.614 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.921ns (routing 0.603ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.925 5.807 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y440 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.147 5.954 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.807 6.761 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X41Y445 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.921 10.614 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X41Y445 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/C clock pessimism 0.186 10.801 clock uncertainty -0.035 10.765 SLICE_X41Y445 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.672 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1] ------------------------------------------------------------------- required time 10.672 arrival time -6.761 ------------------------------------------------------------------- slack 3.911 Slack (MET) : 3.911ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.018ns (logic 0.286ns (7.118%) route 3.732ns (92.882%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.297ns = ( 10.614 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.921ns (routing 0.603ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.925 5.807 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y440 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.147 5.954 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.807 6.761 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X41Y445 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.921 10.614 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X41Y445 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/C clock pessimism 0.186 10.801 clock uncertainty -0.035 10.765 SLICE_X41Y445 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.672 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2] ------------------------------------------------------------------- required time 10.672 arrival time -6.761 ------------------------------------------------------------------- slack 3.911 Slack (MET) : 3.911ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.018ns (logic 0.286ns (7.118%) route 3.732ns (92.882%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.297ns = ( 10.614 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.921ns (routing 0.603ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.925 5.807 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y440 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.147 5.954 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.807 6.761 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X41Y445 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.921 10.614 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X41Y445 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C clock pessimism 0.186 10.801 clock uncertainty -0.035 10.765 SLICE_X41Y445 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.672 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3] ------------------------------------------------------------------- required time 10.672 arrival time -6.761 ------------------------------------------------------------------- slack 3.911 Slack (MET) : 3.911ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 4.018ns (logic 0.286ns (7.118%) route 3.732ns (92.882%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.297ns = ( 10.614 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.921ns (routing 0.603ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.925 5.807 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y440 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.147 5.954 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.807 6.761 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X41Y445 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.921 10.614 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X41Y445 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/C clock pessimism 0.186 10.801 clock uncertainty -0.035 10.765 SLICE_X41Y445 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.672 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4] ------------------------------------------------------------------- required time 10.672 arrival time -6.761 ------------------------------------------------------------------- slack 3.911 Slack (MET) : 4.095ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 3.840ns (logic 0.286ns (7.448%) route 3.554ns (92.552%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.254ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.303ns = ( 10.620 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.927ns (routing 0.603ns, distribution 1.324ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.925 5.807 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y440 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.147 5.954 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.629 6.583 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X41Y440 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.927 10.620 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X41Y440 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/C clock pessimism 0.186 10.807 clock uncertainty -0.035 10.771 SLICE_X41Y440 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 10.678 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5] ------------------------------------------------------------------- required time 10.678 arrival time -6.583 ------------------------------------------------------------------- slack 4.095 Slack (MET) : 4.190ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 3.746ns (logic 0.286ns (7.635%) route 3.460ns (92.365%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.253ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.304ns = ( 10.621 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.928ns (routing 0.603ns, distribution 1.325ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.925 5.807 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y440 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.147 5.954 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.535 6.489 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X42Y443 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.928 10.621 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X42Y443 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/C clock pessimism 0.186 10.808 clock uncertainty -0.035 10.772 SLICE_X42Y443 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.679 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0] ------------------------------------------------------------------- required time 10.679 arrival time -6.489 ------------------------------------------------------------------- slack 4.190 Slack (MET) : 4.202ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 3.737ns (logic 0.286ns (7.653%) route 3.451ns (92.347%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.250ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.931ns (routing 0.603ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.925 5.807 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y440 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.147 5.954 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.526 6.480 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X44Y442 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.624 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X44Y442 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C clock pessimism 0.186 10.811 clock uncertainty -0.035 10.775 SLICE_X44Y442 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.682 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3] ------------------------------------------------------------------- required time 10.682 arrival time -6.480 ------------------------------------------------------------------- slack 4.202 Slack (MET) : 4.202ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 3.737ns (logic 0.286ns (7.653%) route 3.451ns (92.347%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.250ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.307ns = ( 10.624 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.931ns (routing 0.603ns, distribution 1.328ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.925 5.807 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y440 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.147 5.954 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.526 6.480 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X44Y442 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.931 10.624 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X44Y442 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C clock pessimism 0.186 10.811 clock uncertainty -0.035 10.775 SLICE_X44Y442 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.682 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4] ------------------------------------------------------------------- required time 10.682 arrival time -6.480 ------------------------------------------------------------------- slack 4.202 Slack (MET) : 4.208ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 3.730ns (logic 0.286ns (7.668%) route 3.444ns (92.332%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.251ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.306ns = ( 10.623 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.930ns (routing 0.603ns, distribution 1.327ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.925 5.807 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y440 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.147 5.954 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.519 6.473 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X44Y442 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.930 10.623 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X44Y442 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C clock pessimism 0.186 10.810 clock uncertainty -0.035 10.774 SLICE_X44Y442 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 10.681 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2] ------------------------------------------------------------------- required time 10.681 arrival time -6.473 ------------------------------------------------------------------- slack 4.208 Slack (MET) : 4.272ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 3.668ns (logic 0.286ns (7.797%) route 3.382ns (92.203%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.249ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.308ns = ( 10.625 - 8.317 ) Source Clock Delay (SCD): 2.743ns Clock Pessimism Removal (CPR): 0.186ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.318ns (routing 0.667ns, distribution 1.651ns) Clock Net Delay (Destination): 1.932ns (routing 0.603ns, distribution 1.329ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 2.318 2.743 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X6Y474 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y474 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.882 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.925 5.807 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X45Y440 LUT3 (Prop_H6LUT_SLICEL_I0_O) 0.147 5.954 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/O net (fo=15, routed) 0.457 6.411 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X44Y441 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.932 10.625 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] SLICE_X44Y441 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C clock pessimism 0.186 10.812 clock uncertainty -0.035 10.776 SLICE_X44Y441 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.683 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5] ------------------------------------------------------------------- required time 10.683 arrival time -6.411 ------------------------------------------------------------------- slack 4.272 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.158ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.228ns (logic 0.049ns (21.491%) route 0.179ns (78.509%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.159ns Source Clock Delay (SCD): 0.969ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.853ns (routing 0.301ns, distribution 0.552ns) Clock Net Delay (Destination): 1.007ns (routing 0.348ns, distribution 0.659ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.853 0.969 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK SLICE_X44Y439 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X44Y439 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.018 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.179 1.197 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X41Y439 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.007 1.159 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X41Y439 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.125 1.034 SLICE_X41Y439 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.039 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.039 arrival time 1.197 ------------------------------------------------------------------- slack 0.158 Slack (MET) : 0.181ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.270ns (logic 0.048ns (17.778%) route 0.222ns (82.222%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.166ns Source Clock Delay (SCD): 0.956ns Clock Pessimism Removal (CPR): 0.126ns Clock Net Delay (Source): 0.840ns (routing 0.301ns, distribution 0.539ns) Clock Net Delay (Destination): 1.014ns (routing 0.348ns, distribution 0.666ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.840 0.956 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X40Y444 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X40Y444 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.004 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.222 1.226 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X41Y440 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.014 1.166 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X41Y440 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism -0.126 1.040 SLICE_X41Y440 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.045 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time -1.045 arrival time 1.226 ------------------------------------------------------------------- slack 0.181 Slack (MET) : 0.205ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.311ns (logic 0.048ns (15.434%) route 0.263ns (84.566%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.182ns Source Clock Delay (SCD): 0.956ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.840ns (routing 0.301ns, distribution 0.539ns) Clock Net Delay (Destination): 1.030ns (routing 0.348ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.840 0.956 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X40Y444 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X40Y444 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.004 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.263 1.267 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X42Y440 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.030 1.182 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X42Y440 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.125 1.057 SLICE_X42Y440 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.062 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.062 arrival time 1.267 ------------------------------------------------------------------- slack 0.205 Slack (MET) : 0.205ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.311ns (logic 0.048ns (15.434%) route 0.263ns (84.566%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.182ns Source Clock Delay (SCD): 0.956ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.840ns (routing 0.301ns, distribution 0.539ns) Clock Net Delay (Destination): 1.030ns (routing 0.348ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.840 0.956 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X40Y444 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X40Y444 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.004 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.263 1.267 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X42Y440 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.030 1.182 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X42Y440 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.125 1.057 SLICE_X42Y440 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.062 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.062 arrival time 1.267 ------------------------------------------------------------------- slack 0.205 Slack (MET) : 0.205ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.311ns (logic 0.048ns (15.434%) route 0.263ns (84.566%)) Logic Levels: 0 Clock Path Skew: 0.101ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.182ns Source Clock Delay (SCD): 0.956ns Clock Pessimism Removal (CPR): 0.125ns Clock Net Delay (Source): 0.840ns (routing 0.301ns, distribution 0.539ns) Clock Net Delay (Destination): 1.030ns (routing 0.348ns, distribution 0.682ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.840 0.956 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X40Y444 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X40Y444 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.004 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.263 1.267 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X42Y440 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.030 1.182 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X42Y440 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.125 1.057 SLICE_X42Y440 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.062 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.062 arrival time 1.267 ------------------------------------------------------------------- slack 0.205 Slack (MET) : 0.225ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.285ns (logic 0.048ns (16.842%) route 0.237ns (83.158%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.172ns Source Clock Delay (SCD): 0.956ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 0.840ns (routing 0.301ns, distribution 0.539ns) Clock Net Delay (Destination): 1.020ns (routing 0.348ns, distribution 0.672ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.840 0.956 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X40Y444 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X40Y444 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.004 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.237 1.241 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X39Y440 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.020 1.172 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X39Y440 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.161 1.011 SLICE_X39Y440 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.016 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.016 arrival time 1.241 ------------------------------------------------------------------- slack 0.225 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.284ns (logic 0.048ns (16.901%) route 0.236ns (83.099%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.170ns Source Clock Delay (SCD): 0.956ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 0.840ns (routing 0.301ns, distribution 0.539ns) Clock Net Delay (Destination): 1.018ns (routing 0.348ns, distribution 0.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.840 0.956 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X40Y444 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X40Y444 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.004 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.236 1.240 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X40Y440 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.170 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y440 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.161 1.009 SLICE_X40Y440 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.014 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.014 arrival time 1.240 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.284ns (logic 0.048ns (16.901%) route 0.236ns (83.099%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.170ns Source Clock Delay (SCD): 0.956ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 0.840ns (routing 0.301ns, distribution 0.539ns) Clock Net Delay (Destination): 1.018ns (routing 0.348ns, distribution 0.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.840 0.956 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X40Y444 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X40Y444 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.004 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.236 1.240 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X40Y440 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.170 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y440 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.161 1.009 SLICE_X40Y440 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.014 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.014 arrival time 1.240 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.284ns (logic 0.048ns (16.901%) route 0.236ns (83.099%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.170ns Source Clock Delay (SCD): 0.956ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 0.840ns (routing 0.301ns, distribution 0.539ns) Clock Net Delay (Destination): 1.018ns (routing 0.348ns, distribution 0.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.840 0.956 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X40Y444 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X40Y444 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.004 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.236 1.240 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X40Y440 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.170 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y440 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.161 1.009 SLICE_X40Y440 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.014 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.014 arrival time 1.240 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.226ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns) Data Path Delay: 0.284ns (logic 0.048ns (16.901%) route 0.236ns (83.099%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.170ns Source Clock Delay (SCD): 0.956ns Clock Pessimism Removal (CPR): 0.161ns Clock Net Delay (Source): 0.840ns (routing 0.301ns, distribution 0.539ns) Clock Net Delay (Destination): 1.018ns (routing 0.348ns, distribution 0.670ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 0.840 0.956 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X40Y444 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X40Y444 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.004 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.236 1.240 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X40Y440 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y31 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y171 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y7 (CLOCK_ROOT) net (fo=674, routed) 1.018 1.170 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y440 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.161 1.009 SLICE_X40Y440 FDCE (Remov_FFF2_SLICEL_C_CLR) 0.005 1.014 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.014 arrival time 1.240 ------------------------------------------------------------------- slack 0.226 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_42 To Clock: gtwiz_userclk_rx_srcclk_out[0]_42 Setup : 0 Failing Endpoints, Worst Slack 4.537ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.146ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.537ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.729ns (logic 0.377ns (10.110%) route 3.352ns (89.890%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.077ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.606ns = ( 10.923 - 8.317 ) Source Clock Delay (SCD): 2.721ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.296ns (routing 0.692ns, distribution 1.604ns) Clock Net Delay (Destination): 2.230ns (routing 0.629ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.296 2.721 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y496 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y496 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.861 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.352 5.213 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y485 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.237 5.450 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__39/O net (fo=2, routed) 1.000 6.450 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X53Y496 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.230 10.923 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X53Y496 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.192 11.116 clock uncertainty -0.035 11.080 SLICE_X53Y496 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.987 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.987 arrival time -6.450 ------------------------------------------------------------------- slack 4.537 Slack (MET) : 4.537ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.729ns (logic 0.377ns (10.110%) route 3.352ns (89.890%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.077ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.606ns = ( 10.923 - 8.317 ) Source Clock Delay (SCD): 2.721ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.296ns (routing 0.692ns, distribution 1.604ns) Clock Net Delay (Destination): 2.230ns (routing 0.629ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.296 2.721 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y496 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y496 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.861 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.352 5.213 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X54Y485 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.237 5.450 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__39/O net (fo=2, routed) 1.000 6.450 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X53Y496 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.230 10.923 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X53Y496 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.192 11.116 clock uncertainty -0.035 11.080 SLICE_X53Y496 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 10.987 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.987 arrival time -6.450 ------------------------------------------------------------------- slack 4.537 Slack (MET) : 4.693ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.564ns (logic 0.307ns (8.614%) route 3.257ns (91.386%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.597ns = ( 10.914 - 8.317 ) Source Clock Delay (SCD): 2.721ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.296ns (routing 0.692ns, distribution 1.604ns) Clock Net Delay (Destination): 2.221ns (routing 0.629ns, distribution 1.592ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.296 2.721 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y496 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y496 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.861 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.181 5.042 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y485 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.209 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 1.076 6.285 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X58Y494 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.221 10.914 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X58Y494 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C clock pessimism 0.192 11.107 clock uncertainty -0.035 11.071 SLICE_X58Y494 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.978 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4] ------------------------------------------------------------------- required time 10.978 arrival time -6.285 ------------------------------------------------------------------- slack 4.693 Slack (MET) : 4.840ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.426ns (logic 0.307ns (8.961%) route 3.119ns (91.039%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.077ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.606ns = ( 10.923 - 8.317 ) Source Clock Delay (SCD): 2.721ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.296ns (routing 0.692ns, distribution 1.604ns) Clock Net Delay (Destination): 2.230ns (routing 0.629ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.296 2.721 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y496 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y496 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.861 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.181 5.042 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y485 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.209 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.938 6.147 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X57Y496 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.230 10.923 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X57Y496 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C clock pessimism 0.192 11.116 clock uncertainty -0.035 11.080 SLICE_X57Y496 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.987 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3] ------------------------------------------------------------------- required time 10.987 arrival time -6.147 ------------------------------------------------------------------- slack 4.840 Slack (MET) : 4.848ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.416ns (logic 0.307ns (8.987%) route 3.109ns (91.013%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.075ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.604ns = ( 10.921 - 8.317 ) Source Clock Delay (SCD): 2.721ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.296ns (routing 0.692ns, distribution 1.604ns) Clock Net Delay (Destination): 2.228ns (routing 0.629ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.296 2.721 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y496 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y496 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.861 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.181 5.042 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y485 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.209 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.928 6.137 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X57Y496 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.228 10.921 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X57Y496 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C clock pessimism 0.192 11.114 clock uncertainty -0.035 11.078 SLICE_X57Y496 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.985 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1] ------------------------------------------------------------------- required time 10.985 arrival time -6.137 ------------------------------------------------------------------- slack 4.848 Slack (MET) : 4.848ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.416ns (logic 0.307ns (8.987%) route 3.109ns (91.013%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.075ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.604ns = ( 10.921 - 8.317 ) Source Clock Delay (SCD): 2.721ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.296ns (routing 0.692ns, distribution 1.604ns) Clock Net Delay (Destination): 2.228ns (routing 0.629ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.296 2.721 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y496 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y496 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.861 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.181 5.042 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y485 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.209 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.928 6.137 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X57Y496 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.228 10.921 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X57Y496 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C clock pessimism 0.192 11.114 clock uncertainty -0.035 11.078 SLICE_X57Y496 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 10.985 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2] ------------------------------------------------------------------- required time 10.985 arrival time -6.137 ------------------------------------------------------------------- slack 4.848 Slack (MET) : 4.848ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.416ns (logic 0.307ns (8.987%) route 3.109ns (91.013%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.075ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.604ns = ( 10.921 - 8.317 ) Source Clock Delay (SCD): 2.721ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.296ns (routing 0.692ns, distribution 1.604ns) Clock Net Delay (Destination): 2.228ns (routing 0.629ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.296 2.721 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y496 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y496 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.861 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.181 5.042 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y485 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.209 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.928 6.137 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X57Y496 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.228 10.921 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X57Y496 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C clock pessimism 0.192 11.114 clock uncertainty -0.035 11.078 SLICE_X57Y496 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.985 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0] ------------------------------------------------------------------- required time 10.985 arrival time -6.137 ------------------------------------------------------------------- slack 4.848 Slack (MET) : 5.019ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.248ns (logic 0.307ns (9.452%) route 2.941ns (90.548%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.078ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.607ns = ( 10.924 - 8.317 ) Source Clock Delay (SCD): 2.721ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.296ns (routing 0.692ns, distribution 1.604ns) Clock Net Delay (Destination): 2.231ns (routing 0.629ns, distribution 1.602ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.296 2.721 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y496 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y496 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.861 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.181 5.042 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y485 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.209 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.760 5.969 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X57Y495 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.924 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X57Y495 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C clock pessimism 0.192 11.117 clock uncertainty -0.035 11.081 SLICE_X57Y495 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.988 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4] ------------------------------------------------------------------- required time 10.988 arrival time -5.969 ------------------------------------------------------------------- slack 5.019 Slack (MET) : 5.019ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.248ns (logic 0.307ns (9.452%) route 2.941ns (90.548%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.078ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.607ns = ( 10.924 - 8.317 ) Source Clock Delay (SCD): 2.721ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.296ns (routing 0.692ns, distribution 1.604ns) Clock Net Delay (Destination): 2.231ns (routing 0.629ns, distribution 1.602ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.296 2.721 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y496 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y496 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.861 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.181 5.042 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y485 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.209 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.760 5.969 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X57Y495 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.924 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X57Y495 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C clock pessimism 0.192 11.117 clock uncertainty -0.035 11.081 SLICE_X57Y495 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.988 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5] ------------------------------------------------------------------- required time 10.988 arrival time -5.969 ------------------------------------------------------------------- slack 5.019 Slack (MET) : 5.019ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 3.248ns (logic 0.307ns (9.452%) route 2.941ns (90.548%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.078ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.607ns = ( 10.924 - 8.317 ) Source Clock Delay (SCD): 2.721ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.296ns (routing 0.692ns, distribution 1.604ns) Clock Net Delay (Destination): 2.231ns (routing 0.629ns, distribution 1.602ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.296 2.721 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y496 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y496 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.861 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.181 5.042 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X53Y485 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.167 5.209 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/O net (fo=15, routed) 0.760 5.969 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X57Y495 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.924 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] SLICE_X57Y495 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C clock pessimism 0.192 11.117 clock uncertainty -0.035 11.081 SLICE_X57Y495 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.988 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6] ------------------------------------------------------------------- required time 10.988 arrival time -5.969 ------------------------------------------------------------------- slack 5.019 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.146ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.048ns (22.222%) route 0.168ns (77.778%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.982ns (routing 0.317ns, distribution 0.665ns) Clock Net Delay (Destination): 1.157ns (routing 0.366ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.098 SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y482 FDPE r SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y482 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.146 f SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.168 1.314 SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] SLICE_X57Y482 FDCE f SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y482 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.146 1.163 SLICE_X57Y482 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.168 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.168 arrival time 1.314 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.048ns (22.222%) route 0.168ns (77.778%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.982ns (routing 0.317ns, distribution 0.665ns) Clock Net Delay (Destination): 1.157ns (routing 0.366ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.098 SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y482 FDPE r SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y482 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.146 f SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.168 1.314 SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] SLICE_X57Y482 FDCE f SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y482 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.146 1.163 SLICE_X57Y482 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.168 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.168 arrival time 1.314 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.048ns (22.222%) route 0.168ns (77.778%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.982ns (routing 0.317ns, distribution 0.665ns) Clock Net Delay (Destination): 1.157ns (routing 0.366ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.098 SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y482 FDPE r SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y482 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.146 f SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.168 1.314 SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] SLICE_X57Y482 FDCE f SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y482 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.146 1.163 SLICE_X57Y482 FDCE (Remov_GFF_SLICEL_C_CLR) 0.005 1.168 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -1.168 arrival time 1.314 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.146ns (arrival time - required time) Source: SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.048ns (22.222%) route 0.168ns (77.778%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.309ns Source Clock Delay (SCD): 1.098ns Clock Pessimism Removal (CPR): 0.146ns Clock Net Delay (Source): 0.982ns (routing 0.317ns, distribution 0.665ns) Clock Net Delay (Destination): 1.157ns (routing 0.366ns, distribution 0.791ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.098 SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y482 FDPE r SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y482 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.146 f SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.168 1.314 SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] SLICE_X57Y482 FDCE f SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.309 SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y482 FDCE r SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism -0.146 1.163 SLICE_X57Y482 FDCE (Remov_GFF2_SLICEL_C_CLR) 0.005 1.168 SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time -1.168 arrival time 1.314 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[83]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.320ns Source Clock Delay (SCD): 1.096ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 0.980ns (routing 0.317ns, distribution 0.663ns) Clock Net Delay (Destination): 1.168ns (routing 0.366ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.096 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X55Y496 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X55Y496 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.145 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.176 1.321 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y494 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.168 1.320 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X56Y494 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[83]/C clock pessimism -0.180 1.140 SLICE_X56Y494 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.145 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[83] ------------------------------------------------------------------- required time -1.145 arrival time 1.321 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.176ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[83]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.049ns (21.778%) route 0.176ns (78.222%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.320ns Source Clock Delay (SCD): 1.096ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 0.980ns (routing 0.317ns, distribution 0.663ns) Clock Net Delay (Destination): 1.168ns (routing 0.366ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.096 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X55Y496 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X55Y496 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.145 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.176 1.321 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y494 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.168 1.320 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X56Y494 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[83]/C clock pessimism -0.180 1.140 SLICE_X56Y494 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.145 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[83] ------------------------------------------------------------------- required time -1.145 arrival time 1.321 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.179ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.049ns (21.212%) route 0.182ns (78.788%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.323ns Source Clock Delay (SCD): 1.096ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 0.980ns (routing 0.317ns, distribution 0.663ns) Clock Net Delay (Destination): 1.171ns (routing 0.366ns, distribution 0.805ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.096 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X55Y496 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X55Y496 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.145 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.182 1.327 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y494 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.323 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X56Y494 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41]/C clock pessimism -0.180 1.143 SLICE_X56Y494 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.148 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[41] ------------------------------------------------------------------- required time -1.148 arrival time 1.327 ------------------------------------------------------------------- slack 0.179 Slack (MET) : 0.179ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.049ns (21.212%) route 0.182ns (78.788%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.323ns Source Clock Delay (SCD): 1.096ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 0.980ns (routing 0.317ns, distribution 0.663ns) Clock Net Delay (Destination): 1.171ns (routing 0.366ns, distribution 0.805ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.096 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X55Y496 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X55Y496 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.145 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.182 1.327 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y494 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.323 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X56Y494 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]/C clock pessimism -0.180 1.143 SLICE_X56Y494 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.148 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43] ------------------------------------------------------------------- required time -1.148 arrival time 1.327 ------------------------------------------------------------------- slack 0.179 Slack (MET) : 0.179ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[50]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.049ns (21.212%) route 0.182ns (78.788%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.323ns Source Clock Delay (SCD): 1.096ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 0.980ns (routing 0.317ns, distribution 0.663ns) Clock Net Delay (Destination): 1.171ns (routing 0.366ns, distribution 0.805ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.096 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X55Y496 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X55Y496 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.145 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.182 1.327 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y494 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[50]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.323 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X56Y494 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[50]/C clock pessimism -0.180 1.143 SLICE_X56Y494 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.148 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[50] ------------------------------------------------------------------- required time -1.148 arrival time 1.327 ------------------------------------------------------------------- slack 0.179 Slack (MET) : 0.179ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[56]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.049ns (21.212%) route 0.182ns (78.788%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.323ns Source Clock Delay (SCD): 1.096ns Clock Pessimism Removal (CPR): 0.180ns Clock Net Delay (Source): 0.980ns (routing 0.317ns, distribution 0.663ns) Clock Net Delay (Destination): 1.171ns (routing 0.366ns, distribution 0.805ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.980 1.096 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK SLICE_X55Y496 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X55Y496 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.145 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.182 1.327 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y494 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y32 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y196 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.171 1.323 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X56Y494 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[56]/C clock pessimism -0.180 1.143 SLICE_X56Y494 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.148 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[56] ------------------------------------------------------------------- required time -1.148 arrival time 1.327 ------------------------------------------------------------------- slack 0.179 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_43 To Clock: gtwiz_userclk_rx_srcclk_out[0]_43 Setup : 0 Failing Endpoints, Worst Slack 4.180ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.128ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.180ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.092ns (logic 0.285ns (6.965%) route 3.807ns (93.035%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.083ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.592ns = ( 10.909 - 8.317 ) Source Clock Delay (SCD): 2.703ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.278ns (routing 0.667ns, distribution 1.611ns) Clock Net Delay (Destination): 2.216ns (routing 0.603ns, distribution 1.613ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.278 2.703 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y510 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.842 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.081 5.923 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y492 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 6.069 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 0.726 6.795 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X57Y500 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.216 10.909 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X57Y500 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C clock pessimism 0.194 11.104 clock uncertainty -0.035 11.068 SLICE_X57Y500 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.975 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3] ------------------------------------------------------------------- required time 10.975 arrival time -6.795 ------------------------------------------------------------------- slack 4.180 Slack (MET) : 4.188ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.082ns (logic 0.285ns (6.982%) route 3.797ns (93.018%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.590ns = ( 10.907 - 8.317 ) Source Clock Delay (SCD): 2.703ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.278ns (routing 0.667ns, distribution 1.611ns) Clock Net Delay (Destination): 2.214ns (routing 0.603ns, distribution 1.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.278 2.703 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y510 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.842 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.081 5.923 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y492 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 6.069 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 0.716 6.785 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X57Y500 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.214 10.907 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X57Y500 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/C clock pessimism 0.194 11.102 clock uncertainty -0.035 11.066 SLICE_X57Y500 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.973 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6] ------------------------------------------------------------------- required time 10.973 arrival time -6.785 ------------------------------------------------------------------- slack 4.188 Slack (MET) : 4.188ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.082ns (logic 0.285ns (6.982%) route 3.797ns (93.018%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.590ns = ( 10.907 - 8.317 ) Source Clock Delay (SCD): 2.703ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.278ns (routing 0.667ns, distribution 1.611ns) Clock Net Delay (Destination): 2.214ns (routing 0.603ns, distribution 1.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.278 2.703 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y510 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.842 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.081 5.923 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y492 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 6.069 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 0.716 6.785 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X57Y500 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.214 10.907 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X57Y500 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/C clock pessimism 0.194 11.102 clock uncertainty -0.035 11.066 SLICE_X57Y500 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 10.973 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7] ------------------------------------------------------------------- required time 10.973 arrival time -6.785 ------------------------------------------------------------------- slack 4.188 Slack (MET) : 4.188ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.082ns (logic 0.285ns (6.982%) route 3.797ns (93.018%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.081ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.590ns = ( 10.907 - 8.317 ) Source Clock Delay (SCD): 2.703ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.278ns (routing 0.667ns, distribution 1.611ns) Clock Net Delay (Destination): 2.214ns (routing 0.603ns, distribution 1.611ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.278 2.703 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y510 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.842 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.081 5.923 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y492 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 6.069 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 0.716 6.785 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X57Y500 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.214 10.907 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X57Y500 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/C clock pessimism 0.194 11.102 clock uncertainty -0.035 11.066 SLICE_X57Y500 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.973 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5] ------------------------------------------------------------------- required time 10.973 arrival time -6.785 ------------------------------------------------------------------- slack 4.188 Slack (MET) : 4.215ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.058ns (logic 0.285ns (7.023%) route 3.773ns (92.977%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.593ns = ( 10.910 - 8.317 ) Source Clock Delay (SCD): 2.703ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.278ns (routing 0.667ns, distribution 1.611ns) Clock Net Delay (Destination): 2.217ns (routing 0.603ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.278 2.703 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y510 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.842 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.081 5.923 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y492 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 6.069 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 0.692 6.761 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X57Y498 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.217 10.910 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X57Y498 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C clock pessimism 0.194 11.105 clock uncertainty -0.035 11.069 SLICE_X57Y498 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.976 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1] ------------------------------------------------------------------- required time 10.976 arrival time -6.761 ------------------------------------------------------------------- slack 4.215 Slack (MET) : 4.215ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.058ns (logic 0.285ns (7.023%) route 3.773ns (92.977%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.593ns = ( 10.910 - 8.317 ) Source Clock Delay (SCD): 2.703ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.278ns (routing 0.667ns, distribution 1.611ns) Clock Net Delay (Destination): 2.217ns (routing 0.603ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.278 2.703 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y510 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.842 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.081 5.923 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y492 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 6.069 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 0.692 6.761 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X57Y498 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.217 10.910 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X57Y498 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/C clock pessimism 0.194 11.105 clock uncertainty -0.035 11.069 SLICE_X57Y498 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.976 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2] ------------------------------------------------------------------- required time 10.976 arrival time -6.761 ------------------------------------------------------------------- slack 4.215 Slack (MET) : 4.215ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.058ns (logic 0.285ns (7.023%) route 3.773ns (92.977%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.593ns = ( 10.910 - 8.317 ) Source Clock Delay (SCD): 2.703ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.278ns (routing 0.667ns, distribution 1.611ns) Clock Net Delay (Destination): 2.217ns (routing 0.603ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.278 2.703 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y510 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.842 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.081 5.923 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y492 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 6.069 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 0.692 6.761 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X57Y498 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.217 10.910 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X57Y498 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/C clock pessimism 0.194 11.105 clock uncertainty -0.035 11.069 SLICE_X57Y498 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.976 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4] ------------------------------------------------------------------- required time 10.976 arrival time -6.761 ------------------------------------------------------------------- slack 4.215 Slack (MET) : 4.215ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.058ns (logic 0.285ns (7.023%) route 3.773ns (92.977%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.084ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.593ns = ( 10.910 - 8.317 ) Source Clock Delay (SCD): 2.703ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.278ns (routing 0.667ns, distribution 1.611ns) Clock Net Delay (Destination): 2.217ns (routing 0.603ns, distribution 1.614ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.278 2.703 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y510 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.842 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.081 5.923 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y492 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 6.069 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 0.692 6.761 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X57Y498 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.217 10.910 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X57Y498 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/C clock pessimism 0.194 11.105 clock uncertainty -0.035 11.069 SLICE_X57Y498 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.976 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5] ------------------------------------------------------------------- required time 10.976 arrival time -6.761 ------------------------------------------------------------------- slack 4.215 Slack (MET) : 4.223ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.048ns (logic 0.285ns (7.041%) route 3.763ns (92.959%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.082ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.591ns = ( 10.908 - 8.317 ) Source Clock Delay (SCD): 2.703ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.278ns (routing 0.667ns, distribution 1.611ns) Clock Net Delay (Destination): 2.215ns (routing 0.603ns, distribution 1.612ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.278 2.703 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y510 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.842 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.081 5.923 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y492 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 6.069 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 0.682 6.751 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X57Y498 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.215 10.908 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X57Y498 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/C clock pessimism 0.194 11.103 clock uncertainty -0.035 11.067 SLICE_X57Y498 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.974 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0] ------------------------------------------------------------------- required time 10.974 arrival time -6.751 ------------------------------------------------------------------- slack 4.223 Slack (MET) : 4.265ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 4.022ns (logic 0.285ns (7.086%) route 3.737ns (92.914%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.098ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.607ns = ( 10.924 - 8.317 ) Source Clock Delay (SCD): 2.703ns Clock Pessimism Removal (CPR): 0.194ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.278ns (routing 0.667ns, distribution 1.611ns) Clock Net Delay (Destination): 2.231ns (routing 0.603ns, distribution 1.628ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.278 2.703 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X9Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X9Y510 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.842 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.081 5.923 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X55Y492 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.146 6.069 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/O net (fo=15, routed) 0.656 6.725 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X56Y500 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.231 10.924 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] SLICE_X56Y500 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C clock pessimism 0.194 11.119 clock uncertainty -0.035 11.083 SLICE_X56Y500 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.990 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0] ------------------------------------------------------------------- required time 10.990 arrival time -6.725 ------------------------------------------------------------------- slack 4.265 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.128ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.049ns (22.273%) route 0.171ns (77.727%)) Logic Levels: 0 Clock Path Skew: 0.087ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.319ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.972ns (routing 0.301ns, distribution 0.671ns) Clock Net Delay (Destination): 1.167ns (routing 0.348ns, distribution 0.819ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.972 1.088 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK SLICE_X54Y499 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X54Y499 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.137 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.171 1.308 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X56Y500 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.167 1.319 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] SLICE_X56Y500 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.144 1.175 SLICE_X56Y500 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.180 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.180 arrival time 1.308 ------------------------------------------------------------------- slack 0.128 Slack (MET) : 0.160ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.244ns (logic 0.048ns (19.672%) route 0.196ns (80.328%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.299ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.960ns (routing 0.301ns, distribution 0.659ns) Clock Net Delay (Destination): 1.147ns (routing 0.348ns, distribution 0.799ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.076 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y505 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.124 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.196 1.320 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X55Y505 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.299 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y505 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.144 1.155 SLICE_X55Y505 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.160 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.160 arrival time 1.320 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.160ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.244ns (logic 0.048ns (19.672%) route 0.196ns (80.328%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.299ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.960ns (routing 0.301ns, distribution 0.659ns) Clock Net Delay (Destination): 1.147ns (routing 0.348ns, distribution 0.799ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.076 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y505 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.124 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.196 1.320 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X55Y505 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.147 1.299 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X55Y505 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.144 1.155 SLICE_X55Y505 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.160 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -1.160 arrival time 1.320 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.166ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.244ns (logic 0.048ns (19.672%) route 0.196ns (80.328%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.293ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.960ns (routing 0.301ns, distribution 0.659ns) Clock Net Delay (Destination): 1.141ns (routing 0.348ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.076 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y505 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.124 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.196 1.320 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X57Y507 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.141 1.293 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y507 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]/C clock pessimism -0.144 1.149 SLICE_X57Y507 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.154 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17] ------------------------------------------------------------------- required time -1.154 arrival time 1.320 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.166ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.244ns (logic 0.048ns (19.672%) route 0.196ns (80.328%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.293ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.960ns (routing 0.301ns, distribution 0.659ns) Clock Net Delay (Destination): 1.141ns (routing 0.348ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.076 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y505 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.124 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.196 1.320 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X57Y507 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.141 1.293 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y507 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[20]/C clock pessimism -0.144 1.149 SLICE_X57Y507 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.154 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[20] ------------------------------------------------------------------- required time -1.154 arrival time 1.320 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.166ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.244ns (logic 0.048ns (19.672%) route 0.196ns (80.328%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.293ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.960ns (routing 0.301ns, distribution 0.659ns) Clock Net Delay (Destination): 1.141ns (routing 0.348ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.076 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y505 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.124 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.196 1.320 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X57Y507 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.141 1.293 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y507 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.144 1.149 SLICE_X57Y507 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.154 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -1.154 arrival time 1.320 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.166ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.244ns (logic 0.048ns (19.672%) route 0.196ns (80.328%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.293ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.960ns (routing 0.301ns, distribution 0.659ns) Clock Net Delay (Destination): 1.141ns (routing 0.348ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.076 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y505 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.124 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.196 1.320 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X57Y507 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.141 1.293 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y507 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.144 1.149 SLICE_X57Y507 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.154 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -1.154 arrival time 1.320 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.166ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.244ns (logic 0.048ns (19.672%) route 0.196ns (80.328%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.293ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.960ns (routing 0.301ns, distribution 0.659ns) Clock Net Delay (Destination): 1.141ns (routing 0.348ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.076 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y505 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.124 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.196 1.320 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X57Y507 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.141 1.293 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y507 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[29]/C clock pessimism -0.144 1.149 SLICE_X57Y507 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.154 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[29] ------------------------------------------------------------------- required time -1.154 arrival time 1.320 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.166ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.244ns (logic 0.048ns (19.672%) route 0.196ns (80.328%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.293ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.144ns Clock Net Delay (Source): 0.960ns (routing 0.301ns, distribution 0.659ns) Clock Net Delay (Destination): 1.141ns (routing 0.348ns, distribution 0.793ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.076 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y505 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.124 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.196 1.320 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X57Y507 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.141 1.293 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X57Y507 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[30]/C clock pessimism -0.144 1.149 SLICE_X57Y507 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 1.154 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[30] ------------------------------------------------------------------- required time -1.154 arrival time 1.320 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.181ns (arrival time - required time) Source: SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns) Data Path Delay: 0.228ns (logic 0.048ns (21.053%) route 0.180ns (78.947%)) Logic Levels: 0 Clock Path Skew: 0.042ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.295ns Source Clock Delay (SCD): 1.076ns Clock Pessimism Removal (CPR): 0.177ns Clock Net Delay (Source): 0.960ns (routing 0.301ns, distribution 0.659ns) Clock Net Delay (Destination): 1.143ns (routing 0.348ns, distribution 0.795ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.960 1.076 SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y505 FDPE r SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X58Y505 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.124 f SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.180 1.304 SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] SLICE_X58Y507 FDCE f SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y33 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y195 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.143 1.295 SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X58Y507 FDCE r SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]/C clock pessimism -0.177 1.118 SLICE_X58Y507 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.123 SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16] ------------------------------------------------------------------- required time -1.123 arrival time 1.304 ------------------------------------------------------------------- slack 0.181 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_44 To Clock: gtwiz_userclk_rx_srcclk_out[0]_44 Setup : 0 Failing Endpoints, Worst Slack 5.652ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.146ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.652ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 2.376ns (logic 0.140ns (5.892%) route 2.236ns (94.108%)) Logic Levels: 0 Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.262ns = ( 10.579 - 8.317 ) Source Clock Delay (SCD): 2.613ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.188ns (routing 0.699ns, distribution 1.489ns) Clock Net Delay (Destination): 1.886ns (routing 0.636ns, distribution 1.250ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.188 2.613 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X31Y488 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y488 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.753 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.236 4.989 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X25Y508 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.886 10.579 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X25Y508 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.190 10.769 clock uncertainty -0.035 10.734 SLICE_X25Y508 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.641 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 10.641 arrival time -4.989 ------------------------------------------------------------------- slack 5.652 Slack (MET) : 5.652ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 2.376ns (logic 0.140ns (5.892%) route 2.236ns (94.108%)) Logic Levels: 0 Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.262ns = ( 10.579 - 8.317 ) Source Clock Delay (SCD): 2.613ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.188ns (routing 0.699ns, distribution 1.489ns) Clock Net Delay (Destination): 1.886ns (routing 0.636ns, distribution 1.250ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.188 2.613 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X31Y488 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y488 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.753 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.236 4.989 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X25Y508 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.886 10.579 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X25Y508 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.190 10.769 clock uncertainty -0.035 10.734 SLICE_X25Y508 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.641 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 10.641 arrival time -4.989 ------------------------------------------------------------------- slack 5.652 Slack (MET) : 5.715ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 2.305ns (logic 0.140ns (6.074%) route 2.165ns (93.926%)) Logic Levels: 0 Clock Path Skew: -0.169ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.254ns = ( 10.571 - 8.317 ) Source Clock Delay (SCD): 2.613ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.188ns (routing 0.699ns, distribution 1.489ns) Clock Net Delay (Destination): 1.878ns (routing 0.636ns, distribution 1.242ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.188 2.613 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X31Y488 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y488 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.753 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.165 4.918 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/AS[0] SLICE_X25Y507 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.878 10.571 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/CLK SLICE_X25Y507 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C clock pessimism 0.190 10.761 clock uncertainty -0.035 10.726 SLICE_X25Y507 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.633 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].rxBitSlipControl/RX_BITSLIPCMD_o_reg ------------------------------------------------------------------- required time 10.633 arrival time -4.918 ------------------------------------------------------------------- slack 5.715 Slack (MET) : 5.762ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 2.264ns (logic 0.140ns (6.184%) route 2.124ns (93.816%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.260ns = ( 10.577 - 8.317 ) Source Clock Delay (SCD): 2.613ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.188ns (routing 0.699ns, distribution 1.489ns) Clock Net Delay (Destination): 1.884ns (routing 0.636ns, distribution 1.248ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.188 2.613 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X31Y488 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y488 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.753 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.124 4.877 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X27Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.884 10.577 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X27Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0]/C clock pessimism 0.190 10.767 clock uncertainty -0.035 10.732 SLICE_X27Y509 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[0] ------------------------------------------------------------------- required time 10.639 arrival time -4.877 ------------------------------------------------------------------- slack 5.762 Slack (MET) : 5.762ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 2.264ns (logic 0.140ns (6.184%) route 2.124ns (93.816%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.260ns = ( 10.577 - 8.317 ) Source Clock Delay (SCD): 2.613ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.188ns (routing 0.699ns, distribution 1.489ns) Clock Net Delay (Destination): 1.884ns (routing 0.636ns, distribution 1.248ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.188 2.613 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X31Y488 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y488 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.753 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.124 4.877 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X27Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.884 10.577 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X27Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1]/C clock pessimism 0.190 10.767 clock uncertainty -0.035 10.732 SLICE_X27Y509 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 10.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[1] ------------------------------------------------------------------- required time 10.639 arrival time -4.877 ------------------------------------------------------------------- slack 5.762 Slack (MET) : 5.762ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 2.264ns (logic 0.140ns (6.184%) route 2.124ns (93.816%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.260ns = ( 10.577 - 8.317 ) Source Clock Delay (SCD): 2.613ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.188ns (routing 0.699ns, distribution 1.489ns) Clock Net Delay (Destination): 1.884ns (routing 0.636ns, distribution 1.248ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.188 2.613 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X31Y488 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y488 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.753 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.124 4.877 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X27Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.884 10.577 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X27Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/C clock pessimism 0.190 10.767 clock uncertainty -0.035 10.732 SLICE_X27Y509 FDCE (Recov_BFF2_SLICEL_C_CLR) -0.093 10.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2] ------------------------------------------------------------------- required time 10.639 arrival time -4.877 ------------------------------------------------------------------- slack 5.762 Slack (MET) : 5.762ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 2.264ns (logic 0.140ns (6.184%) route 2.124ns (93.816%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.260ns = ( 10.577 - 8.317 ) Source Clock Delay (SCD): 2.613ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.188ns (routing 0.699ns, distribution 1.489ns) Clock Net Delay (Destination): 1.884ns (routing 0.636ns, distribution 1.248ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.188 2.613 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X31Y488 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y488 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.753 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.124 4.877 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X27Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.884 10.577 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X27Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3]/C clock pessimism 0.190 10.767 clock uncertainty -0.035 10.732 SLICE_X27Y509 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[3] ------------------------------------------------------------------- required time 10.639 arrival time -4.877 ------------------------------------------------------------------- slack 5.762 Slack (MET) : 5.762ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 2.264ns (logic 0.140ns (6.184%) route 2.124ns (93.816%)) Logic Levels: 0 Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.260ns = ( 10.577 - 8.317 ) Source Clock Delay (SCD): 2.613ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.188ns (routing 0.699ns, distribution 1.489ns) Clock Net Delay (Destination): 1.884ns (routing 0.636ns, distribution 1.248ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.188 2.613 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X31Y488 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y488 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.753 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.124 4.877 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X27Y509 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.884 10.577 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X27Y509 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]/C clock pessimism 0.190 10.767 clock uncertainty -0.035 10.732 SLICE_X27Y509 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.639 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4] ------------------------------------------------------------------- required time 10.639 arrival time -4.877 ------------------------------------------------------------------- slack 5.762 Slack (MET) : 5.770ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/shiftPsAddr_reg_inv/PRE (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 2.254ns (logic 0.140ns (6.211%) route 2.114ns (93.789%)) Logic Levels: 0 Clock Path Skew: -0.165ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.258ns = ( 10.575 - 8.317 ) Source Clock Delay (SCD): 2.613ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.188ns (routing 0.699ns, distribution 1.489ns) Clock Net Delay (Destination): 1.882ns (routing 0.636ns, distribution 1.246ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.188 2.613 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X31Y488 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y488 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.753 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.114 4.867 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X27Y509 FDPE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/shiftPsAddr_reg_inv/PRE (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.882 10.575 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X27Y509 FDPE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/shiftPsAddr_reg_inv/C clock pessimism 0.190 10.765 clock uncertainty -0.035 10.730 SLICE_X27Y509 FDPE (Recov_HFF_SLICEL_C_PRE) -0.093 10.637 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/shiftPsAddr_reg_inv ------------------------------------------------------------------- required time 10.637 arrival time -4.867 ------------------------------------------------------------------- slack 5.770 Slack (MET) : 5.847ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCmd_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 2.182ns (logic 0.140ns (6.416%) route 2.042ns (93.584%)) Logic Levels: 0 Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.263ns = ( 10.580 - 8.317 ) Source Clock Delay (SCD): 2.613ns Clock Pessimism Removal (CPR): 0.190ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.188ns (routing 0.699ns, distribution 1.489ns) Clock Net Delay (Destination): 1.887ns (routing 0.636ns, distribution 1.251ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.188 2.613 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X31Y488 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X31Y488 FDCE (Prop_AFF_SLICEM_C_Q) 0.140 2.753 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.042 4.795 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitslip_reset_6 SLICE_X27Y507 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCmd_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.887 10.580 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/CLK SLICE_X27Y507 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCmd_reg/C clock pessimism 0.190 10.770 clock uncertainty -0.035 10.735 SLICE_X27Y507 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.642 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/bitSlipCmd_reg ------------------------------------------------------------------- required time 10.642 arrival time -4.795 ------------------------------------------------------------------- slack 5.847 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.146ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.181ns (logic 0.049ns (27.072%) route 0.132ns (72.928%)) Logic Levels: 0 Clock Path Skew: 0.030ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.165ns Source Clock Delay (SCD): 0.961ns Clock Pessimism Removal (CPR): 0.174ns Clock Net Delay (Source): 0.845ns (routing 0.319ns, distribution 0.526ns) Clock Net Delay (Destination): 1.013ns (routing 0.369ns, distribution 0.644ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.845 0.961 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK SLICE_X35Y489 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X35Y489 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.010 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.132 1.142 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X35Y489 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.013 1.165 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X35Y489 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.174 0.991 SLICE_X35Y489 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 0.996 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.996 arrival time 1.142 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.165ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.048ns (21.622%) route 0.174ns (78.378%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.930ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.814ns (routing 0.319ns, distribution 0.495ns) Clock Net Delay (Destination): 0.990ns (routing 0.369ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.814 0.930 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X30Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y510 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.978 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.174 1.152 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X29Y511 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.142 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/CLK SLICE_X29Y511 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.160 0.982 SLICE_X29Y511 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 0.987 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -0.987 arrival time 1.152 ------------------------------------------------------------------- slack 0.165 Slack (MET) : 0.165ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.048ns (21.622%) route 0.174ns (78.378%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.930ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.814ns (routing 0.319ns, distribution 0.495ns) Clock Net Delay (Destination): 0.990ns (routing 0.369ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.814 0.930 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X30Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y510 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.978 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.174 1.152 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X29Y511 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.142 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X29Y511 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C clock pessimism -0.160 0.982 SLICE_X29Y511 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 0.987 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1] ------------------------------------------------------------------- required time -0.987 arrival time 1.152 ------------------------------------------------------------------- slack 0.165 Slack (MET) : 0.165ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.048ns (21.622%) route 0.174ns (78.378%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.930ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.814ns (routing 0.319ns, distribution 0.495ns) Clock Net Delay (Destination): 0.990ns (routing 0.369ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.814 0.930 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X30Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y510 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.978 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.174 1.152 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X29Y511 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.142 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X29Y511 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism -0.160 0.982 SLICE_X29Y511 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 0.987 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time -0.987 arrival time 1.152 ------------------------------------------------------------------- slack 0.165 Slack (MET) : 0.165ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.048ns (21.622%) route 0.174ns (78.378%)) Logic Levels: 0 Clock Path Skew: 0.052ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.930ns Clock Pessimism Removal (CPR): 0.160ns Clock Net Delay (Source): 0.814ns (routing 0.319ns, distribution 0.495ns) Clock Net Delay (Destination): 0.990ns (routing 0.369ns, distribution 0.621ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.814 0.930 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X30Y510 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y510 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 0.978 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.174 1.152 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X29Y511 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.990 1.142 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X29Y511 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism -0.160 0.982 SLICE_X29Y511 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 0.987 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time -0.987 arrival time 1.152 ------------------------------------------------------------------- slack 0.165 Slack (MET) : 0.166ns (arrival time - required time) Source: SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.154ns Source Clock Delay (SCD): 0.941ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.825ns (routing 0.319ns, distribution 0.506ns) Clock Net Delay (Destination): 1.002ns (routing 0.369ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.825 0.941 SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X37Y509 FDPE r SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y509 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.989 f SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.195 SFP_GEN[42].ngCCM_gbt/sync_m_reg[3][0] SLICE_X35Y511 FDCE f SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.154 SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y511 FDCE r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[17]/C clock pessimism -0.130 1.024 SLICE_X35Y511 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.029 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[17] ------------------------------------------------------------------- required time -1.029 arrival time 1.195 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.166ns (arrival time - required time) Source: SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.154ns Source Clock Delay (SCD): 0.941ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.825ns (routing 0.319ns, distribution 0.506ns) Clock Net Delay (Destination): 1.002ns (routing 0.369ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.825 0.941 SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X37Y509 FDPE r SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y509 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.989 f SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.195 SFP_GEN[42].ngCCM_gbt/sync_m_reg[3][0] SLICE_X35Y511 FDCE f SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.154 SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y511 FDCE r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism -0.130 1.024 SLICE_X35Y511 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.029 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time -1.029 arrival time 1.195 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.166ns (arrival time - required time) Source: SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.154ns Source Clock Delay (SCD): 0.941ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.825ns (routing 0.319ns, distribution 0.506ns) Clock Net Delay (Destination): 1.002ns (routing 0.369ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.825 0.941 SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X37Y509 FDPE r SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y509 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.989 f SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.195 SFP_GEN[42].ngCCM_gbt/sync_m_reg[3][0] SLICE_X35Y511 FDCE f SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.154 SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y511 FDCE r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[19]/C clock pessimism -0.130 1.024 SLICE_X35Y511 FDCE (Remov_BFF_SLICEM_C_CLR) 0.005 1.029 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[19] ------------------------------------------------------------------- required time -1.029 arrival time 1.195 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.166ns (arrival time - required time) Source: SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.154ns Source Clock Delay (SCD): 0.941ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.825ns (routing 0.319ns, distribution 0.506ns) Clock Net Delay (Destination): 1.002ns (routing 0.369ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.825 0.941 SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X37Y509 FDPE r SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y509 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.989 f SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.195 SFP_GEN[42].ngCCM_gbt/sync_m_reg[3][0] SLICE_X35Y511 FDCE f SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.154 SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y511 FDCE r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[20]/C clock pessimism -0.130 1.024 SLICE_X35Y511 FDCE (Remov_BFF2_SLICEM_C_CLR) 0.005 1.029 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[20] ------------------------------------------------------------------- required time -1.029 arrival time 1.195 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.166ns (arrival time - required time) Source: SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.048ns (18.898%) route 0.206ns (81.102%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.154ns Source Clock Delay (SCD): 0.941ns Clock Pessimism Removal (CPR): 0.130ns Clock Net Delay (Source): 0.825ns (routing 0.319ns, distribution 0.506ns) Clock Net Delay (Destination): 1.002ns (routing 0.369ns, distribution 0.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.825 0.941 SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X37Y509 FDPE r SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y509 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 0.989 f SFP_GEN[42].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.206 1.195 SFP_GEN[42].ngCCM_gbt/sync_m_reg[3][0] SLICE_X35Y511 FDCE f SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y34 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y197 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.002 1.154 SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X35Y511 FDCE r SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.130 1.024 SLICE_X35Y511 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.029 SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -1.029 arrival time 1.195 ------------------------------------------------------------------- slack 0.166 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_45 To Clock: gtwiz_userclk_rx_srcclk_out[0]_45 Setup : 0 Failing Endpoints, Worst Slack 4.530ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.173ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.530ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 3.327ns (logic 0.358ns (10.760%) route 2.969ns (89.240%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.332ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.365ns = ( 10.682 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 1.989ns (routing 0.721ns, distribution 1.268ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.198 5.238 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.219 5.457 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__42/O net (fo=2, routed) 0.771 6.228 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X42Y492 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.989 10.682 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X42Y492 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.204 10.887 clock uncertainty -0.035 10.851 SLICE_X42Y492 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 10.758 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.758 arrival time -6.228 ------------------------------------------------------------------- slack 4.530 Slack (MET) : 4.530ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 3.327ns (logic 0.358ns (10.760%) route 2.969ns (89.240%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.332ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.365ns = ( 10.682 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 1.989ns (routing 0.721ns, distribution 1.268ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.198 5.238 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT2 (Prop_B6LUT_SLICEL_I0_O) 0.219 5.457 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__42/O net (fo=2, routed) 0.771 6.228 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X42Y492 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.989 10.682 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK SLICE_X42Y492 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.204 10.887 clock uncertainty -0.035 10.851 SLICE_X42Y492 FDCE (Recov_EFF2_SLICEM_C_CLR) -0.093 10.758 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.758 arrival time -6.228 ------------------------------------------------------------------- slack 4.530 Slack (MET) : 4.767ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 3.118ns (logic 0.285ns (9.140%) route 2.833ns (90.860%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.393ns = ( 10.710 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.017ns (routing 0.721ns, distribution 1.296ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.058 5.098 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.146 5.244 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 0.775 6.019 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X38Y522 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.017 10.710 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X38Y522 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C clock pessimism 0.204 10.915 clock uncertainty -0.035 10.879 SLICE_X38Y522 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.786 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1] ------------------------------------------------------------------- required time 10.786 arrival time -6.019 ------------------------------------------------------------------- slack 4.767 Slack (MET) : 4.767ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 3.118ns (logic 0.285ns (9.140%) route 2.833ns (90.860%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.393ns = ( 10.710 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.017ns (routing 0.721ns, distribution 1.296ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.058 5.098 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.146 5.244 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 0.775 6.019 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X38Y522 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.017 10.710 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X38Y522 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/C clock pessimism 0.204 10.915 clock uncertainty -0.035 10.879 SLICE_X38Y522 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.786 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2] ------------------------------------------------------------------- required time 10.786 arrival time -6.019 ------------------------------------------------------------------- slack 4.767 Slack (MET) : 4.767ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 3.118ns (logic 0.285ns (9.140%) route 2.833ns (90.860%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.393ns = ( 10.710 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.017ns (routing 0.721ns, distribution 1.296ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.058 5.098 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.146 5.244 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 0.775 6.019 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X38Y522 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.017 10.710 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X38Y522 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C clock pessimism 0.204 10.915 clock uncertainty -0.035 10.879 SLICE_X38Y522 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 10.786 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3] ------------------------------------------------------------------- required time 10.786 arrival time -6.019 ------------------------------------------------------------------- slack 4.767 Slack (MET) : 4.767ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 3.118ns (logic 0.285ns (9.140%) route 2.833ns (90.860%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.393ns = ( 10.710 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.017ns (routing 0.721ns, distribution 1.296ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.058 5.098 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.146 5.244 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 0.775 6.019 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X38Y522 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.017 10.710 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X38Y522 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/C clock pessimism 0.204 10.915 clock uncertainty -0.035 10.879 SLICE_X38Y522 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.786 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4] ------------------------------------------------------------------- required time 10.786 arrival time -6.019 ------------------------------------------------------------------- slack 4.767 Slack (MET) : 4.849ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 3.024ns (logic 0.285ns (9.425%) route 2.739ns (90.575%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.316ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.381ns = ( 10.698 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.005ns (routing 0.721ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.058 5.098 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.146 5.244 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 0.681 5.925 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X37Y520 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.005 10.698 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X37Y520 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/C clock pessimism 0.204 10.903 clock uncertainty -0.035 10.867 SLICE_X37Y520 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 10.774 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0] ------------------------------------------------------------------- required time 10.774 arrival time -5.925 ------------------------------------------------------------------- slack 4.849 Slack (MET) : 4.849ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 3.024ns (logic 0.285ns (9.425%) route 2.739ns (90.575%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.316ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.381ns = ( 10.698 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.005ns (routing 0.721ns, distribution 1.284ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.058 5.098 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.146 5.244 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 0.681 5.925 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X37Y520 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.005 10.698 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X37Y520 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C clock pessimism 0.204 10.903 clock uncertainty -0.035 10.867 SLICE_X37Y520 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.774 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0] ------------------------------------------------------------------- required time 10.774 arrival time -5.925 ------------------------------------------------------------------- slack 4.849 Slack (MET) : 4.928ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 2.962ns (logic 0.285ns (9.622%) route 2.677ns (90.378%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.299ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.398ns = ( 10.715 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.022ns (routing 0.721ns, distribution 1.301ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.058 5.098 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.146 5.244 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 0.619 5.863 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X37Y519 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.022 10.715 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X37Y519 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C clock pessimism 0.204 10.919 clock uncertainty -0.035 10.884 SLICE_X37Y519 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.791 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1] ------------------------------------------------------------------- required time 10.791 arrival time -5.863 ------------------------------------------------------------------- slack 4.928 Slack (MET) : 4.928ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 2.962ns (logic 0.285ns (9.622%) route 2.677ns (90.378%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.299ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.398ns = ( 10.715 - 8.317 ) Source Clock Delay (SCD): 2.901ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.476ns (routing 0.804ns, distribution 1.672ns) Clock Net Delay (Destination): 2.022ns (routing 0.721ns, distribution 1.301ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.476 2.901 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X8Y531 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y531 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.040 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.058 5.098 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X40Y516 LUT3 (Prop_C6LUT_SLICEL_I0_O) 0.146 5.244 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/O net (fo=15, routed) 0.619 5.863 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X37Y519 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 2.022 10.715 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] SLICE_X37Y519 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C clock pessimism 0.204 10.919 clock uncertainty -0.035 10.884 SLICE_X37Y519 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.791 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6] ------------------------------------------------------------------- required time 10.791 arrival time -5.863 ------------------------------------------------------------------- slack 4.928 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.173ns (arrival time - required time) Source: SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.218ns (logic 0.048ns (22.018%) route 0.170ns (77.982%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.215ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.886ns (routing 0.382ns, distribution 0.504ns) Clock Net Delay (Destination): 1.063ns (routing 0.446ns, distribution 0.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X47Y519 FDPE r SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y519 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.050 f SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.170 1.220 SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] SLICE_X47Y518 FDCE f SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.063 1.215 SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X47Y518 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[44]/C clock pessimism -0.173 1.042 SLICE_X47Y518 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.047 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[44] ------------------------------------------------------------------- required time -1.047 arrival time 1.220 ------------------------------------------------------------------- slack 0.173 Slack (MET) : 0.173ns (arrival time - required time) Source: SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[46]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.218ns (logic 0.048ns (22.018%) route 0.170ns (77.982%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.215ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.886ns (routing 0.382ns, distribution 0.504ns) Clock Net Delay (Destination): 1.063ns (routing 0.446ns, distribution 0.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X47Y519 FDPE r SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y519 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.050 f SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.170 1.220 SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] SLICE_X47Y518 FDCE f SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[46]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.063 1.215 SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X47Y518 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[46]/C clock pessimism -0.173 1.042 SLICE_X47Y518 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.047 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[46] ------------------------------------------------------------------- required time -1.047 arrival time 1.220 ------------------------------------------------------------------- slack 0.173 Slack (MET) : 0.173ns (arrival time - required time) Source: SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.218ns (logic 0.048ns (22.018%) route 0.170ns (77.982%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.215ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.886ns (routing 0.382ns, distribution 0.504ns) Clock Net Delay (Destination): 1.063ns (routing 0.446ns, distribution 0.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X47Y519 FDPE r SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y519 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.050 f SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.170 1.220 SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] SLICE_X47Y518 FDCE f SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.063 1.215 SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X47Y518 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[76]/C clock pessimism -0.173 1.042 SLICE_X47Y518 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.047 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[76] ------------------------------------------------------------------- required time -1.047 arrival time 1.220 ------------------------------------------------------------------- slack 0.173 Slack (MET) : 0.173ns (arrival time - required time) Source: SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.218ns (logic 0.048ns (22.018%) route 0.170ns (77.982%)) Logic Levels: 0 Clock Path Skew: 0.040ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.215ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.173ns Clock Net Delay (Source): 0.886ns (routing 0.382ns, distribution 0.504ns) Clock Net Delay (Destination): 1.063ns (routing 0.446ns, distribution 0.617ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X47Y519 FDPE r SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y519 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.050 f SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.170 1.220 SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] SLICE_X47Y518 FDCE f SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.063 1.215 SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X47Y518 FDCE r SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[78]/C clock pessimism -0.173 1.042 SLICE_X47Y518 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.047 SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[78] ------------------------------------------------------------------- required time -1.047 arrival time 1.220 ------------------------------------------------------------------- slack 0.173 Slack (MET) : 0.206ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.255ns (logic 0.048ns (18.824%) route 0.207ns (81.176%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.253ns Source Clock Delay (SCD): 1.033ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.917ns (routing 0.382ns, distribution 0.535ns) Clock Net Delay (Destination): 1.101ns (routing 0.446ns, distribution 0.655ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.917 1.033 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X38Y525 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X38Y525 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.081 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.207 1.288 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X37Y522 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.101 1.253 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X37Y522 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.176 1.077 SLICE_X37Y522 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.082 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.082 arrival time 1.288 ------------------------------------------------------------------- slack 0.206 Slack (MET) : 0.208ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.283ns (logic 0.048ns (16.961%) route 0.235ns (83.039%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.246ns Source Clock Delay (SCD): 1.033ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.917ns (routing 0.382ns, distribution 0.535ns) Clock Net Delay (Destination): 1.094ns (routing 0.446ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.917 1.033 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X38Y525 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X38Y525 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.081 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.235 1.316 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X43Y524 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.094 1.246 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X43Y524 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C clock pessimism -0.143 1.103 SLICE_X43Y524 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.108 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time -1.108 arrival time 1.316 ------------------------------------------------------------------- slack 0.208 Slack (MET) : 0.208ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.283ns (logic 0.048ns (16.961%) route 0.235ns (83.039%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.246ns Source Clock Delay (SCD): 1.033ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.917ns (routing 0.382ns, distribution 0.535ns) Clock Net Delay (Destination): 1.094ns (routing 0.446ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.917 1.033 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X38Y525 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X38Y525 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.081 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.235 1.316 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X43Y524 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.094 1.246 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X43Y524 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.143 1.103 SLICE_X43Y524 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.108 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.108 arrival time 1.316 ------------------------------------------------------------------- slack 0.208 Slack (MET) : 0.229ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.302ns (logic 0.048ns (15.894%) route 0.254ns (84.106%)) Logic Levels: 0 Clock Path Skew: 0.068ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.244ns Source Clock Delay (SCD): 1.033ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.917ns (routing 0.382ns, distribution 0.535ns) Clock Net Delay (Destination): 1.092ns (routing 0.446ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.917 1.033 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X38Y525 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X38Y525 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.081 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.254 1.335 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X40Y520 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.092 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/CLK SLICE_X40Y520 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.143 1.101 SLICE_X40Y520 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.106 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -1.106 arrival time 1.335 ------------------------------------------------------------------- slack 0.229 Slack (MET) : 0.254ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.048ns (16.327%) route 0.246ns (83.673%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.244ns Source Clock Delay (SCD): 1.033ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.917ns (routing 0.382ns, distribution 0.535ns) Clock Net Delay (Destination): 1.092ns (routing 0.446ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.917 1.033 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X38Y525 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X38Y525 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.081 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.246 1.327 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X37Y520 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.092 1.244 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X37Y520 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.176 1.068 SLICE_X37Y520 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.073 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.073 arrival time 1.327 ------------------------------------------------------------------- slack 0.254 Slack (MET) : 0.285ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns) Data Path Delay: 0.366ns (logic 0.048ns (13.115%) route 0.318ns (86.885%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.252ns Source Clock Delay (SCD): 1.033ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.917ns (routing 0.382ns, distribution 0.535ns) Clock Net Delay (Destination): 1.100ns (routing 0.446ns, distribution 0.654ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 0.917 1.033 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X38Y525 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X38Y525 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.081 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.318 1.399 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X39Y519 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y35 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y215 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y8 (CLOCK_ROOT) net (fo=674, routed) 1.100 1.252 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X39Y519 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.143 1.109 SLICE_X39Y519 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.114 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.114 arrival time 1.399 ------------------------------------------------------------------- slack 0.285 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_46 To Clock: gtwiz_userclk_rx_srcclk_out[0]_46 Setup : 0 Failing Endpoints, Worst Slack 3.590ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.135ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.590ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.690ns (logic 0.229ns (4.883%) route 4.461ns (95.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.588ns = ( 10.905 - 8.317 ) Source Clock Delay (SCD): 2.689ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.264ns (routing 0.666ns, distribution 1.598ns) Clock Net Delay (Destination): 2.212ns (routing 0.602ns, distribution 1.610ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.264 2.689 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y556 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.828 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.228 6.056 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y513 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 6.146 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.233 7.379 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X60Y542 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.905 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X60Y542 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/C clock pessimism 0.192 11.098 clock uncertainty -0.035 11.062 SLICE_X60Y542 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.969 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1] ------------------------------------------------------------------- required time 10.969 arrival time -7.379 ------------------------------------------------------------------- slack 3.590 Slack (MET) : 3.590ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.690ns (logic 0.229ns (4.883%) route 4.461ns (95.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.588ns = ( 10.905 - 8.317 ) Source Clock Delay (SCD): 2.689ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.264ns (routing 0.666ns, distribution 1.598ns) Clock Net Delay (Destination): 2.212ns (routing 0.602ns, distribution 1.610ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.264 2.689 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y556 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.828 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.228 6.056 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y513 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 6.146 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.233 7.379 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X60Y542 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.905 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X60Y542 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/C clock pessimism 0.192 11.098 clock uncertainty -0.035 11.062 SLICE_X60Y542 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 10.969 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2] ------------------------------------------------------------------- required time 10.969 arrival time -7.379 ------------------------------------------------------------------- slack 3.590 Slack (MET) : 3.590ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.690ns (logic 0.229ns (4.883%) route 4.461ns (95.117%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.588ns = ( 10.905 - 8.317 ) Source Clock Delay (SCD): 2.689ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.264ns (routing 0.666ns, distribution 1.598ns) Clock Net Delay (Destination): 2.212ns (routing 0.602ns, distribution 1.610ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.264 2.689 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y556 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.828 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.228 6.056 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y513 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 6.146 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.233 7.379 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X60Y542 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.212 10.905 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X60Y542 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/C clock pessimism 0.192 11.098 clock uncertainty -0.035 11.062 SLICE_X60Y542 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 10.969 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4] ------------------------------------------------------------------- required time 10.969 arrival time -7.379 ------------------------------------------------------------------- slack 3.590 Slack (MET) : 3.598ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.680ns (logic 0.229ns (4.893%) route 4.451ns (95.107%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.586ns = ( 10.903 - 8.317 ) Source Clock Delay (SCD): 2.689ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.264ns (routing 0.666ns, distribution 1.598ns) Clock Net Delay (Destination): 2.210ns (routing 0.602ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.264 2.689 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y556 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.828 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.228 6.056 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y513 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 6.146 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.223 7.369 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X60Y542 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.210 10.903 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X60Y542 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C clock pessimism 0.192 11.096 clock uncertainty -0.035 11.060 SLICE_X60Y542 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.967 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3] ------------------------------------------------------------------- required time 10.967 arrival time -7.369 ------------------------------------------------------------------- slack 3.598 Slack (MET) : 3.598ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.680ns (logic 0.229ns (4.893%) route 4.451ns (95.107%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.586ns = ( 10.903 - 8.317 ) Source Clock Delay (SCD): 2.689ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.264ns (routing 0.666ns, distribution 1.598ns) Clock Net Delay (Destination): 2.210ns (routing 0.602ns, distribution 1.608ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.264 2.689 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y556 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.828 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.228 6.056 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y513 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 6.146 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.223 7.369 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X60Y542 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.210 10.903 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X60Y542 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/C clock pessimism 0.192 11.096 clock uncertainty -0.035 11.060 SLICE_X60Y542 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.967 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5] ------------------------------------------------------------------- required time 10.967 arrival time -7.369 ------------------------------------------------------------------- slack 3.598 Slack (MET) : 3.757ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.514ns (logic 0.229ns (5.073%) route 4.285ns (94.927%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.082ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.689ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.264ns (routing 0.666ns, distribution 1.598ns) Clock Net Delay (Destination): 2.203ns (routing 0.602ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.264 2.689 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y556 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.828 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.228 6.056 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y513 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 6.146 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.057 7.203 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X58Y542 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X58Y542 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/C clock pessimism 0.192 11.089 clock uncertainty -0.035 11.053 SLICE_X58Y542 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 10.960 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2] ------------------------------------------------------------------- required time 10.960 arrival time -7.203 ------------------------------------------------------------------- slack 3.757 Slack (MET) : 3.757ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.514ns (logic 0.229ns (5.073%) route 4.285ns (94.927%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.082ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.689ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.264ns (routing 0.666ns, distribution 1.598ns) Clock Net Delay (Destination): 2.203ns (routing 0.602ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.264 2.689 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y556 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.828 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.228 6.056 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y513 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 6.146 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.057 7.203 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X58Y542 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X58Y542 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C clock pessimism 0.192 11.089 clock uncertainty -0.035 11.053 SLICE_X58Y542 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.960 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5] ------------------------------------------------------------------- required time 10.960 arrival time -7.203 ------------------------------------------------------------------- slack 3.757 Slack (MET) : 3.757ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.514ns (logic 0.229ns (5.073%) route 4.285ns (94.927%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.082ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.579ns = ( 10.896 - 8.317 ) Source Clock Delay (SCD): 2.689ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.264ns (routing 0.666ns, distribution 1.598ns) Clock Net Delay (Destination): 2.203ns (routing 0.602ns, distribution 1.601ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.264 2.689 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y556 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.828 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.228 6.056 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y513 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 6.146 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.057 7.203 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X58Y542 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.203 10.896 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X58Y542 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/C clock pessimism 0.192 11.089 clock uncertainty -0.035 11.053 SLICE_X58Y542 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.960 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6] ------------------------------------------------------------------- required time 10.960 arrival time -7.203 ------------------------------------------------------------------- slack 3.757 Slack (MET) : 3.762ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.507ns (logic 0.229ns (5.081%) route 4.278ns (94.919%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.080ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.577ns = ( 10.894 - 8.317 ) Source Clock Delay (SCD): 2.689ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.264ns (routing 0.666ns, distribution 1.598ns) Clock Net Delay (Destination): 2.201ns (routing 0.602ns, distribution 1.599ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.264 2.689 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y556 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.828 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.228 6.056 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y513 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 6.146 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 1.050 7.196 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X58Y542 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.201 10.894 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X58Y542 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/C clock pessimism 0.192 11.087 clock uncertainty -0.035 11.051 SLICE_X58Y542 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.958 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3] ------------------------------------------------------------------- required time 10.958 arrival time -7.196 ------------------------------------------------------------------- slack 3.762 Slack (MET) : 3.993ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 4.270ns (logic 0.229ns (5.363%) route 4.041ns (94.637%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.074ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.571ns = ( 10.888 - 8.317 ) Source Clock Delay (SCD): 2.689ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.264ns (routing 0.666ns, distribution 1.598ns) Clock Net Delay (Destination): 2.195ns (routing 0.602ns, distribution 1.593ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.264 2.689 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X16Y556 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X16Y556 FDCE (Prop_EFF_SLICEM_C_Q) 0.139 2.828 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 3.228 6.056 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X61Y513 LUT3 (Prop_C6LUT_SLICEM_I0_O) 0.090 6.146 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/O net (fo=15, routed) 0.813 6.959 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8]0 SLICE_X57Y541 FDCE f g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.195 10.888 g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] SLICE_X57Y541 FDCE r g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/C clock pessimism 0.192 11.081 clock uncertainty -0.035 11.045 SLICE_X57Y541 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 10.952 g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8] ------------------------------------------------------------------- required time 10.952 arrival time -6.959 ------------------------------------------------------------------- slack 3.993 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.135ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.049ns (22.273%) route 0.171ns (77.727%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.336ns Source Clock Delay (SCD): 1.114ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.998ns (routing 0.301ns, distribution 0.697ns) Clock Net Delay (Destination): 1.184ns (routing 0.348ns, distribution 0.836ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.114 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X62Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X62Y547 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.171 1.334 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X65Y547 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.184 1.336 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X65Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.142 1.194 SLICE_X65Y547 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.199 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.199 arrival time 1.334 ------------------------------------------------------------------- slack 0.135 Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.219ns (logic 0.049ns (22.374%) route 0.170ns (77.626%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.114ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.998ns (routing 0.301ns, distribution 0.697ns) Clock Net Delay (Destination): 1.182ns (routing 0.348ns, distribution 0.834ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.114 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X62Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X62Y547 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.170 1.333 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X66Y547 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.182 1.334 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X66Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism -0.142 1.192 SLICE_X66Y547 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.197 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time -1.197 arrival time 1.333 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.136ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.219ns (logic 0.049ns (22.374%) route 0.170ns (77.626%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.334ns Source Clock Delay (SCD): 1.114ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.998ns (routing 0.301ns, distribution 0.697ns) Clock Net Delay (Destination): 1.182ns (routing 0.348ns, distribution 0.834ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.114 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X62Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X62Y547 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.170 1.333 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X66Y547 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.182 1.334 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X66Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism -0.142 1.192 SLICE_X66Y547 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.197 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time -1.197 arrival time 1.333 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.142ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.180ns (logic 0.048ns (26.667%) route 0.132ns (73.333%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.325ns Source Clock Delay (SCD): 1.103ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 0.987ns (routing 0.301ns, distribution 0.686ns) Clock Net Delay (Destination): 1.173ns (routing 0.348ns, distribution 0.825ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.987 1.103 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK SLICE_X61Y543 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X61Y543 FDPE (Prop_EFF2_SLICEM_C_Q) 0.048 1.151 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.132 1.283 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X61Y543 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.173 1.325 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X61Y543 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.189 1.136 SLICE_X61Y543 FDCE (Remov_AFF2_SLICEM_C_CLR) 0.005 1.141 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.141 arrival time 1.283 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.148ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.049ns (25.521%) route 0.143ns (74.479%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.114ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 0.998ns (routing 0.301ns, distribution 0.697ns) Clock Net Delay (Destination): 1.190ns (routing 0.348ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.114 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X62Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X62Y547 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.143 1.306 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X63Y547 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.342 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X63Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.189 1.153 SLICE_X63Y547 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.158 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.158 arrival time 1.306 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.049ns (25.521%) route 0.143ns (74.479%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.114ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 0.998ns (routing 0.301ns, distribution 0.697ns) Clock Net Delay (Destination): 1.190ns (routing 0.348ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.114 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X62Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X62Y547 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.143 1.306 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X63Y547 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.342 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X63Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.189 1.153 SLICE_X63Y547 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.158 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.158 arrival time 1.306 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.049ns (25.521%) route 0.143ns (74.479%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.114ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 0.998ns (routing 0.301ns, distribution 0.697ns) Clock Net Delay (Destination): 1.190ns (routing 0.348ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.114 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X62Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X62Y547 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.143 1.306 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X63Y547 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.342 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X63Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.189 1.153 SLICE_X63Y547 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.158 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.158 arrival time 1.306 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.049ns (25.521%) route 0.143ns (74.479%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.114ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 0.998ns (routing 0.301ns, distribution 0.697ns) Clock Net Delay (Destination): 1.190ns (routing 0.348ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.114 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X62Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X62Y547 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.143 1.306 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X63Y547 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.342 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X63Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.189 1.153 SLICE_X63Y547 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.158 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.158 arrival time 1.306 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.148ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.049ns (25.521%) route 0.143ns (74.479%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.342ns Source Clock Delay (SCD): 1.114ns Clock Pessimism Removal (CPR): 0.189ns Clock Net Delay (Source): 0.998ns (routing 0.301ns, distribution 0.697ns) Clock Net Delay (Destination): 1.190ns (routing 0.348ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.114 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X62Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X62Y547 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.143 1.306 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X63Y547 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.190 1.342 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X63Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.189 1.153 SLICE_X63Y547 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.158 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.158 arrival time 1.306 ------------------------------------------------------------------- slack 0.148 Slack (MET) : 0.160ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.049ns (21.304%) route 0.181ns (78.696%)) Logic Levels: 0 Clock Path Skew: 0.065ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.114ns Clock Pessimism Removal (CPR): 0.143ns Clock Net Delay (Source): 0.998ns (routing 0.301ns, distribution 0.697ns) Clock Net Delay (Destination): 1.170ns (routing 0.348ns, distribution 0.822ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.998 1.114 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK SLICE_X62Y547 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X62Y547 FDCE (Prop_AFF_SLICEM_C_Q) 0.049 1.163 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.181 1.344 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X61Y548 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y36 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y219 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.170 1.322 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X61Y548 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.143 1.179 SLICE_X61Y548 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.184 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -1.184 arrival time 1.344 ------------------------------------------------------------------- slack 0.160 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_47 To Clock: gtwiz_userclk_rx_srcclk_out[0]_47 Setup : 0 Failing Endpoints, Worst Slack 5.865ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.195ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.865ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.259ns (logic 0.381ns (16.866%) route 1.878ns (83.134%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.356ns = ( 10.673 - 8.317 ) Source Clock Delay (SCD): 2.709ns Clock Pessimism Removal (CPR): 0.288ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.284ns (routing 0.802ns, distribution 1.482ns) Clock Net Delay (Destination): 1.980ns (routing 0.719ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.284 2.709 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X40Y540 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X40Y540 FDCE (Prop_EFF2_SLICEL_C_Q) 0.138 2.847 r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/Q net (fo=1, routed) 0.863 3.710 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s SLICE_X39Y503 LUT2 (Prop_A6LUT_SLICEM_I1_O) 0.243 3.953 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__44/O net (fo=1, routed) 1.015 4.968 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s0 SLICE_X39Y544 FDPE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.980 10.673 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X39Y544 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C clock pessimism 0.288 10.962 clock uncertainty -0.035 10.926 SLICE_X39Y544 FDPE (Recov_EFF_SLICEM_C_PRE) -0.093 10.833 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg ------------------------------------------------------------------- required time 10.833 arrival time -4.968 ------------------------------------------------------------------- slack 5.865 Slack (MET) : 5.981ns (required time - arrival time) Source: SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.034ns (logic 0.139ns (6.834%) route 1.895ns (93.166%)) Logic Levels: 0 Clock Path Skew: -0.174ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.359ns = ( 10.676 - 8.317 ) Source Clock Delay (SCD): 2.737ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.312ns (routing 0.802ns, distribution 1.510ns) Clock Net Delay (Destination): 1.983ns (routing 0.719ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.312 2.737 SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X38Y562 FDPE r SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y562 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.876 f SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 1.895 4.771 SFP_GEN[45].ngCCM_gbt/sync_m_reg[3][0] SLICE_X36Y570 FDCE f SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.983 10.676 SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X36Y570 FDCE r SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[56]/C clock pessimism 0.204 10.880 clock uncertainty -0.035 10.845 SLICE_X36Y570 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.752 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[56] ------------------------------------------------------------------- required time 10.752 arrival time -4.771 ------------------------------------------------------------------- slack 5.981 Slack (MET) : 5.981ns (required time - arrival time) Source: SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 2.034ns (logic 0.139ns (6.834%) route 1.895ns (93.166%)) Logic Levels: 0 Clock Path Skew: -0.174ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.359ns = ( 10.676 - 8.317 ) Source Clock Delay (SCD): 2.737ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.312ns (routing 0.802ns, distribution 1.510ns) Clock Net Delay (Destination): 1.983ns (routing 0.719ns, distribution 1.264ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.312 2.737 SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X38Y562 FDPE r SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y562 FDPE (Prop_CFF2_SLICEL_C_Q) 0.139 2.876 f SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 1.895 4.771 SFP_GEN[45].ngCCM_gbt/sync_m_reg[3][0] SLICE_X36Y570 FDCE f SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.983 10.676 SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X36Y570 FDCE r SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[58]/C clock pessimism 0.204 10.880 clock uncertainty -0.035 10.845 SLICE_X36Y570 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.752 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[58] ------------------------------------------------------------------- required time 10.752 arrival time -4.771 ------------------------------------------------------------------- slack 5.981 Slack (MET) : 6.076ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 1.929ns (logic 0.364ns (18.870%) route 1.565ns (81.130%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.184ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.358ns = ( 10.675 - 8.317 ) Source Clock Delay (SCD): 2.746ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.802ns, distribution 1.519ns) Clock Net Delay (Destination): 1.982ns (routing 0.719ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X32Y548 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y548 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.885 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 0.994 3.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X41Y541 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.104 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__44/O net (fo=2, routed) 0.571 4.675 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X40Y540 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.982 10.675 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X40Y540 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.204 10.879 clock uncertainty -0.035 10.844 SLICE_X40Y540 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 10.751 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 10.751 arrival time -4.675 ------------------------------------------------------------------- slack 6.076 Slack (MET) : 6.076ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 1.929ns (logic 0.364ns (18.870%) route 1.565ns (81.130%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.184ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.358ns = ( 10.675 - 8.317 ) Source Clock Delay (SCD): 2.746ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.321ns (routing 0.802ns, distribution 1.519ns) Clock Net Delay (Destination): 1.982ns (routing 0.719ns, distribution 1.263ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.321 2.746 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X32Y548 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X32Y548 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.885 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 0.994 3.879 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X41Y541 LUT2 (Prop_D6LUT_SLICEM_I0_O) 0.225 4.104 f g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__44/O net (fo=2, routed) 0.571 4.675 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X40Y540 FDCE f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.982 10.675 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X40Y540 FDCE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.204 10.879 clock uncertainty -0.035 10.844 SLICE_X40Y540 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 10.751 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 10.751 arrival time -4.675 ------------------------------------------------------------------- slack 6.076 Slack (MET) : 6.129ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[101]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 1.908ns (logic 0.139ns (7.285%) route 1.769ns (92.715%)) Logic Levels: 0 Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.356ns = ( 10.673 - 8.317 ) Source Clock Delay (SCD): 2.712ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.802ns, distribution 1.485ns) Clock Net Delay (Destination): 1.980ns (routing 0.719ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.712 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X39Y544 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X39Y544 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.851 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.769 4.620 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X37Y565 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[101]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.980 10.673 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X37Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[101]/C clock pessimism 0.204 10.877 clock uncertainty -0.035 10.842 SLICE_X37Y565 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.749 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[101] ------------------------------------------------------------------- required time 10.749 arrival time -4.620 ------------------------------------------------------------------- slack 6.129 Slack (MET) : 6.129ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 1.908ns (logic 0.139ns (7.285%) route 1.769ns (92.715%)) Logic Levels: 0 Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.356ns = ( 10.673 - 8.317 ) Source Clock Delay (SCD): 2.712ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.802ns, distribution 1.485ns) Clock Net Delay (Destination): 1.980ns (routing 0.719ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.712 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X39Y544 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X39Y544 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.851 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.769 4.620 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X37Y565 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.980 10.673 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X37Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103]/C clock pessimism 0.204 10.877 clock uncertainty -0.035 10.842 SLICE_X37Y565 FDCE (Recov_AFF2_SLICEM_C_CLR) -0.093 10.749 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[103] ------------------------------------------------------------------- required time 10.749 arrival time -4.620 ------------------------------------------------------------------- slack 6.129 Slack (MET) : 6.129ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[119]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 1.908ns (logic 0.139ns (7.285%) route 1.769ns (92.715%)) Logic Levels: 0 Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.356ns = ( 10.673 - 8.317 ) Source Clock Delay (SCD): 2.712ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.802ns, distribution 1.485ns) Clock Net Delay (Destination): 1.980ns (routing 0.719ns, distribution 1.261ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.712 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X39Y544 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X39Y544 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.851 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.769 4.620 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X37Y565 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[119]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.980 10.673 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X37Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[119]/C clock pessimism 0.204 10.877 clock uncertainty -0.035 10.842 SLICE_X37Y565 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.749 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[119] ------------------------------------------------------------------- required time 10.749 arrival time -4.620 ------------------------------------------------------------------- slack 6.129 Slack (MET) : 6.137ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[52]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 1.899ns (logic 0.139ns (7.320%) route 1.760ns (92.680%)) Logic Levels: 0 Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.355ns = ( 10.672 - 8.317 ) Source Clock Delay (SCD): 2.712ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.802ns, distribution 1.485ns) Clock Net Delay (Destination): 1.979ns (routing 0.719ns, distribution 1.260ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.712 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X39Y544 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X39Y544 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.851 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.760 4.611 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X38Y565 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[52]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.979 10.672 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X38Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[52]/C clock pessimism 0.204 10.876 clock uncertainty -0.035 10.841 SLICE_X38Y565 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 10.748 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[52] ------------------------------------------------------------------- required time 10.748 arrival time -4.611 ------------------------------------------------------------------- slack 6.137 Slack (MET) : 6.137ns (required time - arrival time) Source: g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[52]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 1.899ns (logic 0.139ns (7.320%) route 1.760ns (92.680%)) Logic Levels: 0 Clock Path Skew: -0.153ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.355ns = ( 10.672 - 8.317 ) Source Clock Delay (SCD): 2.712ns Clock Pessimism Removal (CPR): 0.204ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.287ns (routing 0.802ns, distribution 1.485ns) Clock Net Delay (Destination): 1.979ns (routing 0.719ns, distribution 1.260ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.041 0.041 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.425 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 2.287 2.712 g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK SLICE_X39Y544 FDPE r g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X39Y544 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 2.851 f g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 1.760 4.611 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X38Y565 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[52]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.030 8.347 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.693 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.979 10.672 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X38Y565 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[52]/C clock pessimism 0.204 10.876 clock uncertainty -0.035 10.841 SLICE_X38Y565 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.748 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[52] ------------------------------------------------------------------- required time 10.748 arrival time -4.611 ------------------------------------------------------------------- slack 6.137 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.195ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.049ns (16.955%) route 0.240ns (83.045%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.233ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.886ns (routing 0.382ns, distribution 0.504ns) Clock Net Delay (Destination): 1.081ns (routing 0.446ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X41Y563 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y563 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.051 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.240 1.291 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X40Y562 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.081 1.233 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C clock pessimism -0.142 1.091 SLICE_X40Y562 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.096 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14] ------------------------------------------------------------------- required time -1.096 arrival time 1.291 ------------------------------------------------------------------- slack 0.195 Slack (MET) : 0.195ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.049ns (16.955%) route 0.240ns (83.045%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.233ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.886ns (routing 0.382ns, distribution 0.504ns) Clock Net Delay (Destination): 1.081ns (routing 0.446ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X41Y563 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y563 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.051 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.240 1.291 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X40Y562 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.081 1.233 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.142 1.091 SLICE_X40Y562 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.096 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.096 arrival time 1.291 ------------------------------------------------------------------- slack 0.195 Slack (MET) : 0.195ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.289ns (logic 0.049ns (16.955%) route 0.240ns (83.045%)) Logic Levels: 0 Clock Path Skew: 0.089ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.233ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.886ns (routing 0.382ns, distribution 0.504ns) Clock Net Delay (Destination): 1.081ns (routing 0.446ns, distribution 0.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X41Y563 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y563 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.051 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.240 1.291 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X40Y562 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.081 1.233 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism -0.142 1.091 SLICE_X40Y562 FDCE (Remov_FFF_SLICEL_C_CLR) 0.005 1.096 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time -1.096 arrival time 1.291 ------------------------------------------------------------------- slack 0.195 Slack (MET) : 0.198ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.249ns (logic 0.049ns (19.679%) route 0.200ns (80.321%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.223ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 0.886ns (routing 0.382ns, distribution 0.504ns) Clock Net Delay (Destination): 1.071ns (routing 0.446ns, distribution 0.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X41Y563 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y563 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.051 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.200 1.251 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X41Y562 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.071 1.223 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X41Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C clock pessimism -0.175 1.048 SLICE_X41Y562 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.053 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11] ------------------------------------------------------------------- required time -1.053 arrival time 1.251 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.198ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.249ns (logic 0.049ns (19.679%) route 0.200ns (80.321%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.223ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 0.886ns (routing 0.382ns, distribution 0.504ns) Clock Net Delay (Destination): 1.071ns (routing 0.446ns, distribution 0.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X41Y563 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y563 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.051 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.200 1.251 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X41Y562 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.071 1.223 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X41Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.175 1.048 SLICE_X41Y562 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.053 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.053 arrival time 1.251 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.198ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.249ns (logic 0.049ns (19.679%) route 0.200ns (80.321%)) Logic Levels: 0 Clock Path Skew: 0.046ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.223ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.175ns Clock Net Delay (Source): 0.886ns (routing 0.382ns, distribution 0.504ns) Clock Net Delay (Destination): 1.071ns (routing 0.446ns, distribution 0.625ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X41Y563 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y563 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.051 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.200 1.251 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X41Y562 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.071 1.223 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X41Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism -0.175 1.048 SLICE_X41Y562 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.053 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time -1.053 arrival time 1.251 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.198ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.295ns (logic 0.049ns (16.610%) route 0.246ns (83.390%)) Logic Levels: 0 Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.236ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.886ns (routing 0.382ns, distribution 0.504ns) Clock Net Delay (Destination): 1.084ns (routing 0.446ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X41Y563 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y563 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.051 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.246 1.297 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X40Y562 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.084 1.236 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism -0.142 1.094 SLICE_X40Y562 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.099 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time -1.099 arrival time 1.297 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.198ns (arrival time - required time) Source: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.295ns (logic 0.049ns (16.610%) route 0.246ns (83.390%)) Logic Levels: 0 Clock Path Skew: 0.092ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.236ns Source Clock Delay (SCD): 1.002ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.886ns (routing 0.382ns, distribution 0.504ns) Clock Net Delay (Destination): 1.084ns (routing 0.446ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.886 1.002 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK SLICE_X41Y563 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X41Y563 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.051 r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.246 1.297 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X40Y562 FDCE f g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.084 1.236 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X40Y562 FDCE r g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism -0.142 1.094 SLICE_X40Y562 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.099 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time -1.099 arrival time 1.297 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.211ns (arrival time - required time) Source: SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.302ns (logic 0.048ns (15.894%) route 0.254ns (84.106%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.246ns Source Clock Delay (SCD): 1.018ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.902ns (routing 0.382ns, distribution 0.520ns) Clock Net Delay (Destination): 1.094ns (routing 0.446ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.902 1.018 SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X38Y562 FDPE r SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y562 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.066 f SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.254 1.320 SFP_GEN[45].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y561 FDCE f SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.094 1.246 SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y561 FDCE r SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.142 1.104 SLICE_X39Y561 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.109 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -1.109 arrival time 1.320 ------------------------------------------------------------------- slack 0.211 Slack (MET) : 0.211ns (arrival time - required time) Source: SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns) Data Path Delay: 0.302ns (logic 0.048ns (15.894%) route 0.254ns (84.106%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.246ns Source Clock Delay (SCD): 1.018ns Clock Pessimism Removal (CPR): 0.142ns Clock Net Delay (Source): 0.902ns (routing 0.382ns, distribution 0.520ns) Clock Net Delay (Destination): 1.094ns (routing 0.446ns, distribution 0.648ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.016 0.016 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.116 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 0.902 1.018 SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X38Y562 FDPE r SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y562 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.066 f SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.254 1.320 SFP_GEN[45].ngCCM_gbt/sync_m_reg[3][0] SLICE_X39Y561 FDCE f SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X0Y37 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.022 0.022 g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X0Y239 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.152 r g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X1Y9 (CLOCK_ROOT) net (fo=674, routed) 1.094 1.246 SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X39Y561 FDCE r SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/C clock pessimism -0.142 1.104 SLICE_X39Y561 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.109 SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34] ------------------------------------------------------------------- required time -1.109 arrival time 1.320 ------------------------------------------------------------------- slack 0.211 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_5 To Clock: gtwiz_userclk_rx_srcclk_out[0]_5 Setup : 0 Failing Endpoints, Worst Slack 3.482ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.187ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.482ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.958ns (logic 0.383ns (9.677%) route 3.575ns (90.323%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.749ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.816ns = ( 11.133 - 8.317 ) Source Clock Delay (SCD): 3.834ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.359ns (routing 1.207ns, distribution 2.152ns) Clock Net Delay (Destination): 2.418ns (routing 1.098ns, distribution 1.320ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.359 3.834 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y102 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y102 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.973 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.862 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y107 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 7.079 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 0.713 7.792 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X86Y114 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.418 11.133 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X86Y114 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C clock pessimism 0.269 11.403 clock uncertainty -0.035 11.367 SLICE_X86Y114 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.274 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4] ------------------------------------------------------------------- required time 11.274 arrival time -7.792 ------------------------------------------------------------------- slack 3.482 Slack (MET) : 3.482ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.958ns (logic 0.383ns (9.677%) route 3.575ns (90.323%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.749ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.816ns = ( 11.133 - 8.317 ) Source Clock Delay (SCD): 3.834ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.359ns (routing 1.207ns, distribution 2.152ns) Clock Net Delay (Destination): 2.418ns (routing 1.098ns, distribution 1.320ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.359 3.834 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y102 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y102 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.973 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.862 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y107 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 7.079 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 0.713 7.792 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X86Y114 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.418 11.133 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X86Y114 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C clock pessimism 0.269 11.403 clock uncertainty -0.035 11.367 SLICE_X86Y114 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.274 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5] ------------------------------------------------------------------- required time 11.274 arrival time -7.792 ------------------------------------------------------------------- slack 3.482 Slack (MET) : 3.482ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.958ns (logic 0.383ns (9.677%) route 3.575ns (90.323%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.749ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.816ns = ( 11.133 - 8.317 ) Source Clock Delay (SCD): 3.834ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.359ns (routing 1.207ns, distribution 2.152ns) Clock Net Delay (Destination): 2.418ns (routing 1.098ns, distribution 1.320ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.359 3.834 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y102 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y102 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.973 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.862 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y107 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 7.079 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 0.713 7.792 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X86Y114 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.418 11.133 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X86Y114 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C clock pessimism 0.269 11.403 clock uncertainty -0.035 11.367 SLICE_X86Y114 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.274 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7] ------------------------------------------------------------------- required time 11.274 arrival time -7.792 ------------------------------------------------------------------- slack 3.482 Slack (MET) : 3.490ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.948ns (logic 0.383ns (9.701%) route 3.565ns (90.299%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.751ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.814ns = ( 11.131 - 8.317 ) Source Clock Delay (SCD): 3.834ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.359ns (routing 1.207ns, distribution 2.152ns) Clock Net Delay (Destination): 2.416ns (routing 1.098ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.359 3.834 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y102 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y102 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.973 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.862 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y107 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 7.079 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 0.703 7.782 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X86Y114 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.416 11.131 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X86Y114 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C clock pessimism 0.269 11.401 clock uncertainty -0.035 11.365 SLICE_X86Y114 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.272 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6] ------------------------------------------------------------------- required time 11.272 arrival time -7.782 ------------------------------------------------------------------- slack 3.490 Slack (MET) : 3.568ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.872ns (logic 0.383ns (9.892%) route 3.489ns (90.108%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.749ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.816ns = ( 11.133 - 8.317 ) Source Clock Delay (SCD): 3.834ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.359ns (routing 1.207ns, distribution 2.152ns) Clock Net Delay (Destination): 2.418ns (routing 1.098ns, distribution 1.320ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.359 3.834 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y102 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y102 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.973 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.862 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y107 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 7.079 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 0.627 7.706 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X86Y112 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.418 11.133 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X86Y112 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C clock pessimism 0.269 11.403 clock uncertainty -0.035 11.367 SLICE_X86Y112 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.274 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1] ------------------------------------------------------------------- required time 11.274 arrival time -7.706 ------------------------------------------------------------------- slack 3.568 Slack (MET) : 3.568ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.872ns (logic 0.383ns (9.892%) route 3.489ns (90.108%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.749ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.816ns = ( 11.133 - 8.317 ) Source Clock Delay (SCD): 3.834ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.359ns (routing 1.207ns, distribution 2.152ns) Clock Net Delay (Destination): 2.418ns (routing 1.098ns, distribution 1.320ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.359 3.834 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y102 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y102 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.973 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.862 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y107 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 7.079 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 0.627 7.706 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X86Y112 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.418 11.133 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X86Y112 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C clock pessimism 0.269 11.403 clock uncertainty -0.035 11.367 SLICE_X86Y112 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 11.274 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2] ------------------------------------------------------------------- required time 11.274 arrival time -7.706 ------------------------------------------------------------------- slack 3.568 Slack (MET) : 3.568ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.872ns (logic 0.383ns (9.892%) route 3.489ns (90.108%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.749ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.816ns = ( 11.133 - 8.317 ) Source Clock Delay (SCD): 3.834ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.359ns (routing 1.207ns, distribution 2.152ns) Clock Net Delay (Destination): 2.418ns (routing 1.098ns, distribution 1.320ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.359 3.834 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y102 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y102 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.973 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.862 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y107 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 7.079 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 0.627 7.706 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X86Y112 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.418 11.133 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X86Y112 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C clock pessimism 0.269 11.403 clock uncertainty -0.035 11.367 SLICE_X86Y112 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.274 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3] ------------------------------------------------------------------- required time 11.274 arrival time -7.706 ------------------------------------------------------------------- slack 3.568 Slack (MET) : 3.576ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.862ns (logic 0.383ns (9.917%) route 3.479ns (90.083%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.751ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.814ns = ( 11.131 - 8.317 ) Source Clock Delay (SCD): 3.834ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.359ns (routing 1.207ns, distribution 2.152ns) Clock Net Delay (Destination): 2.416ns (routing 1.098ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.359 3.834 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y102 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y102 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.973 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.862 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y107 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 7.079 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 0.617 7.696 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X86Y112 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.416 11.131 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X86Y112 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C clock pessimism 0.269 11.401 clock uncertainty -0.035 11.365 SLICE_X86Y112 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 11.272 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3] ------------------------------------------------------------------- required time 11.272 arrival time -7.696 ------------------------------------------------------------------- slack 3.576 Slack (MET) : 3.576ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.862ns (logic 0.383ns (9.917%) route 3.479ns (90.083%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.751ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.814ns = ( 11.131 - 8.317 ) Source Clock Delay (SCD): 3.834ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.359ns (routing 1.207ns, distribution 2.152ns) Clock Net Delay (Destination): 2.416ns (routing 1.098ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.359 3.834 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y102 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y102 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.973 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.862 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y107 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 7.079 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 0.617 7.696 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X86Y112 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.416 11.131 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X86Y112 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C clock pessimism 0.269 11.401 clock uncertainty -0.035 11.365 SLICE_X86Y112 FDCE (Recov_HFF2_SLICEL_C_CLR) -0.093 11.272 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0] ------------------------------------------------------------------- required time 11.272 arrival time -7.696 ------------------------------------------------------------------- slack 3.576 Slack (MET) : 3.576ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 3.862ns (logic 0.383ns (9.917%) route 3.479ns (90.083%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.751ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.814ns = ( 11.131 - 8.317 ) Source Clock Delay (SCD): 3.834ns Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 3.359ns (routing 1.207ns, distribution 2.152ns) Clock Net Delay (Destination): 2.416ns (routing 1.098ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 3.359 3.834 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X135Y102 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y102 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.973 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.862 6.835 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X87Y107 LUT3 (Prop_D6LUT_SLICEM_I0_O) 0.244 7.079 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/O net (fo=15, routed) 0.617 7.696 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3]0 SLICE_X86Y112 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 2.416 11.131 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] SLICE_X86Y112 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/C clock pessimism 0.269 11.401 clock uncertainty -0.035 11.365 SLICE_X86Y112 FDCE (Recov_GFF_SLICEL_C_CLR) -0.093 11.272 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0] ------------------------------------------------------------------- required time 11.272 arrival time -7.696 ------------------------------------------------------------------- slack 3.576 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.187ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.049ns (21.304%) route 0.181ns (78.696%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.418ns Source Clock Delay (SCD): 1.188ns Clock Pessimism Removal (CPR): 0.192ns Clock Net Delay (Source): 1.070ns (routing 0.527ns, distribution 0.543ns) Clock Net Delay (Destination): 1.253ns (routing 0.593ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.070 1.188 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X85Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X85Y101 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.237 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.181 1.418 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X85Y99 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.253 1.418 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/CLK SLICE_X85Y99 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.192 1.226 SLICE_X85Y99 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.231 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -1.231 arrival time 1.418 ------------------------------------------------------------------- slack 0.187 Slack (MET) : 0.187ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.049ns (21.304%) route 0.181ns (78.696%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.418ns Source Clock Delay (SCD): 1.188ns Clock Pessimism Removal (CPR): 0.192ns Clock Net Delay (Source): 1.070ns (routing 0.527ns, distribution 0.543ns) Clock Net Delay (Destination): 1.253ns (routing 0.593ns, distribution 0.660ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.070 1.188 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X85Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X85Y101 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.237 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.181 1.418 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X85Y99 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.253 1.418 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/CLK SLICE_X85Y99 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.192 1.226 SLICE_X85Y99 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.231 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.231 arrival time 1.418 ------------------------------------------------------------------- slack 0.187 Slack (MET) : 0.189ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.267ns (logic 0.049ns (18.352%) route 0.218ns (81.648%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.417ns Source Clock Delay (SCD): 1.188ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.070ns (routing 0.527ns, distribution 0.543ns) Clock Net Delay (Destination): 1.252ns (routing 0.593ns, distribution 0.659ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.070 1.188 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X85Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X85Y101 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.237 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.218 1.455 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X83Y104 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.252 1.417 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X83Y104 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C clock pessimism -0.156 1.261 SLICE_X83Y104 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.266 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13] ------------------------------------------------------------------- required time -1.266 arrival time 1.455 ------------------------------------------------------------------- slack 0.189 Slack (MET) : 0.189ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.267ns (logic 0.049ns (18.352%) route 0.218ns (81.648%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.417ns Source Clock Delay (SCD): 1.188ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.070ns (routing 0.527ns, distribution 0.543ns) Clock Net Delay (Destination): 1.252ns (routing 0.593ns, distribution 0.659ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.070 1.188 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X85Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X85Y101 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.237 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.218 1.455 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X83Y104 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.252 1.417 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X83Y104 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C clock pessimism -0.156 1.261 SLICE_X83Y104 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.266 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15] ------------------------------------------------------------------- required time -1.266 arrival time 1.455 ------------------------------------------------------------------- slack 0.189 Slack (MET) : 0.189ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.267ns (logic 0.049ns (18.352%) route 0.218ns (81.648%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.417ns Source Clock Delay (SCD): 1.188ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 1.070ns (routing 0.527ns, distribution 0.543ns) Clock Net Delay (Destination): 1.252ns (routing 0.593ns, distribution 0.659ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.070 1.188 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X85Y101 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X85Y101 FDCE (Prop_DFF2_SLICEM_C_Q) 0.049 1.237 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.218 1.455 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X83Y104 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.252 1.417 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X83Y104 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.156 1.261 SLICE_X83Y104 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.266 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.266 arrival time 1.455 ------------------------------------------------------------------- slack 0.189 Slack (MET) : 0.199ns (arrival time - required time) Source: SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.251ns (logic 0.048ns (19.123%) route 0.203ns (80.876%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.401ns Source Clock Delay (SCD): 1.164ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.046ns (routing 0.527ns, distribution 0.519ns) Clock Net Delay (Destination): 1.236ns (routing 0.593ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.046 1.164 SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y100 FDPE r SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y100 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.212 f SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.203 1.415 SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] SLICE_X79Y98 FDCE f SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.236 1.401 SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y98 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[81]/C clock pessimism -0.190 1.211 SLICE_X79Y98 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.216 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[81] ------------------------------------------------------------------- required time -1.216 arrival time 1.415 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.199ns (arrival time - required time) Source: SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.251ns (logic 0.048ns (19.123%) route 0.203ns (80.876%)) Logic Levels: 0 Clock Path Skew: 0.047ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.401ns Source Clock Delay (SCD): 1.164ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.046ns (routing 0.527ns, distribution 0.519ns) Clock Net Delay (Destination): 1.236ns (routing 0.593ns, distribution 0.643ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.046 1.164 SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y100 FDPE r SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y100 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.212 f SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.203 1.415 SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] SLICE_X79Y98 FDCE f SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.236 1.401 SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y98 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]/C clock pessimism -0.190 1.211 SLICE_X79Y98 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.216 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83] ------------------------------------------------------------------- required time -1.216 arrival time 1.415 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.201ns (arrival time - required time) Source: SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.048ns (18.750%) route 0.208ns (81.250%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.404ns Source Clock Delay (SCD): 1.164ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.046ns (routing 0.527ns, distribution 0.519ns) Clock Net Delay (Destination): 1.239ns (routing 0.593ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.046 1.164 SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y100 FDPE r SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y100 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.212 f SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.208 1.420 SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] SLICE_X80Y98 FDCE f SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.239 1.404 SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y98 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.190 1.214 SLICE_X80Y98 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.219 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.219 arrival time 1.420 ------------------------------------------------------------------- slack 0.201 Slack (MET) : 0.201ns (arrival time - required time) Source: SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.048ns (18.750%) route 0.208ns (81.250%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.404ns Source Clock Delay (SCD): 1.164ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.046ns (routing 0.527ns, distribution 0.519ns) Clock Net Delay (Destination): 1.239ns (routing 0.593ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.046 1.164 SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y100 FDPE r SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y100 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.212 f SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.208 1.420 SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] SLICE_X80Y98 FDCE f SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.239 1.404 SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y98 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.190 1.214 SLICE_X80Y98 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 1.219 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -1.219 arrival time 1.420 ------------------------------------------------------------------- slack 0.201 Slack (MET) : 0.201ns (arrival time - required time) Source: SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.048ns (18.750%) route 0.208ns (81.250%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.404ns Source Clock Delay (SCD): 1.164ns Clock Pessimism Removal (CPR): 0.190ns Clock Net Delay (Source): 1.046ns (routing 0.527ns, distribution 0.519ns) Clock Net Delay (Destination): 1.239ns (routing 0.593ns, distribution 0.646ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.046 1.164 SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y100 FDPE r SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y100 FDPE (Prop_GFF2_SLICEL_C_Q) 0.048 1.212 f SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.208 1.420 SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] SLICE_X80Y98 FDCE f SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y7 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y27 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X3Y1 (CLOCK_ROOT) net (fo=674, routed) 1.239 1.404 SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X80Y98 FDCE r SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[40]/C clock pessimism -0.190 1.214 SLICE_X80Y98 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.219 SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[40] ------------------------------------------------------------------- required time -1.219 arrival time 1.420 ------------------------------------------------------------------- slack 0.201 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_6 To Clock: gtwiz_userclk_rx_srcclk_out[0]_6 Setup : 0 Failing Endpoints, Worst Slack 4.129ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.128ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.129ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 4.043ns (logic 0.383ns (9.473%) route 3.660ns (90.527%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.657ns = ( 10.974 - 8.317 ) Source Clock Delay (SCD): 2.898ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.423ns (routing 0.718ns, distribution 1.705ns) Clock Net Delay (Destination): 2.259ns (routing 0.653ns, distribution 1.606ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.423 2.898 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.969 6.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y134 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.244 6.250 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.691 6.941 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X88Y135 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.259 10.974 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X88Y135 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C clock pessimism 0.225 11.199 clock uncertainty -0.035 11.163 SLICE_X88Y135 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.070 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4] ------------------------------------------------------------------- required time 11.070 arrival time -6.941 ------------------------------------------------------------------- slack 4.129 Slack (MET) : 4.194ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.981ns (logic 0.383ns (9.621%) route 3.598ns (90.379%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.660ns = ( 10.977 - 8.317 ) Source Clock Delay (SCD): 2.898ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.423ns (routing 0.718ns, distribution 1.705ns) Clock Net Delay (Destination): 2.262ns (routing 0.653ns, distribution 1.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.423 2.898 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.969 6.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y134 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.244 6.250 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.629 6.879 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X89Y133 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.262 10.977 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X89Y133 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/C clock pessimism 0.225 11.202 clock uncertainty -0.035 11.166 SLICE_X89Y133 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.073 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1] ------------------------------------------------------------------- required time 11.073 arrival time -6.879 ------------------------------------------------------------------- slack 4.194 Slack (MET) : 4.194ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.981ns (logic 0.383ns (9.621%) route 3.598ns (90.379%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.660ns = ( 10.977 - 8.317 ) Source Clock Delay (SCD): 2.898ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.423ns (routing 0.718ns, distribution 1.705ns) Clock Net Delay (Destination): 2.262ns (routing 0.653ns, distribution 1.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.423 2.898 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.969 6.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y134 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.244 6.250 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.629 6.879 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X89Y133 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.262 10.977 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X89Y133 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/C clock pessimism 0.225 11.202 clock uncertainty -0.035 11.166 SLICE_X89Y133 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.073 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2] ------------------------------------------------------------------- required time 11.073 arrival time -6.879 ------------------------------------------------------------------- slack 4.194 Slack (MET) : 4.194ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.981ns (logic 0.383ns (9.621%) route 3.598ns (90.379%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.660ns = ( 10.977 - 8.317 ) Source Clock Delay (SCD): 2.898ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.423ns (routing 0.718ns, distribution 1.705ns) Clock Net Delay (Destination): 2.262ns (routing 0.653ns, distribution 1.609ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.423 2.898 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.969 6.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y134 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.244 6.250 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.629 6.879 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X89Y133 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.262 10.977 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X89Y133 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/C clock pessimism 0.225 11.202 clock uncertainty -0.035 11.166 SLICE_X89Y133 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.073 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4] ------------------------------------------------------------------- required time 11.073 arrival time -6.879 ------------------------------------------------------------------- slack 4.194 Slack (MET) : 4.199ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.974ns (logic 0.383ns (9.638%) route 3.591ns (90.362%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.658ns = ( 10.975 - 8.317 ) Source Clock Delay (SCD): 2.898ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.423ns (routing 0.718ns, distribution 1.705ns) Clock Net Delay (Destination): 2.260ns (routing 0.653ns, distribution 1.607ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.423 2.898 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.969 6.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y134 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.244 6.250 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.622 6.872 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X89Y133 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.260 10.975 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X89Y133 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/C clock pessimism 0.225 11.200 clock uncertainty -0.035 11.164 SLICE_X89Y133 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.071 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3] ------------------------------------------------------------------- required time 11.071 arrival time -6.872 ------------------------------------------------------------------- slack 4.199 Slack (MET) : 4.202ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.971ns (logic 0.383ns (9.645%) route 3.588ns (90.355%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.658ns = ( 10.975 - 8.317 ) Source Clock Delay (SCD): 2.898ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.423ns (routing 0.718ns, distribution 1.705ns) Clock Net Delay (Destination): 2.260ns (routing 0.653ns, distribution 1.607ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.423 2.898 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.969 6.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y134 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.244 6.250 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.619 6.869 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X89Y136 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.260 10.975 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X89Y136 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C clock pessimism 0.225 11.200 clock uncertainty -0.035 11.164 SLICE_X89Y136 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.071 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1] ------------------------------------------------------------------- required time 11.071 arrival time -6.869 ------------------------------------------------------------------- slack 4.202 Slack (MET) : 4.202ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.971ns (logic 0.383ns (9.645%) route 3.588ns (90.355%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.658ns = ( 10.975 - 8.317 ) Source Clock Delay (SCD): 2.898ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.423ns (routing 0.718ns, distribution 1.705ns) Clock Net Delay (Destination): 2.260ns (routing 0.653ns, distribution 1.607ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.423 2.898 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.969 6.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y134 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.244 6.250 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.619 6.869 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X89Y136 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.260 10.975 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X89Y136 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C clock pessimism 0.225 11.200 clock uncertainty -0.035 11.164 SLICE_X89Y136 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.071 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2] ------------------------------------------------------------------- required time 11.071 arrival time -6.869 ------------------------------------------------------------------- slack 4.202 Slack (MET) : 4.202ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.971ns (logic 0.383ns (9.645%) route 3.588ns (90.355%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.658ns = ( 10.975 - 8.317 ) Source Clock Delay (SCD): 2.898ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.423ns (routing 0.718ns, distribution 1.705ns) Clock Net Delay (Destination): 2.260ns (routing 0.653ns, distribution 1.607ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.423 2.898 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.969 6.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y134 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.244 6.250 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.619 6.869 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X89Y136 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.260 10.975 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X89Y136 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C clock pessimism 0.225 11.200 clock uncertainty -0.035 11.164 SLICE_X89Y136 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.071 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3] ------------------------------------------------------------------- required time 11.071 arrival time -6.869 ------------------------------------------------------------------- slack 4.202 Slack (MET) : 4.207ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.964ns (logic 0.383ns (9.662%) route 3.581ns (90.338%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.656ns = ( 10.973 - 8.317 ) Source Clock Delay (SCD): 2.898ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.423ns (routing 0.718ns, distribution 1.705ns) Clock Net Delay (Destination): 2.258ns (routing 0.653ns, distribution 1.605ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.423 2.898 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.969 6.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y134 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.244 6.250 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.612 6.862 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X89Y136 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.258 10.973 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X89Y136 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C clock pessimism 0.225 11.198 clock uncertainty -0.035 11.162 SLICE_X89Y136 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.069 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4] ------------------------------------------------------------------- required time 11.069 arrival time -6.862 ------------------------------------------------------------------- slack 4.207 Slack (MET) : 4.207ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 3.964ns (logic 0.383ns (9.662%) route 3.581ns (90.338%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.656ns = ( 10.973 - 8.317 ) Source Clock Delay (SCD): 2.898ns Clock Pessimism Removal (CPR): 0.225ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.423ns (routing 0.718ns, distribution 1.705ns) Clock Net Delay (Destination): 2.258ns (routing 0.653ns, distribution 1.605ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.423 2.898 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y142 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.037 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.969 6.006 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X90Y134 LUT3 (Prop_H6LUT_SLICEM_I0_O) 0.244 6.250 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/O net (fo=15, routed) 0.612 6.862 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4]0 SLICE_X89Y136 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.258 10.973 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] SLICE_X89Y136 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C clock pessimism 0.225 11.198 clock uncertainty -0.035 11.162 SLICE_X89Y136 FDCE (Recov_EFF_SLICEM_C_CLR) -0.093 11.069 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0] ------------------------------------------------------------------- required time 11.069 arrival time -6.862 ------------------------------------------------------------------- slack 4.207 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.128ns (arrival time - required time) Source: SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.208ns (logic 0.048ns (23.077%) route 0.160ns (76.923%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.983ns (routing 0.305ns, distribution 0.678ns) Clock Net Delay (Destination): 1.162ns (routing 0.344ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.101 SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y123 FDPE r SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y123 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.149 f SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.160 1.309 SFP_GEN[4].ngCCM_gbt/sync_m_reg[3][0] SLICE_X85Y123 FDCE f SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.327 SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y123 FDCE r SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[4]/C clock pessimism -0.151 1.176 SLICE_X85Y123 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.181 SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[4] ------------------------------------------------------------------- required time -1.181 arrival time 1.309 ------------------------------------------------------------------- slack 0.128 Slack (MET) : 0.128ns (arrival time - required time) Source: SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.208ns (logic 0.048ns (23.077%) route 0.160ns (76.923%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.983ns (routing 0.305ns, distribution 0.678ns) Clock Net Delay (Destination): 1.162ns (routing 0.344ns, distribution 0.818ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.101 SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y123 FDPE r SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y123 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.149 f SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.160 1.309 SFP_GEN[4].ngCCM_gbt/sync_m_reg[3][0] SLICE_X85Y123 FDCE f SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.327 SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X85Y123 FDCE r SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6]/C clock pessimism -0.151 1.176 SLICE_X85Y123 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.181 SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[6] ------------------------------------------------------------------- required time -1.181 arrival time 1.309 ------------------------------------------------------------------- slack 0.128 Slack (MET) : 0.170ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[24]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.049ns (18.774%) route 0.212ns (81.226%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.319ns Source Clock Delay (SCD): 1.081ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 0.963ns (routing 0.305ns, distribution 0.658ns) Clock Net Delay (Destination): 1.154ns (routing 0.344ns, distribution 0.810ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.963 1.081 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X92Y120 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y120 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.130 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.212 1.342 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X91Y122 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.154 1.319 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X91Y122 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[24]/C clock pessimism -0.152 1.167 SLICE_X91Y122 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.172 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[24] ------------------------------------------------------------------- required time -1.172 arrival time 1.342 ------------------------------------------------------------------- slack 0.170 Slack (MET) : 0.178ns (arrival time - required time) Source: SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.048ns (18.251%) route 0.215ns (81.749%)) Logic Levels: 0 Clock Path Skew: 0.080ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.332ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.151ns Clock Net Delay (Source): 0.983ns (routing 0.305ns, distribution 0.678ns) Clock Net Delay (Destination): 1.167ns (routing 0.344ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.101 SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y123 FDPE r SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y123 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.149 f SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.215 1.364 SFP_GEN[4].ngCCM_gbt/sync_m_reg[3][0] SLICE_X81Y125 FDCE f SFP_GEN[4].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.167 1.332 SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X81Y125 FDCE r SFP_GEN[4].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.151 1.181 SLICE_X81Y125 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.186 SFP_GEN[4].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.186 arrival time 1.364 ------------------------------------------------------------------- slack 0.178 Slack (MET) : 0.198ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.049ns (18.216%) route 0.220ns (81.784%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.306ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 0.970ns (routing 0.305ns, distribution 0.665ns) Clock Net Delay (Destination): 1.141ns (routing 0.344ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.970 1.088 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X89Y128 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y128 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.137 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.220 1.357 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X90Y126 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.141 1.306 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/CLK SLICE_X90Y126 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.152 1.154 SLICE_X90Y126 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.159 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -1.159 arrival time 1.357 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.198ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.049ns (18.216%) route 0.220ns (81.784%)) Logic Levels: 0 Clock Path Skew: 0.066ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.306ns Source Clock Delay (SCD): 1.088ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 0.970ns (routing 0.305ns, distribution 0.665ns) Clock Net Delay (Destination): 1.141ns (routing 0.344ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.970 1.088 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X89Y128 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y128 FDCE (Prop_EFF_SLICEM_C_Q) 0.049 1.137 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.220 1.357 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X90Y126 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.141 1.306 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/CLK SLICE_X90Y126 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism -0.152 1.154 SLICE_X90Y126 FDCE (Remov_DFF2_SLICEM_C_CLR) 0.005 1.159 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time -1.159 arrival time 1.357 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.201ns (arrival time - required time) Source: SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.264ns (logic 0.048ns (18.182%) route 0.216ns (81.818%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.311ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 0.983ns (routing 0.305ns, distribution 0.678ns) Clock Net Delay (Destination): 1.146ns (routing 0.344ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.101 SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y123 FDPE r SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y123 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.149 f SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.216 1.365 SFP_GEN[4].ngCCM_gbt/sync_m_reg[3][0] SLICE_X89Y123 FDCE f SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.146 1.311 SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y123 FDCE r SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[56]/C clock pessimism -0.152 1.159 SLICE_X89Y123 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.164 SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[56] ------------------------------------------------------------------- required time -1.164 arrival time 1.365 ------------------------------------------------------------------- slack 0.201 Slack (MET) : 0.201ns (arrival time - required time) Source: SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.264ns (logic 0.048ns (18.182%) route 0.216ns (81.818%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.311ns Source Clock Delay (SCD): 1.101ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 0.983ns (routing 0.305ns, distribution 0.678ns) Clock Net Delay (Destination): 1.146ns (routing 0.344ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.983 1.101 SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X82Y123 FDPE r SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y123 FDPE (Prop_GFF2_SLICEM_C_Q) 0.048 1.149 f SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.216 1.365 SFP_GEN[4].ngCCM_gbt/sync_m_reg[3][0] SLICE_X89Y123 FDCE f SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.146 1.311 SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X89Y123 FDCE r SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[58]/C clock pessimism -0.152 1.159 SLICE_X89Y123 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.164 SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[58] ------------------------------------------------------------------- required time -1.164 arrival time 1.365 ------------------------------------------------------------------- slack 0.201 Slack (MET) : 0.209ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.306ns Source Clock Delay (SCD): 1.081ns Clock Pessimism Removal (CPR): 0.176ns Clock Net Delay (Source): 0.963ns (routing 0.305ns, distribution 0.658ns) Clock Net Delay (Destination): 1.141ns (routing 0.344ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.963 1.081 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X92Y120 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y120 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.130 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.214 1.344 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X93Y121 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.141 1.306 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X93Y121 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[8]/C clock pessimism -0.176 1.130 SLICE_X93Y121 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.135 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[8] ------------------------------------------------------------------- required time -1.135 arrival time 1.344 ------------------------------------------------------------------- slack 0.209 Slack (MET) : 0.212ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.049ns (16.667%) route 0.245ns (83.333%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.310ns Source Clock Delay (SCD): 1.081ns Clock Pessimism Removal (CPR): 0.152ns Clock Net Delay (Source): 0.963ns (routing 0.305ns, distribution 0.658ns) Clock Net Delay (Destination): 1.145ns (routing 0.344ns, distribution 0.801ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.963 1.081 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X92Y120 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X92Y120 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 1.130 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.245 1.375 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X91Y123 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y8 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y57 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.145 1.310 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X91Y123 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]/C clock pessimism -0.152 1.158 SLICE_X91Y123 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.163 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32] ------------------------------------------------------------------- required time -1.163 arrival time 1.375 ------------------------------------------------------------------- slack 0.212 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_7 To Clock: gtwiz_userclk_rx_srcclk_out[0]_7 Setup : 0 Failing Endpoints, Worst Slack 4.748ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.175ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.748ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 3.409ns (logic 0.305ns (8.947%) route 3.104ns (91.053%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.699ns = ( 11.016 - 8.317 ) Source Clock Delay (SCD): 2.957ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.482ns (routing 0.732ns, distribution 1.750ns) Clock Net Delay (Destination): 2.301ns (routing 0.665ns, distribution 1.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.482 2.957 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y144 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y144 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.253 5.349 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X80Y147 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.515 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.851 6.366 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X83Y142 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 11.016 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X83Y142 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C clock pessimism 0.226 11.242 clock uncertainty -0.035 11.207 SLICE_X83Y142 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1] ------------------------------------------------------------------- required time 11.114 arrival time -6.366 ------------------------------------------------------------------- slack 4.748 Slack (MET) : 4.748ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 3.409ns (logic 0.305ns (8.947%) route 3.104ns (91.053%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.699ns = ( 11.016 - 8.317 ) Source Clock Delay (SCD): 2.957ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.482ns (routing 0.732ns, distribution 1.750ns) Clock Net Delay (Destination): 2.301ns (routing 0.665ns, distribution 1.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.482 2.957 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y144 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y144 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.253 5.349 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X80Y147 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.515 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.851 6.366 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X83Y142 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 11.016 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X83Y142 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C clock pessimism 0.226 11.242 clock uncertainty -0.035 11.207 SLICE_X83Y142 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2] ------------------------------------------------------------------- required time 11.114 arrival time -6.366 ------------------------------------------------------------------- slack 4.748 Slack (MET) : 4.748ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 3.409ns (logic 0.305ns (8.947%) route 3.104ns (91.053%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.699ns = ( 11.016 - 8.317 ) Source Clock Delay (SCD): 2.957ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.482ns (routing 0.732ns, distribution 1.750ns) Clock Net Delay (Destination): 2.301ns (routing 0.665ns, distribution 1.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.482 2.957 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y144 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y144 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.253 5.349 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X80Y147 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.515 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.851 6.366 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X83Y142 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 11.016 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X83Y142 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C clock pessimism 0.226 11.242 clock uncertainty -0.035 11.207 SLICE_X83Y142 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3] ------------------------------------------------------------------- required time 11.114 arrival time -6.366 ------------------------------------------------------------------- slack 4.748 Slack (MET) : 4.748ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 3.409ns (logic 0.305ns (8.947%) route 3.104ns (91.053%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.699ns = ( 11.016 - 8.317 ) Source Clock Delay (SCD): 2.957ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.482ns (routing 0.732ns, distribution 1.750ns) Clock Net Delay (Destination): 2.301ns (routing 0.665ns, distribution 1.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.482 2.957 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y144 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y144 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.253 5.349 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X80Y147 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.515 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.851 6.366 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X83Y142 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 11.016 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X83Y142 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C clock pessimism 0.226 11.242 clock uncertainty -0.035 11.207 SLICE_X83Y142 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4] ------------------------------------------------------------------- required time 11.114 arrival time -6.366 ------------------------------------------------------------------- slack 4.748 Slack (MET) : 4.949ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 3.201ns (logic 0.305ns (9.528%) route 2.896ns (90.472%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.039ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.692ns = ( 11.009 - 8.317 ) Source Clock Delay (SCD): 2.957ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.482ns (routing 0.732ns, distribution 1.750ns) Clock Net Delay (Destination): 2.294ns (routing 0.665ns, distribution 1.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.482 2.957 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y144 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y144 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.253 5.349 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X80Y147 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.515 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.643 6.158 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X81Y144 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 11.009 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X81Y144 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C clock pessimism 0.226 11.235 clock uncertainty -0.035 11.200 SLICE_X81Y144 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.107 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0] ------------------------------------------------------------------- required time 11.107 arrival time -6.158 ------------------------------------------------------------------- slack 4.949 Slack (MET) : 4.949ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 3.201ns (logic 0.305ns (9.528%) route 2.896ns (90.472%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.039ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.692ns = ( 11.009 - 8.317 ) Source Clock Delay (SCD): 2.957ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.482ns (routing 0.732ns, distribution 1.750ns) Clock Net Delay (Destination): 2.294ns (routing 0.665ns, distribution 1.629ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.482 2.957 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y144 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y144 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.253 5.349 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X80Y147 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.515 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.643 6.158 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X81Y144 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.294 11.009 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X81Y144 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/C clock pessimism 0.226 11.235 clock uncertainty -0.035 11.200 SLICE_X81Y144 FDCE (Recov_EFF2_SLICEL_C_CLR) -0.093 11.107 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5] ------------------------------------------------------------------- required time 11.107 arrival time -6.158 ------------------------------------------------------------------- slack 4.949 Slack (MET) : 5.026ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 3.131ns (logic 0.305ns (9.741%) route 2.826ns (90.259%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.699ns = ( 11.016 - 8.317 ) Source Clock Delay (SCD): 2.957ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.482ns (routing 0.732ns, distribution 1.750ns) Clock Net Delay (Destination): 2.301ns (routing 0.665ns, distribution 1.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.482 2.957 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y144 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y144 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.253 5.349 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X80Y147 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.515 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.573 6.088 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X81Y146 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 11.016 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X81Y146 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C clock pessimism 0.226 11.242 clock uncertainty -0.035 11.207 SLICE_X81Y146 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3] ------------------------------------------------------------------- required time 11.114 arrival time -6.088 ------------------------------------------------------------------- slack 5.026 Slack (MET) : 5.026ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 3.131ns (logic 0.305ns (9.741%) route 2.826ns (90.259%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.699ns = ( 11.016 - 8.317 ) Source Clock Delay (SCD): 2.957ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.482ns (routing 0.732ns, distribution 1.750ns) Clock Net Delay (Destination): 2.301ns (routing 0.665ns, distribution 1.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.482 2.957 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y144 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y144 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.253 5.349 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X80Y147 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.515 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.573 6.088 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X81Y146 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 11.016 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X81Y146 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/C clock pessimism 0.226 11.242 clock uncertainty -0.035 11.207 SLICE_X81Y146 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 11.114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4] ------------------------------------------------------------------- required time 11.114 arrival time -6.088 ------------------------------------------------------------------- slack 5.026 Slack (MET) : 5.026ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 3.131ns (logic 0.305ns (9.741%) route 2.826ns (90.259%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.699ns = ( 11.016 - 8.317 ) Source Clock Delay (SCD): 2.957ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.482ns (routing 0.732ns, distribution 1.750ns) Clock Net Delay (Destination): 2.301ns (routing 0.665ns, distribution 1.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.482 2.957 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y144 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y144 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.253 5.349 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X80Y147 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.515 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.573 6.088 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X81Y146 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 11.016 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X81Y146 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/C clock pessimism 0.226 11.242 clock uncertainty -0.035 11.207 SLICE_X81Y146 FDCE (Recov_BFF_SLICEL_C_CLR) -0.093 11.114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6] ------------------------------------------------------------------- required time 11.114 arrival time -6.088 ------------------------------------------------------------------- slack 5.026 Slack (MET) : 5.026ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 3.131ns (logic 0.305ns (9.741%) route 2.826ns (90.259%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.699ns = ( 11.016 - 8.317 ) Source Clock Delay (SCD): 2.957ns Clock Pessimism Removal (CPR): 0.226ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.482ns (routing 0.732ns, distribution 1.750ns) Clock Net Delay (Destination): 2.301ns (routing 0.665ns, distribution 1.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.482 2.957 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X129Y144 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X129Y144 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 3.096 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.253 5.349 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X80Y147 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.515 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/O net (fo=15, routed) 0.573 6.088 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5]0 SLICE_X81Y146 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.301 11.016 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] SLICE_X81Y146 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/C clock pessimism 0.226 11.242 clock uncertainty -0.035 11.207 SLICE_X81Y146 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.114 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7] ------------------------------------------------------------------- required time 11.114 arrival time -6.088 ------------------------------------------------------------------- slack 5.026 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.175ns (arrival time - required time) Source: SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.219ns (logic 0.048ns (21.918%) route 0.171ns (78.082%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.134ns Clock Pessimism Removal (CPR): 0.184ns Clock Net Delay (Source): 1.016ns (routing 0.320ns, distribution 0.696ns) Clock Net Delay (Destination): 1.192ns (routing 0.362ns, distribution 0.830ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.134 SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y139 FDPE r SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y139 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.182 f SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.171 1.353 SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] SLICE_X76Y141 FDCE f SFP_GEN[5].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.357 SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y141 FDCE r SFP_GEN[5].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.184 1.173 SLICE_X76Y141 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.178 SFP_GEN[5].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.178 arrival time 1.353 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.183ns (arrival time - required time) Source: SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.364ns Source Clock Delay (SCD): 1.134ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.016ns (routing 0.320ns, distribution 0.696ns) Clock Net Delay (Destination): 1.199ns (routing 0.362ns, distribution 0.837ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.134 SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y139 FDPE r SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y139 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.182 f SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.217 1.399 SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] SLICE_X78Y137 FDCE f SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.199 1.364 SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y137 FDCE r SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]/C clock pessimism -0.153 1.211 SLICE_X78Y137 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.216 SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40] ------------------------------------------------------------------- required time -1.216 arrival time 1.399 ------------------------------------------------------------------- slack 0.183 Slack (MET) : 0.183ns (arrival time - required time) Source: SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.048ns (18.113%) route 0.217ns (81.887%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.364ns Source Clock Delay (SCD): 1.134ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.016ns (routing 0.320ns, distribution 0.696ns) Clock Net Delay (Destination): 1.199ns (routing 0.362ns, distribution 0.837ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.134 SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y139 FDPE r SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y139 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.182 f SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.217 1.399 SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] SLICE_X78Y137 FDCE f SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.199 1.364 SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y137 FDCE r SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]/C clock pessimism -0.153 1.211 SLICE_X78Y137 FDCE (Remov_HFF2_SLICEL_C_CLR) 0.005 1.216 SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42] ------------------------------------------------------------------- required time -1.216 arrival time 1.399 ------------------------------------------------------------------- slack 0.183 Slack (MET) : 0.224ns (arrival time - required time) Source: SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.299ns (logic 0.048ns (16.054%) route 0.251ns (83.946%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.134ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.016ns (routing 0.320ns, distribution 0.696ns) Clock Net Delay (Destination): 1.192ns (routing 0.362ns, distribution 0.830ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.134 SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y139 FDPE r SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y139 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.182 f SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.251 1.433 SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] SLICE_X77Y138 FDCE f SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.357 SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y138 FDCE r SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.153 1.204 SLICE_X77Y138 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.209 SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -1.209 arrival time 1.433 ------------------------------------------------------------------- slack 0.224 Slack (MET) : 0.224ns (arrival time - required time) Source: SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.299ns (logic 0.048ns (16.054%) route 0.251ns (83.946%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.134ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.016ns (routing 0.320ns, distribution 0.696ns) Clock Net Delay (Destination): 1.192ns (routing 0.362ns, distribution 0.830ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.134 SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y139 FDPE r SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y139 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.182 f SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.251 1.433 SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] SLICE_X77Y138 FDCE f SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.357 SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y138 FDCE r SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[2]/C clock pessimism -0.153 1.204 SLICE_X77Y138 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.209 SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[2] ------------------------------------------------------------------- required time -1.209 arrival time 1.433 ------------------------------------------------------------------- slack 0.224 Slack (MET) : 0.224ns (arrival time - required time) Source: SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.299ns (logic 0.048ns (16.054%) route 0.251ns (83.946%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.357ns Source Clock Delay (SCD): 1.134ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.016ns (routing 0.320ns, distribution 0.696ns) Clock Net Delay (Destination): 1.192ns (routing 0.362ns, distribution 0.830ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.016 1.134 SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X76Y139 FDPE r SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X76Y139 FDPE (Prop_CFF2_SLICEM_C_Q) 0.048 1.182 f SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.251 1.433 SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] SLICE_X77Y138 FDCE f SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.192 1.357 SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X77Y138 FDCE r SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[80]/C clock pessimism -0.153 1.204 SLICE_X77Y138 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.209 SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[80] ------------------------------------------------------------------- required time -1.209 arrival time 1.433 ------------------------------------------------------------------- slack 0.224 Slack (MET) : 0.260ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.344ns (logic 0.049ns (14.244%) route 0.295ns (85.756%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.350ns Source Clock Delay (SCD): 1.118ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.000ns (routing 0.320ns, distribution 0.680ns) Clock Net Delay (Destination): 1.185ns (routing 0.362ns, distribution 0.823ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.118 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X81Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.167 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.295 1.462 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X76Y142 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.185 1.350 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X76Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C clock pessimism -0.153 1.197 SLICE_X76Y142 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.202 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time -1.202 arrival time 1.462 ------------------------------------------------------------------- slack 0.260 Slack (MET) : 0.261ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.364ns (logic 0.049ns (13.462%) route 0.315ns (86.538%)) Logic Levels: 0 Clock Path Skew: 0.098ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.369ns Source Clock Delay (SCD): 1.118ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.000ns (routing 0.320ns, distribution 0.680ns) Clock Net Delay (Destination): 1.204ns (routing 0.362ns, distribution 0.842ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.118 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X81Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.167 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.315 1.482 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X77Y142 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.204 1.369 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X77Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism -0.153 1.216 SLICE_X77Y142 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.221 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time -1.221 arrival time 1.482 ------------------------------------------------------------------- slack 0.261 Slack (MET) : 0.262ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.363ns (logic 0.049ns (13.499%) route 0.314ns (86.501%)) Logic Levels: 0 Clock Path Skew: 0.096ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.118ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.000ns (routing 0.320ns, distribution 0.680ns) Clock Net Delay (Destination): 1.202ns (routing 0.362ns, distribution 0.840ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.118 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X81Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.167 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.314 1.481 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X78Y142 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.202 1.367 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X78Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism -0.153 1.214 SLICE_X78Y142 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.219 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time -1.219 arrival time 1.481 ------------------------------------------------------------------- slack 0.262 Slack (MET) : 0.262ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns) Data Path Delay: 0.363ns (logic 0.049ns (13.499%) route 0.314ns (86.501%)) Logic Levels: 0 Clock Path Skew: 0.096ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.367ns Source Clock Delay (SCD): 1.118ns Clock Pessimism Removal (CPR): 0.153ns Clock Net Delay (Source): 1.000ns (routing 0.320ns, distribution 0.680ns) Clock Net Delay (Destination): 1.202ns (routing 0.362ns, distribution 0.840ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.118 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK SLICE_X81Y141 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y141 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 1.167 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.314 1.481 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X78Y142 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y9 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y51 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.202 1.367 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X78Y142 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism -0.153 1.214 SLICE_X78Y142 FDCE (Remov_EFF2_SLICEL_C_CLR) 0.005 1.219 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time -1.219 arrival time 1.481 ------------------------------------------------------------------- slack 0.262 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_8 To Clock: gtwiz_userclk_rx_srcclk_out[0]_8 Setup : 0 Failing Endpoints, Worst Slack 4.806ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.170ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.806ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.449ns (logic 0.305ns (8.843%) route 3.144ns (91.157%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.694ns = ( 11.011 - 8.317 ) Source Clock Delay (SCD): 2.852ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.377ns (routing 0.728ns, distribution 1.649ns) Clock Net Delay (Destination): 2.296ns (routing 0.664ns, distribution 1.632ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.377 2.852 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y160 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.991 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.318 5.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y161 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.475 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/O net (fo=15, routed) 0.826 6.301 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X78Y166 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.296 11.011 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] SLICE_X78Y166 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/C clock pessimism 0.224 11.235 clock uncertainty -0.035 11.200 SLICE_X78Y166 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.107 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6] ------------------------------------------------------------------- required time 11.107 arrival time -6.301 ------------------------------------------------------------------- slack 4.806 Slack (MET) : 4.893ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.365ns (logic 0.305ns (9.064%) route 3.060ns (90.936%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.069ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 2.852ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.377ns (routing 0.728ns, distribution 1.649ns) Clock Net Delay (Destination): 2.299ns (routing 0.664ns, distribution 1.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.377 2.852 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y160 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.991 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.318 5.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y161 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.475 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/O net (fo=15, routed) 0.742 6.217 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X79Y166 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.299 11.014 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] SLICE_X79Y166 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/C clock pessimism 0.224 11.238 clock uncertainty -0.035 11.203 SLICE_X79Y166 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.110 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0] ------------------------------------------------------------------- required time 11.110 arrival time -6.217 ------------------------------------------------------------------- slack 4.893 Slack (MET) : 4.893ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.365ns (logic 0.305ns (9.064%) route 3.060ns (90.936%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.069ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 2.852ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.377ns (routing 0.728ns, distribution 1.649ns) Clock Net Delay (Destination): 2.299ns (routing 0.664ns, distribution 1.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.377 2.852 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y160 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.991 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.318 5.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y161 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.475 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/O net (fo=15, routed) 0.742 6.217 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X79Y166 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.299 11.014 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] SLICE_X79Y166 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/C clock pessimism 0.224 11.238 clock uncertainty -0.035 11.203 SLICE_X79Y166 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 11.110 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4] ------------------------------------------------------------------- required time 11.110 arrival time -6.217 ------------------------------------------------------------------- slack 4.893 Slack (MET) : 4.893ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.365ns (logic 0.305ns (9.064%) route 3.060ns (90.936%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.069ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.697ns = ( 11.014 - 8.317 ) Source Clock Delay (SCD): 2.852ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.377ns (routing 0.728ns, distribution 1.649ns) Clock Net Delay (Destination): 2.299ns (routing 0.664ns, distribution 1.635ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.377 2.852 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y160 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.991 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.318 5.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y161 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.475 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/O net (fo=15, routed) 0.742 6.217 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X79Y166 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.299 11.014 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] SLICE_X79Y166 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/C clock pessimism 0.224 11.238 clock uncertainty -0.035 11.203 SLICE_X79Y166 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 11.110 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5] ------------------------------------------------------------------- required time 11.110 arrival time -6.217 ------------------------------------------------------------------- slack 4.893 Slack (MET) : 4.972ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.285ns (logic 0.305ns (9.285%) route 2.980ns (90.715%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.696ns = ( 11.013 - 8.317 ) Source Clock Delay (SCD): 2.852ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.377ns (routing 0.728ns, distribution 1.649ns) Clock Net Delay (Destination): 2.298ns (routing 0.664ns, distribution 1.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.377 2.852 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y160 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.991 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.318 5.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y161 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.475 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/O net (fo=15, routed) 0.662 6.137 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X79Y164 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.298 11.013 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] SLICE_X79Y164 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/C clock pessimism 0.224 11.237 clock uncertainty -0.035 11.202 SLICE_X79Y164 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.109 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2] ------------------------------------------------------------------- required time 11.109 arrival time -6.137 ------------------------------------------------------------------- slack 4.972 Slack (MET) : 4.972ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.285ns (logic 0.305ns (9.285%) route 2.980ns (90.715%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.068ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.696ns = ( 11.013 - 8.317 ) Source Clock Delay (SCD): 2.852ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.377ns (routing 0.728ns, distribution 1.649ns) Clock Net Delay (Destination): 2.298ns (routing 0.664ns, distribution 1.634ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.377 2.852 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y160 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.991 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.318 5.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y161 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.475 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/O net (fo=15, routed) 0.662 6.137 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X79Y164 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.298 11.013 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] SLICE_X79Y164 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C clock pessimism 0.224 11.237 clock uncertainty -0.035 11.202 SLICE_X79Y164 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 11.109 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3] ------------------------------------------------------------------- required time 11.109 arrival time -6.137 ------------------------------------------------------------------- slack 4.972 Slack (MET) : 4.978ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.278ns (logic 0.305ns (9.304%) route 2.973ns (90.696%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.067ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.695ns = ( 11.012 - 8.317 ) Source Clock Delay (SCD): 2.852ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.377ns (routing 0.728ns, distribution 1.649ns) Clock Net Delay (Destination): 2.297ns (routing 0.664ns, distribution 1.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.377 2.852 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y160 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.991 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.318 5.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y161 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.475 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/O net (fo=15, routed) 0.655 6.130 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X79Y164 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 11.012 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] SLICE_X79Y164 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/C clock pessimism 0.224 11.236 clock uncertainty -0.035 11.201 SLICE_X79Y164 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 11.108 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1] ------------------------------------------------------------------- required time 11.108 arrival time -6.130 ------------------------------------------------------------------- slack 4.978 Slack (MET) : 4.978ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.278ns (logic 0.305ns (9.304%) route 2.973ns (90.696%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.067ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.695ns = ( 11.012 - 8.317 ) Source Clock Delay (SCD): 2.852ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.377ns (routing 0.728ns, distribution 1.649ns) Clock Net Delay (Destination): 2.297ns (routing 0.664ns, distribution 1.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.377 2.852 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y160 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.991 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.318 5.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y161 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.475 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/O net (fo=15, routed) 0.655 6.130 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X79Y164 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 11.012 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] SLICE_X79Y164 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C clock pessimism 0.224 11.236 clock uncertainty -0.035 11.201 SLICE_X79Y164 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 11.108 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6] ------------------------------------------------------------------- required time 11.108 arrival time -6.130 ------------------------------------------------------------------- slack 4.978 Slack (MET) : 4.978ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.278ns (logic 0.305ns (9.304%) route 2.973ns (90.696%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.067ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.695ns = ( 11.012 - 8.317 ) Source Clock Delay (SCD): 2.852ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.377ns (routing 0.728ns, distribution 1.649ns) Clock Net Delay (Destination): 2.297ns (routing 0.664ns, distribution 1.633ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.377 2.852 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y160 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.991 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.318 5.309 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X81Y161 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.166 5.475 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2/O net (fo=15, routed) 0.655 6.130 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6]0 SLICE_X79Y164 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.297 11.012 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[6] SLICE_X79Y164 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/C clock pessimism 0.224 11.236 clock uncertainty -0.035 11.201 SLICE_X79Y164 FDCE (Recov_FFF_SLICEM_C_CLR) -0.093 11.108 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7] ------------------------------------------------------------------- required time 11.108 arrival time -6.130 ------------------------------------------------------------------- slack 4.978 Slack (MET) : 5.019ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 3.230ns (logic 0.304ns (9.412%) route 2.926ns (90.588%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.688ns = ( 11.005 - 8.317 ) Source Clock Delay (SCD): 2.852ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.377ns (routing 0.728ns, distribution 1.649ns) Clock Net Delay (Destination): 2.290ns (routing 0.664ns, distribution 1.626ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.377 2.852 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X122Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X122Y160 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.991 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 2.317 5.308 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] SLICE_X81Y161 LUT2 (Prop_C6LUT_SLICEL_I0_O) 0.165 5.473 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__5/O net (fo=2, routed) 0.609 6.082 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X80Y159 FDCE f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.290 11.005 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y159 FDCE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.224 11.229 clock uncertainty -0.035 11.194 SLICE_X80Y159 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 11.101 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 11.101 arrival time -6.082 ------------------------------------------------------------------- slack 5.019 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.170ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.048ns (22.222%) route 0.168ns (77.778%)) Logic Levels: 0 Clock Path Skew: 0.041ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.324ns Source Clock Delay (SCD): 1.100ns Clock Pessimism Removal (CPR): 0.183ns Clock Net Delay (Source): 0.982ns (routing 0.317ns, distribution 0.665ns) Clock Net Delay (Destination): 1.159ns (routing 0.360ns, distribution 0.799ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.982 1.100 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X81Y159 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y159 FDCE (Prop_HFF2_SLICEL_C_Q) 0.048 1.148 r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=82, routed) 0.168 1.316 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X81Y160 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.159 1.324 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/CLK SLICE_X81Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg/C clock pessimism -0.183 1.141 SLICE_X81Y160 FDCE (Remov_EFF_SLICEL_C_CLR) 0.005 1.146 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg ------------------------------------------------------------------- required time -1.146 arrival time 1.316 ------------------------------------------------------------------- slack 0.170 Slack (MET) : 0.187ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.162ns (routing 0.360ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y159 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.156 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.207 1.363 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y159 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.327 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X82Y159 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]/C clock pessimism -0.156 1.171 SLICE_X82Y159 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.176 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24] ------------------------------------------------------------------- required time -1.176 arrival time 1.363 ------------------------------------------------------------------- slack 0.187 Slack (MET) : 0.187ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.162ns (routing 0.360ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y159 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.156 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.207 1.363 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y159 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.327 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X82Y159 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/C clock pessimism -0.156 1.171 SLICE_X82Y159 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.176 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32] ------------------------------------------------------------------- required time -1.176 arrival time 1.363 ------------------------------------------------------------------- slack 0.187 Slack (MET) : 0.187ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[24]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.162ns (routing 0.360ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y159 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.156 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.207 1.363 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y159 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.327 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X82Y159 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[24]/C clock pessimism -0.156 1.171 SLICE_X82Y159 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.176 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[24] ------------------------------------------------------------------- required time -1.176 arrival time 1.363 ------------------------------------------------------------------- slack 0.187 Slack (MET) : 0.187ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.049ns (19.141%) route 0.207ns (80.859%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.162ns (routing 0.360ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y159 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.156 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.207 1.363 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X82Y159 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.327 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X82Y159 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]/C clock pessimism -0.156 1.171 SLICE_X82Y159 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.176 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32] ------------------------------------------------------------------- required time -1.176 arrival time 1.363 ------------------------------------------------------------------- slack 0.187 Slack (MET) : 0.192ns (arrival time - required time) Source: SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.048ns (18.391%) route 0.213ns (81.609%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.337ns Source Clock Delay (SCD): 1.118ns Clock Pessimism Removal (CPR): 0.155ns Clock Net Delay (Source): 1.000ns (routing 0.317ns, distribution 0.683ns) Clock Net Delay (Destination): 1.172ns (routing 0.360ns, distribution 0.812ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.000 1.118 SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] SLICE_X78Y165 FDPE r SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X78Y165 FDPE (Prop_CFF2_SLICEL_C_Q) 0.048 1.166 f SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/Q net (fo=52, routed) 0.213 1.379 SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] SLICE_X79Y163 FDCE f SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.172 1.337 SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] SLICE_X79Y163 FDCE r SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg/C clock pessimism -0.155 1.182 SLICE_X79Y163 FDCE (Remov_AFF_SLICEM_C_CLR) 0.005 1.187 SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg ------------------------------------------------------------------- required time -1.187 arrival time 1.379 ------------------------------------------------------------------- slack 0.192 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.049ns (18.491%) route 0.216ns (81.509%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.162ns (routing 0.360ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y159 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.156 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.216 1.372 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X81Y160 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.327 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X81Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.156 1.171 SLICE_X81Y160 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.176 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -1.176 arrival time 1.372 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.049ns (18.491%) route 0.216ns (81.509%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.162ns (routing 0.360ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y159 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.156 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.216 1.372 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X81Y160 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.327 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X81Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]/C clock pessimism -0.156 1.171 SLICE_X81Y160 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.176 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27] ------------------------------------------------------------------- required time -1.176 arrival time 1.372 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.196ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.265ns (logic 0.049ns (18.491%) route 0.216ns (81.509%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.327ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.162ns (routing 0.360ns, distribution 0.802ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y159 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.156 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.216 1.372 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X81Y160 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.162 1.327 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X81Y160 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35]/C clock pessimism -0.156 1.171 SLICE_X81Y160 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.176 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[35] ------------------------------------------------------------------- required time -1.176 arrival time 1.372 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.199ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[2]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns) Data Path Delay: 0.263ns (logic 0.049ns (18.631%) route 0.214ns (81.369%)) Logic Levels: 0 Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.322ns Source Clock Delay (SCD): 1.107ns Clock Pessimism Removal (CPR): 0.156ns Clock Net Delay (Source): 0.989ns (routing 0.317ns, distribution 0.672ns) Clock Net Delay (Destination): 1.157ns (routing 0.360ns, distribution 0.797ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.989 1.107 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X80Y159 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X80Y159 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.156 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.214 1.370 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X81Y158 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y10 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y53 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.157 1.322 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK SLICE_X81Y158 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[2]/C clock pessimism -0.156 1.166 SLICE_X81Y158 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.171 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[2] ------------------------------------------------------------------- required time -1.171 arrival time 1.370 ------------------------------------------------------------------- slack 0.199 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: gtwiz_userclk_rx_srcclk_out[0]_9 To Clock: gtwiz_userclk_rx_srcclk_out[0]_9 Setup : 0 Failing Endpoints, Worst Slack 4.803ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.140ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.803ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.079ns (logic 0.362ns (11.757%) route 2.717ns (88.243%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.318ns = ( 10.635 - 8.317 ) Source Clock Delay (SCD): 2.837ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.362ns (routing 0.678ns, distribution 1.684ns) Clock Net Delay (Destination): 1.920ns (routing 0.616ns, distribution 1.304ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.362 2.837 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y176 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.976 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.963 4.939 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X104Y178 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.162 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.754 5.916 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X103Y177 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.920 10.635 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X103Y177 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C clock pessimism 0.212 10.847 clock uncertainty -0.035 10.812 SLICE_X103Y177 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 10.719 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1] ------------------------------------------------------------------- required time 10.719 arrival time -5.916 ------------------------------------------------------------------- slack 4.803 Slack (MET) : 4.808ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.072ns (logic 0.362ns (11.784%) route 2.710ns (88.216%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.309ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.837ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.362ns (routing 0.678ns, distribution 1.684ns) Clock Net Delay (Destination): 1.918ns (routing 0.616ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.362 2.837 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y176 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.976 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.963 4.939 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X104Y178 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.162 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.747 5.909 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X103Y177 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.918 10.633 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X103Y177 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/C clock pessimism 0.212 10.845 clock uncertainty -0.035 10.810 SLICE_X103Y177 FDCE (Recov_HFF_SLICEM_C_CLR) -0.093 10.717 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7] ------------------------------------------------------------------- required time 10.717 arrival time -5.909 ------------------------------------------------------------------- slack 4.808 Slack (MET) : 4.808ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.072ns (logic 0.362ns (11.784%) route 2.710ns (88.216%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.309ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.837ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.362ns (routing 0.678ns, distribution 1.684ns) Clock Net Delay (Destination): 1.918ns (routing 0.616ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.362 2.837 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y176 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.976 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.963 4.939 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X104Y178 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.162 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.747 5.909 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X103Y177 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.918 10.633 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X103Y177 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/C clock pessimism 0.212 10.845 clock uncertainty -0.035 10.810 SLICE_X103Y177 FDCE (Recov_HFF2_SLICEM_C_CLR) -0.093 10.717 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0] ------------------------------------------------------------------- required time 10.717 arrival time -5.909 ------------------------------------------------------------------- slack 4.808 Slack (MET) : 4.808ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 3.072ns (logic 0.362ns (11.784%) route 2.710ns (88.216%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.309ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.316ns = ( 10.633 - 8.317 ) Source Clock Delay (SCD): 2.837ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.362ns (routing 0.678ns, distribution 1.684ns) Clock Net Delay (Destination): 1.918ns (routing 0.616ns, distribution 1.302ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.362 2.837 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y176 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.976 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.963 4.939 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X104Y178 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.162 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.747 5.909 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X103Y177 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.918 10.633 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X103Y177 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C clock pessimism 0.212 10.845 clock uncertainty -0.035 10.810 SLICE_X103Y177 FDCE (Recov_GFF_SLICEM_C_CLR) -0.093 10.717 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0] ------------------------------------------------------------------- required time 10.717 arrival time -5.909 ------------------------------------------------------------------- slack 4.808 Slack (MET) : 4.975ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 2.921ns (logic 0.362ns (12.393%) route 2.559ns (87.607%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.293ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.332ns = ( 10.649 - 8.317 ) Source Clock Delay (SCD): 2.837ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.362ns (routing 0.678ns, distribution 1.684ns) Clock Net Delay (Destination): 1.934ns (routing 0.616ns, distribution 1.318ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.362 2.837 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y176 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.976 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.963 4.939 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X104Y178 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.162 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.596 5.758 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X102Y176 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.934 10.649 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X102Y176 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/C clock pessimism 0.212 10.861 clock uncertainty -0.035 10.826 SLICE_X102Y176 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 10.733 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7] ------------------------------------------------------------------- required time 10.733 arrival time -5.758 ------------------------------------------------------------------- slack 4.975 Slack (MET) : 4.983ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 2.911ns (logic 0.362ns (12.436%) route 2.549ns (87.564%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.295ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.330ns = ( 10.647 - 8.317 ) Source Clock Delay (SCD): 2.837ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.362ns (routing 0.678ns, distribution 1.684ns) Clock Net Delay (Destination): 1.932ns (routing 0.616ns, distribution 1.316ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.362 2.837 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y176 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.976 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.963 4.939 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X104Y178 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.162 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.586 5.748 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X102Y176 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.932 10.647 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X102Y176 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C clock pessimism 0.212 10.859 clock uncertainty -0.035 10.824 SLICE_X102Y176 FDCE (Recov_HFF_SLICEL_C_CLR) -0.093 10.731 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6] ------------------------------------------------------------------- required time 10.731 arrival time -5.748 ------------------------------------------------------------------- slack 4.983 Slack (MET) : 5.050ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 2.845ns (logic 0.362ns (12.724%) route 2.483ns (87.276%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.294ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.331ns = ( 10.648 - 8.317 ) Source Clock Delay (SCD): 2.837ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.362ns (routing 0.678ns, distribution 1.684ns) Clock Net Delay (Destination): 1.933ns (routing 0.616ns, distribution 1.317ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.362 2.837 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y176 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.976 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.963 4.939 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X104Y178 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.162 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.520 5.682 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X101Y177 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.933 10.648 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X101Y177 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C clock pessimism 0.212 10.860 clock uncertainty -0.035 10.825 SLICE_X101Y177 FDCE (Recov_CFF_SLICEM_C_CLR) -0.093 10.732 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1] ------------------------------------------------------------------- required time 10.732 arrival time -5.682 ------------------------------------------------------------------- slack 5.050 Slack (MET) : 5.050ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 2.845ns (logic 0.362ns (12.724%) route 2.483ns (87.276%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.294ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.331ns = ( 10.648 - 8.317 ) Source Clock Delay (SCD): 2.837ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.362ns (routing 0.678ns, distribution 1.684ns) Clock Net Delay (Destination): 1.933ns (routing 0.616ns, distribution 1.317ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.362 2.837 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y176 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.976 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.963 4.939 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X104Y178 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.162 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.520 5.682 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X101Y177 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.933 10.648 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X101Y177 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/C clock pessimism 0.212 10.860 clock uncertainty -0.035 10.825 SLICE_X101Y177 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 10.732 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2] ------------------------------------------------------------------- required time 10.732 arrival time -5.682 ------------------------------------------------------------------- slack 5.050 Slack (MET) : 5.050ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 2.845ns (logic 0.362ns (12.724%) route 2.483ns (87.276%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.294ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.331ns = ( 10.648 - 8.317 ) Source Clock Delay (SCD): 2.837ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.362ns (routing 0.678ns, distribution 1.684ns) Clock Net Delay (Destination): 1.933ns (routing 0.616ns, distribution 1.317ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.362 2.837 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y176 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.976 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.963 4.939 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X104Y178 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.162 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.520 5.682 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X101Y177 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.933 10.648 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X101Y177 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C clock pessimism 0.212 10.860 clock uncertainty -0.035 10.825 SLICE_X101Y177 FDCE (Recov_AFF_SLICEM_C_CLR) -0.093 10.732 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3] ------------------------------------------------------------------- required time 10.732 arrival time -5.682 ------------------------------------------------------------------- slack 5.050 Slack (MET) : 5.050ns (required time - arrival time) Source: g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C (rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR (recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 2.845ns (logic 0.362ns (12.724%) route 2.483ns (87.276%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.294ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.331ns = ( 10.648 - 8.317 ) Source Clock Delay (SCD): 2.837ns Clock Pessimism Removal (CPR): 0.212ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 2.362ns (routing 0.678ns, distribution 1.684ns) Clock Net Delay (Destination): 1.933ns (routing 0.616ns, distribution 1.317ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 2.362 2.837 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] SLICE_X133Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y176 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 2.976 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q net (fo=32, routed) 1.963 4.939 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] SLICE_X104Y178 LUT3 (Prop_D6LUT_SLICEL_I0_O) 0.223 5.162 f g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/O net (fo=15, routed) 0.520 5.682 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7]0 SLICE_X101Y177 FDCE f g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 8.317 8.317 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 8.317 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 8.369 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 8.715 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 1.933 10.648 g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] SLICE_X101Y177 FDCE r g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/C clock pessimism 0.212 10.860 clock uncertainty -0.035 10.825 SLICE_X101Y177 FDCE (Recov_BFF_SLICEM_C_CLR) -0.093 10.732 g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4] ------------------------------------------------------------------- required time 10.732 arrival time -5.682 ------------------------------------------------------------------- slack 5.050 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[88]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.929ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.811ns (routing 0.297ns, distribution 0.514ns) Clock Net Delay (Destination): 0.977ns (routing 0.341ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.811 0.929 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X109Y176 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y176 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.978 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.175 1.153 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y176 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[88]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.142 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[88]/C clock pessimism -0.134 1.008 SLICE_X107Y176 FDCE (Remov_HFF_SLICEM_C_CLR) 0.005 1.013 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[88] ------------------------------------------------------------------- required time -1.013 arrival time 1.153 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[91]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.929ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.811ns (routing 0.297ns, distribution 0.514ns) Clock Net Delay (Destination): 0.977ns (routing 0.341ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.811 0.929 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X109Y176 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y176 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.978 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.175 1.153 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y176 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[91]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.142 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[91]/C clock pessimism -0.134 1.008 SLICE_X107Y176 FDCE (Remov_GFF_SLICEM_C_CLR) 0.005 1.013 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[91] ------------------------------------------------------------------- required time -1.013 arrival time 1.153 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[98]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.929ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.811ns (routing 0.297ns, distribution 0.514ns) Clock Net Delay (Destination): 0.977ns (routing 0.341ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.811 0.929 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X109Y176 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y176 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.978 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.175 1.153 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y176 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[98]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.142 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[98]/C clock pessimism -0.134 1.008 SLICE_X107Y176 FDCE (Remov_FFF_SLICEM_C_CLR) 0.005 1.013 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[98] ------------------------------------------------------------------- required time -1.013 arrival time 1.153 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[99]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.929ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.811ns (routing 0.297ns, distribution 0.514ns) Clock Net Delay (Destination): 0.977ns (routing 0.341ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.811 0.929 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X109Y176 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y176 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.978 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.175 1.153 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y176 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[99]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.142 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[99]/C clock pessimism -0.134 1.008 SLICE_X107Y176 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.013 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[99] ------------------------------------------------------------------- required time -1.013 arrival time 1.153 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[88]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.929ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.811ns (routing 0.297ns, distribution 0.514ns) Clock Net Delay (Destination): 0.977ns (routing 0.341ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.811 0.929 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X109Y176 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y176 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.978 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.175 1.153 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y176 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[88]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.142 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[88]/C clock pessimism -0.134 1.008 SLICE_X107Y176 FDCE (Remov_HFF2_SLICEM_C_CLR) 0.005 1.013 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[88] ------------------------------------------------------------------- required time -1.013 arrival time 1.153 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[91]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.929ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.811ns (routing 0.297ns, distribution 0.514ns) Clock Net Delay (Destination): 0.977ns (routing 0.341ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.811 0.929 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X109Y176 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y176 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.978 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.175 1.153 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y176 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[91]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.142 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[91]/C clock pessimism -0.134 1.008 SLICE_X107Y176 FDCE (Remov_GFF2_SLICEM_C_CLR) 0.005 1.013 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[91] ------------------------------------------------------------------- required time -1.013 arrival time 1.153 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[98]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.929ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.811ns (routing 0.297ns, distribution 0.514ns) Clock Net Delay (Destination): 0.977ns (routing 0.341ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.811 0.929 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X109Y176 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y176 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.978 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.175 1.153 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y176 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[98]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.142 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[98]/C clock pessimism -0.134 1.008 SLICE_X107Y176 FDCE (Remov_FFF2_SLICEM_C_CLR) 0.005 1.013 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[98] ------------------------------------------------------------------- required time -1.013 arrival time 1.153 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[99]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.224ns (logic 0.049ns (21.875%) route 0.175ns (78.125%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.142ns Source Clock Delay (SCD): 0.929ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.811ns (routing 0.297ns, distribution 0.514ns) Clock Net Delay (Destination): 0.977ns (routing 0.341ns, distribution 0.636ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.811 0.929 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X109Y176 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y176 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.978 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.175 1.153 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y176 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[99]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.977 1.142 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[99]/C clock pessimism -0.134 1.008 SLICE_X107Y176 FDCE (Remov_EFF2_SLICEM_C_CLR) 0.005 1.013 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[99] ------------------------------------------------------------------- required time -1.013 arrival time 1.153 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[83]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.049ns (21.586%) route 0.178ns (78.414%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.144ns Source Clock Delay (SCD): 0.929ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.811ns (routing 0.297ns, distribution 0.514ns) Clock Net Delay (Destination): 0.979ns (routing 0.341ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.811 0.929 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X109Y176 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y176 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.978 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.178 1.156 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y176 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.979 1.144 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[83]/C clock pessimism -0.134 1.010 SLICE_X107Y176 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.015 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[83] ------------------------------------------------------------------- required time -1.015 arrival time 1.156 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[90]/CLR (removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.049ns (21.586%) route 0.178ns (78.414%)) Logic Levels: 0 Clock Path Skew: 0.081ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.144ns Source Clock Delay (SCD): 0.929ns Clock Pessimism Removal (CPR): 0.134ns Clock Net Delay (Source): 0.811ns (routing 0.297ns, distribution 0.514ns) Clock Net Delay (Destination): 0.979ns (routing 0.341ns, distribution 0.638ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.811 0.929 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X109Y176 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X109Y176 FDPE (Prop_EFF_SLICEM_C_Q) 0.049 0.978 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.178 1.156 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X107Y176 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[90]/CLR ------------------------------------------------------------------- ------------------- (clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y11 GTHE3_CHANNEL 0.000 0.000 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] BUFG_GT_X1Y71 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X4Y2 (CLOCK_ROOT) net (fo=674, routed) 0.979 1.144 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK SLICE_X107Y176 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[90]/C clock pessimism -0.134 1.010 SLICE_X107Y176 FDCE (Remov_CFF_SLICEM_C_CLR) 0.005 1.015 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[90] ------------------------------------------------------------------- required time -1.015 arrival time 1.156 ------------------------------------------------------------------- slack 0.141 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxoutclk_out[0] To Clock: rxoutclk_out[0] Setup : 0 Failing Endpoints, Worst Slack 5.586ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.142ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.586ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]/CLR (recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.562ns (logic 0.139ns (24.733%) route 0.423ns (75.267%)) Logic Levels: 0 Clock Path Skew: -0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.339ns = ( 7.739 - 6.400 ) Source Clock Delay (SCD): 1.569ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.094ns (routing 0.114ns, distribution 0.980ns) Clock Net Delay (Destination): 0.941ns (routing 0.097ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.094 1.569 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.708 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.423 2.131 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X138Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.941 7.739 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X138Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]/C clock pessimism 0.106 7.845 clock uncertainty -0.035 7.810 SLICE_X138Y12 FDCE (Recov_BFF2_SLICEL_C_CLR) -0.093 7.717 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0] ------------------------------------------------------------------- required time 7.717 arrival time -2.131 ------------------------------------------------------------------- slack 5.586 Slack (MET) : 5.586ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]/CLR (recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.562ns (logic 0.139ns (24.733%) route 0.423ns (75.267%)) Logic Levels: 0 Clock Path Skew: -0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.339ns = ( 7.739 - 6.400 ) Source Clock Delay (SCD): 1.569ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.094ns (routing 0.114ns, distribution 0.980ns) Clock Net Delay (Destination): 0.941ns (routing 0.097ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.094 1.569 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.708 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.423 2.131 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X138Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.941 7.739 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X138Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]/C clock pessimism 0.106 7.845 clock uncertainty -0.035 7.810 SLICE_X138Y12 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 7.717 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1] ------------------------------------------------------------------- required time 7.717 arrival time -2.131 ------------------------------------------------------------------- slack 5.586 Slack (MET) : 5.586ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]/CLR (recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.562ns (logic 0.139ns (24.733%) route 0.423ns (75.267%)) Logic Levels: 0 Clock Path Skew: -0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.339ns = ( 7.739 - 6.400 ) Source Clock Delay (SCD): 1.569ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.094ns (routing 0.114ns, distribution 0.980ns) Clock Net Delay (Destination): 0.941ns (routing 0.097ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.094 1.569 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.708 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.423 2.131 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X138Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.941 7.739 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X138Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]/C clock pessimism 0.106 7.845 clock uncertainty -0.035 7.810 SLICE_X138Y12 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 7.717 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2] ------------------------------------------------------------------- required time 7.717 arrival time -2.131 ------------------------------------------------------------------- slack 5.586 Slack (MET) : 5.586ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]/CLR (recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.562ns (logic 0.139ns (24.733%) route 0.423ns (75.267%)) Logic Levels: 0 Clock Path Skew: -0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.339ns = ( 7.739 - 6.400 ) Source Clock Delay (SCD): 1.569ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.094ns (routing 0.114ns, distribution 0.980ns) Clock Net Delay (Destination): 0.941ns (routing 0.097ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.094 1.569 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.708 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.423 2.131 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X138Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.941 7.739 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X138Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]/C clock pessimism 0.106 7.845 clock uncertainty -0.035 7.810 SLICE_X138Y12 FDCE (Recov_CFF_SLICEL_C_CLR) -0.093 7.717 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3] ------------------------------------------------------------------- required time 7.717 arrival time -2.131 ------------------------------------------------------------------- slack 5.586 Slack (MET) : 5.586ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]/CLR (recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.562ns (logic 0.139ns (24.733%) route 0.423ns (75.267%)) Logic Levels: 0 Clock Path Skew: -0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.339ns = ( 7.739 - 6.400 ) Source Clock Delay (SCD): 1.569ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.094ns (routing 0.114ns, distribution 0.980ns) Clock Net Delay (Destination): 0.941ns (routing 0.097ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.094 1.569 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.708 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.423 2.131 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X138Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.941 7.739 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X138Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]/C clock pessimism 0.106 7.845 clock uncertainty -0.035 7.810 SLICE_X138Y12 FDCE (Recov_CFF2_SLICEL_C_CLR) -0.093 7.717 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4] ------------------------------------------------------------------- required time 7.717 arrival time -2.131 ------------------------------------------------------------------- slack 5.586 Slack (MET) : 5.586ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]/CLR (recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.562ns (logic 0.139ns (24.733%) route 0.423ns (75.267%)) Logic Levels: 0 Clock Path Skew: -0.124ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.339ns = ( 7.739 - 6.400 ) Source Clock Delay (SCD): 1.569ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.094ns (routing 0.114ns, distribution 0.980ns) Clock Net Delay (Destination): 0.941ns (routing 0.097ns, distribution 0.844ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.094 1.569 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.708 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.423 2.131 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X138Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.941 7.739 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X138Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]/C clock pessimism 0.106 7.845 clock uncertainty -0.035 7.810 SLICE_X138Y12 FDCE (Recov_AFF_SLICEL_C_CLR) -0.093 7.717 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5] ------------------------------------------------------------------- required time 7.717 arrival time -2.131 ------------------------------------------------------------------- slack 5.586 Slack (MET) : 5.589ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]/CLR (recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.564ns (logic 0.139ns (24.645%) route 0.425ns (75.355%)) Logic Levels: 0 Clock Path Skew: -0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.344ns = ( 7.744 - 6.400 ) Source Clock Delay (SCD): 1.569ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.094ns (routing 0.114ns, distribution 0.980ns) Clock Net Delay (Destination): 0.946ns (routing 0.097ns, distribution 0.849ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.094 1.569 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.708 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.425 2.133 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X139Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.946 7.744 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X139Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]/C clock pessimism 0.106 7.850 clock uncertainty -0.035 7.815 SLICE_X139Y12 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 7.722 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6] ------------------------------------------------------------------- required time 7.722 arrival time -2.133 ------------------------------------------------------------------- slack 5.589 Slack (MET) : 5.589ns (required time - arrival time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]/CLR (recovery check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.400ns (rxoutclk_out[0] rise@6.400ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.564ns (logic 0.139ns (24.645%) route 0.425ns (75.355%)) Logic Levels: 0 Clock Path Skew: -0.119ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.344ns = ( 7.744 - 6.400 ) Source Clock Delay (SCD): 1.569ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 1.094ns (routing 0.114ns, distribution 0.980ns) Clock Net Delay (Destination): 0.946ns (routing 0.097ns, distribution 0.849ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.091 0.091 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.384 0.475 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 1.094 1.569 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.139 1.708 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.425 2.133 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X139Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 6.400 6.400 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 6.400 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.052 6.452 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.346 6.798 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.946 7.744 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X139Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]/C clock pessimism 0.106 7.850 clock uncertainty -0.035 7.815 SLICE_X139Y12 FDCE (Recov_DFF2_SLICEL_C_CLR) -0.093 7.722 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7] ------------------------------------------------------------------- required time 7.722 arrival time -2.133 ------------------------------------------------------------------- slack 5.589 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.142ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]/CLR (removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.220ns (logic 0.049ns (22.273%) route 0.171ns (77.727%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.683ns Source Clock Delay (SCD): 0.540ns Clock Pessimism Removal (CPR): 0.070ns Clock Net Delay (Source): 0.422ns (routing 0.059ns, distribution 0.363ns) Clock Net Delay (Destination): 0.518ns (routing 0.075ns, distribution 0.443ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.422 0.540 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.589 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.171 0.760 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X139Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.518 0.683 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X139Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6]/C clock pessimism -0.070 0.613 SLICE_X139Y12 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 0.618 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[6] ------------------------------------------------------------------- required time -0.618 arrival time 0.760 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.142ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]/CLR (removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.220ns (logic 0.049ns (22.273%) route 0.171ns (77.727%)) Logic Levels: 0 Clock Path Skew: 0.073ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.683ns Source Clock Delay (SCD): 0.540ns Clock Pessimism Removal (CPR): 0.070ns Clock Net Delay (Source): 0.422ns (routing 0.059ns, distribution 0.363ns) Clock Net Delay (Destination): 0.518ns (routing 0.075ns, distribution 0.443ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.422 0.540 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.589 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.171 0.760 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X139Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.518 0.683 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X139Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7]/C clock pessimism -0.070 0.613 SLICE_X139Y12 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 0.618 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[7] ------------------------------------------------------------------- required time -0.618 arrival time 0.760 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.143ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]/CLR (removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.218ns (logic 0.049ns (22.477%) route 0.169ns (77.523%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.680ns Source Clock Delay (SCD): 0.540ns Clock Pessimism Removal (CPR): 0.070ns Clock Net Delay (Source): 0.422ns (routing 0.059ns, distribution 0.363ns) Clock Net Delay (Destination): 0.515ns (routing 0.075ns, distribution 0.440ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.422 0.540 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.589 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.169 0.758 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X138Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.515 0.680 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X138Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0]/C clock pessimism -0.070 0.610 SLICE_X138Y12 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 0.615 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[0] ------------------------------------------------------------------- required time -0.615 arrival time 0.758 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.143ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]/CLR (removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.218ns (logic 0.049ns (22.477%) route 0.169ns (77.523%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.680ns Source Clock Delay (SCD): 0.540ns Clock Pessimism Removal (CPR): 0.070ns Clock Net Delay (Source): 0.422ns (routing 0.059ns, distribution 0.363ns) Clock Net Delay (Destination): 0.515ns (routing 0.075ns, distribution 0.440ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.422 0.540 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.589 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.169 0.758 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X138Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.515 0.680 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X138Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1]/C clock pessimism -0.070 0.610 SLICE_X138Y12 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 0.615 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[1] ------------------------------------------------------------------- required time -0.615 arrival time 0.758 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.143ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]/CLR (removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.218ns (logic 0.049ns (22.477%) route 0.169ns (77.523%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.680ns Source Clock Delay (SCD): 0.540ns Clock Pessimism Removal (CPR): 0.070ns Clock Net Delay (Source): 0.422ns (routing 0.059ns, distribution 0.363ns) Clock Net Delay (Destination): 0.515ns (routing 0.075ns, distribution 0.440ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.422 0.540 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.589 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.169 0.758 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X138Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.515 0.680 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X138Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2]/C clock pessimism -0.070 0.610 SLICE_X138Y12 FDCE (Remov_DFF2_SLICEL_C_CLR) 0.005 0.615 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[2] ------------------------------------------------------------------- required time -0.615 arrival time 0.758 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.143ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]/CLR (removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.218ns (logic 0.049ns (22.477%) route 0.169ns (77.523%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.680ns Source Clock Delay (SCD): 0.540ns Clock Pessimism Removal (CPR): 0.070ns Clock Net Delay (Source): 0.422ns (routing 0.059ns, distribution 0.363ns) Clock Net Delay (Destination): 0.515ns (routing 0.075ns, distribution 0.440ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.422 0.540 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.589 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.169 0.758 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X138Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.515 0.680 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X138Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3]/C clock pessimism -0.070 0.610 SLICE_X138Y12 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 0.615 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[3] ------------------------------------------------------------------- required time -0.615 arrival time 0.758 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.143ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]/CLR (removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.218ns (logic 0.049ns (22.477%) route 0.169ns (77.523%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.680ns Source Clock Delay (SCD): 0.540ns Clock Pessimism Removal (CPR): 0.070ns Clock Net Delay (Source): 0.422ns (routing 0.059ns, distribution 0.363ns) Clock Net Delay (Destination): 0.515ns (routing 0.075ns, distribution 0.440ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.422 0.540 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.589 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.169 0.758 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X138Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.515 0.680 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X138Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4]/C clock pessimism -0.070 0.610 SLICE_X138Y12 FDCE (Remov_CFF2_SLICEL_C_CLR) 0.005 0.615 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[4] ------------------------------------------------------------------- required time -0.615 arrival time 0.758 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.143ns (arrival time - required time) Source: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C (rising edge-triggered cell FDCE clocked by rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Destination: i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]/CLR (removal check against rising-edge clock rxoutclk_out[0] {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxoutclk_out[0] rise@0.000ns - rxoutclk_out[0] rise@0.000ns) Data Path Delay: 0.218ns (logic 0.049ns (22.477%) route 0.169ns (77.523%)) Logic Levels: 0 Clock Path Skew: 0.070ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.680ns Source Clock Delay (SCD): 0.540ns Clock Pessimism Removal (CPR): 0.070ns Clock Net Delay (Source): 0.422ns (routing 0.059ns, distribution 0.363ns) Clock Net Delay (Destination): 0.515ns (routing 0.075ns, distribution 0.440ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.018 0.018 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.100 0.118 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.422 0.540 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_usrclk2_out SLICE_X141Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y12 FDCE (Prop_EFF_SLICEL_C_Q) 0.049 0.589 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg/Q net (fo=8, routed) 0.169 0.758 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/gtwiz_userclk_rx_active_out SLICE_X138Y12 FDCE f i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]/CLR (IS_INVERTED) ------------------------------------------------------------------- ------------------- (clock rxoutclk_out[0] rise edge) 0.000 0.000 r GTHE3_CHANNEL_X1Y0 GTHE3_CHANNEL 0.000 0.000 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gt_i/inst/gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK net (fo=2, routed) 0.035 0.035 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gtwiz_userclk_rx_srcclk_in BUFG_GT_X1Y3 BUFG_GT (Prop_BUFG_GT_I_O) 0.130 0.165 r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O X5Y0 (CLOCK_ROOT) net (fo=617, routed) 0.515 0.680 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/ultrascale_rx_userclk_n_1 SLICE_X138Y12 FDCE r i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5]/C clock pessimism -0.070 0.610 SLICE_X138Y12 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 0.615 i_axi_slave/i_aurora/inst/aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/usrclk_rx_active_in_extend_cntr_reg[5] ------------------------------------------------------------------- required time -0.615 arrival time 0.758 ------------------------------------------------------------------- slack 0.143 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: tx_wordclk To Clock: tx_wordclk Setup : 0 Failing Endpoints, Worst Slack 0.414ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.112ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.414ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/ready_reg/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 6.952ns (logic 0.139ns (1.999%) route 6.813ns (98.001%)) Logic Levels: 0 Clock Path Skew: -0.751ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.292ns = ( 11.609 - 8.317 ) Source Clock Delay (SCD): 4.149ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.149ns (routing 1.114ns, distribution 3.035ns) Clock Net Delay (Destination): 3.292ns (routing 1.026ns, distribution 2.266ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 4.149 4.149 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X113Y539 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y539 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 4.288 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 6.813 11.101 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X78Y371 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/ready_reg/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.292 11.609 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X78Y371 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/ready_reg/C clock pessimism 0.106 11.715 clock uncertainty -0.107 11.608 SLICE_X78Y371 FDCE (Recov_EFF_SLICEL_C_CLR) -0.093 11.515 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/ready_reg ------------------------------------------------------------------- required time 11.515 arrival time -11.101 ------------------------------------------------------------------- slack 0.414 Slack (MET) : 0.474ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/PRE (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.213ns (logic 0.139ns (1.927%) route 7.074ns (98.073%)) Logic Levels: 0 Clock Path Skew: -0.430ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.613ns = ( 11.930 - 8.317 ) Source Clock Delay (SCD): 4.149ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.149ns (routing 1.114ns, distribution 3.035ns) Clock Net Delay (Destination): 3.613ns (routing 1.026ns, distribution 2.587ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 4.149 4.149 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X113Y539 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y539 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 4.288 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 7.074 11.362 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/gbt_txreset_s[0] SLICE_X101Y396 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/PRE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.613 11.930 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X101Y396 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10]/C clock pessimism 0.106 12.036 clock uncertainty -0.107 11.929 SLICE_X101Y396 FDPE (Recov_DFF_SLICEM_C_PRE) -0.093 11.836 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[10] ------------------------------------------------------------------- required time 11.836 arrival time -11.362 ------------------------------------------------------------------- slack 0.474 Slack (MET) : 0.474ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[8]/PRE (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 7.213ns (logic 0.139ns (1.927%) route 7.074ns (98.073%)) Logic Levels: 0 Clock Path Skew: -0.430ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.613ns = ( 11.930 - 8.317 ) Source Clock Delay (SCD): 4.149ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.149ns (routing 1.114ns, distribution 3.035ns) Clock Net Delay (Destination): 3.613ns (routing 1.026ns, distribution 2.587ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 4.149 4.149 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X113Y539 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y539 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 4.288 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 7.074 11.362 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/gbt_txreset_s[0] SLICE_X101Y396 FDPE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[8]/PRE ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.613 11.930 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk SLR Crossing[0->1] SLICE_X101Y396 FDPE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[8]/C clock pessimism 0.106 12.036 clock uncertainty -0.107 11.929 SLICE_X101Y396 FDPE (Recov_CFF_SLICEM_C_PRE) -0.093 11.836 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[9].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[8] ------------------------------------------------------------------- required time 11.836 arrival time -11.362 ------------------------------------------------------------------- slack 0.474 Slack (MET) : 0.865ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[0]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 6.504ns (logic 0.139ns (2.137%) route 6.365ns (97.863%)) Logic Levels: 0 Clock Path Skew: -0.748ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.295ns = ( 11.612 - 8.317 ) Source Clock Delay (SCD): 4.149ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.149ns (routing 1.114ns, distribution 3.035ns) Clock Net Delay (Destination): 3.295ns (routing 1.026ns, distribution 2.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 4.149 4.149 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X113Y539 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y539 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 4.288 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 6.365 10.653 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X82Y389 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.295 11.612 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X82Y389 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[0]/C clock pessimism 0.106 11.718 clock uncertainty -0.107 11.611 SLICE_X82Y389 FDCE (Recov_CFF2_SLICEM_C_CLR) -0.093 11.518 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[0] ------------------------------------------------------------------- required time 11.518 arrival time -10.653 ------------------------------------------------------------------- slack 0.865 Slack (MET) : 0.865ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[1]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 6.504ns (logic 0.139ns (2.137%) route 6.365ns (97.863%)) Logic Levels: 0 Clock Path Skew: -0.748ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.295ns = ( 11.612 - 8.317 ) Source Clock Delay (SCD): 4.149ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.149ns (routing 1.114ns, distribution 3.035ns) Clock Net Delay (Destination): 3.295ns (routing 1.026ns, distribution 2.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 4.149 4.149 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X113Y539 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y539 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 4.288 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 6.365 10.653 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X82Y389 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.295 11.612 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X82Y389 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[1]/C clock pessimism 0.106 11.718 clock uncertainty -0.107 11.611 SLICE_X82Y389 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.518 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[1] ------------------------------------------------------------------- required time 11.518 arrival time -10.653 ------------------------------------------------------------------- slack 0.865 Slack (MET) : 0.865ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[2]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 6.504ns (logic 0.139ns (2.137%) route 6.365ns (97.863%)) Logic Levels: 0 Clock Path Skew: -0.748ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.295ns = ( 11.612 - 8.317 ) Source Clock Delay (SCD): 4.149ns Clock Pessimism Removal (CPR): 0.106ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.149ns (routing 1.114ns, distribution 3.035ns) Clock Net Delay (Destination): 3.295ns (routing 1.026ns, distribution 2.269ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 4.149 4.149 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X113Y539 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X113Y539 FDPE (Prop_EFF_SLICEM_C_Q) 0.139 4.288 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 6.365 10.653 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X82Y389 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.295 11.612 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X82Y389 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[2]/C clock pessimism 0.106 11.718 clock uncertainty -0.107 11.611 SLICE_X82Y389 FDCE (Recov_DFF2_SLICEM_C_CLR) -0.093 11.518 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[9].gbt_txgearbox_inst/address_reg[2] ------------------------------------------------------------------- required time 11.518 arrival time -10.653 ------------------------------------------------------------------- slack 0.865 Slack (MET) : 1.166ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[106]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 6.056ns (logic 0.140ns (2.312%) route 5.916ns (97.688%)) Logic Levels: 0 Clock Path Skew: -0.895ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.118ns = ( 11.435 - 8.317 ) Source Clock Delay (SCD): 4.101ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.101ns (routing 1.114ns, distribution 2.987ns) Clock Net Delay (Destination): 3.118ns (routing 1.026ns, distribution 2.092ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 4.101 4.101 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X104Y537 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X104Y537 FDPE (Prop_AFF_SLICEL_C_Q) 0.140 4.241 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 5.916 10.157 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X65Y342 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[106]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.118 11.435 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X65Y342 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[106]/C clock pessimism 0.088 11.523 clock uncertainty -0.107 11.416 SLICE_X65Y342 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.323 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[106] ------------------------------------------------------------------- required time 11.323 arrival time -10.157 ------------------------------------------------------------------- slack 1.166 Slack (MET) : 1.166ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 6.057ns (logic 0.140ns (2.311%) route 5.917ns (97.689%)) Logic Levels: 0 Clock Path Skew: -0.894ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.119ns = ( 11.436 - 8.317 ) Source Clock Delay (SCD): 4.101ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.101ns (routing 1.114ns, distribution 2.987ns) Clock Net Delay (Destination): 3.119ns (routing 1.026ns, distribution 2.093ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 4.101 4.101 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X104Y537 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X104Y537 FDPE (Prop_AFF_SLICEL_C_Q) 0.140 4.241 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 5.917 10.158 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X66Y342 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.119 11.436 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X66Y342 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]/C clock pessimism 0.088 11.524 clock uncertainty -0.107 11.417 SLICE_X66Y342 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.324 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99] ------------------------------------------------------------------- required time 11.324 arrival time -10.158 ------------------------------------------------------------------- slack 1.166 Slack (MET) : 1.234ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[113]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 5.997ns (logic 0.140ns (2.335%) route 5.857ns (97.666%)) Logic Levels: 0 Clock Path Skew: -0.886ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.127ns = ( 11.444 - 8.317 ) Source Clock Delay (SCD): 4.101ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.101ns (routing 1.114ns, distribution 2.987ns) Clock Net Delay (Destination): 3.127ns (routing 1.026ns, distribution 2.101ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 4.101 4.101 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X104Y537 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X104Y537 FDPE (Prop_AFF_SLICEL_C_Q) 0.140 4.241 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 5.857 10.098 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X65Y343 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[113]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.127 11.444 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X65Y343 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[113]/C clock pessimism 0.088 11.532 clock uncertainty -0.107 11.425 SLICE_X65Y343 FDCE (Recov_DFF_SLICEM_C_CLR) -0.093 11.332 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[113] ------------------------------------------------------------------- required time 11.332 arrival time -10.098 ------------------------------------------------------------------- slack 1.234 Slack (MET) : 1.234ns (required time - arrival time) Source: g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[97]/CLR (recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.317ns (tx_wordclk rise@8.317ns - tx_wordclk rise@0.000ns) Data Path Delay: 5.998ns (logic 0.140ns (2.334%) route 5.858ns (97.666%)) Logic Levels: 0 Clock Path Skew: -0.885ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.128ns = ( 11.445 - 8.317 ) Source Clock Delay (SCD): 4.101ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.107ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.202ns Phase Error (PE): 0.000ns Clock Net Delay (Source): 4.101ns (routing 1.114ns, distribution 2.987ns) Clock Net Delay (Destination): 3.128ns (routing 1.026ns, distribution 2.102ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 4.101 4.101 g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk SLR Crossing[0->1] SLICE_X104Y537 FDPE r g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X104Y537 FDPE (Prop_AFF_SLICEL_C_Q) 0.140 4.241 f g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 5.858 10.099 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X66Y343 FDCE f g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[97]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 8.317 8.317 r BUFGCE_X2Y98 BUFGCE 0.000 8.317 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 3.128 11.445 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk SLR Crossing[0->1] SLICE_X66Y343 FDCE r g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[97]/C clock pessimism 0.088 11.533 clock uncertainty -0.107 11.426 SLICE_X66Y343 FDCE (Recov_DFF_SLICEL_C_CLR) -0.093 11.333 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[97] ------------------------------------------------------------------- required time 11.333 arrival time -10.099 ------------------------------------------------------------------- slack 1.234 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.112ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]/CLR (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.203ns (logic 0.049ns (24.138%) route 0.154ns (75.862%)) Logic Levels: 0 Clock Path Skew: 0.086ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.672ns Source Clock Delay (SCD): 1.436ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 1.436ns (routing 0.447ns, distribution 0.989ns) Clock Net Delay (Destination): 1.672ns (routing 0.493ns, distribution 1.179ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.436 1.436 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/tx_wordclk SLICE_X30Y164 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y164 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.485 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.154 1.639 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X31Y164 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.672 1.672 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/tx_wordclk SLICE_X31Y164 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99]/C clock pessimism -0.150 1.522 SLICE_X31Y164 FDCE (Remov_DFF_SLICEM_C_CLR) 0.005 1.527 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[99] ------------------------------------------------------------------- required time -1.527 arrival time 1.639 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[90]/CLR (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.199ns (logic 0.049ns (24.623%) route 0.150ns (75.377%)) Logic Levels: 0 Clock Path Skew: 0.082ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.668ns Source Clock Delay (SCD): 1.436ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 1.436ns (routing 0.447ns, distribution 0.989ns) Clock Net Delay (Destination): 1.668ns (routing 0.493ns, distribution 1.175ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.436 1.436 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/tx_wordclk SLICE_X30Y164 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y164 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.485 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.150 1.635 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X32Y164 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[90]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.668 1.668 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/tx_wordclk SLICE_X32Y164 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[90]/C clock pessimism -0.150 1.518 SLICE_X32Y164 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.523 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[90] ------------------------------------------------------------------- required time -1.523 arrival time 1.635 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.113ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TX_WORD_O_reg[4]/CLR (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.192ns (logic 0.049ns (25.521%) route 0.143ns (74.479%)) Logic Levels: 0 Clock Path Skew: 0.074ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.591ns Source Clock Delay (SCD): 1.385ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 1.385ns (routing 0.447ns, distribution 0.938ns) Clock Net Delay (Destination): 1.591ns (routing 0.493ns, distribution 1.098ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.385 1.385 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk SLICE_X89Y79 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y79 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.434 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.143 1.577 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X88Y79 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TX_WORD_O_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.591 1.591 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk SLICE_X88Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TX_WORD_O_reg[4]/C clock pessimism -0.132 1.459 SLICE_X88Y79 FDCE (Remov_HFF_SLICEL_C_CLR) 0.005 1.464 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TX_WORD_O_reg[4] ------------------------------------------------------------------- required time -1.464 arrival time 1.577 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.115ns (arrival time - required time) Source: g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[112]/CLR (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.205ns (logic 0.049ns (23.902%) route 0.156ns (76.098%)) Logic Levels: 0 Clock Path Skew: 0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.671ns Source Clock Delay (SCD): 1.436ns Clock Pessimism Removal (CPR): 0.150ns Clock Net Delay (Source): 1.436ns (routing 0.447ns, distribution 0.989ns) Clock Net Delay (Destination): 1.671ns (routing 0.493ns, distribution 1.178ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.436 1.436 g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/tx_wordclk SLICE_X30Y164 FDPE r g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X30Y164 FDPE (Prop_EFF_SLICEL_C_Q) 0.049 1.485 f g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.156 1.641 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X32Y164 FDCE f g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[112]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.671 1.671 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/tx_wordclk SLICE_X32Y164 FDCE r g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[112]/C clock pessimism -0.150 1.521 SLICE_X32Y164 FDCE (Remov_DFF_SLICEL_C_CLR) 0.005 1.526 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[112] ------------------------------------------------------------------- required time -1.526 arrival time 1.641 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.116ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[24]/CLR (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.198ns (logic 0.049ns (24.747%) route 0.149ns (75.252%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.594ns Source Clock Delay (SCD): 1.385ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 1.385ns (routing 0.447ns, distribution 0.938ns) Clock Net Delay (Destination): 1.594ns (routing 0.493ns, distribution 1.101ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.385 1.385 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk SLICE_X89Y79 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y79 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.434 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.149 1.583 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X88Y79 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.594 1.594 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk SLICE_X88Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[24]/C clock pessimism -0.132 1.462 SLICE_X88Y79 FDCE (Remov_AFF_SLICEL_C_CLR) 0.005 1.467 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[24] ------------------------------------------------------------------- required time -1.467 arrival time 1.583 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[44]/CLR (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.198ns (logic 0.049ns (24.747%) route 0.149ns (75.252%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.594ns Source Clock Delay (SCD): 1.385ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 1.385ns (routing 0.447ns, distribution 0.938ns) Clock Net Delay (Destination): 1.594ns (routing 0.493ns, distribution 1.101ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.385 1.385 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk SLICE_X89Y79 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y79 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.434 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.149 1.583 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X88Y79 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[44]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.594 1.594 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk SLICE_X88Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[44]/C clock pessimism -0.132 1.462 SLICE_X88Y79 FDCE (Remov_AFF2_SLICEL_C_CLR) 0.005 1.467 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[44] ------------------------------------------------------------------- required time -1.467 arrival time 1.583 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[4]/CLR (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.198ns (logic 0.049ns (24.747%) route 0.149ns (75.252%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.594ns Source Clock Delay (SCD): 1.385ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 1.385ns (routing 0.447ns, distribution 0.938ns) Clock Net Delay (Destination): 1.594ns (routing 0.493ns, distribution 1.101ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.385 1.385 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk SLICE_X89Y79 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y79 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.434 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.149 1.583 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X88Y79 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.594 1.594 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk SLICE_X88Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[4]/C clock pessimism -0.132 1.462 SLICE_X88Y79 FDCE (Remov_BFF_SLICEL_C_CLR) 0.005 1.467 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[4] ------------------------------------------------------------------- required time -1.467 arrival time 1.583 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[64]/CLR (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.198ns (logic 0.049ns (24.747%) route 0.149ns (75.252%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.594ns Source Clock Delay (SCD): 1.385ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 1.385ns (routing 0.447ns, distribution 0.938ns) Clock Net Delay (Destination): 1.594ns (routing 0.493ns, distribution 1.101ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.385 1.385 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk SLICE_X89Y79 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y79 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.434 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.149 1.583 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X88Y79 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[64]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.594 1.594 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk SLICE_X88Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[64]/C clock pessimism -0.132 1.462 SLICE_X88Y79 FDCE (Remov_BFF2_SLICEL_C_CLR) 0.005 1.467 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[64] ------------------------------------------------------------------- required time -1.467 arrival time 1.583 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[84]/CLR (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.198ns (logic 0.049ns (24.747%) route 0.149ns (75.252%)) Logic Levels: 0 Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.594ns Source Clock Delay (SCD): 1.385ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 1.385ns (routing 0.447ns, distribution 0.938ns) Clock Net Delay (Destination): 1.594ns (routing 0.493ns, distribution 1.101ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.385 1.385 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk SLICE_X89Y79 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y79 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.434 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.149 1.583 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X88Y79 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[84]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.594 1.594 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk SLICE_X88Y79 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[84]/C clock pessimism -0.132 1.462 SLICE_X88Y79 FDCE (Remov_CFF_SLICEL_C_CLR) 0.005 1.467 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[84] ------------------------------------------------------------------- required time -1.467 arrival time 1.583 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.141ns (arrival time - required time) Source: g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C (rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Destination: g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[20]/CLR (removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (tx_wordclk rise@0.000ns - tx_wordclk rise@0.000ns) Data Path Delay: 0.239ns (logic 0.049ns (20.502%) route 0.190ns (79.498%)) Logic Levels: 0 Clock Path Skew: 0.093ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.610ns Source Clock Delay (SCD): 1.385ns Clock Pessimism Removal (CPR): 0.132ns Clock Net Delay (Source): 1.385ns (routing 0.447ns, distribution 0.938ns) Clock Net Delay (Destination): 1.610ns (routing 0.493ns, distribution 1.117ns) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.385 1.385 g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/tx_wordclk SLICE_X89Y79 FDPE r g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X89Y79 FDPE (Prop_AFF_SLICEM_C_Q) 0.049 1.434 f g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/Q net (fo=227, routed) 0.190 1.624 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/gbt_txreset_s[0] SLICE_X87Y78 FDCE f g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock tx_wordclk rise edge) 0.000 0.000 r BUFGCE_X2Y98 BUFGCE 0.000 0.000 r tx_wordclk_bufg/O X2Y4 (CLOCK_ROOT) net (fo=27445, routed) 1.610 1.610 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/tx_wordclk SLICE_X87Y78 FDCE r g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[20]/C clock pessimism -0.132 1.478 SLICE_X87Y78 FDCE (Remov_EFF_SLICEM_C_CLR) 0.005 1.483 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[20] ------------------------------------------------------------------- required time -1.483 arrival time 1.624 ------------------------------------------------------------------- slack 0.141